mirror of https://github.com/ARMmbed/mbed-os.git
Rework us_ticker and rtc_api/lp_ticker | Fix compiler warnings for spi_api
Simplify tickers to stop emulating 1us ticks by using native timer resolutions. Implement ticker get info functions. Separate rtc and lp ticker init status by implementing separate functions. Add mbed_critical include file to disable compiler warning messages.pull/6697/head
Keyur Hariya
adbridge
parent
fac4ed0a27
commit
a6cc79faf1
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@ -1,5 +1,5 @@
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/*******************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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* Copyright (C) 2016,2018 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -36,33 +36,24 @@
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#include "rtc.h"
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#include "lp.h"
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#define PRESCALE_VAL RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
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#define SHIFT_AMT (RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
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// LOG2 for 32-bit powers of 2
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#define LOG2_1(n) (((n) >= (1 << 1)) ? 1 : 0)
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#define LOG2_2(n) (((n) >= (1 << 2)) ? ( 2 + (LOG2_1((n) >> 2))) : LOG2_1(n))
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#define LOG2_4(n) (((n) >= (1 << 4)) ? ( 4 + (LOG2_2((n) >> 4))) : LOG2_2(n))
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#define LOG2_8(n) (((n) >= (1 << 8)) ? ( 8 + (LOG2_4((n) >> 8))) : LOG2_4(n))
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#define LOG2(n) (((n) >= (1 << 16)) ? (16 + (LOG2_8((n) >> 16))) : LOG2_8(n))
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#define WINDOW 1000
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#define LP_TIMER_FREQ_HZ 4096
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#define LP_TIMER_PRESCALE RTC_PRESCALE_DIV_2_0
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#define LP_TIMER_RATE_HZ (LP_TIMER_FREQ_HZ >> LP_TIMER_PRESCALE)
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#define LP_TIMER_WIDTH 32
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static int rtc_inited = 0;
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static volatile uint32_t overflow_cnt = 0;
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static uint64_t rtc_read64(void);
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static volatile int rtc_inited = 0;
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static volatile int lp_ticker_inited = 0;
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//******************************************************************************
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static void overflow_handler(void)
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static void init_rtc(void)
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{
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overflow_cnt++;
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RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS);
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}
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//******************************************************************************
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void rtc_init(void)
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{
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if (rtc_inited) {
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return;
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}
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rtc_inited = 1;
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overflow_cnt = 0;
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/* Enable power for RTC for all LPx states */
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MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN |
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MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
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@ -70,21 +61,12 @@ void rtc_init(void)
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/* Enable clock to synchronizers */
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CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1);
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// Prepare interrupt handlers
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NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
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NVIC_EnableIRQ(RTC0_IRQn);
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NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
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NVIC_EnableIRQ(RTC3_IRQn);
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// Enable wakeup on RTC rollover
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LP_ConfigRTCWakeUp(0, 0, 0, 1);
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/* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
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* if it is already running.
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*/
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if (!RTC_IsActive()) {
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rtc_cfg_t cfg = {0};
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cfg.prescaler = PRESCALE_VAL;
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rtc_cfg_t cfg = { 0 };
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cfg.prescaler = LP_TIMER_PRESCALE;
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cfg.snoozeMode = RTC_SNOOZE_DISABLE;
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int retval = RTC_Init(&cfg);
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@ -96,163 +78,128 @@ void rtc_init(void)
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}
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//******************************************************************************
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void lp_ticker_init(void)
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static void overflow_handler(void)
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{
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rtc_init();
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MXC_RTCTMR->comp[1] += ((UINT32_MAX >> LOG2(LP_TIMER_RATE_HZ)) + 1);
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RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS);
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}
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//******************************************************************************
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void rtc_init(void)
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{
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if (rtc_inited) {
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return;
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}
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NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
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NVIC_EnableIRQ(RTC3_IRQn);
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// Enable wakeup on RTC overflow
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LP_ConfigRTCWakeUp(lp_ticker_inited, 0, 0, 1);
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init_rtc();
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rtc_inited = 1;
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}
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//******************************************************************************
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void rtc_free(void)
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{
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if (RTC_IsActive()) {
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// Clear and disable RTC
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MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
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RTC_Stop();
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if (rtc_inited) {
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rtc_inited = 0;
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if (lp_ticker_inited) {
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RTC_DisableINT(MXC_F_RTC_FLAGS_OVERFLOW);
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} else {
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MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
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RTC_Stop();
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}
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}
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}
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//******************************************************************************
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int rtc_isenabled(void)
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{
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return RTC_IsActive();
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}
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//******************************************************************************
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time_t rtc_read(void)
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{
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uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
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uint32_t ovf1, ovf2;
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// Make sure RTC is setup before trying to read
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if (!rtc_inited) {
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rtc_init();
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}
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// Ensure coherency between overflow_cnt and timer
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do {
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ovf_cnt_1 = overflow_cnt;
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ovf1 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
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timer_cnt = RTC_GetCount();
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ovf2 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
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ovf_cnt_2 = overflow_cnt;
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} while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
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// Account for an unserviced interrupt
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if (ovf1) {
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ovf_cnt_1++;
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}
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return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
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}
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//******************************************************************************
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static uint64_t rtc_read64(void)
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{
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uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
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uint32_t ovf1, ovf2;
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uint64_t current_us;
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// Make sure RTC is setup before trying to read
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if (!rtc_inited) {
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rtc_init();
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}
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// Ensure coherency between overflow_cnt and timer
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do {
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ovf_cnt_1 = overflow_cnt;
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ovf1 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
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timer_cnt = RTC_GetCount();
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ovf2 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
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ovf_cnt_2 = overflow_cnt;
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} while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
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// Account for an unserviced interrupt
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if (ovf1) {
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ovf_cnt_1++;
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}
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current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
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return current_us;
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return rtc_inited;
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}
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//******************************************************************************
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void rtc_write(time_t t)
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{
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// Make sure RTC is setup before accessing
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if (!rtc_inited) {
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rtc_init();
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}
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RTC_Stop();
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RTC_SetCount(t << SHIFT_AMT);
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overflow_cnt = t >> (32 - SHIFT_AMT);
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RTC_Start();
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}
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//******************************************************************************
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void lp_ticker_set_interrupt(timestamp_t timestamp)
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{
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uint32_t comp_value;
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uint64_t curr_ts64;
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uint64_t ts64;
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// Note: interrupts are disabled before this function is called.
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// Disable the alarm while it is prepared
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RTC_DisableINT(MXC_F_RTC_INTEN_COMP0);
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curr_ts64 = rtc_read64();
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ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
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// If this event is older than a recent window, it must be in the future
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if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
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ts64 += 0x100000000ULL;
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}
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uint32_t timer = RTC_GetCount();
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if (ts64 <= curr_ts64) {
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// This event has already occurred. Set the alarm to expire immediately.
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comp_value = timer + 1;
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} else {
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comp_value = (ts64 << SHIFT_AMT) / 1000000;
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}
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// Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
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if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
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comp_value = timer + 2;
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}
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MXC_RTCTMR->comp[0] = comp_value;
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MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
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RTC_EnableINT(MXC_F_RTC_INTEN_COMP0);
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// Enable wakeup from RTC
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LP_ConfigRTCWakeUp(1, 0, 0, 1);
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MXC_RTCTMR->comp[1] = t - (MXC_RTCTMR->timer >> LOG2(LP_TIMER_RATE_HZ));
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// Wait for pending transactions
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while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
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}
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//******************************************************************************
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time_t rtc_read(void)
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{
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if (!rtc_inited) {
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rtc_init();
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}
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return (MXC_RTCTMR->timer >> LOG2(LP_TIMER_RATE_HZ)) + MXC_RTCTMR->comp[1];
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}
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//******************************************************************************
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void lp_ticker_init(void)
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{
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if (lp_ticker_inited) {
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return;
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}
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NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
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NVIC_EnableIRQ(RTC0_IRQn);
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init_rtc();
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lp_ticker_inited = 1;
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}
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//******************************************************************************
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uint32_t lp_ticker_read(void)
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{
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return MXC_RTCTMR->timer;
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}
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//******************************************************************************
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void lp_ticker_set_interrupt(timestamp_t timestamp)
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{
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MXC_RTCTMR->comp[0] = timestamp;
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MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
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MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0;
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// Enable wakeup from RTC compare 0
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LP_ConfigRTCWakeUp(1, 0, 0, rtc_inited);
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// Wait for pending transactions
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while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
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}
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//******************************************************************************
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void lp_ticker_disable_interrupt(void)
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{
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RTC_DisableINT(MXC_F_RTC_INTEN_COMP0);
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}
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//******************************************************************************
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void lp_ticker_clear_interrupt(void)
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{
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RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS);
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}
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//******************************************************************************
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void lp_ticker_fire_interrupt(void)
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{
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NVIC_SetPendingIRQ(RTC0_IRQn);
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}
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//******************************************************************************
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inline void lp_ticker_disable_interrupt(void)
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const ticker_info_t *lp_ticker_get_info(void)
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{
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RTC_DisableINT(MXC_F_RTC_INTEN_COMP0);
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}
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static const ticker_info_t info = {
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LP_TIMER_RATE_HZ,
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LP_TIMER_WIDTH
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};
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//******************************************************************************
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inline void lp_ticker_clear_interrupt(void)
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{
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RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS);
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}
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//******************************************************************************
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inline uint32_t lp_ticker_read(void)
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{
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return rtc_read64();
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return &info;
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}
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@ -32,6 +32,7 @@
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*/
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#include "mbed_assert.h"
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#include "mbed_critical.h"
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#include "spi_api.h" // mbed HAL
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#include "spim_regs.h" // bare metal
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#include "spim.h" // Maxim CMSIS driver
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@ -1,5 +1,5 @@
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/*******************************************************************************
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* Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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* Copyright (c) 2016,2018 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -32,251 +32,84 @@
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*/
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#include <stddef.h>
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#include "mbed_error.h"
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#include "mbed_critical.h"
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#include "us_ticker_api.h"
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#include "PeripheralNames.h"
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#include "tmr.h"
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#include "assert.h"
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#define US_TIMER MXC_TMR0
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#define US_TIMER_IRQn TMR0_0_IRQn
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#define US_TIMER MXC_TMR0
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#define US_TIMER_IRQn TMR0_0_IRQn
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#define US_TIMER_PRESCALE TMR_PRESCALE_DIV_2_5
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#define US_TIMER_MODE TMR32_MODE_COMPARE
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#define US_TIMER_WIDTH 32
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static int us_ticker_inited = 0;
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static uint32_t ticks_per_us;
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static uint32_t tick_win;
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static volatile uint64_t current_cnt; // Hold the current ticks
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static volatile uint64_t event_cnt; // Holds the value of the next event
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#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us)
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//******************************************************************************
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static inline void inc_current_cnt_no_crit(uint32_t inc)
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{
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// Overflow the ticker when the us ticker overflows
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current_cnt += inc;
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if (current_cnt > MAX_TICK_VAL) {
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current_cnt -= (MAX_TICK_VAL + 1);
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}
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}
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//******************************************************************************
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static inline void inc_current_cnt(uint32_t inc)
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{
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core_util_critical_section_enter();
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inc_current_cnt_no_crit(inc);
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core_util_critical_section_exit();
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}
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//******************************************************************************
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static inline int event_passed(uint64_t current, uint64_t event)
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{
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// Determine if the event has already happened.
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// If the event is behind the current ticker, within a window,
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// then the event has already happened.
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if (((current < tick_win) && ((event < current) ||
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(event > (MAX_TICK_VAL - (tick_win - current))))) ||
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((event < current) && (event > (current - tick_win)))) {
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return 1;
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}
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return 0;
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}
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//******************************************************************************
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static inline uint64_t event_diff(uint64_t current, uint64_t event)
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{
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// Check to see if the ticker will overflow before the event
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if(current <= event) {
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return (event - current);
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}
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return ((MAX_TICK_VAL - current) + event);
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}
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//******************************************************************************
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static void tmr_handler(void)
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{
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uint32_t cmp = TMR32_GetCompare(US_TIMER);
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TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts
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if (TMR32_GetFlag(US_TIMER)) {
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inc_current_cnt_no_crit(cmp);
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}
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TMR32_ClearFlag(US_TIMER);
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NVIC_ClearPendingIRQ(US_TIMER_IRQn);
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if (event_passed(current_cnt + TMR32_GetCount(US_TIMER), event_cnt)) {
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// the timestamp has expired
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event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value
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us_ticker_irq_handler();
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} else {
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uint64_t diff = event_diff(current_cnt, event_cnt);
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if (diff < (uint64_t)0xFFFFFFFF) {
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// the event occurs before the next overflow
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TMR32_SetCompare(US_TIMER, diff);
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// Since the timer keeps counting after the terminal value is reached, it is possible that the new
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// terminal value is in the past.
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if (TMR32_GetCompare(US_TIMER) < TMR32_GetCount(US_TIMER)) {
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// the timestamp has expired
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TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts
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TMR32_ClearFlag(US_TIMER);
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NVIC_ClearPendingIRQ(US_TIMER_IRQn);
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event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value
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us_ticker_irq_handler();
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}
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}
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}
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}
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static volatile int us_ticker_inited = 0;
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//******************************************************************************
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void us_ticker_init(void)
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{
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tmr32_cfg_t cfg;
|
||||
|
||||
if (us_ticker_inited) {
|
||||
return;
|
||||
}
|
||||
|
||||
us_ticker_inited = 1;
|
||||
current_cnt = 0;
|
||||
event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value
|
||||
ticks_per_us = SystemCoreClock / 1000000;
|
||||
tick_win = SystemCoreClock / 100; // Set the tick window to 10ms
|
||||
|
||||
int retval = TMR_Init(US_TIMER, TMR_PRESCALE_DIV_2_0, NULL);
|
||||
MBED_ASSERT(retval == E_NO_ERROR);
|
||||
|
||||
tmr32_cfg_t cfg;
|
||||
cfg.mode = TMR32_MODE_CONTINUOUS;
|
||||
cfg.mode = US_TIMER_MODE;
|
||||
cfg.polarity = TMR_POLARITY_UNUSED;
|
||||
cfg.compareCount = 0xFFFFFFFF;
|
||||
cfg.compareCount = UINT32_MAX;
|
||||
|
||||
TMR_Init(US_TIMER, US_TIMER_PRESCALE, NULL);
|
||||
TMR32_Config(US_TIMER, &cfg);
|
||||
|
||||
NVIC_SetVector(US_TIMER_IRQn, (uint32_t)tmr_handler);
|
||||
NVIC_SetVector(US_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
|
||||
NVIC_EnableIRQ(US_TIMER_IRQn);
|
||||
TMR32_EnableINT(US_TIMER);
|
||||
|
||||
TMR32_Start(US_TIMER);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void us_ticker_deinit(void)
|
||||
{
|
||||
TMR32_Stop(US_TIMER);
|
||||
TMR32_DisableINT(US_TIMER);
|
||||
TMR32_ClearFlag(US_TIMER);
|
||||
us_ticker_inited = 0;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
uint32_t us_ticker_read(void)
|
||||
{
|
||||
uint64_t current_cnt1, current_cnt2;
|
||||
uint32_t cmp, cnt;
|
||||
uint32_t flag1, flag2;
|
||||
static uint32_t last = 0;
|
||||
|
||||
if (!us_ticker_inited) {
|
||||
us_ticker_init();
|
||||
}
|
||||
|
||||
// Ensure coherency between current_cnt and TMR32_GetCount()
|
||||
do {
|
||||
current_cnt1 = current_cnt;
|
||||
flag1 = TMR32_GetFlag(US_TIMER);
|
||||
cmp = TMR32_GetCompare(US_TIMER);
|
||||
cnt = TMR32_GetCount(US_TIMER);
|
||||
flag2 = TMR32_GetFlag(US_TIMER);
|
||||
current_cnt2 = current_cnt;
|
||||
} while ((current_cnt1 != current_cnt2) || (flag1 != flag2));
|
||||
|
||||
// Account for an unserviced interrupt
|
||||
if (flag1) {
|
||||
// Clear peripheral interrupt flag; leaving NVIC pending set
|
||||
TMR32_ClearFlag(US_TIMER);
|
||||
// Advance global count
|
||||
inc_current_cnt(cmp + cnt);
|
||||
|
||||
current_cnt1 += cmp;
|
||||
}
|
||||
|
||||
current_cnt1 += cnt;
|
||||
|
||||
assert(last <= (current_cnt1 / ticks_per_us));
|
||||
last = (current_cnt1 / ticks_per_us);
|
||||
return last;
|
||||
return US_TIMER->count32;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void us_ticker_set_interrupt(timestamp_t timestamp)
|
||||
{
|
||||
// Note: interrupts are disabled before this function is called.
|
||||
|
||||
TMR32_Stop(US_TIMER);
|
||||
|
||||
if (TMR32_GetFlag(US_TIMER)) {
|
||||
TMR32_ClearFlag(US_TIMER);
|
||||
NVIC_ClearPendingIRQ(US_TIMER_IRQn);
|
||||
inc_current_cnt(TMR32_GetCompare(US_TIMER));
|
||||
}
|
||||
|
||||
// add and reset the current count value
|
||||
inc_current_cnt(TMR32_GetCount(US_TIMER));
|
||||
TMR32_SetCount(US_TIMER, 0);
|
||||
|
||||
// add the number of cycles that the timer is disabled here for
|
||||
inc_current_cnt(200);
|
||||
|
||||
event_cnt = (uint64_t)timestamp * ticks_per_us;
|
||||
|
||||
// Check to see if the event has already passed
|
||||
if (!event_passed(current_cnt, event_cnt)) {
|
||||
uint64_t diff = event_diff(current_cnt, event_cnt);
|
||||
if (diff < (uint64_t)0xFFFFFFFF) {
|
||||
// the event occurs before the next overflow
|
||||
TMR32_SetCompare(US_TIMER, diff);
|
||||
} else {
|
||||
// the event occurs after the next overflow
|
||||
TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // set to max
|
||||
}
|
||||
} else {
|
||||
// the requested timestamp occurs in the past
|
||||
// set the timer up to immediately expire
|
||||
TMR32_SetCompare(US_TIMER, 1);
|
||||
}
|
||||
|
||||
TMR32_Start(US_TIMER);
|
||||
US_TIMER->ctrl = 0;
|
||||
US_TIMER->term_cnt32 = timestamp;
|
||||
US_TIMER->inten = MXC_F_TMR_INTEN_TIMER0;
|
||||
US_TIMER->ctrl = MXC_F_TMR_CTRL_ENABLE0 |
|
||||
(US_TIMER_MODE << MXC_F_TMR_CTRL_MODE_POS) |
|
||||
(US_TIMER_PRESCALE << MXC_F_TMR_CTRL_PRESCALE_POS);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void us_ticker_fire_interrupt(void)
|
||||
{
|
||||
TMR32_SetCompare(US_TIMER, 1);
|
||||
NVIC_SetPendingIRQ(US_TIMER_IRQn);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void us_ticker_disable_interrupt(void)
|
||||
{
|
||||
// There are no more events, set timer overflow to the max
|
||||
TMR32_SetCompare(US_TIMER, 0xFFFFFFFF);
|
||||
US_TIMER->inten = 0;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void us_ticker_clear_interrupt(void)
|
||||
{
|
||||
// cleared in the local handler
|
||||
US_TIMER->intfl = MXC_F_TMR_INTFL_TIMER0;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void us_ticker_set(timestamp_t timestamp)
|
||||
const ticker_info_t* us_ticker_get_info(void)
|
||||
{
|
||||
TMR32_Stop(US_TIMER);
|
||||
current_cnt = (uint64_t)timestamp * ticks_per_us;
|
||||
TMR32_SetCount(US_TIMER, 0);
|
||||
TMR32_SetCompare(US_TIMER, 0xFFFFFFFF);
|
||||
TMR32_Start(US_TIMER);
|
||||
static const ticker_info_t info = {
|
||||
RO_FREQ >> US_TIMER_PRESCALE,
|
||||
US_TIMER_WIDTH
|
||||
};
|
||||
|
||||
if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) {
|
||||
// The next timestamp has elapsed. Trigger the interrupt to handle it.
|
||||
NVIC_SetPendingIRQ(US_TIMER_IRQn);
|
||||
}
|
||||
return &info;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue