mirror of https://github.com/ARMmbed/mbed-os.git
Remove Portenta-specific system clock override as this can be done through targets.json now
Jamie Smith
parent
7cb61d9edf
commit
a5abf7ca11
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@ -8,7 +8,6 @@ add_library(mbed-portenta-h7-m4 INTERFACE)
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target_sources(mbed-portenta-h7-m4
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target_sources(mbed-portenta-h7-m4
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INTERFACE
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INTERFACE
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PeripheralPins.c
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PeripheralPins.c
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system_clock_override.c
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portenta_power.cpp
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portenta_power.cpp
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)
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)
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@ -25,7 +24,6 @@ add_library(mbed-portenta-h7-m7 INTERFACE)
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target_sources(mbed-portenta-h7-m7
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target_sources(mbed-portenta-h7-m7
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INTERFACE
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INTERFACE
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PeripheralPins.c
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PeripheralPins.c
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system_clock_override.c
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portenta_power.cpp
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portenta_power.cpp
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)
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)
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@ -1,309 +0,0 @@
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/*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* <h2><center>© Copyright (c) 2020 Arduino SA.
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* All rights reserved.</center></h2>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/**
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* This file configures the system clock as follows:
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*--------------------------------------------------------------------
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* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
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* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
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* | 3- USE_PLL_HSI (internal 64 MHz clock)
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*--------------------------------------------------------------------
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* SYSCLK(MHz) | 480
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* AHBCLK (MHz) | 240
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* APB1CLK (MHz) | 120
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* APB2CLK (MHz) | 120
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* APB3CLK (MHz) | 120
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* APB4CLK (MHz) | 120
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* USB capable (48 MHz) | YES
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*--------------------------------------------------------------------
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**/
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#include "stm32h7xx.h"
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#include "nvic_addr.h"
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#include "mbed_error.h"
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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// clock source is selected with CLOCK_SOURCE in json config
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#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
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#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
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#define USE_PLL_HSI 0x2 // Use HSI internal clock
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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uint8_t SetSysClock_PLL_HSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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bool lowspeed = false;
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#if defined(LOWSPEED) && (LOWSPEED == 1)
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lowspeed = true;
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#endif
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
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/* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */
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if (SetSysClock_PLL_HSE(1, lowspeed) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
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/* 2- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0, lowspeed) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/* 3- If fail start with HSI clock */
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if (SetSysClock_PLL_HSI() == 0)
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#endif
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{
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error("SetSysClock failed\n");
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}
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}
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}
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}
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static const uint32_t _keep;
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bool isBootloader()
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{
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return ((uint32_t)&_keep < 0x8040000);
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}
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bool isBetaBoard()
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{
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uint8_t *bootloader_data = (uint8_t *)(0x801F000);
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if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
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return true;
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} else {
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return (bootloader_data[10] == 27);
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}
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}
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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// If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration
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if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) {
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
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return 0;
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}
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}
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/* Enable oscillator pin */
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__HAL_RCC_GPIOH_CLK_ENABLE();
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GPIO_InitTypeDef gpio_osc_init_structure;
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gpio_osc_init_structure.Pin = GPIO_PIN_1;
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gpio_osc_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
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gpio_osc_init_structure.Pull = GPIO_PULLUP;
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gpio_osc_init_structure.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOH, &gpio_osc_init_structure);
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HAL_Delay(10);
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HAL_GPIO_WritePin(GPIOH, GPIO_PIN_1, 1);
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/* Supply configuration update enable */
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#if HSE_VALUE == 27000000
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HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT);
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#else
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HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_LDO);
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#endif
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/* Configure the main internal regulator output voltage */
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if (lowspeed) {
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
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} else {
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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}
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while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
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if (bypass) {
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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} else {
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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}
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 5;
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if (lowspeed) {
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RCC_OscInitStruct.PLL.PLLN = 40;
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} else {
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RCC_OscInitStruct.PLL.PLLN = 160;
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}
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#if HSE_VALUE == 27000000
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RCC_OscInitStruct.PLL.PLLM = 9;
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if (lowspeed) {
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RCC_OscInitStruct.PLL.PLLN = 80;
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} else {
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RCC_OscInitStruct.PLL.PLLN = 300;
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}
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#endif
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLQ = 10;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/* Select PLL as system clock source and configure bus clocks dividers */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
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RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 |
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RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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if (lowspeed) {
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
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return 0; // FAIL
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}
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} else {
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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return 0; // FAIL
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}
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}
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// HAL_RCCEx_EnableBootCore(RCC_BOOT_C2);
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#if DEVICE_USBDEVICE
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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HAL_PWREx_EnableUSBVoltageDetector();
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#endif /* DEVICE_USBDEVICE */
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__HAL_RCC_CSI_ENABLE() ;
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__HAL_RCC_SYSCFG_CLK_ENABLE() ;
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HAL_EnableCompensationCell();
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSI(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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/* Supply configuration update enable */
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#if HSE_VALUE == 27000000
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HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT);
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#else
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HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_LDO);
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#endif
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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// Enable HSI oscillator and activate PLL with HSI as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 100;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 10;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/* Select PLL as system clock source and configure bus clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
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RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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return 0; // FAIL
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}
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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#if defined (CORE_CM4)
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void HSEM2_IRQHandler(void)
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{
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HAL_HSEM_IRQHandler();
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}
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#endif
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#if defined (CORE_CM7)
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void HSEM1_IRQHandler(void)
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{
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HAL_HSEM_IRQHandler();
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}
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#endif
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