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RTX - fix missing header guards for Cortex-M4 (GCC ARM) 

The HAL CM4 is valid only for FPU present. These guards were added
to mbed SDK, as there are targets Cortex-M4.
Martin Kojtal 2016-04-11 10:57:04 +01:00
parent 1524c5fca9
commit a573214eff
1 changed files with 20 additions and 0 deletions
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20
core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/HAL_CM4.S
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@ -220,8 +220,12 @@ SVC_Handler_Veneer:
SVC_ContextSave: SVC_ContextSave:
TST LR,#0x10 /* is it extended frame? */ TST LR,#0x10 /* is it extended frame? */
#ifdef __FPU_PRESENT
ITTE EQ ITTE EQ
VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */
#else
ITE EQ
#endif
MOVEQ R0,#0x01 /* os_tsk->stack_frame val */ MOVEQ R0,#0x01 /* os_tsk->stack_frame val */
MOVNE R0,#0x00 MOVNE R0,#0x00
STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */ STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */
@ -239,10 +243,16 @@ SVC_ContextRestore:
LDMIA R12!,{R4-R11} /* Restore New Context */ LDMIA R12!,{R4-R11} /* Restore New Context */
LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */
CMP R0,#0 /* Basic/Extended Stack Frame */ CMP R0,#0 /* Basic/Extended Stack Frame */
#ifdef __FPU_PRESENT
ITEE EQ ITEE EQ
#else
ITE EQ
#endif
MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */ MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */
MVNNE LR,#~0xFFFFFFED MVNNE LR,#~0xFFFFFFED
#ifdef __FPU_PRESENT
VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */ VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */
#endif
MSR PSP,R12 /* Write PSP */ MSR PSP,R12 /* Write PSP */
SVC_Exit: SVC_Exit:
@ -313,8 +323,12 @@ Sys_Switch:
MRS R12,PSP /* Read PSP */ MRS R12,PSP /* Read PSP */
TST LR,#0x10 /* is it extended frame? */ TST LR,#0x10 /* is it extended frame? */
#ifdef __FPU_PRESENT
ITTE EQ ITTE EQ
VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */
#else
ITE EQ
#endif
MOVEQ R0,#0x01 /* os_tsk->stack_frame val */ MOVEQ R0,#0x01 /* os_tsk->stack_frame val */
MOVNE R0,#0x00 MOVNE R0,#0x00
STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */ STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */
@ -331,10 +345,16 @@ Sys_Switch:
LDMIA R12!,{R4-R11} /* Restore New Context */ LDMIA R12!,{R4-R11} /* Restore New Context */
LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */
CMP R0,#0 /* Basic/Extended Stack Frame */ CMP R0,#0 /* Basic/Extended Stack Frame */
#ifdef __FPU_PRESENT
ITEE EQ ITEE EQ
#else
ITE EQ
#endif
MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */ MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */
MVNNE LR,#~0xFFFFFFED MVNNE LR,#~0xFFFFFFED
#ifdef __FPU_PRESENT
VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */ VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */
#endif
MSR PSP,R12 /* Write PSP */ MSR PSP,R12 /* Write PSP */
Sys_Exit: Sys_Exit: