diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld new file mode 100644 index 0000000000..f6839ccde3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld @@ -0,0 +1,164 @@ +/* + * K64F ARM GCC linker script file + */ + +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410 + RAM (rwx) : ORIGIN = 0x1FFF0400, LENGTH = 0x00040000 - 0x00000400 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * _reset_init : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + *(.text.Reset_Handler) + *(.text.System_Init) + . = ALIGN(4); + } > VECTORS + + .flash_protect : + { + KEEP(*(.kinetis_flash_config_field)) + . = ALIGN(4); + } > FLASH_PROTECTION + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.s new file mode 100644 index 0000000000..20021433c4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.s @@ -0,0 +1,357 @@ +/* K64F startup ARM GCC + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.2 + * Date: 15 Nov 2011 + * + * Copyright (c) 2011, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x80 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete */ + .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete */ + .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete */ + .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete */ + .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete */ + .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete */ + .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete */ + .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete */ + .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete */ + .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete */ + .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete */ + .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete */ + .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete */ + .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete */ + .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete */ + .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete */ + .long DMA_Error_IRQHandler /* DMA Error Interrupt */ + .long MCM_IRQHandler /* Normal Interrupt */ + .long FTFE_IRQHandler /* FTFE Command complete interrupt */ + .long Read_Collision_IRQHandler /* Read Collision Interrupt */ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */ + .long LLW_IRQHandler /* Low Leakage Wakeup */ + .long Watchdog_IRQHandler /* WDOG Interrupt */ + .long RNG_IRQHandler /* RNG Interrupt */ + .long I2C0_IRQHandler /* I2C0 interrupt */ + .long I2C1_IRQHandler /* I2C1 interrupt */ + .long SPI0_IRQHandler /* SPI0 Interrupt */ + .long SPI1_IRQHandler /* SPI1 Interrupt */ + .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt */ + .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt */ + .long UART0_LON_IRQHandler /* UART0 LON interrupt */ + .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt */ + .long UART0_ERR_IRQHandler /* UART0 Error interrupt */ + .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt */ + .long UART1_ERR_IRQHandler /* UART1 Error interrupt */ + .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt */ + .long UART2_ERR_IRQHandler /* UART2 Error interrupt */ + .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt */ + .long UART3_ERR_IRQHandler /* UART3 Error interrupt */ + .long ADC0_IRQHandler /* ADC0 interrupt */ + .long CMP0_IRQHandler /* CMP0 interrupt */ + .long CMP1_IRQHandler /* CMP1 interrupt */ + .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt */ + .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt */ + .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt */ + .long CMT_IRQHandler /* CMT interrupt */ + .long RTC_IRQHandler /* RTC interrupt */ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */ + .long PIT0_IRQHandler /* PIT timer channel 0 interrupt */ + .long PIT1_IRQHandler /* PIT timer channel 1 interrupt */ + .long PIT2_IRQHandler /* PIT timer channel 2 interrupt */ + .long PIT3_IRQHandler /* PIT timer channel 3 interrupt */ + .long PDB0_IRQHandler /* PDB0 Interrupt */ + .long USB0_IRQHandler /* USB0 interrupt */ + .long USBDCD_IRQHandler /* USBDCD Interrupt */ + .long Reserved71_IRQHandler /* Reserved interrupt 71 */ + .long DAC0_IRQHandler /* DAC0 interrupt */ + .long MCG_IRQHandler /* MCG Interrupt */ + .long LPTimer_IRQHandler /* LPTimer interrupt */ + .long PORTA_IRQHandler /* Port A interrupt */ + .long PORTB_IRQHandler /* Port B interrupt */ + .long PORTC_IRQHandler /* Port C interrupt */ + .long PORTD_IRQHandler /* Port D interrupt */ + .long PORTE_IRQHandler /* Port E interrupt */ + .long SWI_IRQHandler /* Software interrupt */ + .long SPI2_IRQHandler /* SPI2 Interrupt */ + .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt */ + .long UART4_ERR_IRQHandler /* UART4 Error interrupt */ + .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt */ + .long UART5_ERR_IRQHandler /* UART5 Error interrupt */ + .long CMP2_IRQHandler /* CMP2 interrupt */ + .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt */ + .long DAC1_IRQHandler /* DAC1 interrupt */ + .long ADC1_IRQHandler /* ADC1 interrupt */ + .long I2C2_IRQHandler /* I2C2 interrupt */ + .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt */ + .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt */ + .long CAN0_Error_IRQHandler /* CAN0 error interrupt */ + .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt */ + .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt */ + .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt */ + .long SDHC_IRQHandler /* SDHC interrupt */ + .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt */ + .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt */ + .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt */ + .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + +/* IRQ Handlers */ + def_irq_default_handler DMA0_IRQHandler + def_irq_default_handler DMA1_IRQHandler + def_irq_default_handler DMA2_IRQHandler + def_irq_default_handler DMA3_IRQHandler + def_irq_default_handler DMA4_IRQHandler + def_irq_default_handler DMA5_IRQHandler + def_irq_default_handler DMA6_IRQHandler + def_irq_default_handler DMA7_IRQHandler + def_irq_default_handler DMA8_IRQHandler + def_irq_default_handler DMA9_IRQHandler + def_irq_default_handler DMA10_IRQHandler + def_irq_default_handler DMA11_IRQHandler + def_irq_default_handler DMA12_IRQHandler + def_irq_default_handler DMA13_IRQHandler + def_irq_default_handler DMA14_IRQHandler + def_irq_default_handler DMA15_IRQHandler + def_irq_default_handler DMA_Error_IRQHandler + def_irq_default_handler MCM_IRQHandler + def_irq_default_handler FTFE_IRQHandler + def_irq_default_handler Read_Collision_IRQHandler + def_irq_default_handler LVD_LVW_IRQHandler + def_irq_default_handler LLW_IRQHandler + def_irq_default_handler Watchdog_IRQHandler + def_irq_default_handler RNG_IRQHandler + def_irq_default_handler I2C0_IRQHandler + def_irq_default_handler I2C1_IRQHandler + def_irq_default_handler SPI0_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler I2S0_Tx_IRQHandler + def_irq_default_handler I2S0_Rx_IRQHandler + def_irq_default_handler UART0_LON_IRQHandler + def_irq_default_handler UART0_RX_TX_IRQHandler + def_irq_default_handler UART0_ERR_IRQHandler + def_irq_default_handler UART1_RX_TX_IRQHandler + def_irq_default_handler UART1_ERR_IRQHandler + def_irq_default_handler UART2_RX_TX_IRQHandler + def_irq_default_handler UART2_ERR_IRQHandler + def_irq_default_handler UART3_RX_TX_IRQHandler + def_irq_default_handler UART3_ERR_IRQHandler + def_irq_default_handler ADC0_IRQHandler + def_irq_default_handler CMP0_IRQHandler + def_irq_default_handler CMP1_IRQHandler + def_irq_default_handler FTM0_IRQHandler + def_irq_default_handler FTM1_IRQHandler + def_irq_default_handler FTM2_IRQHandler + def_irq_default_handler CMT_IRQHandler + def_irq_default_handler RTC_IRQHandler + def_irq_default_handler RTC_Seconds_IRQHandler + def_irq_default_handler PIT0_IRQHandler + def_irq_default_handler PIT1_IRQHandler + def_irq_default_handler PIT2_IRQHandler + def_irq_default_handler PIT3_IRQHandler + def_irq_default_handler PDB0_IRQHandler + def_irq_default_handler USB0_IRQHandler + def_irq_default_handler USBDCD_IRQHandler + def_irq_default_handler Reserved71_IRQHandler + def_irq_default_handler DAC0_IRQHandler + def_irq_default_handler MCG_IRQHandler + def_irq_default_handler LPTimer_IRQHandler + def_irq_default_handler PORTA_IRQHandler + def_irq_default_handler PORTB_IRQHandler + def_irq_default_handler PORTC_IRQHandler + def_irq_default_handler PORTD_IRQHandler + def_irq_default_handler PORTE_IRQHandler + def_irq_default_handler SWI_IRQHandler + def_irq_default_handler SPI2_IRQHandler + def_irq_default_handler UART4_RX_TX_IRQHandler + def_irq_default_handler UART4_ERR_IRQHandler + def_irq_default_handler UART5_RX_TX_IRQHandler + def_irq_default_handler UART5_ERR_IRQHandler + def_irq_default_handler CMP2_IRQHandler + def_irq_default_handler FTM3_IRQHandler + def_irq_default_handler DAC1_IRQHandler + def_irq_default_handler ADC1_IRQHandler + def_irq_default_handler I2C2_IRQHandler + def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler + def_irq_default_handler CAN0_Bus_Off_IRQHandler + def_irq_default_handler CAN0_Error_IRQHandler + def_irq_default_handler CAN0_Tx_Warning_IRQHandler + def_irq_default_handler CAN0_Rx_Warning_IRQHandler + def_irq_default_handler CAN0_Wake_Up_IRQHandler + def_irq_default_handler SDHC_IRQHandler + def_irq_default_handler ENET_1588_Timer_IRQHandler + def_irq_default_handler ENET_Transmit_IRQHandler + def_irq_default_handler ENET_Receive_IRQHandler + def_irq_default_handler ENET_Error_IRQHandler + def_irq_default_handler DefaultISR + +/* Flash protection region, placed at 0x400 */ + .text + .thumb + .align 2 + .section .kinetis_flash_config_field,"a",%progbits +kinetis_flash_config: + .long 0xffffffff + .long 0xffffffff + .long 0xffffffff + .long 0xfffffffe + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s index 9d297079d5..5d5eae6e53 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s @@ -1,4 +1,4 @@ -/* KL25Z startup ARM GCC +/* KL46Z startup ARM GCC * Purpose: startup file for Cortex-M0 devices. Should use with * GCC for ARM Embedded Processors * Version: V1.2 @@ -134,8 +134,8 @@ __isr_vector: .section .text.Reset_Handler .thumb .thumb_func - .align 2 - .globl Reset_Handler + .align 2 + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Loop to copy data from read only memory to RAM. The ranges @@ -149,21 +149,21 @@ Reset_Handler: ldr r2, =__data_start__ ldr r3, =__data_end__ - subs r3, r2 + subs r3, r2 ble .Lflash_to_ram_loop_end movs r4, 0 .Lflash_to_ram_loop: ldr r0, [r1,r4] str r0, [r2,r4] - adds r4, 4 + adds r4, 4 cmp r4, r3 blt .Lflash_to_ram_loop .Lflash_to_ram_loop_end: - ldr r0, =SystemInit - blx r0 - ldr r0, =_start + ldr r0, =SystemInit + blx r0 + ldr r0, =_start bx r0 .pool .size Reset_Handler, . - Reset_Handler diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index c1c48deb52..49dffc099c 100644 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -42,7 +42,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('KL05Z', ('ARM', 'uARM', 'GCC_ARM')), ('KL25Z', ('ARM', 'GCC_ARM')), ('KL46Z', ('ARM', 'GCC_ARM')), - ('K64F', ('ARM',)), + ('K64F', ('ARM', 'GCC_ARM')), ('NUCLEO_F030R8', ('ARM', 'uARM')), ('NUCLEO_F072RB', ('ARM', 'uARM')), diff --git a/workspace_tools/export/gcc_arm_k64f.tmpl b/workspace_tools/export/gcc_arm_k64f.tmpl new file mode 100644 index 0000000000..037be828fb --- /dev/null +++ b/workspace_tools/export/gcc_arm_k64f.tmpl @@ -0,0 +1,52 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy + +CPU = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = -mcpu=cortex-m4 -mthumb -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(OBJECTS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + +$(PROJECT).bin: $(PROJECT).elf + $(OBJCOPY) -O binary $< $@ diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index b3c56cd5ca..88039c7305 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -27,6 +27,7 @@ class GccArm(Exporter): 'KL05Z', 'KL25Z', 'KL46Z', + 'K64F', 'K20D5M', 'LPC4088', 'LPC11U24', diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 3d598e3811..918209de87 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -173,7 +173,7 @@ class K64F(Target): self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM"] + self.supported_toolchains = ["ARM", "GCC_ARM"] self.supported_form_factors = ["ARDUINO"]