diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt b/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt index eb84b0db0e..3a8f706017 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt +++ b/targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt @@ -84,7 +84,6 @@ target_sources(mbed-max32670 ${MXM_SOURCE_DIR}/FLC/flc_common.c ${MXM_SOURCE_DIR}/FLC/flc_me15.c ${MXM_SOURCE_DIR}/FLC/flc_reva.c - ${MXM_SOURCE_DIR}/FLC/flc_revb.c ${MXM_SOURCE_DIR}/GPIO/gpio_common.c ${MXM_SOURCE_DIR}/GPIO/gpio_me15.c diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h index 340685942f..27beaf2547 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h @@ -69,9 +69,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h index 2490d2f7d5..1001144686 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h index a2ce912128..eeaa099973 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h index 76bb3c1b02..b642e9753a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h index b7ef2d7037..bbbbf146e5 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -99,7 +96,7 @@ typedef struct { typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ - __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t rsv_0x8_0xff[62]; __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h index 860bd7a9cc..f4921dcf2a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -86,7 +83,7 @@ extern "C" { * Structure type to access the ECC Registers. */ typedef struct { - __R uint32_t rsv_0x0_0x7[2]; + __I uint32_t rsv_0x0_0x7[2]; __IO uint32_t en; /**< \b 0x08: ECC EN Register */ } mxc_ecc_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h index 00aac74a70..6467f573e4 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h index 577042177a..6b84288a29 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -89,19 +86,19 @@ typedef struct { __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ - __R uint32_t rsv_0xc_0x23[6]; + __I uint32_t rsv_0xc_0x23[6]; __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ __IO uint32_t eccdata; /**< \b 0x028: FLC ECCDATA Register */ - __R uint32_t rsv_0x2c; + __I uint32_t rsv_0x2c; __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ - __R uint32_t rsv_0x44_0x7f[15]; + __I uint32_t rsv_0x44_0x7f[15]; __IO uint32_t welr0; /**< \b 0x80: FLC WELR0 Register */ - __R uint32_t rsv_0x84; + __I uint32_t rsv_0x84; __IO uint32_t welr1; /**< \b 0x88: FLC WELR1 Register */ - __R uint32_t rsv_0x8c; + __I uint32_t rsv_0x8c; __IO uint32_t rlr0; /**< \b 0x90: FLC RLR0 Register */ - __R uint32_t rsv_0x94; + __I uint32_t rsv_0x94; __IO uint32_t rlr1; /**< \b 0x98: FLC RLR1 Register */ } mxc_flc_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h index 504d040e3e..ebf419803d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -90,20 +87,20 @@ typedef struct { __IO uint32_t rst0; /**< \b 0x04: GCR RST0 Register */ __IO uint32_t clkctrl; /**< \b 0x08: GCR CLKCTRL Register */ __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ - __R uint32_t rsv_0x10_0x17[2]; + __I uint32_t rsv_0x10_0x17[2]; __IO uint32_t pclkdiv; /**< \b 0x18: GCR PCLKDIV Register */ - __R uint32_t rsv_0x1c_0x23[2]; + __I uint32_t rsv_0x1c_0x23[2]; __IO uint32_t pclkdis0; /**< \b 0x24: GCR PCLKDIS0 Register */ __IO uint32_t memctrl; /**< \b 0x28: GCR MEMCTRL Register */ __IO uint32_t memz; /**< \b 0x2C: GCR MEMZ Register */ - __R uint32_t rsv_0x30_0x3f[4]; + __I uint32_t rsv_0x30_0x3f[4]; __IO uint32_t sysst; /**< \b 0x40: GCR SYSST Register */ __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ __IO uint32_t pclkdis1; /**< \b 0x48: GCR PCLKDIS1 Register */ __IO uint32_t eventen; /**< \b 0x4C: GCR EVENTEN Register */ __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ __IO uint32_t sysie; /**< \b 0x54: GCR SYSIE Register */ - __R uint32_t rsv_0x58_0x63[3]; + __I uint32_t rsv_0x58_0x63[3]; __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ __IO uint32_t eccced; /**< \b 0x68: GCR ECCCED Register */ __IO uint32_t eccie; /**< \b 0x6C: GCR ECCIE Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h index 938bd7b0ce..04e630015e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -103,12 +100,12 @@ typedef struct { __IO uint32_t inten_set; /**< \b 0x38: GPIO INTEN_SET Register */ __IO uint32_t inten_clr; /**< \b 0x3C: GPIO INTEN_CLR Register */ __I uint32_t intfl; /**< \b 0x40: GPIO INTFL Register */ - __R uint32_t rsv_0x44; + __I uint32_t rsv_0x44; __IO uint32_t intfl_clr; /**< \b 0x48: GPIO INTFL_CLR Register */ __IO uint32_t wken; /**< \b 0x4C: GPIO WKEN Register */ __IO uint32_t wken_set; /**< \b 0x50: GPIO WKEN_SET Register */ __IO uint32_t wken_clr; /**< \b 0x54: GPIO WKEN_CLR Register */ - __R uint32_t rsv_0x58; + __I uint32_t rsv_0x58; __IO uint32_t dualedge; /**< \b 0x5C: GPIO DUALEDGE Register */ __IO uint32_t padctrl0; /**< \b 0x60: GPIO PADCTRL0 Register */ __IO uint32_t padctrl1; /**< \b 0x64: GPIO PADCTRL1 Register */ @@ -118,7 +115,7 @@ typedef struct { __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ - __R uint32_t rsv_0x80_0xa7[10]; + __I uint32_t rsv_0x80_0xa7[10]; __IO uint32_t hysen; /**< \b 0xA8: GPIO HYSEN Register */ __IO uint32_t srsel; /**< \b 0xAC: GPIO SRSEL Register */ __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h index 1016527968..ee812ddd3b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h index 0e1f5568a6..472a96f305 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -87,13 +84,13 @@ extern "C" { */ typedef struct { __IO uint32_t ctrl0ch0; /**< \b 0x00: I2S CTRL0CH0 Register */ - __R uint32_t rsv_0x4_0xf[3]; + __I uint32_t rsv_0x4_0xf[3]; __IO uint32_t ctrl1ch0; /**< \b 0x10: I2S CTRL1CH0 Register */ - __R uint32_t rsv_0x14_0x2f[7]; + __I uint32_t rsv_0x14_0x2f[7]; __IO uint32_t dmach0; /**< \b 0x30: I2S DMACH0 Register */ - __R uint32_t rsv_0x34_0x3f[3]; + __I uint32_t rsv_0x34_0x3f[3]; __IO uint32_t fifoch0; /**< \b 0x40: I2S FIFOCH0 Register */ - __R uint32_t rsv_0x44_0x4f[3]; + __I uint32_t rsv_0x44_0x4f[3]; __IO uint32_t intfl; /**< \b 0x50: I2S INTFL Register */ __IO uint32_t inten; /**< \b 0x54: I2S INTEN Register */ __IO uint32_t extsetup; /**< \b 0x58: I2S EXTSETUP Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h index 948c381d6e..d2051ec784 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -88,9 +85,9 @@ extern "C" { typedef struct { __I uint32_t info; /**< \b 0x0000: ICC INFO Register */ __I uint32_t sz; /**< \b 0x0004: ICC SZ Register */ - __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t rsv_0x8_0xff[62]; __IO uint32_t ctrl; /**< \b 0x0100: ICC CTRL Register */ - __R uint32_t rsv_0x104_0x6ff[383]; + __I uint32_t rsv_0x104_0x6ff[383]; __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ } mxc_icc_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h index f3685a2d82..e74b748e4c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h @@ -208,7 +208,7 @@ typedef enum { #define MXC_FLASH0_MEM_BASE 0x10000000UL #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE #define MXC_FLASH_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_MEM_SIZE 0x00060000UL +#define MXC_FLASH_MEM_SIZE (0x00060000UL - MXC_FLASH_PAGE_SIZE) #define MXC_INFO0_MEM_BASE 0x10800000UL #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE #define MXC_INFO_MEM_SIZE 0x00004000UL diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h index 6fc8dd792c..76d8ec0eaa 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -86,11 +83,11 @@ extern "C" { * Structure type to access the MCR Registers. */ typedef struct { - __R uint32_t rsv_0x0; + __I uint32_t rsv_0x0; __IO uint32_t rst; /**< \b 0x04: MCR RST Register */ - __R uint32_t rsv_0x8_0xf[2]; + __I uint32_t rsv_0x8_0xf[2]; __IO uint32_t lppioctrl; /**< \b 0x10: MCR LPPIOCTRL Register */ - __R uint32_t rsv_0x14_0x23[4]; + __I uint32_t rsv_0x14_0x23[4]; __IO uint32_t clkdis; /**< \b 0x24: MCR CLKDIS Register */ } mxc_mcr_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h index f38f09221c..03a4eab8e2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -91,12 +88,12 @@ typedef struct { __IO uint32_t lpwken0; /**< \b 0x08: PWRSEQ LPWKEN0 Register */ __IO uint32_t lpwkst1; /**< \b 0x0C: PWRSEQ LPWKST1 Register */ __IO uint32_t lpwken1; /**< \b 0x10: PWRSEQ LPWKEN1 Register */ - __R uint32_t rsv_0x14_0x2f[7]; + __I uint32_t rsv_0x14_0x2f[7]; __IO uint32_t lppwkst; /**< \b 0x30: PWRSEQ LPPWKST Register */ __IO uint32_t lppwken; /**< \b 0x34: PWRSEQ LPPWKEN Register */ - __R uint32_t rsv_0x38_0x3f[2]; + __I uint32_t rsv_0x38_0x3f[2]; __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ - __R uint32_t rsv_0x44; + __I uint32_t rsv_0x44; __IO uint32_t gp0; /**< \b 0x48: PWRSEQ GP0 Register */ __IO uint32_t gp1; /**< \b 0x4C: PWRSEQ GP1 Register */ } mxc_pwrseq_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h index 28b40c96c8..61699ec4b0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h index fe8542deb0..6fbb32a4be 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h index 69e7626f64..da60b36b47 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -96,7 +93,7 @@ typedef struct { __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ __IO uint32_t sstime; /**< \b 0x10: SPI SSTIME Register */ __IO uint32_t clkctrl; /**< \b 0x14: SPI CLKCTRL Register */ - __R uint32_t rsv_0x18; + __I uint32_t rsv_0x18; __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ __IO uint32_t intfl; /**< \b 0x20: SPI INTFL Register */ __IO uint32_t inten; /**< \b 0x24: SPI INTEN Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h index cd7ae193d7..5b0368f6be 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h index a13282e638..d7aeb41924 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h index 4683973311..5a5f534ed4 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -95,7 +92,7 @@ typedef struct { __IO uint32_t txpeek; /**< \b 0x0018: UART TXPEEK Register */ __IO uint32_t pnr; /**< \b 0x001C: UART PNR Register */ __IO uint32_t fifo; /**< \b 0x0020: UART FIFO Register */ - __R uint32_t rsv_0x24_0x2f[3]; + __I uint32_t rsv_0x24_0x2f[3]; __IO uint32_t dma; /**< \b 0x0030: UART DMA Register */ __IO uint32_t wken; /**< \b 0x0034: UART WKEN Register */ __IO uint32_t wkfl; /**< \b 0x0038: UART WKFL Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h index a91b015f50..3a23e1e576 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c index 9f0311cb16..ef6abfaabf 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c @@ -39,10 +39,6 @@ #include "pwrseq_regs.h" #include "mxc_sys.h" -extern void (*const __vector_table[])(void); - -extern void (*const __isr_vector[])(void); - uint32_t SystemCoreClock = HIRC_FREQ; __weak void SystemCoreClockUpdate(void) @@ -107,6 +103,12 @@ __weak int Board_Init(void) return 0; } +/* Override this function for early platform initialization */ +__weak void low_level_init(void) +{ + /* Do nothing */ +} + /* This function is called just before control is transferred to main(). * * You may over-ride this function in your program by defining a custom @@ -115,58 +117,24 @@ __weak int Board_Init(void) */ __weak void SystemInit(void) { - /* Configure the interrupt controller to use the application vector table in */ - /* the application space */ -#if defined(__CC_ARM) || defined(__GNUC__) - /* IAR sets the VTOR pointer incorrectly and causes stack corruption */ - SCB->VTOR = (uint32_t)__isr_vector; -#endif /* __CC_ARM || __GNUC__ */ - -#if defined __ICCARM__ - SCB->VTOR = (uint32_t)__vector_table; -#endif - /* Make sure interrupts are enabled. */ __enable_irq(); +#if (__FPU_PRESENT == 1) /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ /* Grant full access, per "Table B3-24 CPACR bit assignments". */ /* DDI0403D "ARMv7-M Architecture Reference Manual" */ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); +#endif /* Change system clock source to the main high-speed clock */ MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); SystemCoreClockUpdate(); - /* Make sure INRO is enabled. INRO should already be enabled during power up. */ - MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_INRO_EN; - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); - Board_Init(); + low_level_init(); } - -#if defined(__CC_ARM) -/* Global variable initialization does not occur until post scatterload in Keil tools.*/ - -/* External function called after our post scatterload function implementation. */ -extern void $Super$$__main_after_scatterload(void); - -/** - * @brief Initialization function for SystemCoreClock and Board_Init. - * @details $Sub$$__main_after_scatterload is called during system startup in the Keil - * toolset. Global variable and static variable space must be set up by the compiler - * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init - * require global memory for variable storage and are called from this function in - * the Keil tool chain. - */ -void $Sub$$__main_after_scatterload(void) -{ - SystemInit(); - $Super$$__main_after_scatterload(); - while (1) {} -} -#endif /* __CC_ARM */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h index 02b3139fdd..e7605103ec 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h @@ -203,18 +203,18 @@ void MXC_LP_ClearWakeStatus(void); * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. * Call this function multiple times to enable pins on multiple ports. This function does not configure * the GPIO pins nor does it setup their interrupt functionality. - * @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the - * structure are used. The func and pad fields are ignored. \ref mxc_gpio_cfg_t + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. */ -void MXC_LP_EnableGPIOWakeup(mxc_gpio_cfg_t *wu_pins); +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask); /** * @brief Disables the selected GPIO port and its selected pins as a wake up source. * Call this function multiple times to disable pins on multiple ports. - * @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the - * structure are used. The func and pad fields are ignored. \ref mxc_gpio_cfg_t + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. */ -void MXC_LP_DisableGPIOWakeup(mxc_gpio_cfg_t *wu_pins); +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask); /** * @brief Enables the RTC alarm to wake up the device from any low power mode. diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h index 697d61c248..4095f4a18a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h @@ -54,7 +54,9 @@ // Create a string definition for the TARGET #define STRING_ARG(arg) #arg #define STRING_NAME(name) STRING_ARG(name) +#if MBED_VERSION && MBED_VERSION < 51200 #define TARGET_NAME STRING_NAME(TARGET) +#endif // Define which revisions of the IP we are using #ifndef TARGET_REV diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h index 9cea8ff900..4e000f120f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h @@ -40,6 +40,9 @@ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32670_MXC_LOCK_H_ +// To enable disable this module +#define USE_LOCK_IN_DRIVERS 0 + /* **** Includes **** */ #include "mxc_device.h" @@ -47,6 +50,8 @@ extern "C" { #endif +#if USE_LOCK_IN_DRIVERS + /** * @ingroup syscfg * @defgroup mxc_lock_utilities Exclusive Access Locks @@ -84,6 +89,13 @@ void MXC_FreeLock(uint32_t *lock); /**@} end of group mxc_lock_utilities */ +#else // USE_LOCK_IN_DRIVERS + +#define MXC_GetLock(x, y) E_NO_ERROR +#define MXC_FreeLock(x) + +#endif // USE_LOCK_IN_DRIVERS + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h index 400f38aa35..be402cdd74 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h @@ -41,6 +41,8 @@ #include "gpio.h" +typedef enum { MAP_A, MAP_B, MAP_C } sys_map_t; + /***** Global Variables *****/ // Predefined GPIO Configurations extern const mxc_gpio_cfg_t gpio_cfg_lpextclk; @@ -51,15 +53,24 @@ extern const mxc_gpio_cfg_t gpio_cfg_i2c2; extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; -extern const mxc_gpio_cfg_t gpio_cfg_uart0; -extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; -extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable; -extern const mxc_gpio_cfg_t gpio_cfg_uart1; -extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; -extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable; -extern const mxc_gpio_cfg_t gpio_cfg_uart2; -extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow; -extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable; +extern const mxc_gpio_cfg_t gpio_cfg_uart0a; +extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow_disable; +extern const mxc_gpio_cfg_t gpio_cfg_uart0b; +extern const mxc_gpio_cfg_t gpio_cfg_uart0b_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart0b_flow_disable; + +extern const mxc_gpio_cfg_t gpio_cfg_uart1a; +extern const mxc_gpio_cfg_t gpio_cfg_uart1a_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart1a_flow_disable; +extern const mxc_gpio_cfg_t gpio_cfg_uart1b; +extern const mxc_gpio_cfg_t gpio_cfg_uart1b_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart1b_flow_disable; + +extern const mxc_gpio_cfg_t gpio_cfg_uart2b; +extern const mxc_gpio_cfg_t gpio_cfg_uart2b_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart2b_flow_disable; + extern const mxc_gpio_cfg_t gpio_cfg_uart3; extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h index 07616e435d..b20d52ff50 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h @@ -174,7 +174,7 @@ struct _mxc_spi_req_t { * \ref MXC_Error_Codes for a list of return codes. */ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz); + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); /** * @brief Disable and shutdown SPI peripheral. diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h index 454ee672bd..d26e94e0de 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h @@ -159,7 +159,7 @@ typedef struct { int in_critical; } mxc_crit_state_t; -static mxc_crit_state_t _state = { .ie_status = 0xFFFFFFFF, .in_critical = 0 }; +static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 }; static inline void _mxc_crit_get_state() { diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h index 08661d25c4..08a4f258e0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h @@ -166,7 +166,7 @@ struct _mxc_uart_req_t { * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map); /** * @brief Disable and shutdown UART peripheral. @@ -253,7 +253,7 @@ int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map); /** * @brief Sets the clock source for the baud rate generator diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h index 70beee7927..7d4cbf380d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h @@ -35,7 +35,7 @@ #define LIBRARIES_PERIPHDRIVERS_SOURCE_AES_AES_REVB_H_ #include -#include "aes.h" +#include "mxc_aes.h" #include "aes_revb_regs.h" #include "aeskeys_revb_regs.h" #include "trng_revb_regs.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h index 4b856a0e63..192aacb891 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h @@ -66,9 +66,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h index 58177947ea..e536e40d82 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aeskeys_revb_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c index ff85892cc5..93936835f2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c @@ -42,7 +42,7 @@ #include "mxc_delay.h" #include "i2c_regs.h" #include "dma_regs.h" -#include "i2c.h" +#include "mxc_i2c.h" #include "i2c_reva.h" /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index cf13776de6..eff201190b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -40,7 +40,7 @@ #include "mxc_sys.h" #include "mxc_delay.h" #include "i2c_regs.h" -#include "i2c.h" +#include "mxc_i2c.h" #include "i2c_reva.h" #include "dma.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c index 895b5cbbe1..74b3023a0c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c @@ -190,29 +190,29 @@ void MXC_LP_ClearWakeStatus(void) MXC_PWRSEQ->lppwkst = 0xFFFFFFFF; } -void MXC_LP_EnableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask) { MXC_GCR->pm |= MXC_F_GCR_PM_GPIO_WE; - switch (1 << MXC_GPIO_GET_IDX(wu_pins->port)) { + switch (1 << port) { case MXC_GPIO_PORT_0: - MXC_PWRSEQ->lpwken0 |= wu_pins->mask; + MXC_PWRSEQ->lpwken0 |= mask; break; case MXC_GPIO_PORT_1: - MXC_PWRSEQ->lpwken1 |= wu_pins->mask; + MXC_PWRSEQ->lpwken1 |= mask; } } -void MXC_LP_DisableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask) { - switch (1 << MXC_GPIO_GET_IDX(wu_pins->port)) { + switch (1 << port) { case MXC_GPIO_PORT_0: - MXC_PWRSEQ->lpwken0 &= ~wu_pins->mask; + MXC_PWRSEQ->lpwken0 &= ~mask; break; case MXC_GPIO_PORT_1: - MXC_PWRSEQ->lpwken1 &= ~wu_pins->mask; + MXC_PWRSEQ->lpwken1 &= ~mask; } if (MXC_PWRSEQ->lpwken1 == 0 && MXC_PWRSEQ->lpwken0 == 0) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c index a5a0a2bab5..b0909b2236 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c @@ -45,7 +45,7 @@ /* **** Functions **** */ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz) + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { int spi_num; @@ -81,7 +81,7 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS } return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves, - ssPolarity, hz); + ssPolarity, hz, drv_ssel); } int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index c7a9667341..2726ede611 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -40,7 +40,7 @@ #include "mxc_lock.h" #include "mxc_sys.h" #include "mxc_delay.h" -#include "spi.h" +#include "mxc_spi.h" #include "spi_reva.h" #include "dma_reva.h" @@ -58,6 +58,7 @@ typedef struct { bool txrx_req; uint8_t req_done; uint8_t async; + unsigned drv_ssel; } spi_req_reva_state_t; static spi_req_reva_state_t states[MXC_SPI_INSTANCES]; @@ -69,7 +70,7 @@ static void MXC_SPI_RevA_SwapByte(uint8_t *arr, size_t length); static int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req); int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz) + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { int spi_num; @@ -84,6 +85,7 @@ int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed states[spi_num].mtFirstTrans = 0; states[spi_num].channelTx = E_NO_DEVICE; states[spi_num].channelRx = E_NO_DEVICE; + states[spi_num].drv_ssel = drv_ssel; spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN); spi->sstime = @@ -109,22 +111,25 @@ int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed // Clear the interrupts spi->intfl = spi->intfl; - if (numSlaves == 1) { - spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; - } + // Driver will drive SS pin? + if (states[spi_num].drv_ssel) { + if (numSlaves == 1) { + spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; + } - if (numSlaves == 2) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); - } + else if (numSlaves == 2) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); + } - if (numSlaves == 3) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | - MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); - } + else if (numSlaves == 3) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); + } - if (numSlaves == 4) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + else if (numSlaves == 4) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); + } } //set quad mode @@ -364,12 +369,14 @@ int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx) MXC_ASSERT(spi_num >= 0); (void)spi_num; - // Setup the slave select - // Activate chosen SS pin - spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; - // Deactivate all unchosen pins - spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | - ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); + if (states[spi_num].drv_ssel) { + // Setup the slave select + // Activate chosen SS pin + spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; + // Deactivate all unchosen pins + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | + ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); + } return E_NO_ERROR; } @@ -823,8 +830,10 @@ uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_ spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); // Leave slave select asserted at the end of the transaction - if (!req->ssDeassert) { - spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + if (states[spi_num].drv_ssel) { + if (!req->ssDeassert) { + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } retval = MXC_SPI_RevA_TransHandler(spi, req); @@ -835,8 +844,10 @@ uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_ } // Deassert slave select at the end of the transaction - if (req->ssDeassert) { - spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + if (states[spi_num].drv_ssel) { + if (req->ssDeassert) { + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } return retval; diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h index bfc190d66a..6f46c8562d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h @@ -44,7 +44,7 @@ #include "mxc_delay.h" #include "spi_regs.h" #include "spi_reva_regs.h" -#include "spi.h" +#include "mxc_spi.h" #include "dma.h" #ifdef __cplusplus @@ -81,7 +81,7 @@ struct _mxc_spi_reva_req_t { }; int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz); + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi); int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi); int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz); diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c index 459df723f1..a28121d281 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -35,6 +35,8 @@ #include "mxc_device.h" #include "mxc_lock.h" +#if USE_LOCK_IN_DRIVERS + #ifndef __riscv /* ************************************************************************** */ int MXC_GetLock(uint32_t *lock, uint32_t value) @@ -75,3 +77,5 @@ void MXC_FreeLock(uint32_t *lock) #warning "Unimplemented for RISCV" } #endif + +#endif // USE_LOCK_IN_DRIVERS diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c index a01886e5cf..e2d09f3f00 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c @@ -57,30 +57,28 @@ const mxc_gpio_cfg_t gpio_cfg_i2c2 = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PI MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO }; -const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), - MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart1 = { MXC_GPIO0, (MXC_GPIO_PIN_28 | MXC_GPIO_PIN_29), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), - MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), - MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO0, (MXC_GPIO_PIN_26 | MXC_GPIO_PIN_27), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart3_flow = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), - MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0a = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0a_flow = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0a_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; + +const mxc_gpio_cfg_t gpio_cfg_uart0b = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0b_flow = { MXC_GPIO0, (MXC_GPIO_PIN_26 | MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0b_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_26 | MXC_GPIO_PIN_27), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; + +const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_28 | MXC_GPIO_PIN_29), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1a_flow = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1a_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; + +const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1b_flow = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1b_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; + +const mxc_gpio_cfg_t gpio_cfg_uart2b = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart2b_flow = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart2b_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO0, (MXC_GPIO_PIN_26 | MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart3_flow = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE }; const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), @@ -88,19 +86,24 @@ const mxc_gpio_cfg_t gpio_cfg_i2s0 = { }; const mxc_gpio_cfg_t gpio_cfg_spi0 = { - MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), + MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_5, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; + // NOTE: SPI1 definied here with SS0 only const mxc_gpio_cfg_t gpio_cfg_spi1 = { - MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), + MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1_ss = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; + // NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2 const mxc_gpio_cfg_t gpio_cfg_spi2 = { - MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), + MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi2_ss = { MXC_GPIO1, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; // Timers are only defined once, depending on package, each timer could be mapped to other pins const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c index 54790e9c20..c51784f240 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c @@ -166,7 +166,8 @@ void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg) #if TARGET_NUM == 32655 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002 tmr->ctrl1 &= ~(MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); #else - tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); + // on default disable timer gpio out + //tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); #endif // If configured as TIMER_16B then enable the interrupt and start the timer diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c index e6afb68ecd..85ef30db96 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/UART/uart_me15.c @@ -55,7 +55,7 @@ int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) return MXC_UART_RevB_AsyncStop((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map) { int retval; @@ -96,17 +96,25 @@ int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clo switch (MXC_UART_GET_IDX(uart)) { case 0: - MXC_GPIO_Config(&gpio_cfg_uart0); + if (map == MAP_B) { + MXC_GPIO_Config(&gpio_cfg_uart0b); + } else { + MXC_GPIO_Config(&gpio_cfg_uart0a); + } MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0); break; case 1: - MXC_GPIO_Config(&gpio_cfg_uart1); + if (map == MAP_B) { + MXC_GPIO_Config(&gpio_cfg_uart1b); + } else { + MXC_GPIO_Config(&gpio_cfg_uart1a); + } MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART1); break; case 2: - MXC_GPIO_Config(&gpio_cfg_uart2); + MXC_GPIO_Config(&gpio_cfg_uart2b); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART2); break; @@ -285,20 +293,28 @@ int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) return MXC_UART_RevB_SetParity((mxc_uart_revb_regs_t *)uart, parity); } -int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map) { if (flowCtrl == MXC_UART_FLOW_EN) { switch (MXC_UART_GET_IDX(uart)) { case 0: - MXC_GPIO_Config(&gpio_cfg_uart0_flow); + if (map == MAP_B) { + MXC_GPIO_Config(&gpio_cfg_uart0b_flow); + } else { + MXC_GPIO_Config(&gpio_cfg_uart0a_flow); + } break; case 1: - MXC_GPIO_Config(&gpio_cfg_uart1_flow); + if (map == MAP_B) { + MXC_GPIO_Config(&gpio_cfg_uart1b_flow); + } else { + MXC_GPIO_Config(&gpio_cfg_uart1a_flow); + } break; case 2: - MXC_GPIO_Config(&gpio_cfg_uart2_flow); + MXC_GPIO_Config(&gpio_cfg_uart2b_flow); break; case 3: @@ -311,15 +327,23 @@ int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rt } else { switch (MXC_UART_GET_IDX(uart)) { case 0: - MXC_GPIO_Config(&gpio_cfg_uart0_flow_disable); + if (map == MAP_B) { + MXC_GPIO_Config(&gpio_cfg_uart0b_flow_disable); + } else { + MXC_GPIO_Config(&gpio_cfg_uart0a_flow_disable); + } break; case 1: - MXC_GPIO_Config(&gpio_cfg_uart1_flow_disable); + if (map == MAP_B) { + MXC_GPIO_Config(&gpio_cfg_uart1b_flow_disable); + } else { + MXC_GPIO_Config(&gpio_cfg_uart1a_flow_disable); + } break; case 2: - MXC_GPIO_Config(&gpio_cfg_uart2_flow_disable); + MXC_GPIO_Config(&gpio_cfg_uart2b_flow_disable); break; case 3: