From 2c88a8314a27166179d335eaf25d9f622ea7b7e5 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 14 May 2018 11:30:34 +0100 Subject: [PATCH 01/11] FastModels: add a new parent platform ARM_FM create a new platform folder TARGET_ARM_FM add general drivers files for FVP_MPS2 --- .../TARGET_FVP_MPS2/PeripheralNames.h | 91 +++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h | 243 ++++++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/PortNames.h | 31 + .../TARGET_FVP_MPS2/SDK/ETH_MPS2.c | 450 +++++++++++++++ .../TARGET_FVP_MPS2/SDK/ETH_MPS2.h | 65 +++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c | 90 +++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.h | 34 ++ .../TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c | 166 ++++++ .../TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h | 57 ++ .../TARGET_FVP_MPS2/analogin_api.c | 110 ++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/device.h | 43 ++ .../TARGET_FVP_MPS2/ethernet_api.c | 164 ++++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c | 140 +++++ .../TARGET_FVP_MPS2/gpio_irq_api.c | 241 ++++++++ .../TARGET_FVP_MPS2/gpio_object.h | 55 ++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c | 533 ++++++++++++++++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h | 82 +++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/pinmap.c | 28 + .../TARGET_ARM_FM/TARGET_FVP_MPS2/port_api.c | 68 +++ .../TARGET_FVP_MPS2/serial_api.c | 369 ++++++++++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c | 301 ++++++++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h | 174 ++++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c | 83 +++ targets/TARGET_ARM_FM/mbed_rtx.h | 28 + 24 files changed, 3646 insertions(+) create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PortNames.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/pinmap.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/port_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c create mode 100644 targets/TARGET_ARM_FM/mbed_rtx.h diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h new file mode 100644 index 0000000000..9c07b3bfa4 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)CMSDK_UART0_BASE, + UART_1 = (int)CMSDK_UART1_BASE, + UART_2 = (int)CMSDK_UART3_BASE, + UART_3 = (int)CMSDK_UART4_BASE +} UARTName; + +typedef enum { + I2C_0 = (int)MPS2_TSC_I2C_BASE, + I2C_1 = (int)MPS2_AAIC_I2C_BASE, + I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, + I2C_3 = (int)MPS2_SHIELD1_I2C_BASE + +} I2CName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7, + ADC0_8, + ADC0_9, + ADC0_10, + ADC0_11 +} ADCName; + +typedef enum { + SPI_0 = (int)MPS2_SSP1_BASE, + SPI_1 = (int)MPS2_SSP0_BASE, + SPI_2 = (int)MPS2_SSP2_BASE, + SPI_3 = (int)MPS2_SSP3_BASE, + SPI_4 = (int)MPS2_SSP4_BASE +} SPIName; + +typedef enum { + PWM_1 = 0, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11 +} PWMName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +#define MBED_UART0 USBTX, USBRX +#define MBED_UART1 XB_TX, XB_RX +#define MBED_UART2 SH0_TX, SH0_RX +#define MBED_UART3 SH1_TX, SH1_RX +#define MBED_UARTUSB USBTX, USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h new file mode 100644 index 0000000000..6dedbd7d42 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h @@ -0,0 +1,243 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // MPS2 EXP Pin Names + EXP0 = 0, + EXP1 = 1, + EXP2 = 2, + EXP3 = 3, + EXP4 = 4, + EXP5 = 5, + EXP6 = 6, + EXP7 = 7, + EXP8 = 8, + EXP9 = 9, + EXP10 = 10, + EXP11 = 11, + EXP12 = 12, + EXP13 = 13, + EXP14 = 14, + EXP15 = 15, + EXP16 = 16, + EXP17 = 17, + EXP18 = 18, + EXP19 = 19, + EXP20 = 20, + EXP21 = 21, + EXP22 = 22, + EXP23 = 23, + EXP24 = 24, + EXP25 = 25, + + EXP26 = 26, + EXP27 = 27, + EXP28 = 28, + EXP29 = 29, + EXP30 = 30, + EXP31 = 31, + EXP32 = 32, + EXP33 = 33, + EXP34 = 34, + EXP35 = 35, + EXP36 = 36, + EXP37 = 37, + EXP38 = 38, + EXP39 = 39, + EXP40 = 40, + EXP41 = 41, + EXP42 = 42, + EXP43 = 43, + EXP44 = 44, + EXP45 = 45, + EXP46 = 46, + EXP47 = 47, + EXP48 = 48, + EXP49 = 49, + EXP50 = 50, + EXP51 = 51, + +// Other mbed Pin Names + + //LEDs on mps2 + //user leds + USERLED1 = 100, + USERLED2 = 101, + //user switches + USERSW1 = 110, + USERSW2 = 111, + + //mcc leds + LED1 = 200, + LED2 = 201, + LED3 = 202, + LED4 = 203, + LED5 = 204, + LED6 = 205, + LED7 = 206, + LED8 = 207, + + //MCC Switches + SW1 = 210, + SW2 = 211, + SW3 = 212, + SW4 = 213, + SW5 = 214, + SW6 = 215, + SW7 = 216, + SW8 = 217, + + //MPS2 SPI header pins j21 + MOSI_SPI = 300, + MISO_SPI = 301, + SCLK_SPI = 302, + SSEL_SPI = 303, + + //MPS2 CLCD SPI + CLCD_MOSI = 304, + CLCD_MISO = 305, + CLCD_SCLK = 306, + CLCD_SSEL = 307, + CLCD_RESET = 308, + CLCD_RS = 309, + CLCD_RD = 310, + CLCD_BL_CTRL = 311, + + //MPS2 shield 0 SPI + SHIELD_0_SPI_SCK = 320, + SHIELD_0_SPI_MOSI = 321, + SHIELD_0_SPI_MISO = 322, + SHIELD_0_SPI_nCS = 323, + + //MPS2 shield 1 SPI + SHIELD_1_SPI_SCK = 331, + SHIELD_1_SPI_MOSI = 332, + SHIELD_1_SPI_MISO = 333, + SHIELD_1_SPI_nCS = 334, + + //MPS2 shield ADC SPI + ADC_MOSI = 650, + ADC_MISO = 651, + ADC_SCLK = 652, + ADC_SSEL = 653, + + //MPS2 Uart + USBTX = 400, + USBRX = 401, + XB_TX = 402, + XB_RX = 403, + UART_TX2 = 404, + UART_RX2 = 405, + SH0_TX = 406, + SH0_RX = 407, + SH1_TX = 408, + SH1_RX = 409, + + //MPS2 I2C touchscreen and audio + TSC_SDA = 500, + TSC_SCL = 501, + AUD_SDA = 502, + AUD_SCL = 503, + + //MPS2 I2C for shield + SHIELD_0_SDA = 504, + SHIELD_0_SCL = 505, + SHIELD_1_SDA = 506, + SHIELD_1_SCL = 507, + + //MPS2 shield Analog pins + A0_0 = 600, + A0_1 = 601, + A0_2 = 602, + A0_3 = 603, + A0_4 = 604, + A0_5 = 605, + A1_0 = 606, + A1_1 = 607, + A1_2 = 608, + A1_3 = 609, + A1_4 = 610, + A1_5 = 611, + //MPS2 Shield Digital pins + D0_0 = EXP0, + D0_1 = EXP4, + D0_2 = EXP2, + D0_3 = EXP3, + D0_4 = EXP1, + D0_5 = EXP6, + D0_6 = EXP7, + D0_7 = EXP8, + D0_8 = EXP9, + D0_9 = EXP10, + D0_10 = EXP12, + D0_11 = EXP13, + D0_12 = EXP14, + D0_13 = EXP11, + D0_14 = EXP15, + D0_15 = EXP5, + + D1_0 = EXP26, + D1_1 = EXP30, + D1_2 = EXP28, + D1_3 = EXP29, + D1_4 = EXP27, + D1_5 = EXP32, + D1_6 = EXP33, + D1_7 = EXP34, + D1_8 = EXP35, + D1_9 = EXP36, + D1_10 = EXP38, + D1_11 = EXP39, + D1_12 = EXP40, + D1_13 = EXP44, + D1_14 = EXP41, + D1_15 = EXP31, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PortNames.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PortNames.h new file mode 100644 index 0000000000..adb25a9ade --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PortNames.h @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c new file mode 100644 index 0000000000..9c8fc46bb7 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c @@ -0,0 +1,450 @@ +/* MPS2 Peripheral Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*/ + +/* + * Code implementation file for the LAN Ethernet interface. + */ + +#include +#include "mbed_wait_api.h" +#include "ETH_MPS2.h" + +// SMSC9220 low-level operations +unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) +{ + unsigned int val, maccmd; + int timedout; + int error; + + error = 0; + val = SMSC9220->MAC_CSR_CMD; + if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation + maccmd = 0; + maccmd |= regoffset; + maccmd |= ((unsigned int)1 << 30); // Indicates read + maccmd |= ((unsigned int)1 << 31); // Start bit + SMSC9220->MAC_CSR_CMD = maccmd; // Start operation + + timedout = 50; + do { + val = SMSC9220->BYTE_TEST; // A no-op read. + wait_ms(1); + timedout--; + } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); + + if(!timedout) { + error = 1; + } + else + *data = SMSC9220->MAC_CSR_DATA; + } else { + *data = 0; + } + return error; +} + +unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data) +{ + unsigned int read, maccmd; + int timedout; + int error; + + error = 0; + read = SMSC9220->MAC_CSR_CMD; + if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation + SMSC9220->MAC_CSR_DATA = data; // Store data. + maccmd = 0; + maccmd |= regoffset; + maccmd &= ~((unsigned int)1 << 30); // Clear indicates write + maccmd |= ((unsigned int)1 << 31); // Indicate start of operation + SMSC9220->MAC_CSR_CMD = maccmd; + + timedout = 50; + do { + read = SMSC9220->BYTE_TEST; // A no-op read. + wait_ms(1); + timedout--; + } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); + + if(!timedout) { + error = 1; + } + } else { + printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n"); + } + return error; +} + +unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) +{ + unsigned int val, phycmd; int error; + int timedout; + + error = 0; + + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); + + if(!(val & 1)) { // Not busy + phycmd = 0; + phycmd |= (1 << 11); // 1 to [15:11] + phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] + phycmd &= ~(1 << 1); // Clear [1] indicates read. + phycmd |= (1 << 0); // Set [0] indicates operation start + + smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); + + val = 0; + timedout = 50; + do { + wait_ms(1); + timedout--; + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val); + } while(timedout && (val & ((unsigned int)1 << 0))); + + if(!timedout) { + error = 1; + } + else + smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data); + + } else { + *data = 0; + } + return error; +} + +unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) +{ + unsigned int val, phycmd; int error; + int timedout; + + error = 0; + + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); + + if(!(val & 1)) { // Not busy + smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data + phycmd = 0; + phycmd |= (1 << 11); // 1 to [15:11] + phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] + phycmd |= (1 << 1); // Set [1] indicates write. + phycmd |= (1 << 0); // Set [0] indicates operation start + smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); // Start operation + + phycmd = 0; + timedout = 50; + + do { + + wait_ms(1); + timedout--; + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd); + } while(timedout && (phycmd & (1 << 0))); + + if(!timedout) { + error = 1; + } + + } else { + printf("Warning: SMSC9220 MAC MII is busy. No data written.\n"); + } + return error; +} + +// Returns smsc9220 id. +unsigned int smsc9220_read_id(void) +{ + return SMSC9220->ID_REV; +} + +// Initiates a soft reset, returns failure or success. +unsigned int smsc9220_soft_reset(void) +{ + int timedout; + + timedout = 10; + // Soft reset + SMSC9220->HW_CFG |= 1; + + do { + wait_ms(1); + timedout--; + } while(timedout && (SMSC9220->HW_CFG & 1)); + + if(!timedout) + return 1; + + return 0; +} + +void smsc9220_set_txfifo(unsigned int val) +{ + // 2kb minimum, 14kb maximum + if(val < 2 || val > 14) + return; + + SMSC9220->HW_CFG = val << 16; +} + + +unsigned int smsc9220_wait_eeprom(void) +{ + int timedout; + + timedout = 50; + + do { + wait_ms(1); + timedout--; + + } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); + + if(!timedout) + return 1; + + return 0; +} + +/* initialise irqs */ +void smsc9220_init_irqs(void) +{ + SMSC9220->INT_EN = 0x0; + SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts + SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable. +} + +unsigned int smsc9220_check_phy(void) +{ + unsigned short phyid1, phyid2; + + smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1); + smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2); + return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || + (phyid1 == 0x0 && phyid2 == 0x0)); +} + +unsigned int smsc9220_reset_phy(void) +{ + unsigned short read; + int error; + + error = 0; + if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { + error = 1; + return error; + } + + read |= (1 << 15); + if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { + error = 1; + return error; + } + return 0; +} + +/* Advertise all speeds and pause capabilities */ +void smsc9220_advertise_cap(void) +{ + unsigned short aneg_adv; + aneg_adv = 0; + + + smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); + aneg_adv |= 0xDE0; + + smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv); + smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); + return; +} + +void smsc9220_establish_link(void) +{ + unsigned short bcr; + + smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); + bcr |= (1 << 12) | (1 << 9); + smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr); + smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); + + { + unsigned int hw_cfg; + + hw_cfg = 0; + hw_cfg = SMSC9220->HW_CFG; + + hw_cfg &= 0xF0000; + hw_cfg |= (1 << 20); + SMSC9220->HW_CFG = hw_cfg; + } + + return; +} + +void smsc9220_enable_xmit(void) +{ + SMSC9220->TX_CFG = 0x2; // Enable trasmission + return; +} + +void smsc9220_enable_mac_xmit(void) +{ + unsigned int mac_cr; + + mac_cr = 0; + smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); + + mac_cr |= (1 << 3); // xmit enable + mac_cr |= (1 << 28); // Heartbeat disable + + smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); + return; +} + +void smsc9220_enable_mac_recv(void) +{ + unsigned int mac_cr; + + mac_cr = 0; + smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); + mac_cr |= (1 << 2); // Recv enable + smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); + + return; +} + + +unsigned int smsc9220_check_ready(void) +{ + return !(SMSC9220->PMT_CTRL & 1); +} + +/* Generate a soft irq */ +void smsc9220_set_soft_int(void) +{ + SMSC9220->INT_EN |= 0x80000000; +} + +/* clear soft irq */ +void smsc9220_clear_soft_int(void) +{ + SMSC9220->INT_STS |= 0x80000000; +} + + +unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) +{ + unsigned int rxfifo_inf; // Tells us the status of rx payload and status fifos. + unsigned int rxfifo_stat; + + unsigned int pktsize; + unsigned int dwords_to_read; + + rxfifo_inf = SMSC9220->RX_FIFO_INF; + + if(rxfifo_inf & 0xFFFF) { // If there's data + rxfifo_stat = SMSC9220->RX_STAT_PORT; + if(rxfifo_stat != 0) { // Fetch status of this packet + pktsize = ((rxfifo_stat >> 16) & 0x3FFF); + if(rxfifo_stat & (1 << 15)) { + printf("Error occured during receiving of packets on the bus.\n"); + return 1; + } else { + /* Below formula (recommended by SMSC9220 code) + * gives 1 more than required. This is perhaps because + * a last word is needed for not word aligned packets. + */ + dwords_to_read = (pktsize + 3) >> 2; + // PIO copy of data received: + while(dwords_to_read > 0) { + recvbuf[*index] = SMSC9220->RX_DATA_PORT; + (*index)++; + dwords_to_read--; + } + } + } else { + return 1; + } + } else { + return 1; + } + + rxfifo_stat = SMSC9220->RX_STAT_PORT; + rxfifo_inf = SMSC9220->RX_FIFO_INF; + + return 0; +} + + +// Does the actual transfer of data to FIFO, note it does no +// fifo availability checking. This should be done by caller. +// Assumes the whole frame is transferred at once as a single segment +void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length) +{ + unsigned int txcmd_a, txcmd_b; + unsigned int dwords_to_write; + volatile unsigned int dwritten; + unsigned int *pktptr; + volatile unsigned int xmit_stat, xmit_stat2, xmit_inf; + int i; + + pktptr = (unsigned int *) pkt; + txcmd_a = 0; + txcmd_b = 0; + + txcmd_a |= (1 << 12) | (1 << 13); // First and last segments + txcmd_a |= length & 0x7FF; // [10:0] contains length + + txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length + txcmd_b |= length & 0x7FF; // [10:0] also contains length + + + SMSC9220->TX_DATA_PORT = txcmd_a; + SMSC9220->TX_DATA_PORT = txcmd_b; + dwritten = dwords_to_write = (length + 3) >> 2; + + // PIO Copy to FIFO. Could replace this with DMA. + while(dwords_to_write > 0) { + SMSC9220->TX_DATA_PORT = *pktptr; + pktptr++; + dwords_to_write--; + } + + xmit_stat = SMSC9220->TX_STAT_PORT; + xmit_stat2 = SMSC9220->TX_STAT_PORT; + xmit_inf = SMSC9220->TX_FIFO_INF; + + if(xmit_stat2 != 0 ) { + for(i = 0; i < 6; i++) { + xmit_stat2 = SMSC9220->TX_STAT_PORT; + } + } +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h new file mode 100644 index 0000000000..a4f514c80b --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h @@ -0,0 +1,65 @@ +/* MPS2 Peripheral Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _ETH_MPS2_H_ +#define _ETH_MPS2_H_ + +#include "SMM_MPS2.h" + +// Function declarations + +unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data); +unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data); +unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data); +unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data); + +unsigned int smsc9220_read_id(void); +unsigned int smsc9220_soft_reset(void); +void smsc9220_set_txfifo(unsigned int val); +unsigned int smsc9220_wait_eeprom(void); +void smsc9220_init_irqs(void); +unsigned int smsc9220_check_phy(void); +unsigned int smsc9220_reset_phy(void); + +void smsc9220_advertise_cap(void); +void smsc9220_establish_link(void); +void smsc9220_enable_xmit(void); +void smsc9220_enable_mac_xmit(void); +void smsc9220_enable_mac_recv(void); +unsigned int smsc9220_check_ready(void); +void smsc9220_set_soft_int(void); +void smsc9220_clear_soft_int(void); + +unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index); +void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length); + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c new file mode 100644 index 0000000000..6a07e98dcb --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ---------------------------------------------------------------- + * File: fpga.c + * Release: Version 1.0 + * ---------------------------------------------------------------- + */ + +/* + * Code implementation file for the fpga functions. + */ + +#include "SMM_MPS2.h" // MPS2 common header + +// Function to delay n*ticks (25MHz = 40nS per tick) +// Used for I2C drivers +void i2c_delay(unsigned int tick) +{ + unsigned int end; + unsigned int start; + + start = MPS2_FPGAIO->COUNTER; + end = start + (tick); + + if(end >= start) + { + while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); + } + else + { + while (MPS2_FPGAIO->COUNTER >= start); + while (MPS2_FPGAIO->COUNTER < end); + } +} + +/* Sleep function to delay n*mS + * Uses FPGA counter. + */ +void Sleepms(unsigned int msec) +{ + unsigned int end; + unsigned int start; + + start = MPS2_FPGAIO->COUNTER; + end = start + (25 * msec * 1000); + + if(end >= start) + { + while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); + } + else + { + while (MPS2_FPGAIO->COUNTER >= start); + while (MPS2_FPGAIO->COUNTER < end); + } +} + +/* Sleep function to delay n*uS + */ +void Sleepus(unsigned int usec) +{ + unsigned int end; + unsigned int start; + + start = MPS2_FPGAIO->COUNTER; + end = start + (25 * usec); + + if(end >= start) + { + while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); + } + else + { + while (MPS2_FPGAIO->COUNTER >= start); + while (MPS2_FPGAIO->COUNTER < end); + } +} + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.h new file mode 100644 index 0000000000..37a75717d0 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.h @@ -0,0 +1,34 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Code implementation file for the fpga functions. + */ + +#include "SMM_MPS2.h" // MPS2 common header + +// Function to delay n*ticks (25MHz = 40nS per tick) +// Used for I2C drivers +void i2c_delay(unsigned int tick); + +/* Sleep function to delay n*mS + * Uses FPGA counter. + */ +void Sleepms(unsigned int msec); + +/* Sleep function to delay n*uS + */ +void Sleepus(unsigned int usec); diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c new file mode 100644 index 0000000000..47a7ed1019 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c @@ -0,0 +1,166 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "mps2_ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "mbed_toolchain.h" +#include "mbed_error.h" +#include "ETH_MPS2.h" +#include "mbed_wait_api.h" + +#define TX_PKT_SIZE 256 +#define RX_PKT_SIZE 300 + +// Types +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 + + +int smsc9220_check_id(void) +{ + int error; + unsigned int id; + error = 0; + + id = smsc9220_read_id(); + + // If bottom and top halves of the word are the same + if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { + error = 1; + return error; + } + switch(((id >> 16) & 0xFFFF)) { + case 0x9220: + break; + + default: + error = 1; + break; + } + + return error; +} + +int smsc9220_check_macaddress(void) +{ + int error; + const unsigned int mac_valid_high = 0xC00A; + const unsigned int mac_valid_low = 0x00F70200; + unsigned int mac_low; + unsigned int mac_high; + + error = 0; + + // Read current mac address. + smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); + smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); + + // Writing temporary address: + smsc9220_mac_regwrite(SMSC9220_MAC_ADDRH, mac_valid_high); + smsc9220_mac_regwrite(SMSC9220_MAC_ADDRL, mac_valid_low); + + // Verify write was correct: + smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); + smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); + + + if(mac_high != mac_valid_high || mac_low != mac_valid_low) { + error = TRUE; + return error; + } + + return error; +} + +void smsc9220_print_mac_registers() +{ + unsigned int read; + int i; + + i = 0; + read = 0; + + for(i = 1; i <= 0xC; i++) { + smsc9220_mac_regread(i, &read); + } + return; +} + + +void smsc9220_print_phy_registers() +{ + unsigned short read; + unsigned int i; + + i = 0; + read = 0; + for(i = 0; i <= 6; i++) { + smsc9220_phy_regread(i, &read); + } + smsc9220_phy_regread(i = 17, &read); + + smsc9220_phy_regread(i = 18, &read); + + smsc9220_phy_regread(i = 27, &read); + + smsc9220_phy_regread(i = 29, &read); + + smsc9220_phy_regread(i = 30, &read); + + smsc9220_phy_regread(i = 31, &read); + + return; +} + +/*---------------------------------------------------------------------------- + Ethernet Device initialize + *----------------------------------------------------------------------------*/ + +int ethernet_transmission(unsigned char * pkt, unsigned int length) +{ + smsc9220_xmit_packet(pkt, length); + return 0; +} + +int ethernet_reception(unsigned int *recvbuf, unsigned int *index) +{ + return smsc9220_recv_packet((unsigned int *)recvbuf, index); +} + +int ethernet_mac_address(char *mac) +{ + return smsc9220_check_macaddress(); +} + +unsigned int ethernet_check_ready(void) +{ + return smsc9220_check_ready(); +} + +unsigned int ethernet_intf() +{ + unsigned int txfifo_inf; + + txfifo_inf = SMSC9220->TX_FIFO_INF; + + return txfifo_inf; + +} + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h new file mode 100644 index 0000000000..b5fff1763e --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MPS2_ETHERNET_API_H +#define MPS2_ETHERNET_API_H + +#include "device.h" + +#if DEVICE_ETHERNET + +#ifdef __cplusplus +extern "C" { +#endif + +// Connection constants + +// send ethernet write buffer, returning the packet size sent +int ethernet_transmission(unsigned char * pkt, unsigned int length); + +// recieve from ethernet buffer, returning packet size, or 0 if no packet +int ethernet_reception(unsigned int *recvbuf, unsigned int *index); + +// get the ethernet address +int ethernet_mac_address(char *mac); + +unsigned int ethernet_check_ready(void); + +unsigned int ethernet_intf(void); + +int smsc9220_check_id(void); + +int smsc9220_check_macaddress(void); + +void smsc9220_print_mac_registers(void); +void smsc9220_print_phy_registers(void); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c new file mode 100644 index 0000000000..9df01717c8 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#include "cmsis.h" +#include "pinmap.h" + +#define ADC_12BIT_RANGE 0xFFF + +static const PinMap PinMap_ADC[] = { + {A0_0, ADC0_0, 0}, + {A0_1, ADC0_1, 0}, + {A0_2, ADC0_2, 0}, + {A0_3, ADC0_3, 0}, + {A0_4, ADC0_4, 0}, + {A0_5, ADC0_5, 0}, + {A1_0, ADC0_6, 0}, + {A1_1, ADC0_7, 0}, + {A1_2, ADC0_8, 0}, + {A1_3, ADC0_9, 0}, + {A1_4, ADC0_10, 0}, + {A1_5, ADC0_11, 0}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SCLK[] = { + {ADC_SCLK , SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {ADC_MOSI, SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {ADC_MISO, SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {ADC_SSEL, SPI_3, 0}, + {NC , NC , 0} +}; + +#define ADC_RANGE ADC_12BIT_RANGE +int analog_spi_inited = 0; + +void analogin_init(analogin_t *obj, PinName pin) { + + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + obj->pin = pin; + obj->pin_number = pin-600; + obj->address = (0x0000 | (pin-600)); + + SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI); + SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO); + SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK); + SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL); + SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso); + SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel); + obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl); + + if(analog_spi_inited == 0){ + obj->adc_spi->CR1 = 0; + obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16; + obj->adc_spi->CPSR = SSP_CPSR_DFLT; + obj->adc_spi->IMSC = 0x8; + obj->adc_spi->DMACR = 0; + obj->adc_spi->CR1 = SSP_CR1_SSE_Msk; + obj->adc_spi->ICR = 0x3; + analog_spi_inited = 1; + } + + pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI); + pinmap_pinout(ADC_MISO, PinMap_SPI_MISO); + pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK); + pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL); + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + return 0; +} + + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read(obj); + return 0; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + return 0; +} + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h new file mode 100644 index 0000000000..b38cfffcf7 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. + + #ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c new file mode 100644 index 0000000000..401c3bcdad --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c @@ -0,0 +1,164 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "ethernet_api.h" +#include "mps2_ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "mbed_toolchain.h" +#include "mbed_error.h" +#include "ETH_MPS2.h" +#include "mbed_wait_api.h" + +#define TX_PKT_SIZE 256 +#define RX_PKT_SIZE 300 + +// Types +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 + +/*---------------------------------------------------------------------------- + Ethernet Device initialize + *----------------------------------------------------------------------------*/ +int ethernet_init() +{ + int error; + error = 0; + + if(smsc9220_check_id()) { + error = TRUE; + } + + if(smsc9220_soft_reset()) { + error = TRUE; + } + + smsc9220_set_txfifo(5); + + // Sets automatic flow control thresholds, and backpressure + // threshold to defaults specified. + SMSC9220->AFC_CFG = 0x006E3740; + + if(smsc9220_wait_eeprom()) { + error = TRUE; + } + + // Configure GPIOs as LED outputs. + SMSC9220->GPIO_CFG = 0x70070000; + + smsc9220_init_irqs(); + + /* Configure MAC addresses here if needed. */ + + if(smsc9220_check_phy()) { + error = TRUE; + } + + if(smsc9220_reset_phy()) { + error = TRUE; + return error; + } + + wait_ms(100); + // Checking whether phy reset completed successfully. + { + unsigned short phyreset; + phyreset = 0; + smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); + if(phyreset & (1 << 15)) { + error = TRUE; + return error; + } + } + + /* Advertise capabilities */ + smsc9220_advertise_cap(); + + + /* Begin to establish link */ + smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing. + // Although it's not so in the manual. + + /* Interrupt threshold */ + SMSC9220->FIFO_INT = 0xFF000000; + + smsc9220_enable_mac_xmit(); + + smsc9220_enable_xmit(); + + SMSC9220->RX_CFG = 0; + + smsc9220_enable_mac_recv(); + + // Rx status FIFO level irq threshold + SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles + + // This sleep is compulsory otherwise txmit/receive will fail. + wait_ms(2000); + return error; + +} + +/*---------------------------------------------------------------------------- + Ethernet Device Uninitialize + *----------------------------------------------------------------------------*/ +void ethernet_free() { +} + +int ethernet_write(const char *data, int size) +{ + return 0; +} + +int ethernet_send() +{ + return 0; +} + +int ethernet_receive() +{ + return 0; +} + +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is +// possible to read bytes from this packet. +// Read will write up to size bytes into data. +// It is possible to use read multible times. +// Each time read will start reading after the last read byte before. + +int ethernet_read(char *data, int dlen) +{ + return 0; +} + +void ethernet_address(char *mac) { + mbed_mac_address(mac); +} + +int ethernet_link(void) +{ + return 0; +} + +void ethernet_set_link(int speed, int duplex) +{ + smsc9220_establish_link(); +} + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c new file mode 100644 index 0000000000..96e905d560 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c @@ -0,0 +1,140 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" + +// function to enable the GPIO pin +uint32_t gpio_set(PinName pin) { + return (1); +} + +//function to initialise the gpio pin +// this links the board control bits for each pin +// with the object created for the pin +void gpio_init(gpio_t *obj, PinName pin) { + if(pin == NC){ return;} + else { + int pin_value = 0; + obj->pin = pin; + if(pin <=15){ + pin_value = pin; + }else if (pin >= 16 && pin <= 31){ + pin_value = pin-16; + }else if (pin >= 32 && pin <= 47){ + pin_value = pin-32; + }else if (pin >= 48 && pin <= 51){ + pin_value = pin-48; + }else if (pin == 100 || pin == 101){ + pin_value = pin-100; + }else if (pin == 110 || pin == 111){ + pin_value = pin-110; + }else if (pin >= 200 && pin <= 207){ + pin_value = pin-200; + }else if (pin >= 210 && pin <= 217){ + pin_value = pin-210; + }else if (pin == 303){ + pin_value = pin-302; + }else if (pin == 307){ + pin_value = pin-307; + }else if (pin == 308){ + pin_value = pin-305; + }else if (pin == 309){ + pin_value = pin-305; + }else if (pin == 310){ + pin_value = pin-305; + }else if (pin == 311){ + pin_value = pin-305; + }else if (pin == 323){ + pin_value = pin-315; + }else if (pin == 334){ + pin_value = pin-325; + }else if (pin == 653){ + pin_value = pin-646; + } + + obj->mask = 0x1 << pin_value; + obj->pin_number = pin; + if(pin <=15) { + obj->reg_data = &CMSDK_GPIO0->DATAOUT ; + obj->reg_in = &CMSDK_GPIO0->DATA ; + obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ; + } else if (pin >= 16 && pin <= 31){ + obj->reg_data = &CMSDK_GPIO1->DATAOUT ; + obj->reg_in = &CMSDK_GPIO1->DATA ; + obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ; + } else if (pin >= 32 && pin <= 47){ + obj->reg_data = &CMSDK_GPIO2->DATAOUT; + obj->reg_in = &CMSDK_GPIO2->DATA; + obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ; + } else if (pin >= 48 && pin <= 51){ + obj->reg_data = &CMSDK_GPIO3->DATAOUT; + obj->reg_in = &CMSDK_GPIO3->DATA; + obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ; + } else if (pin == 100 || pin == 101){ + obj->reg_data = &MPS2_FPGAIO->LED; //user leds + obj->reg_in = &MPS2_FPGAIO->LED; + } else if (pin == 110 || pin == 111){ + obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches + obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches + }else if (pin >= 200 && pin <= 207){ + obj->reg_data = &MPS2_SCC->LEDS; //mcc leds + obj->reg_in = &MPS2_SCC->LEDS; //mcc leds + }else if (pin >= 210 && pin <= 217){ + obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches + }else if (pin == 303 || pin == 307){ + obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307 + }else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){ + obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits + }else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653 + obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits + } + + if (pin == 323){ + CMSDK_GPIO0->ALTFUNCSET |= 0x1000; + }else if (pin == 334){ + CMSDK_GPIO2->ALTFUNCSET |= 0x0040; + }else if (pin == 653){ + CMSDK_GPIO1->ALTFUNCSET |= 0x0001; + } + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + if(obj->pin >= 0 && obj->pin <= 51) + { + switch (direction) { + case PIN_INPUT : *obj->reg_dirclr = obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } + } else {return;} +} + +int gpio_is_connected(const gpio_t *obj){ + if(obj->pin != (PinName)NC){ + return 1; + } else { + return 0; + } +} + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c new file mode 100644 index 0000000000..0f6ebb6852 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c @@ -0,0 +1,241 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +#define CHANNEL_NUM 32 +#define CMSDK_GPIO_0 CMSDK_GPIO0 +#define CMSDK_GPIO_1 CMSDK_GPIO1 +#define PININT_IRQ 0 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +static inline void handle_interrupt_in(uint32_t channel) { + uint32_t ch_bit = (1 << channel); + // Return immediately if: + // * The interrupt was already served + // * There is no user handler + // * It is a level interrupt, not an edge interrupt + if (ch_bit <16){ + if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; + + if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_0->INTPOLSET = ch_bit; + } + if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_FALL); + } + CMSDK_GPIO_0->INTCLEAR = ch_bit; + } + + if (ch_bit>=16) { + if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; + + if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_1->INTPOLSET = ch_bit; + } + if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_FALL); + } + CMSDK_GPIO_1->INTCLEAR = ch_bit; + } +} + +void gpio0_irq0(void) {handle_interrupt_in(0);} +void gpio0_irq1(void) {handle_interrupt_in(1);} +void gpio0_irq2(void) {handle_interrupt_in(2);} +void gpio0_irq3(void) {handle_interrupt_in(3);} +void gpio0_irq4(void) {handle_interrupt_in(4);} +void gpio0_irq5(void) {handle_interrupt_in(5);} +void gpio0_irq6(void) {handle_interrupt_in(6);} +void gpio0_irq7(void) {handle_interrupt_in(7);} +void gpio0_irq8(void) {handle_interrupt_in(8);} +void gpio0_irq9(void) {handle_interrupt_in(9);} +void gpio0_irq10(void) {handle_interrupt_in(10);} +void gpio0_irq11(void) {handle_interrupt_in(11);} +void gpio0_irq12(void) {handle_interrupt_in(12);} +void gpio0_irq13(void) {handle_interrupt_in(13);} +void gpio0_irq14(void) {handle_interrupt_in(14);} +void gpio0_irq15(void) {handle_interrupt_in(15);} +void gpio1_irq0(void) {handle_interrupt_in(16);} +void gpio1_irq1(void) {handle_interrupt_in(17);} +void gpio1_irq2(void) {handle_interrupt_in(18);} +void gpio1_irq3(void) {handle_interrupt_in(19);} +void gpio1_irq4(void) {handle_interrupt_in(20);} +void gpio1_irq5(void) {handle_interrupt_in(21);} +void gpio1_irq6(void) {handle_interrupt_in(22);} +void gpio1_irq7(void) {handle_interrupt_in(23);} +void gpio1_irq8(void) {handle_interrupt_in(24);} +void gpio1_irq9(void) {handle_interrupt_in(25);} +void gpio1_irq10(void) {handle_interrupt_in(26);} +void gpio1_irq11(void) {handle_interrupt_in(27);} +void gpio1_irq12(void) {handle_interrupt_in(28);} +void gpio1_irq13(void) {handle_interrupt_in(29);} +void gpio1_irq14(void) {handle_interrupt_in(30);} +void gpio1_irq15(void) {handle_interrupt_in(31);} + + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) {return -1;} + else { + + irq_handler = handler; + + int found_free_channel = 0; + int i = 0; + for (i=0; ich = i; + found_free_channel = 1; + break; + } + } + if (!found_free_channel) return -1; + + + /* To select a pin for any of the eight pin interrupts, write the pin number + * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. + * @see: mbed_capi/PinNames.h + */ + if (pin <16) + { + CMSDK_GPIO_0->INTENSET |= (0x1 << pin); + } + + if (pin >= 16) + { + CMSDK_GPIO_1->INTENSET |= (0x1 << pin); + } + + void (*channels_irq)(void) = NULL; + switch (obj->ch) { + case 0: channels_irq = &gpio0_irq0; break; + case 1: channels_irq = &gpio0_irq1; break; + case 2: channels_irq = &gpio0_irq2; break; + case 3: channels_irq = &gpio0_irq3; break; + case 4: channels_irq = &gpio0_irq4; break; + case 5: channels_irq = &gpio0_irq5; break; + case 6: channels_irq = &gpio0_irq6; break; + case 7: channels_irq = &gpio0_irq7; break; + case 8: channels_irq = &gpio0_irq8; break; + case 9: channels_irq = &gpio0_irq9; break; + case 10: channels_irq = &gpio0_irq10; break; + case 11: channels_irq = &gpio0_irq11; break; + case 12: channels_irq = &gpio0_irq12; break; + case 13: channels_irq = &gpio0_irq13; break; + case 14: channels_irq = &gpio0_irq14; break; + case 15: channels_irq = &gpio0_irq15; break; + case 16: channels_irq = &gpio1_irq0; break; + case 17: channels_irq = &gpio1_irq1; break; + case 18: channels_irq = &gpio1_irq2; break; + case 19: channels_irq = &gpio1_irq3; break; + case 20: channels_irq = &gpio1_irq4; break; + case 21: channels_irq = &gpio1_irq5; break; + case 22: channels_irq = &gpio1_irq6; break; + case 23: channels_irq = &gpio1_irq7; break; + case 24: channels_irq = &gpio1_irq8; break; + case 25: channels_irq = &gpio1_irq9; break; + case 26: channels_irq = &gpio1_irq10; break; + case 27: channels_irq = &gpio1_irq11; break; + case 28: channels_irq = &gpio1_irq12; break; + case 29: channels_irq = &gpio1_irq13; break; + case 30: channels_irq = &gpio1_irq14; break; + case 31: channels_irq = &gpio1_irq15; break; + + } + NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); + + return 0; + } +} + +void gpio_irq_free(gpio_irq_t *obj) { +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + unsigned int ch_bit = (1 << obj->ch); + + // Clear interrupt + if (obj->ch <16) + { + if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) + { + CMSDK_GPIO_0->INTCLEAR = ch_bit; + } + } + if (obj->ch >= 16) + { + if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) + { + CMSDK_GPIO_1->INTCLEAR = ch_bit; + } + } + + // Edge trigger + if (obj->ch <16) + { + CMSDK_GPIO_0->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_0->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_0->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } + } + } + if (obj->ch >= 16) + { + CMSDK_GPIO_1->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_1->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_1->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } + } + } +} + +void gpio_irq_enable(gpio_irq_t *obj) { + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h new file mode 100644 index 0000000000..f6ba621d30 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + uint32_t pin_number; + + __IO uint32_t *reg_dir; + __IO uint32_t *reg_dirclr; + __IO uint32_t *reg_data; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + if (value){ + *obj->reg_data |= (obj->mask); + } else { + *obj->reg_data &= ~(obj->mask); + } +} + +static inline int gpio_read(gpio_t *obj) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c new file mode 100644 index 0000000000..b620c21d6d --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c @@ -0,0 +1,533 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "SMM_MPS2.h" +#include "mbed_wait_api.h" +#include "fpga.h" + +// Types +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 + +// TSC I2C controller +#define TSC_I2C_ADDR 0x82 +// AACI I2C controller I2C address +#define AAIC_I2C_ADDR 0x96 + +#define TSC_I2C_CID 0x0811 + +// TSC I2C controller registers +#define TSC_I2C_CRID 0x00 + + +// TSSPCPSR Clock prescale register +#define TSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR) + +// TSC defaults +#define TSC_XOFF 20 // X offset +#define TSC_YOFF 20 // Y offset +#define TSC_MAXVAL 37000 // 0x0FFF * 10 with TSC to LCD scaling + +#define TSC_TSU 15 // Setup delay 600nS min +#define AAIC_TSU 25 // Setup delay 1000nS min +#define SHIELD_TSU 25 // Setup delay 1000nS min + + +static const PinMap PinMap_I2C_SDA[] = { + {TSC_SDA, I2C_0, 0}, + {AUD_SDA, I2C_1, 0}, + {SHIELD_0_SDA, I2C_2, 0}, + {SHIELD_1_SDA, I2C_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {TSC_SCL, I2C_0, 0}, + {AUD_SCL, I2C_1, 0}, + {SHIELD_0_SCL, I2C_2, 0}, + {SHIELD_1_SCL, I2C_3, 0}, + {NC , NC, 0} +}; + +static inline void i2c_send_byte(i2c_t *obj, unsigned char c) +{ + int loop; + switch ((int)obj->i2c) { + case I2C_0: + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + + for (loop = 0; loop < 8; loop++) + { + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(TSC_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(TSC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + } + + obj->i2c->CONTROLS = SDA; + i2c_delay(TSC_TSU); + break; + case I2C_1: + for (loop = 0; loop < 8; loop++) { + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(AAIC_TSU); + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + } + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SDA; + i2c_delay(AAIC_TSU); + break; + case I2C_2: + case I2C_3: + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + + for (loop = 0; loop < 8; loop++) + { + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(SHIELD_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(SHIELD_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + } + + obj->i2c->CONTROLS = SDA; + i2c_delay(SHIELD_TSU); + break; + } +} + +static inline unsigned char i2c_receive_byte(i2c_t *obj) +{ + int data_receive_byte, loop; + switch ((int)obj->i2c) { + case I2C_0: + obj->i2c->CONTROLS = SDA; + i2c_delay(TSC_TSU); + + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) + { + obj->i2c->CONTROLS = SCL; + i2c_delay(TSC_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + } + + obj->i2c->CONTROLC = SDA; + i2c_delay(TSC_TSU); + break; + case I2C_1: + obj->i2c->CONTROLS = SDA; + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) { + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SCL | SDA; + i2c_delay(AAIC_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + } + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SDA; + i2c_delay(AAIC_TSU); + break; + case I2C_2: + case I2C_3: + obj->i2c->CONTROLS = SDA; + i2c_delay(SHIELD_TSU); + + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) + { + obj->i2c->CONTROLS = SCL; + i2c_delay(SHIELD_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + } + + obj->i2c->CONTROLC = SDA; + i2c_delay(SHIELD_TSU); + break; + } + return data_receive_byte; +} + +static inline int i2c_receive_ack(i2c_t *obj) +{ + int nack; + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + nack = obj->i2c->CONTROL & SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + if(nack==0) + return 1; + + return 0; +} + + +static inline void i2c_send_nack(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + +} + +static inline void i2c_send_ack(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // determine the SPI to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = (MPS2_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); + + if ((int)obj->i2c == NC) { + error("I2C pin mapping failed"); + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + switch ((int)obj->i2c) { + case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break; + case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000; + CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break; + } + + +} + +int i2c_start(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA | SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + + return 0; +} + +int i2c_start_tsc(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + // Actual stop bit + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + + return 0; +} + + + +void i2c_frequency(i2c_t *obj, int hz) { +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + unsigned int loop, rxdata; + int sadr, ack, bytes_read; + rxdata=0; + switch ((int)obj->i2c) { + case I2C_0: + sadr = TSC_I2C_ADDR; + break; + case I2C_1: + sadr = AAIC_I2C_ADDR; + break; + case I2C_2: + case I2C_3: + sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR; + break; + } + bytes_read = 0; + // Start bit + i2c_start(obj); + + switch ((int)obj->i2c) { + case I2C_0: + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, address); + ack += i2c_receive_ack(obj); + + // Stop bit + i2c_stop(obj); + + // Start bit + i2c_start_tsc(obj); + + // Read from I2C address + i2c_send_byte(obj,sadr | 1); + ack += i2c_receive_ack(obj); + + rxdata = (i2c_receive_byte(obj) & 0xFF); + data[((length-1)-bytes_read)] = (char)rxdata; + bytes_read++; + // Read multiple bytes + if ((length > 1) && (length < 5)) + { + for (loop = 1; loop <= (length - 1); loop++) + { + // Send ACK + i2c_send_ack(obj); + + // Next byte + //rxdata = ((rxdata << 8) & 0xFFFFFF00); + //rxdata |= (i2c_receive_byte(obj) & 0xFF); + rxdata = i2c_receive_byte(obj); + data[(length-1)-bytes_read] = (char)rxdata; + bytes_read++; + + } + } + break; + case I2C_1: + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, address); + ack += i2c_receive_ack(obj); + + // Stop bit + i2c_stop(obj); + + // Start bit + i2c_start_tsc(obj); + // Fall through to read data + case I2C_2: + case I2C_3: + // Read from preset register address pointer + i2c_send_byte(obj,sadr | 1); + ack += i2c_receive_ack(obj); + + rxdata = i2c_receive_byte(obj); + data[bytes_read] = (char)rxdata; + bytes_read++; + // Read multiple bytes + if ((length > 1) && (length < 5)) + { + for (loop = 1; loop <= (length - 1); loop++) + { + // Send ACK + i2c_send_ack(obj); + + // Next byte + rxdata = i2c_receive_byte(obj); + data[loop] = (char)rxdata; + bytes_read++; + + } + } + break; + } + i2c_send_nack(obj); + + i2c_stop(obj); // Actual stop bit + + return bytes_read; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int ack=0; + int sadr; + char * ptr; + char addr; + ptr = (char*)data; + switch ((int)obj->i2c) + { + case I2C_0: + sadr = TSC_I2C_ADDR; + addr = address; + break; + case I2C_1: + sadr = AAIC_I2C_ADDR; + addr = address; + break; + case I2C_2: + case I2C_3: + sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR; + addr = *ptr++; + break; + } + +// printf("adr = %x, reg = %x\n",sadr, address); + i2c_start(obj); + + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, addr); + ack += i2c_receive_ack(obj); + + for(int i = 1; iport = port; + obj->mask = mask; + + CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10)); + + obj->reg_in = &port_reg->DATAOUT; + obj->reg_dir = &port_reg->OUTENABLESET; + obj->reg_dirclr = &port_reg->OUTENABLECLR; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<16; i++) { + if (obj->mask & (1<port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_in = value; +} + +int port_read(port_t *obj) { + return (*obj->reg_in); +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c new file mode 100644 index 0000000000..284c3affb5 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c @@ -0,0 +1,369 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_api.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ + +static const PinMap PinMap_UART_TX[] = { + {USBTX , UART_0, 0}, + {XB_TX , UART_1, 0}, + {SH0_TX , UART_2, 0}, + {SH1_TX , UART_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {USBRX , UART_0, 0}, + {XB_RX , UART_1, 0}, + {SH0_RX , UART_2, 0}, + {SH1_RX , UART_3, 0}, + {NC , NC , 0} +}; + +#define UART_NUM 4 + +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +struct serial_global_data_s { + uint32_t serial_irq_id; + gpio_t sw_rts, sw_cts; + uint8_t count, rx_irq_set_flow, rx_irq_set_api; +}; + +static struct serial_global_data_s uart_data[UART_NUM]; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + if ((int)uart == NC) { + error("Serial pinout mapping failed"); + } + + obj->uart = (CMSDK_UART_TypeDef *)uart; + //set baud rate and enable Uart in normarl mode (RX and TX enabled) + switch (uart) + { + case UART_0: + { + CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration + if((int)uart_tx != NC) + { + CMSDK_UART0->CTRL |= 0x01; // TX enable + } else { + CMSDK_UART0->CTRL &= 0xFFFE; // TX disable + } + + + if((int)uart_rx != NC) + { + CMSDK_UART0->CTRL |= 0x02; // RX enable + } else { + CMSDK_UART0->CTRL &= 0xFFFD; // RX disable + } + + } + break; + case UART_1: //XBEE SOCKET UART + { + CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART1->CTRL = 0x1; // TX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0100; + } + if((int)rx != NC) + { + CMSDK_UART1->CTRL |= 0x2; // RX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0080; + } + } + break; + case UART_2: //Sheild0 UART + { + CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART3->CTRL = 0x1; // TX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0010; + } + if((int)rx != NC) + { + CMSDK_UART3->CTRL |= 0x2; // RX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0001; + } + } + break; + case UART_3: //Sheild1 UART + { + CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART4->CTRL = 0x1; // TX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x4000; + } + if((int)rx != NC) + { + CMSDK_UART4->CTRL |= 0x2; // RX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0400; + } + } + break; + } + + // set default baud rate and format + serial_baud (obj, 9600); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + switch (uart) { + case UART_0: obj->index = 0; break; + case UART_1: obj->index = 1; break; + case UART_2: obj->index = 2; break; + case UART_3: obj->index = 3; break; + } + uart_data[obj->index].sw_rts.pin = NC; + uart_data[obj->index].sw_cts.pin = NC; + serial_set_flow_control(obj, FlowControlNone, NC, NC); + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + uart_data[obj->index].serial_irq_id = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + // The MPS2 has a simple divider to control the baud rate. The formula is: + // + // Baudrate = PCLK / BAUDDIV + // + // PCLK = 25 Mhz + // so for a desired baud rate of 9600 + // 25000000 / 9600 = 2604 + // + //check to see if minimum baud value entered + int baudrate_div = 0; + baudrate_div = SystemCoreClock / baudrate; + if(baudrate >= 16){ + switch ((int)obj->uart) { + case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break; + case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break; + case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break; + case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break; + default: error("serial_baud"); break; + } + } else { + error("serial_baud"); + } + +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) { + SerialIrq irq_type; + switch (intstatus) + { + case 1: + { + irq_type = TxIrq; + } + break; + + case 2: + { + irq_type = RxIrq; + } + break; + + default: return; + } /* End of Switch */ + + if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) + { + gpio_write(&uart_data[index].sw_rts, 1); + // Disable interrupt if it wasn't enabled by other part of the application + if (!uart_data[index].rx_irq_set_api) + { + /* Disable Rx interrupt */ + puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); + } + } + + if (uart_data[index].serial_irq_id != 0) + { + if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) + { + irq_handler(uart_data[index].serial_irq_id, irq_type); + } + } + + if( irq_type == TxIrq ) + { + /* Clear the TX interrupt Flag */ + puart->INTCLEAR |= 0x01; + } + else + { + /* Clear the Rx interupt Flag */ + puart->INTCLEAR |= 0x02; + } +} + +void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);} +void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);} +void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);} +void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + uart_data[obj->index].serial_irq_id = id; +} + +static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { + /* Declare a variable of type IRQn, initialise to 0 */ + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) + { + case UART_0: + { + irq_n = (( irq == TxIrq ) ? UARTTX0_IRQn : UARTRX0_IRQn); + vector = (uint32_t)&uart0_irq; + } + break; + + case UART_1: + { + irq_n = (( irq == TxIrq ) ? UARTTX1_IRQn : UARTRX1_IRQn); + vector = (uint32_t)&uart1_irq; + } + break; + case UART_2: + { + irq_n = (( irq == TxIrq ) ? UARTTX3_IRQn : UARTRX3_IRQn); + vector = (uint32_t)&uart2_irq; + } + break; + case UART_3: + { + irq_n = (( irq == TxIrq ) ? UARTTX4_IRQn : UARTRX4_IRQn); + vector = (uint32_t)&uart3_irq; + } + break; + } + + if (enable) + { + if( irq == TxIrq ) + { + /* Transmit IRQ, set appripriate enable */ + + /* set TX interrupt enable in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; + } + else + { + /* set Rx interrupt on in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + } + else + { /* Disable IRQ */ + + obj->uart->CTRL &= ~(1 << (irq + 2)); + + NVIC_DisableIRQ(irq_n); + } +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + serial_irq_set_internal(obj, irq, enable); +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (serial_readable(obj) == 0); + int data = obj->uart->DATA; + return data; +} + +void serial_putc(serial_t *obj, int c) { + while (serial_writable(obj) == 0); + obj->uart->DATA = c; +} + +int serial_readable(serial_t *obj) { + return obj->uart->STATE & 0x2; +} + +int serial_writable(serial_t *obj) { + return !(obj->uart->STATE & 0x1); +} + +void serial_clear(serial_t *obj) { + obj->uart->DATA = 0x00; +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { +} + +void serial_break_clear(serial_t *obj) { +} +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { +} + diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c new file mode 100644 index 0000000000..b0b668ad44 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c @@ -0,0 +1,301 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "spi_api.h" +#include "spi_def.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "mbed_wait_api.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {SCLK_SPI , SPI_0, 0}, + {CLCD_SCLK , SPI_1, 0}, + {ADC_SCLK , SPI_2, 0}, + {SHIELD_0_SPI_SCK , SPI_3, 0}, + {SHIELD_1_SPI_SCK , SPI_4, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {MOSI_SPI, SPI_0, 0}, + {CLCD_MOSI, SPI_1, 0}, + {ADC_MOSI, SPI_2, 0}, + {SHIELD_0_SPI_MOSI, SPI_3, 0}, + {SHIELD_1_SPI_MOSI, SPI_4, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {MISO_SPI, SPI_0, 0}, + {CLCD_MISO, SPI_1, 0}, + {ADC_MISO, SPI_2, 0}, + {SHIELD_0_SPI_MISO, SPI_3, 0}, + {SHIELD_1_SPI_MISO, SPI_4, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {SSEL_SPI, SPI_0, 0}, + {CLCD_SSEL, SPI_1, 0}, + {ADC_SSEL, SPI_2, 0}, + {SHIELD_0_SPI_nCS, SPI_3, 0}, + {SHIELD_1_SPI_nCS, SPI_4, 0}, + {NC , NC , 0} +}; + +static inline int ssp_disable(spi_t *obj); +static inline int ssp_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + + int altfunction[4]; + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + if ((int)obj->spi == NC) { + error("SPI pinout mapping failed"); + } + + // enable power and clocking + switch ((int)obj->spi) { + case (int)SPI_0: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_1: + /* Configure SSP used for LCD */ + obj->spi->CR1 = 0; /* Synchronous serial port disable */ + obj->spi->DMACR = 0; /* Disable FIFO DMA */ + obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */ + obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */ + (1ul << 1) ); /* Clear SSPRTINTR interrupt */ + obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */ + (0ul << 4) | /* Motorola frame format */ + (0ul << 6) | /* CPOL = 0 */ + (0ul << 7) | /* CPHA = 0 */ + (1ul << 8) ); /* Set serial clock rate */ + obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */ + obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */ + (0ul << 2) ); /* Device configured as master */ + break; + case (int)SPI_2: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_3: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_4: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + } + + if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} + if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} + if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} + if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} + + // enable alt function + switch ((int)obj->spi) { + case (int)SPI_2: + CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]); + break; + case (int)SPI_3: + CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11); + break; + case (int)SPI_4: + CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6); + break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + ssp_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + ssp_disable(obj); + if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { + error("SPI format error"); + } + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int DSS = bits - 1; // DSS (data select size) + int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity + int SPH = (phase) ? 1 : 0; // SPH - clock out phase + + int FRF = 0; // FRF (frame format) = SPI + uint32_t tmp = obj->spi->CR0; + tmp &= ~(0xFFFF); + tmp |= DSS << 0 + | FRF << 4 + | SPO << 6 + | SPH << 7; + obj->spi->CR0 = tmp; + + tmp = obj->spi->CR1; + tmp &= ~(0xD); + tmp |= 0 << 0 // LBM - loop back mode - off + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na + obj->spi->CR1 = tmp; + + ssp_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + ssp_disable(obj); + + uint32_t PCLK = SystemCoreClock; + + int prescaler; + + for (prescaler = 2; prescaler <= 254; prescaler += 2) { + int prescale_hz = PCLK / prescaler; + + // calculate the divider + int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); + + // check we can support the divider + if (divider < 256) { + // prescaler + obj->spi->CPSR = prescaler; + + // divider + obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 |= (divider - 1) << 8; + ssp_enable(obj); + return; + } + } + error("Couldn't setup requested SPI frequency"); +} + +static inline int ssp_disable(spi_t *obj) { + return obj->spi->CR1 &= ~(1 << 1); +} + +static inline int ssp_enable(spi_t *obj) { + return obj->spi->CR1 |= SSP_CR1_SSE_Msk; +} + +static inline int ssp_readable(spi_t *obj) { + return obj->spi->SR & (1 << 2); +} + +static inline int ssp_writeable(spi_t *obj) { + return obj->spi->SR & SSP_SR_BSY_Msk; +} + +static inline void ssp_write(spi_t *obj, int value) { + obj->spi->DR = value; + while (ssp_writeable(obj)); +} +static inline int ssp_read(spi_t *obj) { + int read_DR = obj->spi->DR; + return read_DR; +} + +static inline int ssp_busy(spi_t *obj) { + return (obj->spi->SR & (1 << 4)) ? (1) : (0); +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ + return (ssp_read(obj)); +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) { + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_slave_receive(spi_t *obj) { + return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (ssp_writeable(obj) == 0) ; + obj->spi->DR = value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h new file mode 100644 index 0000000000..ac76b34c6e --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h @@ -0,0 +1,174 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ---------------------------------------------------------------- + * File: apspi.h + * Release: Version 2.0 + * ---------------------------------------------------------------- + * + * SSP interface Support + * ===================== + */ + +#define SSPCS_BASE (0x4002804C) // SSP chip select register +#define SSP_BASE (0x40020000) // SSP Prime Cell + +#define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00)) +#define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04)) +#define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08)) +#define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C)) +#define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10)) +#define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14)) +#define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18)) +#define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C)) +#define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20)) +#define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24)) +#define SSPCS ((volatile unsigned int *)(SSPCS_BASE)) + +// SSPCR0 Control register 0 +#define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3 +#define SSPCR0_SPH 0x0080 // SSPCLKOUT phase +#define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity +#define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola +#define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits +#define SSPCR0_DSS_16 0x000F // Data packet size, 16bits + +// SSPCR1 Control register 1 +#define SSPCR1_SOD 0x0008 // Slave Output mode Disable +#define SSPCR1_MS 0x0004 // Master or Slave mode +#define SSPCR1_SSE 0x0002 // Serial port enable +#define SSPCR1_LBM 0x0001 // Loop Back Mode + +// SSPSR Status register +#define SSPSR_BSY 0x0010 // Busy +#define SSPSR_RFF 0x0008 // Receive FIFO full +#define SSPSR_RNE 0x0004 // Receive FIFO not empty +#define SSPSR_TNF 0x0002 // Transmit FIFO not full +#define SSPSR_TFE 0x0001 // Transmit FIFO empty + +// SSPCPSR Clock prescale register +#define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8 + +// SSPIMSC Interrupt mask set and clear register +#define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked +#define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked +#define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked +#define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked + +// SSPRIS Raw interrupt status register +#define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag +#define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag +#define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag +#define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag + +// SSPMIS Masked interrupt status register +#define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag +#define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag +#define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag +#define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag + +// SSPICR Interrupt clear register +#define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag +#define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag + +// SSPDMACR DMA control register +#define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA +#define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA + +// SPICS register (0=Chip Select low) +#define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS) + +// SPI defaults +#define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS) + +// EEPROM instruction set +#define EEWRSR 0x0001 // Write status +#define EEWRITE 0x0002 // Write data +#define EEREAD 0x0003 // Read data +#define EEWDI 0x0004 // Write disable +#define EEWREN 0x0006 // Write enable +#define EERDSR 0x0005 // Read status + +// EEPROM status register flags +#define EERDSR_WIP 0x0001 // Write in process +#define EERDSR_WEL 0x0002 // Write enable latch +#define EERDSR_BP0 0x0004 // Block protect 0 +#define EERDSR_BP1 0x0008 // Block protect 1 +#define EERDSR_WPEN 0x0080 // Write protect enable + + /* ---------------------------------------------------------------- + * + * Color LCD Support + * ================= + */ + +// Color LCD Controller Internal Register addresses +#define LSSPCS_BASE (0x4002804C) // LSSP chip select register +#define LSSP_BASE (0x40021000) // LSSP Prime Cell + +#define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00)) +#define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04)) +#define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08)) +#define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C)) +#define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10)) +#define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14)) +#define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18)) +#define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C)) +#define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20)) +#define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24)) +#define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE)) + +// LSSPCR0 Control register 0 +#define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR)) +#define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase +#define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity +#define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola +#define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits +#define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits + +// LSSPCR1 Control register 1 +#define LSSPCR1_SOD 0x0008 // Slave Output mode Disable +#define LSSPCR1_MS 0x0004 // Master or Slave mode +#define LSSPCR1_SSE 0x0002 // Serial port enable +#define LSSPCR1_LBM 0x0001 // Loop Back Mode + +// LSSPSR Status register +#define LSSPSR_BSY 0x0010 // Busy +#define LSSPSR_RFF 0x0008 // Receive FIFO full +#define LSSPSR_RNE 0x0004 // Receive FIFO not empty +#define LSSPSR_TNF 0x0002 // Transmit FIFO not full +#define LSSPSR_TFE 0x0001 // Transmit FIFO empty + +// LSSPCPSR Clock prescale register +#define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR) + +// SPICS register +#define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS) +#define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS) +#define LCD_RESET 0x0008 // RESET (CLCD_RESET) +#define LCD_RS 0x0010 // RS (CLCD_RS) +#define LCD_RD 0x0020 // RD (CLCD_RD) +#define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL) + +// SPI defaults +#define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS) +#define LSPI_START (0x70) // Start byte for SPI transfer +#define LSPI_RD (0x01) // WR bit 1 within start +#define LSPI_WR (0x00) // WR bit 0 within start +#define LSPI_DATA (0x02) // RS bit 1 within start byte +#define LSPI_INDEX (0x00) // RS bit 0 within start byte + +// Screen size +#define LCD_WIDTH 320 // Screen Width (in pixels) +#define LCD_HEIGHT 240 // Screen Height (in pixels) diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c new file mode 100644 index 0000000000..6ae74aea9c --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c @@ -0,0 +1,83 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" + +#define US_TICKER_TIMER1 CMSDK_DUALTIMER1 +#define US_TICKER_TIMER2 CMSDK_DUALTIMER2 +#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn + +int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) return; + us_ticker_inited = 1; + + US_TICKER_TIMER1->TimerControl = 0x0; // disable timer + US_TICKER_TIMER2->TimerControl = 0x00; // disable timer + US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF; + US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF; + + US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode + US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter + + US_TICKER_TIMER1->TimerControl |= 0x80; // enable counter + US_TICKER_TIMER2->TimerControl |= 0x80; // enable counter + + NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); +} + +uint32_t us_ticker_read() { +uint32_t return_value = 0; + if (!us_ticker_inited) + us_ticker_init(); + return_value = ((~US_TICKER_TIMER2->TimerValue)/25); + return return_value; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + if (!us_ticker_inited) + us_ticker_init(); + + uint32_t delta = timestamp - us_ticker_read(); + // enable interrupt + US_TICKER_TIMER1->TimerControl = 0x0; // disable timer + US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode + US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value + US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); +} + + +void us_ticker_disable_interrupt(void) { + + US_TICKER_TIMER1->TimerControl &= 0xDF; + US_TICKER_TIMER2->TimerControl &= 0xDF; + +} + +void us_ticker_clear_interrupt(void) { + + US_TICKER_TIMER1->TimerIntClr = 0x1; + US_TICKER_TIMER2->TimerIntClr = 0x1; + +} diff --git a/targets/TARGET_ARM_FM/mbed_rtx.h b/targets/TARGET_ARM_FM/mbed_rtx.h new file mode 100644 index 0000000000..16445479f6 --- /dev/null +++ b/targets/TARGET_ARM_FM/mbed_rtx.h @@ -0,0 +1,28 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_FVP_MPS2) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20020000UL) +#endif + +#endif /* defined(TARGET_...) */ + +#endif /* MBED_MBED_RTX_H */ From 2e4a0234896c462d0e7ebc03c330b95e8fb72dd8 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 14 May 2018 11:32:52 +0100 Subject: [PATCH 02/11] FastModels: add FVP_MPS2_M3 target support add cmsis drivers and toolchain scripts for FVP_MPS2_M3 --- .../TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h | 724 ++++++++++++++++++ .../TARGET_FVP_MPS2_M3/device/SMM_MPS2.h | 614 +++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MPS2.sct | 47 ++ .../device/TOOLCHAIN_ARM_STD/startup_MPS2.S | 290 +++++++ .../device/TOOLCHAIN_GCC_ARM/MPS2.ld | 211 +++++ .../device/TOOLCHAIN_GCC_ARM/startup_MPS2.S | 257 +++++++ .../device/TOOLCHAIN_IAR/MPS2.icf | 56 ++ .../device/TOOLCHAIN_IAR/startup_MPS2.S | 340 ++++++++ .../TARGET_FVP_MPS2_M3/device/cmsis.h | 42 + .../TARGET_FVP_MPS2_M3/device/cmsis_nvic.h | 39 + .../device/peripherallink.h | 53 ++ .../device/system_CMSDK_CM3.c | 93 +++ .../device/system_CMSDK_CM3.h | 76 ++ 13 files changed, 2842 insertions(+) create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis_nvic.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h new file mode 100644 index 0000000000..cc1152b2a7 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h @@ -0,0 +1,724 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_CM3.h +* @brief CMSIS Core Peripheral Access Layer Header File for +* CMSDK_CM3 Device +* +*******************************************************************************/ + + +#ifndef CMSDK_CM3_H +#define CMSDK_CM3_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/****** CMSDK Specific Interrupt Numbers *********************************************************/ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ +#define __CM3_REV 0x0201 /* Core revision r2p1 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_CM3.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined ( __CC_ARM ) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) +#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_CM3_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h new file mode 100644 index 0000000000..3b78c8b44f --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h @@ -0,0 +1,614 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* File: smm_mps2.h +* Release: Version 1.1 +*******************************************************************************/ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld new file mode 100644 index 0000000000..2518b646a3 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld @@ -0,0 +1,211 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 gcc_arm.ld + */ +/* Linker script for mbed FVP Cortex-M3 on MPS2 */ + +/* Linker script to configure memory regions. */ +/* The length of the VECTORS region is a bit larger than + * is necessary based on the number of exception handlers. + */ +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x4000; +STACK_SIZE = 0x1000; + +/* Size of the vector table in SRAM */ +M_VECTOR_RAM_SIZE = 0x140; + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(4); + } > VECTORS + + .text : + { + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > RAM + + .data : + { + PROVIDE(__etext = LOADADDR(.data)); + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + + } > RAM + + bss_size = __bss_end__ - __bss_start__; + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + +} /* End of sections */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S new file mode 100644 index 0000000000..c5d12692ec --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S @@ -0,0 +1,257 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 startup_ARMCM3.S + */ + .syntax unified + .arch armv7-m + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */ + .long Spare_IRQHandler /* 1: Undefined */ + .long UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */ + .long APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */ + .long APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */ + .long RTC_IRQHandler /* 5: RTC Interrupt */ + .long PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */ + .long PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */ + .long TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */ + .long TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */ + .long DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */ + .long APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */ + .long UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */ + .long APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */ + .long RESERVED0_IRQHandler /* 14: Reserved */ + .long TSC_IRQHandler /* 15: Touch Screen Interrupt */ + .long PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */ + .long PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */ + .long PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */ + .long PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */ + .long PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */ + .long PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */ + .long PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */ + .long PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */ + .long PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */ + .long PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */ + .long PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */ + .long PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */ + .long PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */ + .long PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */ + .long PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */ + .long PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */ + .long FLASH0_IRQHandler /* 32: Reserved for Flash */ + .long FLASH1_IRQHandler /* 33: Reserved for Flash */ + .long RESERVED1_IRQHandler /* 34: Reserved */ + .long RESERVED2_IRQHandler /* 35: Reserved */ + .long RESERVED3_IRQHandler /* 36: Reserved */ + .long RESERVED4_IRQHandler /* 37: Reserved */ + .long RESERVED5_IRQHandler /* 38: Reserved */ + .long RESERVED6_IRQHandler /* 39: Reserved */ + .long RESERVED7_IRQHandler /* 40: Reserved */ + .long RESERVED8_IRQHandler /* 41: Reserved */ + .long PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */ + .long PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */ + .long TRNG_IRQHandler /* 44: Random number generator Interrupt */ + .long UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */ + .long UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */ + .long ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */ + .long I2S_IRQHandler /* 48: I2S Interrupt */ + .long MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */ + .long MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */ + .long MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */ + .long MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */ + .long MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */ + .long PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */ + .long PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */ + .long UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =SystemInit + blx r0 +/* + * Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. + */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + +/* Initialize .bss */ +init_bss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + ldr r3, =bss_size + + cmp r3, #0 + beq system_startup + + mov r4, #0 +zero: + strb r4, [r1], #1 + subs r3, r3, #1 + bne zero + +system_startup: + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* + * Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers + */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + /* External interrupts */ + def_irq_default_handler UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */ + def_irq_default_handler Spare_IRQHandler /* 1: Undefined */ + def_irq_default_handler UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */ + def_irq_default_handler APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */ + def_irq_default_handler APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */ + def_irq_default_handler RTC_IRQHandler /* 5: RTC Interrupt */ + def_irq_default_handler PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */ + def_irq_default_handler PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */ + def_irq_default_handler TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */ + def_irq_default_handler TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */ + def_irq_default_handler DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */ + def_irq_default_handler APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */ + def_irq_default_handler UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */ + def_irq_default_handler APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */ + def_irq_default_handler RESERVED0_IRQHandler /* 14: Reserved */ + def_irq_default_handler TSC_IRQHandler /* 15: Touch Screen Interrupt */ + def_irq_default_handler PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */ + def_irq_default_handler PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */ + def_irq_default_handler PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */ + def_irq_default_handler PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */ + def_irq_default_handler PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */ + def_irq_default_handler PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */ + def_irq_default_handler PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */ + def_irq_default_handler PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */ + def_irq_default_handler PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */ + def_irq_default_handler PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */ + def_irq_default_handler PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */ + def_irq_default_handler PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */ + def_irq_default_handler PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */ + def_irq_default_handler PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */ + def_irq_default_handler PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */ + def_irq_default_handler PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */ + def_irq_default_handler FLASH0_IRQHandler /* 32: Reserved for Flash */ + def_irq_default_handler FLASH1_IRQHandler /* 33: Reserved for Flash */ + def_irq_default_handler RESERVED1_IRQHandler /* 34: Reserved */ + def_irq_default_handler RESERVED2_IRQHandler /* 35: Reserved */ + def_irq_default_handler RESERVED3_IRQHandler /* 36: Reserved */ + def_irq_default_handler RESERVED4_IRQHandler /* 37: Reserved */ + def_irq_default_handler RESERVED5_IRQHandler /* 38: Reserved */ + def_irq_default_handler RESERVED6_IRQHandler /* 39: Reserved */ + def_irq_default_handler RESERVED7_IRQHandler /* 40: Reserved */ + def_irq_default_handler RESERVED8_IRQHandler /* 41: Reserved */ + def_irq_default_handler PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */ + def_irq_default_handler PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */ + def_irq_default_handler TRNG_IRQHandler /* 44: Random number generator Interrupt */ + def_irq_default_handler UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */ + def_irq_default_handler UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */ + def_irq_default_handler ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */ + def_irq_default_handler I2S_IRQHandler /* 48: I2S Interrupt */ + def_irq_default_handler MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */ + def_irq_default_handler MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */ + def_irq_default_handler MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */ + def_irq_default_handler MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */ + def_irq_default_handler MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */ + def_irq_default_handler PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */ + def_irq_default_handler PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */ + def_irq_default_handler UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */ + + .end diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf new file mode 100644 index 0000000000..60b104bcf3 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf @@ -0,0 +1,56 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License) you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* The RAM region doesn't start at the beginning of the RAM address + * space to create space for the vector table copied over to the RAM by mbed. + * The space left is a bit bigger than is necessary based on the number of + * interrupt handlers. + */ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000140; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +/* Heap and Stack size */ +define symbol __ICFEDIT_size_heap__ = 0x4000; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/startup_MPS2.S new file mode 100644 index 0000000000..fcabe102c9 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/startup_MPS2.S @@ -0,0 +1,340 @@ +;/* +; * MPS2 CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2018 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UARTRX0_Handler ; 0: UART 0 RX Handler + DCD UARTTX0_Handler ; 1: UART 0 TX Handler + DCD UARTRX1_Handler ; 2: UART 1 RX Handler + DCD UARTTX1_Handler ; 3: UART 1 TX Handler + DCD UARTRX2_Handler ; 4: UART 2 RX Handler + DCD UARTTX2_Handler ; 5: UART 2 TX Handler + DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; 8: TIMER 0 handler + DCD TIMER1_Handler ; 9: TIMER 1 handler + DCD DUALTIMER_HANDLER ; 10: Dual timer handler + DCD SPI_Handler ; 11: SPI exceptions Handler + DCD UARTOVF_Handler ; 12: UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; 13: Ethernet Overflow Handler + DCD I2S_Handler ; 14: I2S Handler + DCD TSC_Handler ; 15: Touch Screen handler + DCD PORT2_COMB_Handler ; 16: GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; 17: GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; 18: UART 3 RX Handler + DCD UARTTX3_Handler ; 19: UART 3 TX Handler + DCD UARTRX4_Handler ; 20: UART 4 RX Handler + DCD UARTTX4_Handler ; 21: UART 4 TX Handler + DCD ADCSPI_Handler ; 22: SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; 23: SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; 24: GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; 25: GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; 26: GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; 27: GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; 28: GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; 29: GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; 30: GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; 31: GPIO Port 0 pin 7 Handler + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UARTRX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX0_Handler + B UARTRX0_Handler + + PUBWEAK UARTTX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX0_Handler + B UARTTX0_Handler + + PUBWEAK UARTRX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX1_Handler + B UARTRX1_Handler + + PUBWEAK UARTTX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX1_Handler + B UARTTX1_Handler + + PUBWEAK UARTRX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX2_Handler + B UARTRX2_Handler + + PUBWEAK UARTTX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX2_Handler + B UARTTX2_Handler + + PUBWEAK PORT0_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_COMB_Handler + B PORT0_COMB_Handler + + PUBWEAK PORT1_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_COMB_Handler + B PORT1_COMB_Handler + + PUBWEAK TIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_Handler + B TIMER0_Handler + + PUBWEAK TIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_Handler + B TIMER1_Handler + + PUBWEAK DUALTIMER_HANDLER + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_HANDLER + B DUALTIMER_HANDLER + + PUBWEAK SPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI_Handler + B SPI_Handler + + PUBWEAK UARTOVF_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_Handler + B UARTOVF_Handler + + PUBWEAK ETHERNET_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ETHERNET_Handler + B ETHERNET_Handler + + PUBWEAK I2S_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S_Handler + B I2S_Handler + + PUBWEAK TSC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_Handler + B TSC_Handler + + PUBWEAK PORT2_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_COMB_Handler + B PORT2_COMB_Handler + + PUBWEAK PORT3_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_COMB_Handler + B PORT3_COMB_Handler + + PUBWEAK UARTRX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX3_Handler + B UARTRX3_Handler + + PUBWEAK UARTTX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX3_Handler + B UARTTX3_Handler + + PUBWEAK UARTRX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX4_Handler + B UARTRX4_Handler + + PUBWEAK UARTTX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX4_Handler + B UARTTX4_Handler + + PUBWEAK ADCSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADCSPI_Handler + B ADCSPI_Handler + + PUBWEAK SHIELDSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SHIELDSPI_Handler + B SHIELDSPI_Handler + + PUBWEAK PORT0_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_Handler + B PORT0_0_Handler + + PUBWEAK PORT0_1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_Handler + B PORT0_1_Handler + + PUBWEAK PORT0_2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_Handler + B PORT0_2_Handler + + PUBWEAK PORT0_3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_Handler + B PORT0_3_Handler + + PUBWEAK PORT0_4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_Handler + B PORT0_4_Handler + + PUBWEAK PORT0_5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_Handler + B PORT0_5_Handler + + PUBWEAK PORT0_6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_Handler + B PORT0_6_Handler + + PUBWEAK PORT0_7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_Handler + B PORT0_7_Handler + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis.h new file mode 100644 index 0000000000..ecbc50ae86 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis.h @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM3.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis_nvic.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis_nvic.h new file mode 100644 index 0000000000..a564abfc18 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 48) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h new file mode 100644 index 0000000000..04fb9ba365 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c new file mode 100644 index 0000000000..9d036d81f4 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c @@ -0,0 +1,93 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file system_CMSDK_CM3.c +* @brief CMSIS Device System Source File for +* CMSDK_M3 Device +* +*******************************************************************************/ + + + +#include "CMSDK_CM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (50000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h new file mode 100644 index 0000000000..148614229f --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h @@ -0,0 +1,76 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************* +* @file system_CMSDK_CM3.h +* @brief CMSIS Device Peripheral Access Layer Header File for +* CMSDK_CM3 Device +* +******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_CM3_H +#define SYSTEM_CMSDK_CM3_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_CM3_H */ From ce2c21a1f49736e23d28753bec106e948030c316 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 14 May 2018 11:33:31 +0100 Subject: [PATCH 03/11] FastModels: add FVP_MPS2_M4 target support add cmsis drivers and toolchain scripts for FVP_MPS2_M4 --- .../TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h | 1300 +++++++++++++++++ .../TARGET_FVP_MPS2_M4/device/SMM_MPS2.h | 614 ++++++++ .../device/TOOLCHAIN_ARM_STD/MPS2.sct | 47 + .../device/TOOLCHAIN_ARM_STD/startup_MPS2.S | 290 ++++ .../device/TOOLCHAIN_GCC_ARM/MPS2.ld | 211 +++ .../device/TOOLCHAIN_GCC_ARM/startup_MPS2.S | 257 ++++ .../device/TOOLCHAIN_IAR/MPS2.icf | 56 + .../device/TOOLCHAIN_IAR/startup_MPS2.S | 340 +++++ .../TARGET_FVP_MPS2_M4/device/cmsis.h | 42 + .../TARGET_FVP_MPS2_M4/device/cmsis_nvic.h | 39 + .../device/peripherallink.h | 53 + .../device/system_CMSDK_CM4.c | 96 ++ .../device/system_CMSDK_CM4.h | 75 + 13 files changed, 3420 insertions(+) create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis_nvic.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h new file mode 100644 index 0000000000..7b49315127 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h @@ -0,0 +1,1300 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_CM4.h +* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for +* Device CMSDK_CM4 +* +*******************************************************************************/ + + +#ifndef CMSDK_CM4_H +#define CMSDK_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/****** CMSDK Specific Interrupt Numbers *********************************************************/ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Core Revision r0p1 */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +/*@}*/ /* end of group CMSDK_CM4_CMSIS */ + + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_CMSDK_CM4.h" /* CMSDK_CM4 System include file */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +/** @addtogroup CMSDK_CM4_Peripherals CMSDK_CM4 Peripherals + CMSDK_CM4 Device Specific Peripheral registers structures + @{ +*/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** @addtogroup CMSDK_UART CMSDK Universal Asynchronous Receiver/Transmitter + memory mapped structure for CMSDK_UART + @{ +*/ +typedef struct +{ + __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ + __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ + __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ + }; + __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /*!< CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /*!< CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /*!< CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /*!< CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /*!< CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /*!< CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /*!< CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /*!< CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /*!< CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /*!< CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /*!< CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /*!< CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /*!< CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /*!< CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /*!< CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /*!< CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /*!< CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /*!< CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /*!< CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /*!< CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /*!< CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /*!< CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /*!< CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /*!< CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /*!< CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /*!< CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /*!< CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /*!< CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /*!< CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /*!< CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /*!< CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /*!< CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /*!< CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /*!< CMSDK_UART BAUDDIV: BAUDDIV Mask */ + +/*@}*/ /* end of group CMSDK_UART */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +/** @addtogroup CMSDK_TIMER CMSDK Timer + @{ +*/ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ + __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */ + __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /*!< CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /*!< CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /*!< CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /*!< CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /*!< CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /*!< CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /*!< CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /*!< CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /*!< CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /*!< CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /*!< CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /*!< CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /*!< CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /*!< CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + +/*@}*/ /* end of group CMSDK_TIMER */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +// Timer (TIM) + +/** @addtogroup CMSDK_DualTIMER CMSDK Dual Timer + @{ +*/ + +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /*!< CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /*!< CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /*!< CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /*!< CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /*!< CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /*!< CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /*!< CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /*!< CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /*!< CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /*!< CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /*!< CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /*!< CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + +/*@}*/ /* end of group CMSDK_DualTIMER */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +/** @addtogroup CMSDK_GPIO CMSDK GPIO + @{ +*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /*!< CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /*!< CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /*!< CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + +/*@}*/ /* end of group CMSDK_GPIO */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +/** @addtogroup CMSDK_SYSCON CMSDK System Control + @{ +*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /*!< CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /*!< CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /*!< CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /*!< CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /*!< CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /*!< CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + +/*@}*/ /* end of group CMSDK_SYSCON */ + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +/** @addtogroup CMSDK_PL230 CMSDK uDMA controller + @{ +*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /*!< CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /*!< CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /*!< CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /*!< CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /*!< CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /*!< CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /*!< CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /*!< CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /*!< CMSDK_PL230 ERR: CLR Mask */ + + +/*@}*/ /* end of group CMSDK_PL230 */ + + +/*------------- PrimeCell UART (PL110) --------------------------------------*/ +/** @addtogroup CMSDK_PL110 CMSDK PrimeCell UART + @{ +*/ + +typedef struct +{ + __IO uint32_t UARTDR; // Data + // OE: Overrun error + // BE: Break error + // PE: Parity error + // FE: Framing error + // DATA: Received or Transmitting data (0..255) + // + union { + __I uint32_t UARTRSR; // Receive Status + // OE: Overrun error + // BE: Break error + // PE: Parity error + // FE: Framing error + // + __O uint32_t UARTECR; // Error Clear + // OE: Overrun error + // BE: Break error + // PE: Parity error + // FE: Framing error + // + }; + uint32_t RESERVED0[4]; + __IO uint32_t UARTFR; // Flags + // RI: Ring indicator + // TXFE: Transmit FIFO empty + // RXFF: Receive FIFO full + // TXFF: Transmit FIFO full + // RXFE: Receive FIFO empty + // BUSY: UART busy + // DCD: Data carrier detect + // DSR: Data set ready + // CTS: Clear to send + // + uint32_t RESERVED1; + __IO uint32_t UARTILPR; // IrDA Low-power Counter + // ILPDVSR: 8-bit low-power divisor value (0..255) + // + __IO uint32_t UARTIBRD; // Integer Baud Rate + // BAUD DIVINT: Integer baud rate divisor (0..65535) + // + __IO uint32_t UARTFBRD; // Fractional Baud Rate + // BAUD DIVFRAC: Fractional baud rate divisor (0..63) + // + __IO uint32_t UARTLCR_H; // Line Control + // SPS: Stick parity select + // WLEN: Word length + // <0=> 5 bits + // <1=> 6 bits + // <2=> 7 bits + // <3=> 8 bits + // FEN: Enable FIFOs + // STP2: Two stop bits select + // EPS: Even parity select + // PEN: Parity enable + // BRK: Send break + // + __IO uint32_t UARTCR; // Control + // CTSEn: CTS hardware flow control enable + // RTSEn: RTS hardware flow control enable + // Out2: Complement of Out2 modem status output + // Out1: Complement of Out1 modem status output + // RTS: Request to send + // DTR: Data transmit ready + // RXE: Receive enable + // TXE: Transmit enable + // LBE: Loop-back enable + // SIRLP: IrDA SIR low power mode + // SIREN: SIR enable + // UARTEN: UART enable + // + __IO uint32_t UARTIFLS; // Interrupt FIFO Level Select + // RXIFLSEL: Receive interrupt FIFO level select + // <0=> >= 1/8 full + // <1=> >= 1/4 full + // <2=> >= 1/2 full + // <3=> >= 3/4 full + // <4=> >= 7/8 full + // <5=> reserved + // <6=> reserved + // <7=> reserved + // TXIFLSEL: Transmit interrupt FIFO level select + // <0=> <= 1/8 full + // <1=> <= 1/4 full + // <2=> <= 1/2 full + // <3=> <= 3/4 full + // <4=> <= 7/8 full + // <5=> reserved + // <6=> reserved + // <7=> reserved + // + __IO uint32_t UARTIMSC; // Interrupt Mask Set / Clear + // OEIM: Overrun error interrupt mask + // BEIM: Break error interrupt mask + // PEIM: Parity error interrupt mask + // FEIM: Framing error interrupt mask + // RTIM: Receive interrupt mask + // TXIM: Transmit interrupt mask + // RXIM: Receive interrupt mask + // DSRMIM: nUARTDSR modem interrupt mask + // DCDMIM: nUARTDCD modem interrupt mask + // CTSMIM: nUARTCTS modem interrupt mask + // RIMIM: nUARTRI modem interrupt mask + // + __IO uint32_t UARTRIS; // Raw Interrupt Status + // OERIS: Overrun error interrupt status + // BERIS: Break error interrupt status + // PERIS: Parity error interrupt status + // FERIS: Framing error interrupt status + // RTRIS: Receive timeout interrupt status + // TXRIS: Transmit interrupt status + // RXRIS: Receive interrupt status + // DSRRMIS: nUARTDSR modem interrupt status + // DCDRMIS: nUARTDCD modem interrupt status + // CTSRMIS: nUARTCTS modem interrupt status + // RIRMIS: nUARTRI modem interrupt status + // + __IO uint32_t UARTMIS; // Masked Interrupt Status + // OEMIS: Overrun error masked interrupt status + // BEMIS: Break error masked interrupt status + // PEMIS: Parity error masked interrupt status + // FEMIS: Framing error masked interrupt status + // RTMIS: Receive timeout masked interrupt status + // TXMIS: Transmit masked interrupt status + // RXMIS: Receive masked interrupt status + // DSRMMIS: nUARTDSR modem masked interrupt status + // DCDMMIS: nUARTDCD modem masked interrupt status + // CTSMMIS: nUARTCTS modem masked interrupt status + // RIMMIS: nUARTRI modem masked interrupt status + // + __O uint32_t UARTICR; // Interrupt Clear + // OEIC: Overrun error interrupt clear + // BEIC: Break error interrupt clear + // PEIC: Parity error interrupt clear + // FEIC: Framing error interrupt clear + // RTIC: Receive timeout interrupt clear + // TXIC: Transmit interrupt clear + // RXIC: Receive interrupt clear + // DSRMIC: nUARTDSR modem interrupt clear + // DCDMIC: nUARTDCD modem interrupt clear + // CTSMIC: nUARTCTS modem interrupt clear + // RIMIC: nUARTRI modem interrupt clear + // + __IO uint32_t UARTDMACR; // DMA Control + // DMAONERR: DMA on error + // TXDMAE: Transmit DMA enable + // RXDMAE: Receive DMA enable + // +} PL110_UART_TypeDef; + +#define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */ +#define CMSDK_PL110_DATAOVRRUN_Msk (0x1ul << CMSDK_PL110_DATAOVRRUN_Pos) /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Mask */ + +#define CMSDK_PL110_DATABREAKERR_Pos 10 /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Position */ +#define CMSDK_PL110_DATABREAKERR_Msk (0x1ul << CMSDK_PL110_DATABREAKERR_Pos) /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Mask */ + +#define CMSDK_PL110_DATAPARITYERR_Pos 9 /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Position */ +#define CMSDK_PL110_DATAPARITYERR_Msk (0x1ul << CMSDK_PL110_DATAPARITYERR_Pos) /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Mask */ + +#define CMSDK_PL110_DATAFRAMEERR_Pos 8 /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Position */ +#define CMSDK_PL110_DATAFRAMEERR_Msk (0x1ul << CMSDK_PL110_DATAFRAMEERR_Pos) /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Mask */ + +#define CMSDK_PL110_RECOVRRUN_Pos 3 /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Position */ +#define CMSDK_PL110_RECOVRRUN_Msk (0x1ul << CMSDK_PL110_RECOVRRUN_Pos) /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Mask */ + +#define CMSDK_PL110_RECBREAKERR_Pos 2 /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Position */ +#define CMSDK_PL110_RECBREAKERR_Msk (0x1ul << CMSDK_PL110_RECBREAKERR_Pos) /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Mask */ + +#define CMSDK_PL110_RECPARITYERR_Pos 1 /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Position */ +#define CMSDK_PL110_RECPARITYERR_Msk (0x1ul << CMSDK_PL110_RECPARITYERR_Pos) /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Mask */ + +#define CMSDK_PL110_RECFRAMEERR_Pos 0 /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Position */ +#define CMSDK_PL110_RECFRAMEERR_Msk (0x1ul << CMSDK_PL110_RECFRAMEERR_Pos) /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Mask */ + +#define CMSDK_PL110_ERRCLROVRRUN_Pos 3 /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Position */ +#define CMSDK_PL110_ERRCLROVRRUN_Msk (0x1ul << CMSDK_PL110_ERRCLROVRRUN_Pos) /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Mask */ + +#define CMSDK_PL110_ERRCLRBREAKERR_Pos 2 /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Position */ +#define CMSDK_PL110_ERRCLRBREAKERR_Msk (0x1ul << CMSDK_PL110_ERRCLRBREAKERR_Pos) /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Mask */ + +#define CMSDK_PL110_ERRCLRPARITYERR_Pos 1 /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Position */ +#define CMSDK_PL110_ERRCLRPARITYERR_Msk (0x1ul << CMSDK_PL110_ERRCLRPARITYERR_Pos) /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Mask */ + +#define CMSDK_PL110_ERRCLRFRAMEERR_Pos 0 /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Position */ +#define CMSDK_PL110_ERRCLRFRAMEERR_Msk (0x1ul << CMSDK_PL110_ERRCLRFRAMEERR_Pos) /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Mask */ + +#define CMSDK_PL110_FLAG_RINGIND_Pos 8 /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Position */ +#define CMSDK_PL110_FLAG_RINGIND_Msk (0x1ul << CMSDK_PL110_FLAG_RINGIND_Pos) /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Mask */ + +#define CMSDK_PL110_FLAG_TXFEMPTY_Pos 7 /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Position */ +#define CMSDK_PL110_FLAG_TXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_TXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Mask */ + +#define CMSDK_PL110_FLAG_RXFFULL_Pos 6 /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Position */ +#define CMSDK_PL110_FLAG_RXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_RXFFULL_Pos) /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Mask */ + +#define CMSDK_PL110_FLAG_TXFFULL_Pos 5 /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Position */ +#define CMSDK_PL110_FLAG_TXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_TXFFULL_Pos) /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Mask */ + +#define CMSDK_PL110_FLAG_RXFEMPTY_Pos 4 /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Position */ +#define CMSDK_PL110_FLAG_RXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_RXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Mask */ + +#define CMSDK_PL110_FLAG_UARTBUSY_Pos 3 /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Position */ +#define CMSDK_PL110_FLAG_UARTBUSY_Msk (0x1ul << CMSDK_PL110_FLAG_UARTBUSY_Pos) /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Mask */ + +#define CMSDK_PL110_FLAG_CARRIERDETECT_Pos 2 /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Position */ +#define CMSDK_PL110_FLAG_CARRIERDETECT_Msk (0x1ul << CMSDK_PL110_FLAG_CARRIERDETECT_Pos) /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Mask */ + +#define CMSDK_PL110_FLAG_DATASETREADY_Pos 1 /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Position */ +#define CMSDK_PL110_FLAG_DATASETREADY_Msk (0x1ul << CMSDK_PL110_FLAG_DATASETREADY_Pos) /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Mask */ + +#define CMSDK_PL110_FLAG_CLR2SEND_Pos 0 /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Position */ +#define CMSDK_PL110_FLAG_CLR2SEND_Msk (0x1ul << CMSDK_PL110_FLAG_CLR2SEND_Pos) /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Mask */ + +#define CMSDK_PL110_IRDALOWPOWERCOUNT_Pos 0 /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Position */ +#define CMSDK_PL110_IRDALOWPOWERCOUNT_Msk (0xFFul << CMSDK_PL110_IRDALOWPOWERCOUNT_Pos) /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Mask */ + +#define CMSDK_PL110_INTDIVIDER_Pos 0 /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Position */ +#define CMSDK_PL110_INTDIVIDER_Msk (0xFFFFul << CMSDK_PL110_INTDIVIDER_Pos) /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Mask */ + +#define CMSDK_PL110_FRACTDIVIDER_Pos 0 /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Position */ +#define CMSDK_PL110_FRACTDIVIDER_Msk (0x3Ful << CMSDK_PL110_FRACTDIVIDER_Pos) /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Mask */ + +#define CMSDK_PL110_STICKPARITYSEL_Pos 8 /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Position */ +#define CMSDK_PL110_STICKPARITYSEL_Msk (0x1ul << CMSDK_PL110_STICKPARITYSEL_Pos) /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Mask */ + +#define CMSDK_PL110_WORDLEN_Pos 5 /*!< CMSDK_PL110 WORDLEN: Word Length Select Position */ +#define CMSDK_PL110_WORDLEN_Msk (0x3ul << CMSDK_PL110_WORDLEN_Pos) /*!< CMSDK_PL110 WORDLEN: Word Length Select Mask */ + +#define CMSDK_PL110_ENFIFOS_Pos 4 /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Position */ +#define CMSDK_PL110_ENFIFOS_Msk (0x1ul << CMSDK_PL110_ENFIFOS_Pos) /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Mask */ + +#define CMSDK_PL110_2STOPBITS_Pos 3 /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Position */ +#define CMSDK_PL110_2STOPBITS_Msk (0x1ul << CMSDK_PL110_2STOPBITS_Pos) /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Mask */ + +#define CMSDK_PL110_EVENPARITY_Pos 2 /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Position */ +#define CMSDK_PL110_EVENPARITY_Msk (0x1ul << CMSDK_PL110_EVENPARITY_Pos) /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Mask */ + +#define CMSDK_PL110_PARITYEN_Pos 1 /*!< CMSDK_PL110 PARITYEN: Parity Enable Position */ +#define CMSDK_PL110_PARITYEN_Msk (0x1ul << CMSDK_PL110_PARITYEN_Pos) /*!< CMSDK_PL110 PARITYEN: Parity Enable Mask */ + +#define CMSDK_PL110_SENDBREAK_Pos 0 /*!< CMSDK_PL110 SENDBREAK: Send Break Position */ +#define CMSDK_PL110_SENDBREAK_Msk (0x1ul << CMSDK_PL110_SENDBREAK_Pos) /*!< CMSDK_PL110 SENDBREAK: Send Break Mask */ + +#define CMSDK_PL110_CTS_FLOWCTRL_Pos 15 /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Position */ +#define CMSDK_PL110_CTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_CTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Mask */ + +#define CMSDK_PL110_RTS_FLOWCTRL_Pos 14 /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Position */ +#define CMSDK_PL110_RTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_RTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Mask */ + +#define CMSDK_PL110_OUT2_Pos 13 /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Position */ +#define CMSDK_PL110_OUT2_Msk (0x1ul << CMSDK_PL110_OUT2_Pos) /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Mask */ + +#define CMSDK_PL110_OUT1_Pos 12 /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Position */ +#define CMSDK_PL110_OUT1_Msk (0x1ul << CMSDK_PL110_OUT1_Pos) /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Mask */ + +#define CMSDK_PL110_REQ2SEND_Pos 11 /*!< CMSDK_PL110 REQ2SEND: Request To Send Position */ +#define CMSDK_PL110_REQ2SEND_Msk (0x1ul << CMSDK_PL110_REQ2SEND_Pos) /*!< CMSDK_PL110 REQ2SEND: Request To Send Mask */ + +#define CMSDK_PL110_DATATRANSREADY_Pos 10 /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Position */ +#define CMSDK_PL110_DATATRANSREADY_Msk (0x1ul << CMSDK_PL110_DATATRANSREADY_Pos) /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Mask */ + +#define CMSDK_PL110_RXEN_Pos 9 /*!< CMSDK_PL110 RXEN: Receive Enable Position */ +#define CMSDK_PL110_RXEN_Msk (0x1ul << CMSDK_PL110_RXEN_Pos) /*!< CMSDK_PL110 RXEN: Receive Enable Mask */ + +#define CMSDK_PL110_TXEN_Pos 8 /*!< CMSDK_PL110 TXEN: Transmit Enable Position */ +#define CMSDK_PL110_TXEN_Msk (0x1ul << CMSDK_PL110_TXEN_Pos) /*!< CMSDK_PL110 TXEN: Transmit Enable Mask */ + +#define CMSDK_PL110_LOOPBACKEN_Pos 7 /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Position */ +#define CMSDK_PL110_LOOPBACKEN_Msk (0x1ul << CMSDK_PL110_LOOPBACKEN_Pos) /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Mask */ + +#define CMSDK_PL110_IRDASIRLPM_Pos 2 /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Position */ +#define CMSDK_PL110_IRDASIRLPM_Msk (0x1ul << CMSDK_PL110_IRDASIRLPM_Pos) /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Mask */ + +#define CMSDK_PL110_SIREN_Pos 1 /*!< CMSDK_PL110 SIREN: SIR Enable Position */ +#define CMSDK_PL110_SIREN_Msk (0x1ul << CMSDK_PL110_SIREN_Pos) /*!< CMSDK_PL110 SIREN: SIR Enable Mask */ + +#define CMSDK_PL110_UARTEN_Pos 0 /*!< CMSDK_PL110 UARTEN: UART Enable Position */ +#define CMSDK_PL110_UARTEN_Msk (0x1ul << CMSDK_PL110_UARTEN_Pos) /*!< CMSDK_PL110 UARTEN: UART Enable Mask */ + +#define CMSDK_PL110_RECINTFIFOLEVEL_Pos 3 /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Position */ +#define CMSDK_PL110_RECINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_RECINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Mask */ + +#define CMSDK_PL110_TRANSINTFIFOLEVEL_Pos 0 /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Position */ +#define CMSDK_PL110_TRANSINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_TRANSINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Mask */ + +#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Position */ +#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Position */ +#define CMSDK_PL110_SETMASK_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_BREAKERRINT_Pos) /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Position */ +#define CMSDK_PL110_SETMASK_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_PARITYERRINT_Pos) /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Position */ +#define CMSDK_PL110_SETMASK_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_FRAMEERRINT_Pos) /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Position */ +#define CMSDK_PL110_SETMASK_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECTRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_TRANSINT_Pos 5 /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Position */ +#define CMSDK_PL110_SETMASK_TRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_TRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_RECINT_Pos 4 /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Position */ +#define CMSDK_PL110_SETMASK_RECINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECINT_Pos) /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Position */ +#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Position */ +#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Position */ +#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Mask */ + +#define CMSDK_PL110_SETMASK_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Position */ +#define CMSDK_PL110_SETMASK_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_RIMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Mask */ + +#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask Position */ +#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask Position */ +#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask Position */ +#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask Position */ +#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Position */ +#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Position */ +#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Position */ +#define CMSDK_PL110_RAWINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 RAWINTSTAT_UART_DSRMODINT: Raw Data Set Ready Int Status Position */ +#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UARTD_SRMODINT: Raw Data Set Ready Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Position */ +#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Position */ +#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Mask */ + +#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Position */ +#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Mask */ + +#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Position */ +#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Mask */ + +#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Position */ +#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Mask */ + +#define CMSDK_PL110_INTCLR_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Position */ +#define CMSDK_PL110_INTCLR_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_BREAKERRINT_Pos) /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Mask */ + +#define CMSDK_PL110_INTCLR_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Position */ +#define CMSDK_PL110_INTCLR_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_PARITYERRINT_Pos) /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Mask */ + +#define CMSDK_PL110_INTCLR_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Position */ +#define CMSDK_PL110_INTCLR_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_FRAMEERRINT_Pos) /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Mask */ + +#define CMSDK_PL110_INTCLR_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Position */ +#define CMSDK_PL110_INTCLR_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECTRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Mask */ + +#define CMSDK_PL110_INTCLR_TRANSINT_Pos 5 /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Position */ +#define CMSDK_PL110_INTCLR_TRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_TRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Mask */ + +#define CMSDK_PL110_INTCLR_RECINT_Pos 4 /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Position */ +#define CMSDK_PL110_INTCLR_RECINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECINT_Pos) /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Mask */ + +#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 INTCLR_UART_DSRMODINT: Clear Data Carrier Detect Int Position */ +#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UARTD_SRMODINT: Clear Data Carrier Detect Int Mask */ + +#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Position */ +#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Mask */ + +#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Position */ +#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Mask */ + +#define CMSDK_PL110_INTCLR_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Position */ +#define CMSDK_PL110_INTCLR_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_RIMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Mask */ + +#define CMSDK_PL110_DMA_ERR_Pos 2 /*!< CMSDK_PL110 DMA_ERR: DMA Error Position */ +#define CMSDK_PL110_DMA_ERR_Msk (0x1ul << CMSDK_PL110_DMA_ERR_Pos) /*!< CMSDK_PL110 DMA_ERR: DMA Error Mask */ + +#define CMSDK_PL110_DMA_TRANS_EN_Pos 1 /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Position */ +#define CMSDK_PL110_DMA_TRANS_EN_Msk (0x1ul << CMSDK_PL110_DMA_TRANS_EN_Pos) /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Mask */ + +#define CMSDK_PL110_DMA_REC_EN_Pos 0 /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Position */ +#define CMSDK_PL110_DMA_REC_EN_Msk (0x1ul << CMSDK_PL110_DMA_REC_EN_Pos) /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Mask */ + + +/*@}*/ /* end of group CMSDK_PL110 */ + +/*------------------- Watchdog ----------------------------------------------*/ +/** @addtogroup CMSDK_Watchdog CMSDK Watchdog + @{ +*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + /* RESEN: Reset enable */ + /* INTEN: Interrupt enable */ + /* */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /*!< CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /*!< CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /*!< CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /*!< CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /*!< CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /*!< CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + +/*@}*/ /* end of group CMSDK_Watchdog */ + +/*------------------- PrimeCell APB GPIO --------------------------------------*/ +/** @addtogroup CMSDK_PL061 CMSDK APB GPIO + @{ +*/ +typedef struct +{ + +__IO uint32_t DATA[256]; +__IO uint32_t DIR; +__IO uint32_t INTSENSE; +__IO uint32_t INTBOTHEDGE; +__IO uint32_t INTEVENT; +__IO uint32_t INTMASK; +__O uint32_t RAWINTSTAT; +__O uint32_t MASKINTSTAT; +__I uint32_t INTCLR; +__IO uint32_t MODECTRL; + +}APBGPIO_TypeDef; + +#define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */ +#define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */ + +#define CMSDK_PL061_DIR_Pos 0 /*!< CMSDK_PL061 DIR: Data Direction Position */ +#define CMSDK_PL061_DIR_Msk (0x1ul << CMSDK_PL061_DIR_Pos) /*!< CMSDK_PL061 DIR: Data Direction Mask */ + +#define CMSDK_PL061_INTSENSE_Pos 0 /*!< CMSDK_PL061 INTSENSE: INT SENSE Position */ +#define CMSDK_PL061_INTSENSE_Msk (0x1ul << CMSDK_PL061_INTSENSE_Pos) /*!< CMSDK_PL061 INTSENSE: INT SENSE Mask */ + +#define CMSDK_PL061_INTBOTHEDGE_Pos 0 /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Position */ +#define CMSDK_PL061_INTBOTHEDGE_Msk (0x1ul << CMSDK_PL061_INTBOTHEDGE_Pos) /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Mask */ + +#define CMSDK_PL061_INTEVENT_Pos 0 /*!< CMSDK_PL061 INTEVENT: INT EVENT Position */ +#define CMSDK_PL061_INTEVENT_Msk (0x1ul << CMSDK_PL061_INTEVENT_Pos) /*!< CMSDK_PL061 INTEVENT: INT EVENT Mask */ + +#define CMSDK_PL061_INTMASK_Pos 0 /*!< CMSDK_PL061 INTMASK: INT MASK Position */ +#define CMSDK_PL061_INTMASK_Msk (0x1ul << CMSDK_PL061_INTMASK_Pos) /*!< CMSDK_PL061 INTMASK: INT MASK Mask */ + +#define CMSDK_PL061_RAWINTSTAT_Pos 0 /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_PL061_RAWINTSTAT_Msk (0x1ul << CMSDK_PL061_RAWINTSTAT_Pos) /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_PL061_MASKINTSTAT_Pos 0 /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_PL061_MASKINTSTAT_Msk (0x1ul << CMSDK_PL061_MASKINTSTAT_Pos) /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_PL061_INTCLR_Pos 0 /*!< CMSDK_PL061 INTCLR: Int Clear Position */ +#define CMSDK_PL061_INTCLR_Msk (0x1ul << CMSDK_PL061_INTCLR_Pos) /*!< CMSDK_PL061 INTCLR: Int Clear Mask */ + +#define CMSDK_PL061_MODECTRL_HWEN_Pos 0 /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Position */ +#define CMSDK_PL061_MODECTRL_HWEN_Msk (0x1ul << CMSDK_PL061_MODECTRL_HWEN_Pos) /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Mask */ + + +/*@}*/ /* end of group CMSDK_PL061 */ + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/*@}*/ /* end of group CMSDK_CM4_Peripherals */ + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup CMSDK_CM4_MemoryMap CMSDK_CM4 Memory Mapping + @{ +*/ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ +#define CMSDK_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define CMSDK_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ + +/* Base addresses */ +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) +#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) +/*@}*/ /* end of group CMSDK_CM4_MemoryMap */ + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +/** @addtogroup CMSDK_CM4_PeripheralDecl CMSDK_CM4 Peripheral Declaration + @{ +*/ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) +/*@}*/ /* end of group CMSDK_CM4_PeripheralDecl */ + +/*@}*/ /* end of group CMSDK_CM4_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_CM4_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h new file mode 100644 index 0000000000..6b2a5ac3d7 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h @@ -0,0 +1,614 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* File: smm_mps2.h +* Release: Version 1.1 +*******************************************************************************/ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld new file mode 100644 index 0000000000..2d020431a9 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld @@ -0,0 +1,211 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 gcc_arm.ld + */ +/* Linker script for mbed FVP Cortex-M4 on MPS2 */ + +/* Linker script to configure memory regions. */ +/* The length of the VECTORS region is a bit larger than + * is necessary based on the number of exception handlers. + */ +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x4000; +STACK_SIZE = 0x1000; + +/* Size of the vector table in SRAM */ +M_VECTOR_RAM_SIZE = 0x140; + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(4); + } > VECTORS + + .text : + { + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > RAM + + .data : + { + PROVIDE(__etext = LOADADDR(.data)); + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + + } > RAM + + bss_size = __bss_end__ - __bss_start__; + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + +} /* End of sections */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S new file mode 100644 index 0000000000..57dc8d21f2 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S @@ -0,0 +1,257 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 startup_ARMCM4.S + */ + .syntax unified + .arch armv7-m + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */ + .long Spare_IRQHandler /* 1: Undefined */ + .long UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */ + .long APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */ + .long APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */ + .long RTC_IRQHandler /* 5: RTC Interrupt */ + .long PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */ + .long PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */ + .long TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */ + .long TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */ + .long DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */ + .long APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */ + .long UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */ + .long APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */ + .long RESERVED0_IRQHandler /* 14: Reserved */ + .long TSC_IRQHandler /* 15: Touch Screen Interrupt */ + .long PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */ + .long PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */ + .long PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */ + .long PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */ + .long PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */ + .long PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */ + .long PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */ + .long PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */ + .long PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */ + .long PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */ + .long PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */ + .long PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */ + .long PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */ + .long PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */ + .long PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */ + .long PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */ + .long FLASH0_IRQHandler /* 32: Reserved for Flash */ + .long FLASH1_IRQHandler /* 33: Reserved for Flash */ + .long RESERVED1_IRQHandler /* 34: Reserved */ + .long RESERVED2_IRQHandler /* 35: Reserved */ + .long RESERVED3_IRQHandler /* 36: Reserved */ + .long RESERVED4_IRQHandler /* 37: Reserved */ + .long RESERVED5_IRQHandler /* 38: Reserved */ + .long RESERVED6_IRQHandler /* 39: Reserved */ + .long RESERVED7_IRQHandler /* 40: Reserved */ + .long RESERVED8_IRQHandler /* 41: Reserved */ + .long PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */ + .long PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */ + .long TRNG_IRQHandler /* 44: Random number generator Interrupt */ + .long UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */ + .long UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */ + .long ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */ + .long I2S_IRQHandler /* 48: I2S Interrupt */ + .long MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */ + .long MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */ + .long MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */ + .long MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */ + .long MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */ + .long PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */ + .long PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */ + .long UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =SystemInit + blx r0 +/* + * Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. + */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + +/* Initialize .bss */ +init_bss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + ldr r3, =bss_size + + cmp r3, #0 + beq system_startup + + mov r4, #0 +zero: + strb r4, [r1], #1 + subs r3, r3, #1 + bne zero + +system_startup: + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* + * Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers + */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + /* External interrupts */ + def_irq_default_handler UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */ + def_irq_default_handler Spare_IRQHandler /* 1: Undefined */ + def_irq_default_handler UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */ + def_irq_default_handler APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */ + def_irq_default_handler APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */ + def_irq_default_handler RTC_IRQHandler /* 5: RTC Interrupt */ + def_irq_default_handler PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */ + def_irq_default_handler PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */ + def_irq_default_handler TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */ + def_irq_default_handler TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */ + def_irq_default_handler DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */ + def_irq_default_handler APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */ + def_irq_default_handler UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */ + def_irq_default_handler APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */ + def_irq_default_handler RESERVED0_IRQHandler /* 14: Reserved */ + def_irq_default_handler TSC_IRQHandler /* 15: Touch Screen Interrupt */ + def_irq_default_handler PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */ + def_irq_default_handler PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */ + def_irq_default_handler PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */ + def_irq_default_handler PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */ + def_irq_default_handler PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */ + def_irq_default_handler PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */ + def_irq_default_handler PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */ + def_irq_default_handler PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */ + def_irq_default_handler PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */ + def_irq_default_handler PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */ + def_irq_default_handler PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */ + def_irq_default_handler PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */ + def_irq_default_handler PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */ + def_irq_default_handler PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */ + def_irq_default_handler PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */ + def_irq_default_handler PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */ + def_irq_default_handler FLASH0_IRQHandler /* 32: Reserved for Flash */ + def_irq_default_handler FLASH1_IRQHandler /* 33: Reserved for Flash */ + def_irq_default_handler RESERVED1_IRQHandler /* 34: Reserved */ + def_irq_default_handler RESERVED2_IRQHandler /* 35: Reserved */ + def_irq_default_handler RESERVED3_IRQHandler /* 36: Reserved */ + def_irq_default_handler RESERVED4_IRQHandler /* 37: Reserved */ + def_irq_default_handler RESERVED5_IRQHandler /* 38: Reserved */ + def_irq_default_handler RESERVED6_IRQHandler /* 39: Reserved */ + def_irq_default_handler RESERVED7_IRQHandler /* 40: Reserved */ + def_irq_default_handler RESERVED8_IRQHandler /* 41: Reserved */ + def_irq_default_handler PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */ + def_irq_default_handler PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */ + def_irq_default_handler TRNG_IRQHandler /* 44: Random number generator Interrupt */ + def_irq_default_handler UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */ + def_irq_default_handler UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */ + def_irq_default_handler ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */ + def_irq_default_handler I2S_IRQHandler /* 48: I2S Interrupt */ + def_irq_default_handler MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */ + def_irq_default_handler MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */ + def_irq_default_handler MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */ + def_irq_default_handler MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */ + def_irq_default_handler MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */ + def_irq_default_handler PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */ + def_irq_default_handler PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */ + def_irq_default_handler UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */ + + .end diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf new file mode 100644 index 0000000000..60b104bcf3 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf @@ -0,0 +1,56 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License) you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* The RAM region doesn't start at the beginning of the RAM address + * space to create space for the vector table copied over to the RAM by mbed. + * The space left is a bit bigger than is necessary based on the number of + * interrupt handlers. + */ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000140; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +/* Heap and Stack size */ +define symbol __ICFEDIT_size_heap__ = 0x4000; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/startup_MPS2.S new file mode 100644 index 0000000000..fcabe102c9 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/startup_MPS2.S @@ -0,0 +1,340 @@ +;/* +; * MPS2 CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2018 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UARTRX0_Handler ; 0: UART 0 RX Handler + DCD UARTTX0_Handler ; 1: UART 0 TX Handler + DCD UARTRX1_Handler ; 2: UART 1 RX Handler + DCD UARTTX1_Handler ; 3: UART 1 TX Handler + DCD UARTRX2_Handler ; 4: UART 2 RX Handler + DCD UARTTX2_Handler ; 5: UART 2 TX Handler + DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; 8: TIMER 0 handler + DCD TIMER1_Handler ; 9: TIMER 1 handler + DCD DUALTIMER_HANDLER ; 10: Dual timer handler + DCD SPI_Handler ; 11: SPI exceptions Handler + DCD UARTOVF_Handler ; 12: UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; 13: Ethernet Overflow Handler + DCD I2S_Handler ; 14: I2S Handler + DCD TSC_Handler ; 15: Touch Screen handler + DCD PORT2_COMB_Handler ; 16: GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; 17: GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; 18: UART 3 RX Handler + DCD UARTTX3_Handler ; 19: UART 3 TX Handler + DCD UARTRX4_Handler ; 20: UART 4 RX Handler + DCD UARTTX4_Handler ; 21: UART 4 TX Handler + DCD ADCSPI_Handler ; 22: SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; 23: SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; 24: GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; 25: GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; 26: GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; 27: GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; 28: GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; 29: GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; 30: GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; 31: GPIO Port 0 pin 7 Handler + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UARTRX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX0_Handler + B UARTRX0_Handler + + PUBWEAK UARTTX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX0_Handler + B UARTTX0_Handler + + PUBWEAK UARTRX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX1_Handler + B UARTRX1_Handler + + PUBWEAK UARTTX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX1_Handler + B UARTTX1_Handler + + PUBWEAK UARTRX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX2_Handler + B UARTRX2_Handler + + PUBWEAK UARTTX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX2_Handler + B UARTTX2_Handler + + PUBWEAK PORT0_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_COMB_Handler + B PORT0_COMB_Handler + + PUBWEAK PORT1_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_COMB_Handler + B PORT1_COMB_Handler + + PUBWEAK TIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_Handler + B TIMER0_Handler + + PUBWEAK TIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_Handler + B TIMER1_Handler + + PUBWEAK DUALTIMER_HANDLER + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_HANDLER + B DUALTIMER_HANDLER + + PUBWEAK SPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI_Handler + B SPI_Handler + + PUBWEAK UARTOVF_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_Handler + B UARTOVF_Handler + + PUBWEAK ETHERNET_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ETHERNET_Handler + B ETHERNET_Handler + + PUBWEAK I2S_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S_Handler + B I2S_Handler + + PUBWEAK TSC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_Handler + B TSC_Handler + + PUBWEAK PORT2_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_COMB_Handler + B PORT2_COMB_Handler + + PUBWEAK PORT3_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_COMB_Handler + B PORT3_COMB_Handler + + PUBWEAK UARTRX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX3_Handler + B UARTRX3_Handler + + PUBWEAK UARTTX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX3_Handler + B UARTTX3_Handler + + PUBWEAK UARTRX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX4_Handler + B UARTRX4_Handler + + PUBWEAK UARTTX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX4_Handler + B UARTTX4_Handler + + PUBWEAK ADCSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADCSPI_Handler + B ADCSPI_Handler + + PUBWEAK SHIELDSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SHIELDSPI_Handler + B SHIELDSPI_Handler + + PUBWEAK PORT0_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_Handler + B PORT0_0_Handler + + PUBWEAK PORT0_1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_Handler + B PORT0_1_Handler + + PUBWEAK PORT0_2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_Handler + B PORT0_2_Handler + + PUBWEAK PORT0_3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_Handler + B PORT0_3_Handler + + PUBWEAK PORT0_4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_Handler + B PORT0_4_Handler + + PUBWEAK PORT0_5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_Handler + B PORT0_5_Handler + + PUBWEAK PORT0_6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_Handler + B PORT0_6_Handler + + PUBWEAK PORT0_7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_Handler + B PORT0_7_Handler + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis.h new file mode 100644 index 0000000000..bb04d163bf --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis.h @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM4.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis_nvic.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis_nvic.h new file mode 100644 index 0000000000..a564abfc18 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 48) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h new file mode 100644 index 0000000000..04fb9ba365 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c new file mode 100644 index 0000000000..81657dda17 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c @@ -0,0 +1,96 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file system_CMSDK_CM4.c +* @brief CMSIS Device System Source File for +* CMSDK_M4 Device +* +*******************************************************************************/ + + +#include "CMSDK_CM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (50000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h new file mode 100644 index 0000000000..8208fd832c --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h @@ -0,0 +1,75 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************* +* @file system_CMSDK_CM4.h +* @brief CMSIS Device Peripheral Access Layer Header File for +* CMSDK_CM4 Device +* +******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_CM4_H +#define SYSTEM_CMSDK_CM4_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_CMSDK_CM4_H */ From 67abec3998e0055a8b1bf197e2495dc0b1b64eba Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 14 May 2018 11:33:57 +0100 Subject: [PATCH 04/11] FastModels: add FVP_MPS2_M0 target support add cmsis drivers and toolchain scripts for FVP_MPS2_M0 --- .../TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h | 722 ++++++++++++++++++ .../TARGET_FVP_MPS2_M0/device/SMM_MPS2.h | 614 +++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MPS2.sct | 47 ++ .../device/TOOLCHAIN_ARM_STD/startup_MPS2.S | 270 +++++++ .../device/TOOLCHAIN_GCC_ARM/MPS2.ld | 211 +++++ .../device/TOOLCHAIN_GCC_ARM/startup_MPS2.S | 205 +++++ .../device/TOOLCHAIN_IAR/MPS2.icf | 56 ++ .../device/TOOLCHAIN_IAR/startup_MPS2.S | 320 ++++++++ .../TARGET_FVP_MPS2_M0/device/cmsis.h | 42 + .../TARGET_FVP_MPS2_M0/device/cmsis_nvic.c | 54 ++ .../TARGET_FVP_MPS2_M0/device/cmsis_nvic.h | 54 ++ .../device/peripherallink.h | 53 ++ .../device/system_CMSDK_CM0.c | 88 +++ .../device/system_CMSDK_CM0.h | 76 ++ 14 files changed, 2812 insertions(+) create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/SMM_MPS2.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h new file mode 100644 index 0000000000..b39cc0f8a3 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h @@ -0,0 +1,722 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_CM0.h +* @brief CMSIS Core Peripheral Access Layer Header File for +* CMSDK_CM0 Device +* +*******************************************************************************/ + + +#ifndef CMSDK_CM0_H +#define CMSDK_CM0_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */ +#define __CM0_REV 0x0000 /* Core revision r0p0 */ +#define __MPU_PRESENT 0 /* MPU present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_CM0.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined ( __CC_ARM ) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) +#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_M0_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/SMM_MPS2.h new file mode 100644 index 0000000000..3b78c8b44f --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/SMM_MPS2.h @@ -0,0 +1,614 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* File: smm_mps2.h +* Release: Version 1.1 +*******************************************************************************/ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld new file mode 100644 index 0000000000..7da273eae6 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld @@ -0,0 +1,211 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 gcc_arm.ld + */ +/* Linker script for mbed FVP Cortex-M0 on MPS2 */ + +/* Linker script to configure memory regions. */ +/* The length of the VECTORS region is a bit larger than + * is necessary based on the number of exception handlers. + */ +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x4000; +STACK_SIZE = 0x1000; + +/* Size of the vector table in SRAM */ +M_VECTOR_RAM_SIZE = 0x140; + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(4); + } > VECTORS + + .text : + { + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > RAM + + .data : + { + PROVIDE(__etext = LOADADDR(.data)); + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + + } > RAM + + bss_size = __bss_end__ - __bss_start__; + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + +} /* End of sections */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S new file mode 100644 index 0000000000..e82e72b469 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S @@ -0,0 +1,205 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 startup_ARMCM3.S + */ + .syntax unified + .arch armv6-m + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long UARTRX0_Handler /* UART 0 RX Handler */ + .long UARTTX0_Handler /* UART 0 TX Handler */ + .long UARTRX1_Handler /* UART 1 RX Handler */ + .long UARTTX1_Handler /* UART 1 TX Handler */ + .long UARTRX2_Handler /* UART 2 RX Handler */ + .long UARTTX2_Handler /* UART 2 TX Handler */ + .long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */ + .long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */ + .long TIMER0_Handler /* TIMER 0 handler */ + .long TIMER1_Handler /* TIMER 1 handler */ + .long DUALTIMER_HANDLER /* Dual timer handler */ + .long SPI_Handler /* SPI exceptions Handler */ + .long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */ + .long ETHERNET_Handler /* Ethernet Overflow Handler */ + .long I2S_Handler /* I2S Handler */ + .long TSC_Handler /* Touch Screen handler */ + .long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */ + .long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */ + .long UARTRX3_Handler /* UART 3 RX Handler */ + .long UARTTX3_Handler /* UART 3 TX Handler */ + .long UARTRX4_Handler /* UART 4 RX Handler */ + .long UARTTX4_Handler /* UART 4 TX Handler */ + .long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */ + .long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */ + .long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */ + .long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */ + .long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */ + .long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */ + .long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */ + .long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */ + .long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */ + .long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =SystemInit + blx r0 +/* + * Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. + */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + +/* Initialize .bss */ +init_bss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + ldr r3, =bss_size + + movs r0, 0 + + subs r2, r1 + ble .L_zero_done + +.L_zero: + subs r2, #4 + str r0, [r1, r2] + bgt .L_zero +.L_zero_done: + +system_startup: + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* + * Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers + */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + /* External interrupts */ + def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */ + def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */ + def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */ + def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */ + def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */ + def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */ + def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 Combined Handler */ + def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 Combined Handler */ + def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 handler */ + def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 handler */ + def_irq_default_handler DUALTIMER_HANDLER /* 10: Dual timer handler */ + def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */ + def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */ + def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */ + def_irq_default_handler I2S_Handler /* 14: I2S Handler */ + def_irq_default_handler TSC_Handler /* 15: Touch Screen handler */ + def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 Combined Handler */ + def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 Combined Handler */ + def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */ + def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */ + def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */ + def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */ + def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handler */ + def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handler */ + def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */ + def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */ + def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */ + def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */ + def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */ + def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */ + def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */ + def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */ + + .end diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf new file mode 100644 index 0000000000..60b104bcf3 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf @@ -0,0 +1,56 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License) you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* The RAM region doesn't start at the beginning of the RAM address + * space to create space for the vector table copied over to the RAM by mbed. + * The space left is a bit bigger than is necessary based on the number of + * interrupt handlers. + */ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000140; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +/* Heap and Stack size */ +define symbol __ICFEDIT_size_heap__ = 0x4000; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/startup_MPS2.S new file mode 100644 index 0000000000..6ae40b0dfe --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/startup_MPS2.S @@ -0,0 +1,320 @@ +;/* +; * MPS2 CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2018 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UARTRX0_Handler ; 0: UART 0 RX Handler + DCD UARTTX0_Handler ; 1: UART 0 TX Handler + DCD UARTRX1_Handler ; 2: UART 1 RX Handler + DCD UARTTX1_Handler ; 3: UART 1 TX Handler + DCD UARTRX2_Handler ; 4: UART 2 RX Handler + DCD UARTTX2_Handler ; 5: UART 2 TX Handler + DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; 8: TIMER 0 handler + DCD TIMER1_Handler ; 9: TIMER 1 handler + DCD DUALTIMER_HANDLER ; 10: Dual timer handler + DCD SPI_Handler ; 11: SPI exceptions Handler + DCD UARTOVF_Handler ; 12: UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; 13: Ethernet Overflow Handler + DCD I2S_Handler ; 14: I2S Handler + DCD TSC_Handler ; 15: Touch Screen handler + DCD PORT2_COMB_Handler ; 16: GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; 17: GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; 18: UART 3 RX Handler + DCD UARTTX3_Handler ; 19: UART 3 TX Handler + DCD UARTRX4_Handler ; 20: UART 4 RX Handler + DCD UARTTX4_Handler ; 21: UART 4 TX Handler + DCD ADCSPI_Handler ; 22: SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; 23: SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; 24: GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; 25: GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; 26: GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; 27: GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; 28: GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; 29: GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; 30: GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; 31: GPIO Port 0 pin 7 Handler + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UARTRX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX0_Handler + B UARTRX0_Handler + + PUBWEAK UARTTX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX0_Handler + B UARTTX0_Handler + + PUBWEAK UARTRX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX1_Handler + B UARTRX1_Handler + + PUBWEAK UARTTX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX1_Handler + B UARTTX1_Handler + + PUBWEAK UARTRX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX2_Handler + B UARTRX2_Handler + + PUBWEAK UARTTX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX2_Handler + B UARTTX2_Handler + + PUBWEAK PORT0_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_COMB_Handler + B PORT0_COMB_Handler + + PUBWEAK PORT1_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_COMB_Handler + B PORT1_COMB_Handler + + PUBWEAK TIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_Handler + B TIMER0_Handler + + PUBWEAK TIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_Handler + B TIMER1_Handler + + PUBWEAK DUALTIMER_HANDLER + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_HANDLER + B DUALTIMER_HANDLER + + PUBWEAK SPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI_Handler + B SPI_Handler + + PUBWEAK UARTOVF_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_Handler + B UARTOVF_Handler + + PUBWEAK ETHERNET_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ETHERNET_Handler + B ETHERNET_Handler + + PUBWEAK I2S_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S_Handler + B I2S_Handler + + PUBWEAK TSC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_Handler + B TSC_Handler + + PUBWEAK PORT2_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_COMB_Handler + B PORT2_COMB_Handler + + PUBWEAK PORT3_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_COMB_Handler + B PORT3_COMB_Handler + + PUBWEAK UARTRX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX3_Handler + B UARTRX3_Handler + + PUBWEAK UARTTX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX3_Handler + B UARTTX3_Handler + + PUBWEAK UARTRX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX4_Handler + B UARTRX4_Handler + + PUBWEAK UARTTX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX4_Handler + B UARTTX4_Handler + + PUBWEAK ADCSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADCSPI_Handler + B ADCSPI_Handler + + PUBWEAK SHIELDSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SHIELDSPI_Handler + B SHIELDSPI_Handler + + PUBWEAK PORT0_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_Handler + B PORT0_0_Handler + + PUBWEAK PORT0_1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_Handler + B PORT0_1_Handler + + PUBWEAK PORT0_2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_Handler + B PORT0_2_Handler + + PUBWEAK PORT0_3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_Handler + B PORT0_3_Handler + + PUBWEAK PORT0_4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_Handler + B PORT0_4_Handler + + PUBWEAK PORT0_5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_Handler + B PORT0_5_Handler + + PUBWEAK PORT0_6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_Handler + B PORT0_6_Handler + + PUBWEAK PORT0_7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_Handler + B PORT0_7_Handler + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis.h new file mode 100644 index 0000000000..e48e81cdce --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis.h @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM0.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c new file mode 100644 index 0000000000..9d2b3d8420 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c @@ -0,0 +1,54 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* CMSIS-style functionality to support dynamic vectors +*******************************************************************************/ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + // int i; + // Space for dynamic vectors, initialised to allocate in R/W + static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + + // Set the vector + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + // We can always read vectors at 0x0, as the addresses are remapped + uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + + // Return the vector + return vectors[IRQn + 16]; +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.h new file mode 100644 index 0000000000..08faa70cff --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* CMSIS-style functionality to support dynamic vectors +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS (16 + 48) +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h new file mode 100644 index 0000000000..04fb9ba365 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c new file mode 100644 index 0000000000..64c01489bb --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c @@ -0,0 +1,88 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file system_CMSDK_CM0.c +* @brief CMSIS Device System Source File for +* CMSDK_M0 Device +* +*******************************************************************************/ + + +#include "CMSDK_CM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (50000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h new file mode 100644 index 0000000000..6269267607 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h @@ -0,0 +1,76 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************* +* @file system_CMSDK_CM0.h +* @brief CMSIS Device Peripheral Access Layer Header File for +* CMSDK_CM0 Device +* +******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_CM0_H +#define SYSTEM_CMSDK_CM0_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_CM0_H */ From 1bf59cd54d6644006e09b6f986b4925b3191daa2 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 14 May 2018 11:34:23 +0100 Subject: [PATCH 05/11] FastModels: add FVP_MPS2_M0P target support add cmsis drivers and toolchain scripts for FVP_MPS2_M0P --- .../device/CMSDK_CM0plus.h | 723 ++++++++++++++++++ .../TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h | 614 +++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MPS2.sct | 47 ++ .../device/TOOLCHAIN_ARM_STD/startup_MPS2.S | 270 +++++++ .../device/TOOLCHAIN_GCC_ARM/MPS2.ld | 211 +++++ .../device/TOOLCHAIN_GCC_ARM/startup_MPS2.S | 205 +++++ .../device/TOOLCHAIN_IAR/MPS2.icf | 56 ++ .../device/TOOLCHAIN_IAR/startup_MPS2.S | 320 ++++++++ .../TARGET_FVP_MPS2_M0P/device/cmsis.h | 42 + .../TARGET_FVP_MPS2_M0P/device/cmsis_nvic.h | 39 + .../device/peripherallink.h | 53 ++ .../device/system_CMSDK_CM0plus.c | 88 +++ .../device/system_CMSDK_CM0plus.h | 76 ++ 13 files changed, 2744 insertions(+) create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis_nvic.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h new file mode 100644 index 0000000000..6628b97ab7 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h @@ -0,0 +1,723 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_CM0plus.h +* @brief CMSIS Core Peripheral Access Layer Header File for +* CMSDK_CM0plus Device +* +*******************************************************************************/ + + +#ifndef CMSDK_CM0plus_H +#define CMSDK_CM0plus_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */ +#define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __VTOR_PRESENT 1 /* VTOR present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_CM0plus.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined ( __CC_ARM ) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) +#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_CM0plus_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h new file mode 100644 index 0000000000..af11e0b478 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h @@ -0,0 +1,614 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* File: smm_mps2.h +* Release: Version 1.1 +*******************************************************************************/ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld new file mode 100644 index 0000000000..f9167e9edd --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld @@ -0,0 +1,211 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 gcc_arm.ld + */ +/* Linker script for mbed FVP Cortex-M0-Plus on MPS2 */ + +/* Linker script to configure memory regions. */ +/* The length of the VECTORS region is a bit larger than + * is necessary based on the number of exception handlers. + */ +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x4000; +STACK_SIZE = 0x1000; + +/* Size of the vector table in SRAM */ +M_VECTOR_RAM_SIZE = 0x140; + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(4); + } > VECTORS + + .text : + { + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > RAM + + .data : + { + PROVIDE(__etext = LOADADDR(.data)); + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + + } > RAM + + bss_size = __bss_end__ - __bss_start__; + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + +} /* End of sections */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S new file mode 100644 index 0000000000..e82e72b469 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S @@ -0,0 +1,205 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 startup_ARMCM3.S + */ + .syntax unified + .arch armv6-m + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long UARTRX0_Handler /* UART 0 RX Handler */ + .long UARTTX0_Handler /* UART 0 TX Handler */ + .long UARTRX1_Handler /* UART 1 RX Handler */ + .long UARTTX1_Handler /* UART 1 TX Handler */ + .long UARTRX2_Handler /* UART 2 RX Handler */ + .long UARTTX2_Handler /* UART 2 TX Handler */ + .long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */ + .long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */ + .long TIMER0_Handler /* TIMER 0 handler */ + .long TIMER1_Handler /* TIMER 1 handler */ + .long DUALTIMER_HANDLER /* Dual timer handler */ + .long SPI_Handler /* SPI exceptions Handler */ + .long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */ + .long ETHERNET_Handler /* Ethernet Overflow Handler */ + .long I2S_Handler /* I2S Handler */ + .long TSC_Handler /* Touch Screen handler */ + .long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */ + .long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */ + .long UARTRX3_Handler /* UART 3 RX Handler */ + .long UARTTX3_Handler /* UART 3 TX Handler */ + .long UARTRX4_Handler /* UART 4 RX Handler */ + .long UARTTX4_Handler /* UART 4 TX Handler */ + .long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */ + .long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */ + .long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */ + .long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */ + .long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */ + .long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */ + .long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */ + .long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */ + .long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */ + .long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =SystemInit + blx r0 +/* + * Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. + */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + +/* Initialize .bss */ +init_bss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + ldr r3, =bss_size + + movs r0, 0 + + subs r2, r1 + ble .L_zero_done + +.L_zero: + subs r2, #4 + str r0, [r1, r2] + bgt .L_zero +.L_zero_done: + +system_startup: + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* + * Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers + */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + /* External interrupts */ + def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */ + def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */ + def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */ + def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */ + def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */ + def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */ + def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 Combined Handler */ + def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 Combined Handler */ + def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 handler */ + def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 handler */ + def_irq_default_handler DUALTIMER_HANDLER /* 10: Dual timer handler */ + def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */ + def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */ + def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */ + def_irq_default_handler I2S_Handler /* 14: I2S Handler */ + def_irq_default_handler TSC_Handler /* 15: Touch Screen handler */ + def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 Combined Handler */ + def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 Combined Handler */ + def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */ + def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */ + def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */ + def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */ + def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handler */ + def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handler */ + def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */ + def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */ + def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */ + def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */ + def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */ + def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */ + def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */ + def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */ + + .end diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf new file mode 100644 index 0000000000..60b104bcf3 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf @@ -0,0 +1,56 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License) you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* The RAM region doesn't start at the beginning of the RAM address + * space to create space for the vector table copied over to the RAM by mbed. + * The space left is a bit bigger than is necessary based on the number of + * interrupt handlers. + */ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000140; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +/* Heap and Stack size */ +define symbol __ICFEDIT_size_heap__ = 0x4000; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/startup_MPS2.S new file mode 100644 index 0000000000..6ae40b0dfe --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/startup_MPS2.S @@ -0,0 +1,320 @@ +;/* +; * MPS2 CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2018 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UARTRX0_Handler ; 0: UART 0 RX Handler + DCD UARTTX0_Handler ; 1: UART 0 TX Handler + DCD UARTRX1_Handler ; 2: UART 1 RX Handler + DCD UARTTX1_Handler ; 3: UART 1 TX Handler + DCD UARTRX2_Handler ; 4: UART 2 RX Handler + DCD UARTTX2_Handler ; 5: UART 2 TX Handler + DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; 8: TIMER 0 handler + DCD TIMER1_Handler ; 9: TIMER 1 handler + DCD DUALTIMER_HANDLER ; 10: Dual timer handler + DCD SPI_Handler ; 11: SPI exceptions Handler + DCD UARTOVF_Handler ; 12: UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; 13: Ethernet Overflow Handler + DCD I2S_Handler ; 14: I2S Handler + DCD TSC_Handler ; 15: Touch Screen handler + DCD PORT2_COMB_Handler ; 16: GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; 17: GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; 18: UART 3 RX Handler + DCD UARTTX3_Handler ; 19: UART 3 TX Handler + DCD UARTRX4_Handler ; 20: UART 4 RX Handler + DCD UARTTX4_Handler ; 21: UART 4 TX Handler + DCD ADCSPI_Handler ; 22: SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; 23: SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; 24: GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; 25: GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; 26: GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; 27: GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; 28: GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; 29: GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; 30: GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; 31: GPIO Port 0 pin 7 Handler + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UARTRX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX0_Handler + B UARTRX0_Handler + + PUBWEAK UARTTX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX0_Handler + B UARTTX0_Handler + + PUBWEAK UARTRX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX1_Handler + B UARTRX1_Handler + + PUBWEAK UARTTX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX1_Handler + B UARTTX1_Handler + + PUBWEAK UARTRX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX2_Handler + B UARTRX2_Handler + + PUBWEAK UARTTX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX2_Handler + B UARTTX2_Handler + + PUBWEAK PORT0_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_COMB_Handler + B PORT0_COMB_Handler + + PUBWEAK PORT1_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_COMB_Handler + B PORT1_COMB_Handler + + PUBWEAK TIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_Handler + B TIMER0_Handler + + PUBWEAK TIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_Handler + B TIMER1_Handler + + PUBWEAK DUALTIMER_HANDLER + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_HANDLER + B DUALTIMER_HANDLER + + PUBWEAK SPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI_Handler + B SPI_Handler + + PUBWEAK UARTOVF_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_Handler + B UARTOVF_Handler + + PUBWEAK ETHERNET_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ETHERNET_Handler + B ETHERNET_Handler + + PUBWEAK I2S_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S_Handler + B I2S_Handler + + PUBWEAK TSC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_Handler + B TSC_Handler + + PUBWEAK PORT2_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_COMB_Handler + B PORT2_COMB_Handler + + PUBWEAK PORT3_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_COMB_Handler + B PORT3_COMB_Handler + + PUBWEAK UARTRX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX3_Handler + B UARTRX3_Handler + + PUBWEAK UARTTX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX3_Handler + B UARTTX3_Handler + + PUBWEAK UARTRX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX4_Handler + B UARTRX4_Handler + + PUBWEAK UARTTX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX4_Handler + B UARTTX4_Handler + + PUBWEAK ADCSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADCSPI_Handler + B ADCSPI_Handler + + PUBWEAK SHIELDSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SHIELDSPI_Handler + B SHIELDSPI_Handler + + PUBWEAK PORT0_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_Handler + B PORT0_0_Handler + + PUBWEAK PORT0_1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_Handler + B PORT0_1_Handler + + PUBWEAK PORT0_2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_Handler + B PORT0_2_Handler + + PUBWEAK PORT0_3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_Handler + B PORT0_3_Handler + + PUBWEAK PORT0_4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_Handler + B PORT0_4_Handler + + PUBWEAK PORT0_5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_Handler + B PORT0_5_Handler + + PUBWEAK PORT0_6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_Handler + B PORT0_6_Handler + + PUBWEAK PORT0_7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_Handler + B PORT0_7_Handler + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis.h new file mode 100644 index 0000000000..3097efd1b8 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis.h @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM0plus.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis_nvic.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis_nvic.h new file mode 100644 index 0000000000..a564abfc18 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 48) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h new file mode 100644 index 0000000000..04fb9ba365 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c new file mode 100644 index 0000000000..eae03be72d --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c @@ -0,0 +1,88 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file system_CMSDK_CM0plus.c +* @brief CMSIS Device System Source File for +* CMSDK_M0 Device +* +*******************************************************************************/ + + +#include "CMSDK_CM0plus.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (50000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h new file mode 100644 index 0000000000..022e3e7deb --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h @@ -0,0 +1,76 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************* +* @file system_CMSDK_CM0plus.h +* @brief CMSIS Device Peripheral Access Layer Header File for +* CMSDK_CM0plus Device +* +******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_CM0plus_H +#define SYSTEM_CMSDK_CM0plus_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_CM0plus_H */ From 76dc715a0ed1d91e3ea1d26d22335f6806f410a1 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 14 May 2018 11:34:50 +0100 Subject: [PATCH 06/11] FastModels: add FVP_MPS2_M7 target support add cmsis drivers and toolchain scripts for FVP_MPS2_M7 --- .../TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h | 732 ++++++++++++++++++ .../TARGET_FVP_MPS2_M7/device/SMM_MPS2.h | 610 +++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MPS2.sct | 47 ++ .../TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S | 290 +++++++ .../device/TOOLCHAIN_GCC_ARM/MPS2.ld | 211 +++++ .../device/TOOLCHAIN_GCC_ARM/startup_MPS2.S | 257 ++++++ .../device/TOOLCHAIN_IAR/MPS2.icf | 56 ++ .../device/TOOLCHAIN_IAR/startup_MPS2.S | 340 ++++++++ .../TARGET_FVP_MPS2_M7/device/cmsis.h | 42 + .../TARGET_FVP_MPS2_M7/device/cmsis_nvic.h | 39 + .../device/peripherallink.h | 53 ++ .../device/system_CMSDK_CM7.c | 104 +++ .../device/system_CMSDK_CM7.h | 76 ++ 13 files changed, 2857 insertions(+) create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/MPS2.icf create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/startup_MPS2.S create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h new file mode 100644 index 0000000000..43b59b9316 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h @@ -0,0 +1,732 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_CM7.h +* @brief CMSIS Core Peripheral Access Layer Header File for +* CMSDK_CM7 Device +* +*******************************************************************************/ + + +#ifndef CMSDK_CM7_H +#define CMSDK_CM7_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */ + UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ + PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ + SPI_IRQn = 11, /* SPI Interrupt */ + UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /* Ethernet Interrupt */ + I2S_IRQn = 14, /* I2S Interrupt */ + TSC_IRQn = 15, /* Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the CM7 Processor and Core Peripherals --------- */ +#define __CM7_REV 0x0101 /* Core revision r1p1 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* no FPU present */ +#define __FPU_DP 1 /* unused */ +#define __ICACHE_PRESENT 1 +#define __DCACHE_PRESENT 1 + +#include "core_cm7.h" /* Processor and core peripherals */ +#include "system_CMSDK_CM7.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) +#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_CM7_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h new file mode 100644 index 0000000000..e438d840f6 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h @@ -0,0 +1,610 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* File: smm_mps2.h +* Release: Version 1.1 +*******************************************************************************/ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld new file mode 100644 index 0000000000..a1540322f0 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld @@ -0,0 +1,211 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 gcc_arm.ld + */ +/* Linker script for mbed FVP Cortex-M7 on MPS2 */ + +/* Linker script to configure memory regions. */ +/* The length of the VECTORS region is a bit larger than + * is necessary based on the number of exception handlers. + */ +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x4000; +STACK_SIZE = 0x1000; + +/* Size of the vector table in SRAM */ +M_VECTOR_RAM_SIZE = 0x140; + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(4); + } > VECTORS + + .text : + { + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > RAM + + .data : + { + PROVIDE(__etext = LOADADDR(.data)); + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + + } > RAM + + bss_size = __bss_end__ - __bss_start__; + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + +} /* End of sections */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S new file mode 100644 index 0000000000..c5d12692ec --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S @@ -0,0 +1,257 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 startup_ARMCM3.S + */ + .syntax unified + .arch armv7-m + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */ + .long Spare_IRQHandler /* 1: Undefined */ + .long UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */ + .long APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */ + .long APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */ + .long RTC_IRQHandler /* 5: RTC Interrupt */ + .long PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */ + .long PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */ + .long TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */ + .long TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */ + .long DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */ + .long APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */ + .long UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */ + .long APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */ + .long RESERVED0_IRQHandler /* 14: Reserved */ + .long TSC_IRQHandler /* 15: Touch Screen Interrupt */ + .long PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */ + .long PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */ + .long PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */ + .long PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */ + .long PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */ + .long PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */ + .long PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */ + .long PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */ + .long PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */ + .long PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */ + .long PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */ + .long PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */ + .long PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */ + .long PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */ + .long PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */ + .long PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */ + .long FLASH0_IRQHandler /* 32: Reserved for Flash */ + .long FLASH1_IRQHandler /* 33: Reserved for Flash */ + .long RESERVED1_IRQHandler /* 34: Reserved */ + .long RESERVED2_IRQHandler /* 35: Reserved */ + .long RESERVED3_IRQHandler /* 36: Reserved */ + .long RESERVED4_IRQHandler /* 37: Reserved */ + .long RESERVED5_IRQHandler /* 38: Reserved */ + .long RESERVED6_IRQHandler /* 39: Reserved */ + .long RESERVED7_IRQHandler /* 40: Reserved */ + .long RESERVED8_IRQHandler /* 41: Reserved */ + .long PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */ + .long PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */ + .long TRNG_IRQHandler /* 44: Random number generator Interrupt */ + .long UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */ + .long UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */ + .long ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */ + .long I2S_IRQHandler /* 48: I2S Interrupt */ + .long MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */ + .long MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */ + .long MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */ + .long MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */ + .long MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */ + .long PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */ + .long PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */ + .long UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =SystemInit + blx r0 +/* + * Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. + */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + +/* Initialize .bss */ +init_bss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + ldr r3, =bss_size + + cmp r3, #0 + beq system_startup + + mov r4, #0 +zero: + strb r4, [r1], #1 + subs r3, r3, #1 + bne zero + +system_startup: + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* + * Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers + */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + /* External interrupts */ + def_irq_default_handler UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */ + def_irq_default_handler Spare_IRQHandler /* 1: Undefined */ + def_irq_default_handler UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */ + def_irq_default_handler APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */ + def_irq_default_handler APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */ + def_irq_default_handler RTC_IRQHandler /* 5: RTC Interrupt */ + def_irq_default_handler PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */ + def_irq_default_handler PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */ + def_irq_default_handler TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */ + def_irq_default_handler TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */ + def_irq_default_handler DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */ + def_irq_default_handler APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */ + def_irq_default_handler UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */ + def_irq_default_handler APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */ + def_irq_default_handler RESERVED0_IRQHandler /* 14: Reserved */ + def_irq_default_handler TSC_IRQHandler /* 15: Touch Screen Interrupt */ + def_irq_default_handler PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */ + def_irq_default_handler PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */ + def_irq_default_handler PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */ + def_irq_default_handler PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */ + def_irq_default_handler PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */ + def_irq_default_handler PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */ + def_irq_default_handler PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */ + def_irq_default_handler PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */ + def_irq_default_handler PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */ + def_irq_default_handler PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */ + def_irq_default_handler PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */ + def_irq_default_handler PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */ + def_irq_default_handler PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */ + def_irq_default_handler PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */ + def_irq_default_handler PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */ + def_irq_default_handler PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */ + def_irq_default_handler FLASH0_IRQHandler /* 32: Reserved for Flash */ + def_irq_default_handler FLASH1_IRQHandler /* 33: Reserved for Flash */ + def_irq_default_handler RESERVED1_IRQHandler /* 34: Reserved */ + def_irq_default_handler RESERVED2_IRQHandler /* 35: Reserved */ + def_irq_default_handler RESERVED3_IRQHandler /* 36: Reserved */ + def_irq_default_handler RESERVED4_IRQHandler /* 37: Reserved */ + def_irq_default_handler RESERVED5_IRQHandler /* 38: Reserved */ + def_irq_default_handler RESERVED6_IRQHandler /* 39: Reserved */ + def_irq_default_handler RESERVED7_IRQHandler /* 40: Reserved */ + def_irq_default_handler RESERVED8_IRQHandler /* 41: Reserved */ + def_irq_default_handler PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */ + def_irq_default_handler PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */ + def_irq_default_handler TRNG_IRQHandler /* 44: Random number generator Interrupt */ + def_irq_default_handler UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */ + def_irq_default_handler UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */ + def_irq_default_handler ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */ + def_irq_default_handler I2S_IRQHandler /* 48: I2S Interrupt */ + def_irq_default_handler MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */ + def_irq_default_handler MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */ + def_irq_default_handler MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */ + def_irq_default_handler MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */ + def_irq_default_handler MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */ + def_irq_default_handler PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */ + def_irq_default_handler PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */ + def_irq_default_handler UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */ + + .end diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/MPS2.icf b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/MPS2.icf new file mode 100644 index 0000000000..60b104bcf3 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/MPS2.icf @@ -0,0 +1,56 @@ +/* + * MPS2 CMSIS Library + */ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License) you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* The RAM region doesn't start at the beginning of the RAM address + * space to create space for the vector table copied over to the RAM by mbed. + * The space left is a bit bigger than is necessary based on the number of + * interrupt handlers. + */ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000140; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +/* Heap and Stack size */ +define symbol __ICFEDIT_size_heap__ = 0x4000; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/startup_MPS2.S b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/startup_MPS2.S new file mode 100644 index 0000000000..fcabe102c9 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_IAR/startup_MPS2.S @@ -0,0 +1,340 @@ +;/* +; * MPS2 CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2018 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UARTRX0_Handler ; 0: UART 0 RX Handler + DCD UARTTX0_Handler ; 1: UART 0 TX Handler + DCD UARTRX1_Handler ; 2: UART 1 RX Handler + DCD UARTTX1_Handler ; 3: UART 1 TX Handler + DCD UARTRX2_Handler ; 4: UART 2 RX Handler + DCD UARTTX2_Handler ; 5: UART 2 TX Handler + DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; 8: TIMER 0 handler + DCD TIMER1_Handler ; 9: TIMER 1 handler + DCD DUALTIMER_HANDLER ; 10: Dual timer handler + DCD SPI_Handler ; 11: SPI exceptions Handler + DCD UARTOVF_Handler ; 12: UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; 13: Ethernet Overflow Handler + DCD I2S_Handler ; 14: I2S Handler + DCD TSC_Handler ; 15: Touch Screen handler + DCD PORT2_COMB_Handler ; 16: GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; 17: GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; 18: UART 3 RX Handler + DCD UARTTX3_Handler ; 19: UART 3 TX Handler + DCD UARTRX4_Handler ; 20: UART 4 RX Handler + DCD UARTTX4_Handler ; 21: UART 4 TX Handler + DCD ADCSPI_Handler ; 22: SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; 23: SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; 24: GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; 25: GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; 26: GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; 27: GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; 28: GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; 29: GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; 30: GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; 31: GPIO Port 0 pin 7 Handler + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UARTRX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX0_Handler + B UARTRX0_Handler + + PUBWEAK UARTTX0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX0_Handler + B UARTTX0_Handler + + PUBWEAK UARTRX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX1_Handler + B UARTRX1_Handler + + PUBWEAK UARTTX1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX1_Handler + B UARTTX1_Handler + + PUBWEAK UARTRX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX2_Handler + B UARTRX2_Handler + + PUBWEAK UARTTX2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX2_Handler + B UARTTX2_Handler + + PUBWEAK PORT0_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_COMB_Handler + B PORT0_COMB_Handler + + PUBWEAK PORT1_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_COMB_Handler + B PORT1_COMB_Handler + + PUBWEAK TIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_Handler + B TIMER0_Handler + + PUBWEAK TIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_Handler + B TIMER1_Handler + + PUBWEAK DUALTIMER_HANDLER + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_HANDLER + B DUALTIMER_HANDLER + + PUBWEAK SPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI_Handler + B SPI_Handler + + PUBWEAK UARTOVF_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_Handler + B UARTOVF_Handler + + PUBWEAK ETHERNET_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ETHERNET_Handler + B ETHERNET_Handler + + PUBWEAK I2S_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S_Handler + B I2S_Handler + + PUBWEAK TSC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_Handler + B TSC_Handler + + PUBWEAK PORT2_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_COMB_Handler + B PORT2_COMB_Handler + + PUBWEAK PORT3_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_COMB_Handler + B PORT3_COMB_Handler + + PUBWEAK UARTRX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX3_Handler + B UARTRX3_Handler + + PUBWEAK UARTTX3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX3_Handler + B UARTTX3_Handler + + PUBWEAK UARTRX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTRX4_Handler + B UARTRX4_Handler + + PUBWEAK UARTTX4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTTX4_Handler + B UARTTX4_Handler + + PUBWEAK ADCSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADCSPI_Handler + B ADCSPI_Handler + + PUBWEAK SHIELDSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SHIELDSPI_Handler + B SHIELDSPI_Handler + + PUBWEAK PORT0_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_Handler + B PORT0_0_Handler + + PUBWEAK PORT0_1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_Handler + B PORT0_1_Handler + + PUBWEAK PORT0_2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_Handler + B PORT0_2_Handler + + PUBWEAK PORT0_3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_Handler + B PORT0_3_Handler + + PUBWEAK PORT0_4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_Handler + B PORT0_4_Handler + + PUBWEAK PORT0_5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_Handler + B PORT0_5_Handler + + PUBWEAK PORT0_6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_Handler + B PORT0_6_Handler + + PUBWEAK PORT0_7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_Handler + B PORT0_7_Handler + + + END diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h new file mode 100644 index 0000000000..4576f5e32e --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM7.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h new file mode 100644 index 0000000000..7dd4ba9509 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 48) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h new file mode 100644 index 0000000000..b6663cf719 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c new file mode 100644 index 0000000000..23deb6640f --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c @@ -0,0 +1,104 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file system_CMSDK_CM7.c +* @brief CMSIS Device System Source File for +* CMSDK_CM7 Device +* +*******************************************************************************/ + + +#if defined (CMSDK_CM7) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (50000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h new file mode 100644 index 0000000000..24b7112c55 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h @@ -0,0 +1,76 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************* +* @file system_CMSDK_CM7.h +* @brief CMSIS Device Peripheral Access Layer Header File for +* CMSDK_CM7 Device +* +******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_CM7_H +#define SYSTEM_CMSDK_CM7_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_CM7_H */ From 953a7351298241109eac2607d173c6e8921ff5fb Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 14 May 2018 11:40:21 +0100 Subject: [PATCH 07/11] FastModels: enable FVP_MPS2 targets for mbed os add ARM_FM top level category add second level parent FVP_MPS2 inherits ARM_FM add each target ( M0 M0P M3 M4 M7 ) inherits FVP_MPS2 --- targets/targets.json | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index b789f71ed7..d63395b9c7 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -4008,5 +4008,49 @@ "detect_code": ["7013"], "release_versions": ["5"], "bootloader_supported": true + }, + "ARM_FM": { + "inherits": ["Target"], + "public": false, + "extra_labels": ["ARM_FM"] + }, + "FVP_MPS2": { + "inherits": ["ARM_FM"], + "public": false, + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "extra_labels_add": ["FVP_MPS2"], + "OUTPUT_EXT": "elf", + "device_has": ["AACI", "ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"], + "release_versions": ["5"] + }, + "FVP_MPS2_M0": { + "inherits": ["FVP_MPS2"], + "core": "Cortex-M0", + "extra_labels_add": ["FVP_MPS2_M0"], + "macros": ["CMSDK_CM0","CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""] + }, + "FVP_MPS2_M0P": { + "inherits": ["FVP_MPS2"], + "core": "Cortex-M0+", + "extra_labels_add": ["FVP_MPS2_M0P"], + "macros": ["CMSDK_CM0plus"] + }, + "FVP_MPS2_M3": { + "inherits": ["FVP_MPS2"], + "core": "Cortex-M3", + "extra_labels_add": ["FVP_MPS2_M3"], + "macros": ["CMSDK_CM3"] + }, + "FVP_MPS2_M4": { + "inherits": ["FVP_MPS2"], + "core": "Cortex-M4", + "extra_labels_add": ["FVP_MPS2_M4"], + "macros": ["CMSDK_CM4"] + }, + "FVP_MPS2_M7": { + "inherits": ["FVP_MPS2"], + "core": "Cortex-M7", + "extra_labels_add": ["FVP_MPS2_M7"], + "macros": ["CMSDK_CM7"] } } From aab82a78b3670d42ea181b1e5194d25d5f184348 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Fri, 18 May 2018 15:52:55 +0100 Subject: [PATCH 08/11] reformat coding styles based on coding guidelines --- .../TARGET_FVP_MPS2/PeripheralNames.h | 8 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h | 382 ++++----- .../TARGET_FVP_MPS2/SDK/ETH_MPS2.c | 129 ++-- .../TARGET_FVP_MPS2/SDK/ETH_MPS2.h | 46 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c | 21 +- .../TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c | 22 +- .../TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h | 2 +- .../TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h | 315 ++++---- .../TARGET_FVP_MPS2_M0/device/cmsis_nvic.c | 12 +- .../device/peripherallink.h | 12 +- .../device/system_CMSDK_CM0.c | 8 +- .../device/system_CMSDK_CM0.h | 4 +- .../device/CMSDK_CM0plus.h | 315 ++++---- .../TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h | 566 +++++++------- .../device/peripherallink.h | 12 +- .../device/system_CMSDK_CM0plus.c | 8 +- .../device/system_CMSDK_CM0plus.h | 4 +- .../TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h | 321 ++++---- .../TARGET_FVP_MPS2_M3/device/SMM_MPS2.h | 566 +++++++------- .../device/peripherallink.h | 12 +- .../device/system_CMSDK_CM3.c | 10 +- .../device/system_CMSDK_CM3.h | 4 +- .../TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h | 729 +++++++++--------- .../TARGET_FVP_MPS2_M4/device/SMM_MPS2.h | 560 +++++++------- .../device/peripherallink.h | 12 +- .../device/system_CMSDK_CM4.c | 22 +- .../device/system_CMSDK_CM4.h | 4 +- .../TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h | 371 +++++---- .../TARGET_FVP_MPS2_M7/device/SMM_MPS2.h | 610 ++++++++------- .../TARGET_FVP_MPS2_M7/device/cmsis.h | 44 +- .../TARGET_FVP_MPS2_M7/device/cmsis_nvic.h | 44 +- .../device/peripherallink.h | 56 +- .../device/system_CMSDK_CM7.c | 74 +- .../device/system_CMSDK_CM7.h | 48 +- .../TARGET_FVP_MPS2/analogin_api.c | 78 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/device.h | 6 +- .../TARGET_FVP_MPS2/ethernet_api.c | 34 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c | 139 ++-- .../TARGET_FVP_MPS2/gpio_irq_api.c | 493 ++++++++---- .../TARGET_FVP_MPS2/gpio_object.h | 24 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c | 300 ++++--- .../TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h | 8 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/pinmap.c | 10 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/port_api.c | 42 +- .../TARGET_FVP_MPS2/serial_api.c | 363 ++++----- .../TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c | 208 ++--- .../TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h | 12 +- .../TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c | 45 +- 48 files changed, 3675 insertions(+), 3440 deletions(-) diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h index 9c07b3bfa4..4224fc874a 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PeripheralNames.h @@ -32,9 +32,9 @@ typedef enum { typedef enum { I2C_0 = (int)MPS2_TSC_I2C_BASE, I2C_1 = (int)MPS2_AAIC_I2C_BASE, - I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, - I2C_3 = (int)MPS2_SHIELD1_I2C_BASE - + I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, + I2C_3 = (int)MPS2_SHIELD1_I2C_BASE + } I2CName; typedef enum { @@ -55,7 +55,7 @@ typedef enum { typedef enum { SPI_0 = (int)MPS2_SSP1_BASE, SPI_1 = (int)MPS2_SSP0_BASE, - SPI_2 = (int)MPS2_SSP2_BASE, + SPI_2 = (int)MPS2_SSP2_BASE, SPI_3 = (int)MPS2_SSP3_BASE, SPI_4 = (int)MPS2_SSP4_BASE } SPIName; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h index 6dedbd7d42..062661e379 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/PinNames.h @@ -23,206 +23,206 @@ extern "C" { #endif typedef enum { - PIN_INPUT, - PIN_OUTPUT + PIN_INPUT, + PIN_OUTPUT } PinDirection; #define PORT_SHIFT 5 typedef enum { // MPS2 EXP Pin Names - EXP0 = 0, - EXP1 = 1, - EXP2 = 2, - EXP3 = 3, - EXP4 = 4, - EXP5 = 5, - EXP6 = 6, - EXP7 = 7, - EXP8 = 8, - EXP9 = 9, - EXP10 = 10, - EXP11 = 11, - EXP12 = 12, - EXP13 = 13, - EXP14 = 14, - EXP15 = 15, - EXP16 = 16, - EXP17 = 17, - EXP18 = 18, - EXP19 = 19, - EXP20 = 20, - EXP21 = 21, - EXP22 = 22, - EXP23 = 23, - EXP24 = 24, - EXP25 = 25, - - EXP26 = 26, - EXP27 = 27, - EXP28 = 28, - EXP29 = 29, - EXP30 = 30, - EXP31 = 31, - EXP32 = 32, - EXP33 = 33, - EXP34 = 34, - EXP35 = 35, - EXP36 = 36, - EXP37 = 37, - EXP38 = 38, - EXP39 = 39, - EXP40 = 40, - EXP41 = 41, - EXP42 = 42, - EXP43 = 43, - EXP44 = 44, - EXP45 = 45, - EXP46 = 46, - EXP47 = 47, - EXP48 = 48, - EXP49 = 49, - EXP50 = 50, - EXP51 = 51, - + EXP0 = 0, + EXP1 = 1, + EXP2 = 2, + EXP3 = 3, + EXP4 = 4, + EXP5 = 5, + EXP6 = 6, + EXP7 = 7, + EXP8 = 8, + EXP9 = 9, + EXP10 = 10, + EXP11 = 11, + EXP12 = 12, + EXP13 = 13, + EXP14 = 14, + EXP15 = 15, + EXP16 = 16, + EXP17 = 17, + EXP18 = 18, + EXP19 = 19, + EXP20 = 20, + EXP21 = 21, + EXP22 = 22, + EXP23 = 23, + EXP24 = 24, + EXP25 = 25, + + EXP26 = 26, + EXP27 = 27, + EXP28 = 28, + EXP29 = 29, + EXP30 = 30, + EXP31 = 31, + EXP32 = 32, + EXP33 = 33, + EXP34 = 34, + EXP35 = 35, + EXP36 = 36, + EXP37 = 37, + EXP38 = 38, + EXP39 = 39, + EXP40 = 40, + EXP41 = 41, + EXP42 = 42, + EXP43 = 43, + EXP44 = 44, + EXP45 = 45, + EXP46 = 46, + EXP47 = 47, + EXP48 = 48, + EXP49 = 49, + EXP50 = 50, + EXP51 = 51, + // Other mbed Pin Names - //LEDs on mps2 - //user leds - USERLED1 = 100, - USERLED2 = 101, - //user switches - USERSW1 = 110, - USERSW2 = 111, - - //mcc leds - LED1 = 200, - LED2 = 201, - LED3 = 202, - LED4 = 203, - LED5 = 204, - LED6 = 205, - LED7 = 206, - LED8 = 207, - - //MCC Switches - SW1 = 210, - SW2 = 211, - SW3 = 212, - SW4 = 213, - SW5 = 214, - SW6 = 215, - SW7 = 216, - SW8 = 217, - - //MPS2 SPI header pins j21 - MOSI_SPI = 300, - MISO_SPI = 301, - SCLK_SPI = 302, - SSEL_SPI = 303, - - //MPS2 CLCD SPI - CLCD_MOSI = 304, - CLCD_MISO = 305, - CLCD_SCLK = 306, - CLCD_SSEL = 307, - CLCD_RESET = 308, - CLCD_RS = 309, - CLCD_RD = 310, - CLCD_BL_CTRL = 311, - - //MPS2 shield 0 SPI - SHIELD_0_SPI_SCK = 320, - SHIELD_0_SPI_MOSI = 321, - SHIELD_0_SPI_MISO = 322, - SHIELD_0_SPI_nCS = 323, + //LEDs on mps2 + //user leds + USERLED1 = 100, + USERLED2 = 101, + //user switches + USERSW1 = 110, + USERSW2 = 111, - //MPS2 shield 1 SPI - SHIELD_1_SPI_SCK = 331, - SHIELD_1_SPI_MOSI = 332, - SHIELD_1_SPI_MISO = 333, - SHIELD_1_SPI_nCS = 334, - - //MPS2 shield ADC SPI - ADC_MOSI = 650, - ADC_MISO = 651, - ADC_SCLK = 652, - ADC_SSEL = 653, - - //MPS2 Uart - USBTX = 400, - USBRX = 401, - XB_TX = 402, - XB_RX = 403, - UART_TX2 = 404, - UART_RX2 = 405, - SH0_TX = 406, - SH0_RX = 407, - SH1_TX = 408, - SH1_RX = 409, - - //MPS2 I2C touchscreen and audio - TSC_SDA = 500, - TSC_SCL = 501, - AUD_SDA = 502, - AUD_SCL = 503, - - //MPS2 I2C for shield - SHIELD_0_SDA = 504, - SHIELD_0_SCL = 505, - SHIELD_1_SDA = 506, - SHIELD_1_SCL = 507, - - //MPS2 shield Analog pins - A0_0 = 600, - A0_1 = 601, - A0_2 = 602, - A0_3 = 603, - A0_4 = 604, - A0_5 = 605, - A1_0 = 606, - A1_1 = 607, - A1_2 = 608, - A1_3 = 609, - A1_4 = 610, - A1_5 = 611, - //MPS2 Shield Digital pins - D0_0 = EXP0, - D0_1 = EXP4, - D0_2 = EXP2, - D0_3 = EXP3, - D0_4 = EXP1, - D0_5 = EXP6, - D0_6 = EXP7, - D0_7 = EXP8, - D0_8 = EXP9, - D0_9 = EXP10, - D0_10 = EXP12, - D0_11 = EXP13, - D0_12 = EXP14, - D0_13 = EXP11, - D0_14 = EXP15, - D0_15 = EXP5, - - D1_0 = EXP26, - D1_1 = EXP30, - D1_2 = EXP28, - D1_3 = EXP29, - D1_4 = EXP27, - D1_5 = EXP32, - D1_6 = EXP33, - D1_7 = EXP34, - D1_8 = EXP35, - D1_9 = EXP36, - D1_10 = EXP38, - D1_11 = EXP39, - D1_12 = EXP40, - D1_13 = EXP44, - D1_14 = EXP41, - D1_15 = EXP31, - - // Not connected - NC = (int)0xFFFFFFFF, + //mcc leds + LED1 = 200, + LED2 = 201, + LED3 = 202, + LED4 = 203, + LED5 = 204, + LED6 = 205, + LED7 = 206, + LED8 = 207, + + //MCC Switches + SW1 = 210, + SW2 = 211, + SW3 = 212, + SW4 = 213, + SW5 = 214, + SW6 = 215, + SW7 = 216, + SW8 = 217, + + //MPS2 SPI header pins j21 + MOSI_SPI = 300, + MISO_SPI = 301, + SCLK_SPI = 302, + SSEL_SPI = 303, + + //MPS2 CLCD SPI + CLCD_MOSI = 304, + CLCD_MISO = 305, + CLCD_SCLK = 306, + CLCD_SSEL = 307, + CLCD_RESET = 308, + CLCD_RS = 309, + CLCD_RD = 310, + CLCD_BL_CTRL = 311, + + //MPS2 shield 0 SPI + SHIELD_0_SPI_SCK = 320, + SHIELD_0_SPI_MOSI = 321, + SHIELD_0_SPI_MISO = 322, + SHIELD_0_SPI_nCS = 323, + + //MPS2 shield 1 SPI + SHIELD_1_SPI_SCK = 331, + SHIELD_1_SPI_MOSI = 332, + SHIELD_1_SPI_MISO = 333, + SHIELD_1_SPI_nCS = 334, + + //MPS2 shield ADC SPI + ADC_MOSI = 650, + ADC_MISO = 651, + ADC_SCLK = 652, + ADC_SSEL = 653, + + //MPS2 Uart + USBTX = 400, + USBRX = 401, + XB_TX = 402, + XB_RX = 403, + UART_TX2 = 404, + UART_RX2 = 405, + SH0_TX = 406, + SH0_RX = 407, + SH1_TX = 408, + SH1_RX = 409, + + //MPS2 I2C touchscreen and audio + TSC_SDA = 500, + TSC_SCL = 501, + AUD_SDA = 502, + AUD_SCL = 503, + + //MPS2 I2C for shield + SHIELD_0_SDA = 504, + SHIELD_0_SCL = 505, + SHIELD_1_SDA = 506, + SHIELD_1_SCL = 507, + + //MPS2 shield Analog pins + A0_0 = 600, + A0_1 = 601, + A0_2 = 602, + A0_3 = 603, + A0_4 = 604, + A0_5 = 605, + A1_0 = 606, + A1_1 = 607, + A1_2 = 608, + A1_3 = 609, + A1_4 = 610, + A1_5 = 611, + //MPS2 Shield Digital pins + D0_0 = EXP0, + D0_1 = EXP4, + D0_2 = EXP2, + D0_3 = EXP3, + D0_4 = EXP1, + D0_5 = EXP6, + D0_6 = EXP7, + D0_7 = EXP8, + D0_8 = EXP9, + D0_9 = EXP10, + D0_10 = EXP12, + D0_11 = EXP13, + D0_12 = EXP14, + D0_13 = EXP11, + D0_14 = EXP15, + D0_15 = EXP5, + + D1_0 = EXP26, + D1_1 = EXP30, + D1_2 = EXP28, + D1_3 = EXP29, + D1_4 = EXP27, + D1_5 = EXP32, + D1_6 = EXP33, + D1_7 = EXP34, + D1_8 = EXP35, + D1_9 = EXP36, + D1_10 = EXP38, + D1_11 = EXP39, + D1_12 = EXP40, + D1_13 = EXP44, + D1_14 = EXP41, + D1_15 = EXP31, + + // Not connected + NC = (int)0xFFFFFFFF, } PinName; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c index 9c8fc46bb7..0e1c17d2f1 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. */ /* @@ -47,7 +47,7 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) error = 0; val = SMSC9220->MAC_CSR_CMD; - if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation + if (!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation maccmd = 0; maccmd |= regoffset; maccmd |= ((unsigned int)1 << 30); // Indicates read @@ -59,13 +59,13 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) val = SMSC9220->BYTE_TEST; // A no-op read. wait_ms(1); timedout--; - } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); + } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); - if(!timedout) { + if (!timedout) { error = 1; - } - else + } else { *data = SMSC9220->MAC_CSR_DATA; + } } else { *data = 0; } @@ -80,7 +80,7 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data) error = 0; read = SMSC9220->MAC_CSR_CMD; - if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation + if (!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation SMSC9220->MAC_CSR_DATA = data; // Store data. maccmd = 0; maccmd |= regoffset; @@ -93,27 +93,28 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data) read = SMSC9220->BYTE_TEST; // A no-op read. wait_ms(1); timedout--; - } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); + } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); - if(!timedout) { + if (!timedout) { error = 1; } } else { - printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n"); + printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n"); } return error; } unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) { - unsigned int val, phycmd; int error; + unsigned int val, phycmd; + int error; int timedout; error = 0; smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); - if(!(val & 1)) { // Not busy + if (!(val & 1)) { // Not busy phycmd = 0; phycmd |= (1 << 11); // 1 to [15:11] phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] @@ -127,14 +128,14 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) do { wait_ms(1); timedout--; - smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val); - } while(timedout && (val & ((unsigned int)1 << 0))); + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); + } while (timedout && (val & ((unsigned int)1 << 0))); - if(!timedout) { + if (!timedout) { error = 1; - } - else + } else { smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data); + } } else { *data = 0; @@ -144,14 +145,15 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) { - unsigned int val, phycmd; int error; + unsigned int val, phycmd; + int error; int timedout; error = 0; smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); - if(!(val & 1)) { // Not busy + if (!(val & 1)) { // Not busy smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data phycmd = 0; phycmd |= (1 << 11); // 1 to [15:11] @@ -168,9 +170,9 @@ unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) wait_ms(1); timedout--; smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd); - } while(timedout && (phycmd & (1 << 0))); + } while (timedout && (phycmd & (1 << 0))); - if(!timedout) { + if (!timedout) { error = 1; } @@ -198,10 +200,11 @@ unsigned int smsc9220_soft_reset(void) do { wait_ms(1); timedout--; - } while(timedout && (SMSC9220->HW_CFG & 1)); + } while (timedout && (SMSC9220->HW_CFG & 1)); - if(!timedout) + if (!timedout) { return 1; + } return 0; } @@ -209,8 +212,9 @@ unsigned int smsc9220_soft_reset(void) void smsc9220_set_txfifo(unsigned int val) { // 2kb minimum, 14kb maximum - if(val < 2 || val > 14) + if (val < 2 || val > 14) { return; + } SMSC9220->HW_CFG = val << 16; } @@ -226,10 +230,11 @@ unsigned int smsc9220_wait_eeprom(void) wait_ms(1); timedout--; - } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); + } while (timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); - if(!timedout) + if (!timedout) { return 1; + } return 0; } @@ -246,8 +251,8 @@ unsigned int smsc9220_check_phy(void) { unsigned short phyid1, phyid2; - smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1); - smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2); + smsc9220_phy_regread(SMSC9220_PHY_ID1, &phyid1); + smsc9220_phy_regread(SMSC9220_PHY_ID2, &phyid2); return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || (phyid1 == 0x0 && phyid2 == 0x0)); } @@ -258,13 +263,13 @@ unsigned int smsc9220_reset_phy(void) int error; error = 0; - if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { + if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { error = 1; return error; } read |= (1 << 15); - if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { + if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { error = 1; return error; } @@ -370,11 +375,11 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) rxfifo_inf = SMSC9220->RX_FIFO_INF; - if(rxfifo_inf & 0xFFFF) { // If there's data + if (rxfifo_inf & 0xFFFF) { // If there's data rxfifo_stat = SMSC9220->RX_STAT_PORT; - if(rxfifo_stat != 0) { // Fetch status of this packet + if (rxfifo_stat != 0) { // Fetch status of this packet pktsize = ((rxfifo_stat >> 16) & 0x3FFF); - if(rxfifo_stat & (1 << 15)) { + if (rxfifo_stat & (1 << 15)) { printf("Error occured during receiving of packets on the bus.\n"); return 1; } else { @@ -384,7 +389,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) */ dwords_to_read = (pktsize + 3) >> 2; // PIO copy of data received: - while(dwords_to_read > 0) { + while (dwords_to_read > 0) { recvbuf[*index] = SMSC9220->RX_DATA_PORT; (*index)++; dwords_to_read--; @@ -407,7 +412,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) // Does the actual transfer of data to FIFO, note it does no // fifo availability checking. This should be done by caller. // Assumes the whole frame is transferred at once as a single segment -void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length) +void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length) { unsigned int txcmd_a, txcmd_b; unsigned int dwords_to_write; @@ -432,18 +437,18 @@ void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length) dwritten = dwords_to_write = (length + 3) >> 2; // PIO Copy to FIFO. Could replace this with DMA. - while(dwords_to_write > 0) { - SMSC9220->TX_DATA_PORT = *pktptr; - pktptr++; - dwords_to_write--; + while (dwords_to_write > 0) { + SMSC9220->TX_DATA_PORT = *pktptr; + pktptr++; + dwords_to_write--; } xmit_stat = SMSC9220->TX_STAT_PORT; xmit_stat2 = SMSC9220->TX_STAT_PORT; xmit_inf = SMSC9220->TX_FIFO_INF; - if(xmit_stat2 != 0 ) { - for(i = 0; i < 6; i++) { + if (xmit_stat2 != 0) { + for (i = 0; i < 6; i++) { xmit_stat2 = SMSC9220->TX_STAT_PORT; } } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h index a4f514c80b..38e9d66610 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. */ #ifndef _ETH_MPS2_H_ @@ -60,6 +60,6 @@ void smsc9220_set_soft_int(void); void smsc9220_clear_soft_int(void); unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index); -void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length); +void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length); #endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c index 6a07e98dcb..c1de220b66 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c @@ -34,12 +34,9 @@ void i2c_delay(unsigned int tick) start = MPS2_FPGAIO->COUNTER; end = start + (tick); - if(end >= start) - { + if (end >= start) { while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); - } - else - { + } else { while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER < end); } @@ -56,12 +53,9 @@ void Sleepms(unsigned int msec) start = MPS2_FPGAIO->COUNTER; end = start + (25 * msec * 1000); - if(end >= start) - { + if (end >= start) { while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); - } - else - { + } else { while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER < end); } @@ -77,12 +71,9 @@ void Sleepus(unsigned int usec) start = MPS2_FPGAIO->COUNTER; end = start + (25 * usec); - if(end >= start) - { + if (end >= start) { while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); - } - else - { + } else { while (MPS2_FPGAIO->COUNTER >= start); while (MPS2_FPGAIO->COUNTER < end); } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c index 47a7ed1019..0b8b928e7d 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c @@ -42,11 +42,11 @@ int smsc9220_check_id(void) id = smsc9220_read_id(); // If bottom and top halves of the word are the same - if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { + if (((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { error = 1; return error; } - switch(((id >> 16) & 0xFFFF)) { + switch (((id >> 16) & 0xFFFF)) { case 0x9220: break; @@ -81,7 +81,7 @@ int smsc9220_check_macaddress(void) smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); - if(mac_high != mac_valid_high || mac_low != mac_valid_low) { + if (mac_high != mac_valid_high || mac_low != mac_valid_low) { error = TRUE; return error; } @@ -97,7 +97,7 @@ void smsc9220_print_mac_registers() i = 0; read = 0; - for(i = 1; i <= 0xC; i++) { + for (i = 1; i <= 0xC; i++) { smsc9220_mac_regread(i, &read); } return; @@ -111,7 +111,7 @@ void smsc9220_print_phy_registers() i = 0; read = 0; - for(i = 0; i <= 6; i++) { + for (i = 0; i <= 6; i++) { smsc9220_phy_regread(i, &read); } smsc9220_phy_regread(i = 17, &read); @@ -133,18 +133,18 @@ void smsc9220_print_phy_registers() Ethernet Device initialize *----------------------------------------------------------------------------*/ -int ethernet_transmission(unsigned char * pkt, unsigned int length) +int ethernet_transmission(unsigned char *pkt, unsigned int length) { smsc9220_xmit_packet(pkt, length); return 0; } -int ethernet_reception(unsigned int *recvbuf, unsigned int *index) +int ethernet_reception(unsigned int *recvbuf, unsigned int *index) { return smsc9220_recv_packet((unsigned int *)recvbuf, index); } -int ethernet_mac_address(char *mac) +int ethernet_mac_address(char *mac) { return smsc9220_check_macaddress(); } @@ -156,10 +156,10 @@ unsigned int ethernet_check_ready(void) unsigned int ethernet_intf() { - unsigned int txfifo_inf; - + unsigned int txfifo_inf; + txfifo_inf = SMSC9220->TX_FIFO_INF; - + return txfifo_inf; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h index b5fff1763e..33a9d83a58 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h @@ -28,7 +28,7 @@ extern "C" { // Connection constants // send ethernet write buffer, returning the packet size sent -int ethernet_transmission(unsigned char * pkt, unsigned int length); +int ethernet_transmission(unsigned char *pkt, unsigned int length); // recieve from ethernet buffer, returning packet size, or 0 if no packet int ethernet_reception(unsigned int *recvbuf, unsigned int *index); diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h index b39cc0f8a3..1daab820b3 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h @@ -40,56 +40,55 @@ #define CMSDK_CM0_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ +typedef enum IRQn { + /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ -/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ -/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ - UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ - PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ - SPI_IRQn = 11, /*!< SPI Interrupt */ - UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ - I2S_IRQn = 14, /*!< I2S Interrupt */ - TSC_IRQn = 15, /*!< Touch Screen Interrupt */ - PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ - PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ - UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ - UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ - UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ - UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ - ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ - SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ - PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ - PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ - PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ - PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ - PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ - PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ - PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ - PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ + /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -113,31 +112,30 @@ typedef enum IRQn /* ------------------- Start of section using anonymous unions ------------------ */ #if defined ( __CC_ARM ) - #pragma push +#pragma push #pragma anon_unions #elif defined(__ICCARM__) - #pragma language=extended +#pragma language=extended #elif defined(__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #else - #warning Not supported compiler type +#warning Not supported compiler type #endif /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ - __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; - __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ } CMSDK_UART_TypeDef; @@ -196,14 +194,13 @@ typedef struct /*----------------------------- Timer (TIMER) -------------------------------*/ -typedef struct -{ - __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ - __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ - __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; } CMSDK_TIMER_TypeDef; @@ -236,26 +233,25 @@ typedef struct /*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ - __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ - __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ - __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ - __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ - __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ - __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ - uint32_t RESERVED0; - __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ - __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ - __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ - __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ - __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ - __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ - __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ - uint32_t RESERVED1[945]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +typedef struct { + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ } CMSDK_DUALTIMER_BOTH_TypeDef; #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ @@ -331,15 +327,14 @@ typedef struct #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ -typedef struct -{ - __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ - __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ - __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ - __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ - __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ - __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ - __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +typedef struct { + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ } CMSDK_DUALTIMER_SINGLE_TypeDef; #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ @@ -380,28 +375,27 @@ typedef struct /*-------------------- General Purpose Input Output (GPIO) -------------------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ - __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ - uint32_t RESERVED0[2]; - __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ - __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ - __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ - __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ - __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ - __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ - __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ - __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ - __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ - __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ }; - uint32_t RESERVED1[241]; - __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ - __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ } CMSDK_GPIO_TypeDef; #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ @@ -454,13 +448,12 @@ typedef struct /*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ - __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ - __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ - __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ - __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +typedef struct { + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ } CMSDK_SYSCON_TypeDef; #define CMSDK_SYSCON_REMAP_Pos 0 @@ -495,26 +488,25 @@ typedef struct /*------------- PL230 uDMA (PL230) --------------------------------------*/ -typedef struct -{ - __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ - __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ - __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ - __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ - __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ - __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ - __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ - __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ - __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ - __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ - __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ - __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ - __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ - __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ - __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ - __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ - uint32_t RESERVED0[3]; - __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ +typedef struct { + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ } CMSDK_PL230_TypeDef; @@ -591,21 +583,20 @@ typedef struct /*------------------- Watchdog ----------------------------------------------*/ -typedef struct -{ +typedef struct { - __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ - __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ - __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ - __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ - uint32_t RESERVED0[762]; - __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ - uint32_t RESERVED1[191]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ -}CMSDK_WATCHDOG_TypeDef; + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +} CMSDK_WATCHDOG_TypeDef; #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ @@ -641,17 +632,17 @@ typedef struct /* -------------------- End of section using anonymous unions ------------------- */ #if defined ( __CC_ARM ) - #pragma pop +#pragma pop #elif defined(__ICCARM__) - /* leave anonymous unions enabled */ +/* leave anonymous unions enabled */ #elif defined(__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #else - #warning Not supported compiler type +#warning Not supported compiler type #endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c index 9d2b3d8420..98d463113f 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c @@ -36,18 +36,20 @@ #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - // int i; +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + // int i; // Space for dynamic vectors, initialised to allocate in R/W - static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; // Set the vector vectors[IRQn + 16] = vector; } -uint32_t NVIC_GetVector(IRQn_Type IRQn) { +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ // We can always read vectors at 0x0, as the addresses are remapped - uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; // Return the vector return vectors[IRQn + 16]; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h index 04fb9ba365..29bad23617 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h @@ -37,17 +37,17 @@ #define __DEVICE_H #if defined CMSDK_CM0 - #include "CMSDK_CM0.h" /* device specific header file */ +#include "CMSDK_CM0.h" /* device specific header file */ #elif defined CMSDK_CM0plus - #include "CMSDK_CM0plus.h" /* device specific header file */ +#include "CMSDK_CM0plus.h" /* device specific header file */ #elif defined CMSDK_CM3 - #include "CMSDK_CM3.h" /* device specific header file */ +#include "CMSDK_CM3.h" /* device specific header file */ #elif defined CMSDK_CM4 - #include "CMSDK_CM4.h" /* device specific header file */ +#include "CMSDK_CM4.h" /* device specific header file */ #elif defined CMSDK_CM7 - #include "CMSDK_CM7.h" /* device specific header file */ +#include "CMSDK_CM7.h" /* device specific header file */ #else - #warning "no appropriate header file found!" +#warning "no appropriate header file found!" #endif #endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c index 64c01489bb..33cb7d64b1 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.c @@ -64,10 +64,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } @@ -80,9 +80,9 @@ void SystemCoreClockUpdate (void) * @brief Setup the microcontroller system. * Initialize the System. */ -void SystemInit (void) +void SystemInit(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h index 6269267607..dc533c9e34 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h @@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) * * @brief Setup the microcontroller system. * Initialize the System and update the SystemCoreClock variable. */ -extern void SystemInit (void); +extern void SystemInit(void); /** * Update SystemCoreClock variable @@ -67,7 +67,7 @@ extern void SystemInit (void); * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -extern void SystemCoreClockUpdate (void); +extern void SystemCoreClockUpdate(void); #ifdef __cplusplus } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h index 6628b97ab7..a63b6c1448 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h @@ -40,56 +40,55 @@ #define CMSDK_CM0plus_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ +typedef enum IRQn { + /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ -/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ -/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ - UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ - PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ - SPI_IRQn = 11, /*!< SPI Interrupt */ - UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ - I2S_IRQn = 14, /*!< I2S Interrupt */ - TSC_IRQn = 15, /*!< Touch Screen Interrupt */ - PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ - PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ - UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ - UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ - UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ - UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ - ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ - SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ - PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ - PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ - PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ - PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ - PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ - PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ - PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ - PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ + /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -114,31 +113,30 @@ typedef enum IRQn /* ------------------- Start of section using anonymous unions ------------------ */ #if defined ( __CC_ARM ) - #pragma push +#pragma push #pragma anon_unions #elif defined(__ICCARM__) - #pragma language=extended +#pragma language=extended #elif defined(__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #else - #warning Not supported compiler type +#warning Not supported compiler type #endif /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ - __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; - __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ } CMSDK_UART_TypeDef; @@ -197,14 +195,13 @@ typedef struct /*----------------------------- Timer (TIMER) -------------------------------*/ -typedef struct -{ - __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ - __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ - __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; } CMSDK_TIMER_TypeDef; @@ -237,26 +234,25 @@ typedef struct /*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ - __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ - __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ - __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ - __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ - __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ - __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ - uint32_t RESERVED0; - __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ - __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ - __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ - __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ - __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ - __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ - __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ - uint32_t RESERVED1[945]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +typedef struct { + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ } CMSDK_DUALTIMER_BOTH_TypeDef; #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ @@ -332,15 +328,14 @@ typedef struct #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ -typedef struct -{ - __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ - __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ - __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ - __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ - __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ - __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ - __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +typedef struct { + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ } CMSDK_DUALTIMER_SINGLE_TypeDef; #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ @@ -381,28 +376,27 @@ typedef struct /*-------------------- General Purpose Input Output (GPIO) -------------------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ - __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ - uint32_t RESERVED0[2]; - __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ - __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ - __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ - __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ - __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ - __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ - __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ - __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ - __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ - __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ }; - uint32_t RESERVED1[241]; - __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ - __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ } CMSDK_GPIO_TypeDef; #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ @@ -455,13 +449,12 @@ typedef struct /*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ - __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ - __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ - __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ - __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +typedef struct { + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ } CMSDK_SYSCON_TypeDef; #define CMSDK_SYSCON_REMAP_Pos 0 @@ -496,26 +489,25 @@ typedef struct /*------------- PL230 uDMA (PL230) --------------------------------------*/ -typedef struct -{ - __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ - __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ - __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ - __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ - __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ - __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ - __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ - __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ - __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ - __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ - __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ - __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ - __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ - __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ - __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ - __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ - uint32_t RESERVED0[3]; - __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ +typedef struct { + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ } CMSDK_PL230_TypeDef; @@ -592,21 +584,20 @@ typedef struct /*------------------- Watchdog ----------------------------------------------*/ -typedef struct -{ +typedef struct { - __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ - __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ - __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ - __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ - uint32_t RESERVED0[762]; - __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ - uint32_t RESERVED1[191]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ -}CMSDK_WATCHDOG_TypeDef; + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +} CMSDK_WATCHDOG_TypeDef; #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ @@ -642,17 +633,17 @@ typedef struct /* -------------------- End of section using anonymous unions ------------------- */ #if defined ( __CC_ARM ) - #pragma pop +#pragma pop #elif defined(__ICCARM__) - /* leave anonymous unions enabled */ +/* leave anonymous unions enabled */ #elif defined(__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #else - #warning Not supported compiler type +#warning Not supported compiler type #endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h index af11e0b478..1e11483c3a 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h @@ -46,40 +46,39 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct -{ - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct { + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -107,58 +106,57 @@ typedef struct /* SCC Register declaration */ /******************************************************************************/ -typedef struct // -{ - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct { // + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -166,60 +164,59 @@ typedef struct // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf -{ - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct { + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -331,107 +327,106 @@ typedef struct /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct { + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -486,44 +481,43 @@ typedef struct /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct // SMSC LAN9220 -{ -__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; -__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct { // SMSC LAN9220 + __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; + __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; -__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) -__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) -__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) -__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) + __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) + __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) + __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) + __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) -__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) -__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) -__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) -__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) -__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) -__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) -__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) -__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) -__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) -__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) -__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) -__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) -__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) -__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) -__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) -__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) -__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) -__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) -__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) -__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) -__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) -__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) -__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) -__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) + __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) + __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) + __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) + __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) + __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) + __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) + __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) + __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) + __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) + __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) + __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) + __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) + __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) + __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) + __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) + __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) + __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) + __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) + __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) + __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) + __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) + __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) + __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) + __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -596,9 +590,9 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h index 04fb9ba365..29bad23617 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/peripherallink.h @@ -37,17 +37,17 @@ #define __DEVICE_H #if defined CMSDK_CM0 - #include "CMSDK_CM0.h" /* device specific header file */ +#include "CMSDK_CM0.h" /* device specific header file */ #elif defined CMSDK_CM0plus - #include "CMSDK_CM0plus.h" /* device specific header file */ +#include "CMSDK_CM0plus.h" /* device specific header file */ #elif defined CMSDK_CM3 - #include "CMSDK_CM3.h" /* device specific header file */ +#include "CMSDK_CM3.h" /* device specific header file */ #elif defined CMSDK_CM4 - #include "CMSDK_CM4.h" /* device specific header file */ +#include "CMSDK_CM4.h" /* device specific header file */ #elif defined CMSDK_CM7 - #include "CMSDK_CM7.h" /* device specific header file */ +#include "CMSDK_CM7.h" /* device specific header file */ #else - #warning "no appropriate header file found!" +#warning "no appropriate header file found!" #endif #endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c index eae03be72d..71d075705d 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.c @@ -64,10 +64,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } @@ -80,9 +80,9 @@ void SystemCoreClockUpdate (void) * @brief Setup the microcontroller system. * Initialize the System. */ -void SystemInit (void) +void SystemInit(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h index 022e3e7deb..75eda4c7aa 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/system_CMSDK_CM0plus.h @@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) * * @brief Setup the microcontroller system. * Initialize the System and update the SystemCoreClock variable. */ -extern void SystemInit (void); +extern void SystemInit(void); /** * Update SystemCoreClock variable @@ -67,7 +67,7 @@ extern void SystemInit (void); * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -extern void SystemCoreClockUpdate (void); +extern void SystemCoreClockUpdate(void); #ifdef __cplusplus } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h index cc1152b2a7..0b4746d1a7 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/CMSDK_CM3.h @@ -40,58 +40,57 @@ #define CMSDK_CM3_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ -typedef enum IRQn -{ -/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +typedef enum IRQn { + /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ -/****** CMSDK Specific Interrupt Numbers *********************************************************/ - UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ - PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ - SPI_IRQn = 11, /*!< SPI Interrupt */ - UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ - I2S_IRQn = 14, /*!< I2S Interrupt */ - TSC_IRQn = 15, /*!< Touch Screen Interrupt */ - PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ - PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ - UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ - UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ - UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ - UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ - ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ - SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ - PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ - PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ - PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ - PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ - PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ - PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ - PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ - PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ + /****** CMSDK Specific Interrupt Numbers *********************************************************/ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -115,31 +114,30 @@ typedef enum IRQn /* ------------------- Start of section using anonymous unions ------------------ */ #if defined ( __CC_ARM ) - #pragma push +#pragma push #pragma anon_unions #elif defined(__ICCARM__) - #pragma language=extended +#pragma language=extended #elif defined(__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #else - #warning Not supported compiler type +#warning Not supported compiler type #endif /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ - __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; - __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ } CMSDK_UART_TypeDef; @@ -198,14 +196,13 @@ typedef struct /*----------------------------- Timer (TIMER) -------------------------------*/ -typedef struct -{ - __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ - __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ - __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; } CMSDK_TIMER_TypeDef; @@ -238,26 +235,25 @@ typedef struct /*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ - __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ - __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ - __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ - __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ - __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ - __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ - uint32_t RESERVED0; - __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ - __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ - __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ - __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ - __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ - __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ - __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ - uint32_t RESERVED1[945]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +typedef struct { + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ } CMSDK_DUALTIMER_BOTH_TypeDef; #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ @@ -333,15 +329,14 @@ typedef struct #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ -typedef struct -{ - __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ - __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ - __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ - __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ - __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ - __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ - __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +typedef struct { + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ } CMSDK_DUALTIMER_SINGLE_TypeDef; #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ @@ -382,28 +377,27 @@ typedef struct /*-------------------- General Purpose Input Output (GPIO) -------------------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ - __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ - uint32_t RESERVED0[2]; - __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ - __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ - __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ - __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ - __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ - __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ - __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ - __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ - __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ - __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ }; - uint32_t RESERVED1[241]; - __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ - __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ } CMSDK_GPIO_TypeDef; #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ @@ -456,13 +450,12 @@ typedef struct /*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ - __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ - __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ - __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ - __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +typedef struct { + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ } CMSDK_SYSCON_TypeDef; #define CMSDK_SYSCON_REMAP_Pos 0 @@ -497,26 +490,25 @@ typedef struct /*------------- PL230 uDMA (PL230) --------------------------------------*/ -typedef struct -{ - __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ - __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ - __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ - __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ - __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ - __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ - __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ - __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ - __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ - __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ - __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ - __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ - __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ - __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ - __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ - __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ - uint32_t RESERVED0[3]; - __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ +typedef struct { + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ } CMSDK_PL230_TypeDef; @@ -593,21 +585,20 @@ typedef struct /*------------------- Watchdog ----------------------------------------------*/ -typedef struct -{ +typedef struct { - __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ - __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ - __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ - __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ - uint32_t RESERVED0[762]; - __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ - uint32_t RESERVED1[191]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ -}CMSDK_WATCHDOG_TypeDef; + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +} CMSDK_WATCHDOG_TypeDef; #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ @@ -643,17 +634,17 @@ typedef struct /* -------------------- End of section using anonymous unions ------------------- */ #if defined ( __CC_ARM ) - #pragma pop +#pragma pop #elif defined(__ICCARM__) - /* leave anonymous unions enabled */ +/* leave anonymous unions enabled */ #elif defined(__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #else - #warning Not supported compiler type +#warning Not supported compiler type #endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h index 3b78c8b44f..1e11483c3a 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h @@ -46,40 +46,39 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct -{ - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct { + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -107,58 +106,57 @@ typedef struct /* SCC Register declaration */ /******************************************************************************/ -typedef struct // -{ - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct { // + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -166,60 +164,59 @@ typedef struct // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf -{ - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct { + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -331,107 +327,106 @@ typedef struct /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct { + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -486,44 +481,43 @@ typedef struct /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct // SMSC LAN9220 -{ -__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; -__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct { // SMSC LAN9220 + __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; + __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; -__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) -__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) -__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) -__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) + __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) + __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) + __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) + __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) -__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) -__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) -__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) -__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) -__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) -__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) -__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) -__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) -__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) -__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) -__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) -__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) -__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) -__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) -__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) -__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) -__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) -__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) -__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) -__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) -__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) -__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) -__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) -__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) + __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) + __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) + __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) + __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) + __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) + __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) + __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) + __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) + __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) + __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) + __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) + __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) + __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) + __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) + __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) + __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) + __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) + __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) + __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) + __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) + __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) + __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) + __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) + __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -596,9 +590,9 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h index 04fb9ba365..29bad23617 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/peripherallink.h @@ -37,17 +37,17 @@ #define __DEVICE_H #if defined CMSDK_CM0 - #include "CMSDK_CM0.h" /* device specific header file */ +#include "CMSDK_CM0.h" /* device specific header file */ #elif defined CMSDK_CM0plus - #include "CMSDK_CM0plus.h" /* device specific header file */ +#include "CMSDK_CM0plus.h" /* device specific header file */ #elif defined CMSDK_CM3 - #include "CMSDK_CM3.h" /* device specific header file */ +#include "CMSDK_CM3.h" /* device specific header file */ #elif defined CMSDK_CM4 - #include "CMSDK_CM4.h" /* device specific header file */ +#include "CMSDK_CM4.h" /* device specific header file */ #elif defined CMSDK_CM7 - #include "CMSDK_CM7.h" /* device specific header file */ +#include "CMSDK_CM7.h" /* device specific header file */ #else - #warning "no appropriate header file found!" +#warning "no appropriate header file found!" #endif #endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c index 9d036d81f4..45983f9dc7 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.c @@ -65,10 +65,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } @@ -81,13 +81,13 @@ void SystemCoreClockUpdate (void) * @brief Setup the microcontroller system. * Initialize the System. */ -void SystemInit (void) +void SystemInit(void) { #ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h index 148614229f..f55970385c 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/system_CMSDK_CM3.h @@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) * * @brief Setup the microcontroller system. * Initialize the System and update the SystemCoreClock variable. */ -extern void SystemInit (void); +extern void SystemInit(void); /** * Update SystemCoreClock variable @@ -67,7 +67,7 @@ extern void SystemInit (void); * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -extern void SystemCoreClockUpdate (void); +extern void SystemCoreClockUpdate(void); #ifdef __cplusplus } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h index 7b49315127..a7bb39bfe9 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/CMSDK_CM4.h @@ -40,58 +40,57 @@ #define CMSDK_CM4_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ -typedef enum IRQn -{ -/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +typedef enum IRQn { + /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ -/****** CMSDK Specific Interrupt Numbers *********************************************************/ - UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ - PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ - SPI_IRQn = 11, /*!< SPI Interrupt */ - UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ - I2S_IRQn = 14, /*!< I2S Interrupt */ - TSC_IRQn = 15, /*!< Touch Screen Interrupt */ - PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ - PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ - UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ - UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ - UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ - UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ - ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ - SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ - PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ - PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ - PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ - PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ - PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ - PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ - PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ - PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ + /****** CMSDK Specific Interrupt Numbers *********************************************************/ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -132,16 +131,15 @@ typedef enum IRQn memory mapped structure for CMSDK_UART @{ */ -typedef struct -{ - __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ - __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ - __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ - union { - __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ - __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ +typedef struct { + __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ + __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ + __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ }; - __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ + __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ } CMSDK_UART_TypeDef; @@ -205,14 +203,13 @@ typedef struct /** @addtogroup CMSDK_TIMER CMSDK Timer @{ */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ - __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */ - __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */ - union { - __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ - __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ + __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */ + __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ }; } CMSDK_TIMER_TypeDef; @@ -253,60 +250,59 @@ typedef struct @{ */ -typedef struct -{ - __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ - __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ - __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ - /* TimerEn: Timer Enable */ - /* TimerMode: Timer Mode */ - /* <0=> Freerunning-mode */ - /* <1=> Periodic mode */ - /* IntEnable: Interrupt Enable */ - /* TimerPre: Timer Prescale */ - /* <0=> / 1 */ - /* <1=> / 16 */ - /* <2=> / 256 */ - /* <3=> Undefined! */ - /* TimerSize: Timer Size */ - /* <0=> 16-bit counter */ - /* <1=> 32-bit counter */ - /* OneShot: One-shoot mode */ - /* <0=> Wrapping mode */ - /* <1=> One-shot mode */ - /* */ - __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ - __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ - __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ - __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ - uint32_t RESERVED0; - __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ - __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ - __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ - /* TimerEn: Timer Enable */ - /* TimerMode: Timer Mode */ - /* <0=> Freerunning-mode */ - /* <1=> Periodic mode */ - /* IntEnable: Interrupt Enable */ - /* TimerPre: Timer Prescale */ - /* <0=> / 1 */ - /* <1=> / 16 */ - /* <2=> / 256 */ - /* <3=> Undefined! */ - /* TimerSize: Timer Size */ - /* <0=> 16-bit counter */ - /* <1=> 32-bit counter */ - /* OneShot: One-shoot mode */ - /* <0=> Wrapping mode */ - /* <1=> One-shot mode */ - /* */ - __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ - __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ - __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ - __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ - uint32_t RESERVED1[945]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +typedef struct { + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ } CMSDK_DUALTIMER_BOTH_TypeDef; #define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */ @@ -381,32 +377,31 @@ typedef struct #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ -typedef struct -{ - __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ - __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ - __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ - /* TimerEn: Timer Enable */ - /* TimerMode: Timer Mode */ - /* <0=> Freerunning-mode */ - /* <1=> Periodic mode */ - /* IntEnable: Interrupt Enable */ - /* TimerPre: Timer Prescale */ - /* <0=> / 1 */ - /* <1=> / 16 */ - /* <2=> / 256 */ - /* <3=> Undefined! */ - /* TimerSize: Timer Size */ - /* <0=> 16-bit counter */ - /* <1=> 32-bit counter */ - /* OneShot: One-shoot mode */ - /* <0=> Wrapping mode */ - /* <1=> One-shot mode */ - /* */ - __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ - __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ - __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ - __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +typedef struct { + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ } CMSDK_DUALTIMER_SINGLE_TypeDef; #define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */ @@ -452,28 +447,27 @@ typedef struct /** @addtogroup CMSDK_GPIO CMSDK GPIO @{ */ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ - __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ - uint32_t RESERVED0[2]; - __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ - __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ - __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ - __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ - __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ - __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ - __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ - __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ - __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ - __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ }; - uint32_t RESERVED1[241]; - __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ - __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ } CMSDK_GPIO_TypeDef; #define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */ @@ -531,13 +525,12 @@ typedef struct /** @addtogroup CMSDK_SYSCON CMSDK System Control @{ */ -typedef struct -{ - __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ - __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ - __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ - __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ - __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +typedef struct { + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ } CMSDK_SYSCON_TypeDef; #define CMSDK_SYSCON_REMAP_Pos 0 @@ -576,26 +569,25 @@ typedef struct /** @addtogroup CMSDK_PL230 CMSDK uDMA controller @{ */ -typedef struct -{ - __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ - __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ - __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ - __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ - __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ - __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ - __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ - __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ - __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ - __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ - __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ - __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ - __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ - __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ - __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ - __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ - uint32_t RESERVED0[3]; - __IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */ +typedef struct { + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */ } CMSDK_PL230_TypeDef; @@ -679,155 +671,154 @@ typedef struct @{ */ -typedef struct -{ - __IO uint32_t UARTDR; // Data - // OE: Overrun error - // BE: Break error - // PE: Parity error - // FE: Framing error - // DATA: Received or Transmitting data (0..255) - // - union { - __I uint32_t UARTRSR; // Receive Status - // OE: Overrun error - // BE: Break error - // PE: Parity error - // FE: Framing error - // - __O uint32_t UARTECR; // Error Clear - // OE: Overrun error - // BE: Break error - // PE: Parity error - // FE: Framing error - // - }; - uint32_t RESERVED0[4]; - __IO uint32_t UARTFR; // Flags - // RI: Ring indicator - // TXFE: Transmit FIFO empty - // RXFF: Receive FIFO full - // TXFF: Transmit FIFO full - // RXFE: Receive FIFO empty - // BUSY: UART busy - // DCD: Data carrier detect - // DSR: Data set ready - // CTS: Clear to send - // - uint32_t RESERVED1; - __IO uint32_t UARTILPR; // IrDA Low-power Counter - // ILPDVSR: 8-bit low-power divisor value (0..255) - // - __IO uint32_t UARTIBRD; // Integer Baud Rate - // BAUD DIVINT: Integer baud rate divisor (0..65535) - // - __IO uint32_t UARTFBRD; // Fractional Baud Rate - // BAUD DIVFRAC: Fractional baud rate divisor (0..63) - // - __IO uint32_t UARTLCR_H; // Line Control - // SPS: Stick parity select - // WLEN: Word length - // <0=> 5 bits - // <1=> 6 bits - // <2=> 7 bits - // <3=> 8 bits - // FEN: Enable FIFOs - // STP2: Two stop bits select - // EPS: Even parity select - // PEN: Parity enable - // BRK: Send break - // - __IO uint32_t UARTCR; // Control - // CTSEn: CTS hardware flow control enable - // RTSEn: RTS hardware flow control enable - // Out2: Complement of Out2 modem status output - // Out1: Complement of Out1 modem status output - // RTS: Request to send - // DTR: Data transmit ready - // RXE: Receive enable - // TXE: Transmit enable - // LBE: Loop-back enable - // SIRLP: IrDA SIR low power mode - // SIREN: SIR enable - // UARTEN: UART enable - // - __IO uint32_t UARTIFLS; // Interrupt FIFO Level Select - // RXIFLSEL: Receive interrupt FIFO level select - // <0=> >= 1/8 full - // <1=> >= 1/4 full - // <2=> >= 1/2 full - // <3=> >= 3/4 full - // <4=> >= 7/8 full - // <5=> reserved - // <6=> reserved - // <7=> reserved - // TXIFLSEL: Transmit interrupt FIFO level select - // <0=> <= 1/8 full - // <1=> <= 1/4 full - // <2=> <= 1/2 full - // <3=> <= 3/4 full - // <4=> <= 7/8 full - // <5=> reserved - // <6=> reserved - // <7=> reserved - // - __IO uint32_t UARTIMSC; // Interrupt Mask Set / Clear - // OEIM: Overrun error interrupt mask - // BEIM: Break error interrupt mask - // PEIM: Parity error interrupt mask - // FEIM: Framing error interrupt mask - // RTIM: Receive interrupt mask - // TXIM: Transmit interrupt mask - // RXIM: Receive interrupt mask - // DSRMIM: nUARTDSR modem interrupt mask - // DCDMIM: nUARTDCD modem interrupt mask - // CTSMIM: nUARTCTS modem interrupt mask - // RIMIM: nUARTRI modem interrupt mask - // - __IO uint32_t UARTRIS; // Raw Interrupt Status - // OERIS: Overrun error interrupt status - // BERIS: Break error interrupt status - // PERIS: Parity error interrupt status - // FERIS: Framing error interrupt status - // RTRIS: Receive timeout interrupt status - // TXRIS: Transmit interrupt status - // RXRIS: Receive interrupt status - // DSRRMIS: nUARTDSR modem interrupt status - // DCDRMIS: nUARTDCD modem interrupt status - // CTSRMIS: nUARTCTS modem interrupt status - // RIRMIS: nUARTRI modem interrupt status - // - __IO uint32_t UARTMIS; // Masked Interrupt Status - // OEMIS: Overrun error masked interrupt status - // BEMIS: Break error masked interrupt status - // PEMIS: Parity error masked interrupt status - // FEMIS: Framing error masked interrupt status - // RTMIS: Receive timeout masked interrupt status - // TXMIS: Transmit masked interrupt status - // RXMIS: Receive masked interrupt status - // DSRMMIS: nUARTDSR modem masked interrupt status - // DCDMMIS: nUARTDCD modem masked interrupt status - // CTSMMIS: nUARTCTS modem masked interrupt status - // RIMMIS: nUARTRI modem masked interrupt status - // - __O uint32_t UARTICR; // Interrupt Clear - // OEIC: Overrun error interrupt clear - // BEIC: Break error interrupt clear - // PEIC: Parity error interrupt clear - // FEIC: Framing error interrupt clear - // RTIC: Receive timeout interrupt clear - // TXIC: Transmit interrupt clear - // RXIC: Receive interrupt clear - // DSRMIC: nUARTDSR modem interrupt clear - // DCDMIC: nUARTDCD modem interrupt clear - // CTSMIC: nUARTCTS modem interrupt clear - // RIMIC: nUARTRI modem interrupt clear - // - __IO uint32_t UARTDMACR; // DMA Control - // DMAONERR: DMA on error - // TXDMAE: Transmit DMA enable - // RXDMAE: Receive DMA enable - // +typedef struct { + __IO uint32_t UARTDR; // Data + // OE: Overrun error + // BE: Break error + // PE: Parity error + // FE: Framing error + // DATA: Received or Transmitting data (0..255) + // + union { + __I uint32_t UARTRSR; // Receive Status + // OE: Overrun error + // BE: Break error + // PE: Parity error + // FE: Framing error + // + __O uint32_t UARTECR; // Error Clear + // OE: Overrun error + // BE: Break error + // PE: Parity error + // FE: Framing error + // + }; + uint32_t RESERVED0[4]; + __IO uint32_t UARTFR; // Flags + // RI: Ring indicator + // TXFE: Transmit FIFO empty + // RXFF: Receive FIFO full + // TXFF: Transmit FIFO full + // RXFE: Receive FIFO empty + // BUSY: UART busy + // DCD: Data carrier detect + // DSR: Data set ready + // CTS: Clear to send + // + uint32_t RESERVED1; + __IO uint32_t UARTILPR; // IrDA Low-power Counter + // ILPDVSR: 8-bit low-power divisor value (0..255) + // + __IO uint32_t UARTIBRD; // Integer Baud Rate + // BAUD DIVINT: Integer baud rate divisor (0..65535) + // + __IO uint32_t UARTFBRD; // Fractional Baud Rate + // BAUD DIVFRAC: Fractional baud rate divisor (0..63) + // + __IO uint32_t UARTLCR_H; // Line Control + // SPS: Stick parity select + // WLEN: Word length + // <0=> 5 bits + // <1=> 6 bits + // <2=> 7 bits + // <3=> 8 bits + // FEN: Enable FIFOs + // STP2: Two stop bits select + // EPS: Even parity select + // PEN: Parity enable + // BRK: Send break + // + __IO uint32_t UARTCR; // Control + // CTSEn: CTS hardware flow control enable + // RTSEn: RTS hardware flow control enable + // Out2: Complement of Out2 modem status output + // Out1: Complement of Out1 modem status output + // RTS: Request to send + // DTR: Data transmit ready + // RXE: Receive enable + // TXE: Transmit enable + // LBE: Loop-back enable + // SIRLP: IrDA SIR low power mode + // SIREN: SIR enable + // UARTEN: UART enable + // + __IO uint32_t UARTIFLS; // Interrupt FIFO Level Select + // RXIFLSEL: Receive interrupt FIFO level select + // <0=> >= 1/8 full + // <1=> >= 1/4 full + // <2=> >= 1/2 full + // <3=> >= 3/4 full + // <4=> >= 7/8 full + // <5=> reserved + // <6=> reserved + // <7=> reserved + // TXIFLSEL: Transmit interrupt FIFO level select + // <0=> <= 1/8 full + // <1=> <= 1/4 full + // <2=> <= 1/2 full + // <3=> <= 3/4 full + // <4=> <= 7/8 full + // <5=> reserved + // <6=> reserved + // <7=> reserved + // + __IO uint32_t UARTIMSC; // Interrupt Mask Set / Clear + // OEIM: Overrun error interrupt mask + // BEIM: Break error interrupt mask + // PEIM: Parity error interrupt mask + // FEIM: Framing error interrupt mask + // RTIM: Receive interrupt mask + // TXIM: Transmit interrupt mask + // RXIM: Receive interrupt mask + // DSRMIM: nUARTDSR modem interrupt mask + // DCDMIM: nUARTDCD modem interrupt mask + // CTSMIM: nUARTCTS modem interrupt mask + // RIMIM: nUARTRI modem interrupt mask + // + __IO uint32_t UARTRIS; // Raw Interrupt Status + // OERIS: Overrun error interrupt status + // BERIS: Break error interrupt status + // PERIS: Parity error interrupt status + // FERIS: Framing error interrupt status + // RTRIS: Receive timeout interrupt status + // TXRIS: Transmit interrupt status + // RXRIS: Receive interrupt status + // DSRRMIS: nUARTDSR modem interrupt status + // DCDRMIS: nUARTDCD modem interrupt status + // CTSRMIS: nUARTCTS modem interrupt status + // RIRMIS: nUARTRI modem interrupt status + // + __IO uint32_t UARTMIS; // Masked Interrupt Status + // OEMIS: Overrun error masked interrupt status + // BEMIS: Break error masked interrupt status + // PEMIS: Parity error masked interrupt status + // FEMIS: Framing error masked interrupt status + // RTMIS: Receive timeout masked interrupt status + // TXMIS: Transmit masked interrupt status + // RXMIS: Receive masked interrupt status + // DSRMMIS: nUARTDSR modem masked interrupt status + // DCDMMIS: nUARTDCD modem masked interrupt status + // CTSMMIS: nUARTCTS modem masked interrupt status + // RIMMIS: nUARTRI modem masked interrupt status + // + __O uint32_t UARTICR; // Interrupt Clear + // OEIC: Overrun error interrupt clear + // BEIC: Break error interrupt clear + // PEIC: Parity error interrupt clear + // FEIC: Framing error interrupt clear + // RTIC: Receive timeout interrupt clear + // TXIC: Transmit interrupt clear + // RXIC: Receive interrupt clear + // DSRMIC: nUARTDSR modem interrupt clear + // DCDMIC: nUARTDCD modem interrupt clear + // CTSMIC: nUARTCTS modem interrupt clear + // RIMIC: nUARTRI modem interrupt clear + // + __IO uint32_t UARTDMACR; // DMA Control + // DMAONERR: DMA on error + // TXDMAE: Transmit DMA enable + // RXDMAE: Receive DMA enable + // } PL110_UART_TypeDef; #define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */ @@ -1113,24 +1104,23 @@ typedef struct /** @addtogroup CMSDK_Watchdog CMSDK Watchdog @{ */ -typedef struct -{ +typedef struct { - __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ - __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - /* RESEN: Reset enable */ - /* INTEN: Interrupt enable */ - /* */ - __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ - __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ - __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ - uint32_t RESERVED0[762]; - __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ - uint32_t RESERVED1[191]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ -}CMSDK_WATCHDOG_TypeDef; + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + /* RESEN: Reset enable */ + /* INTEN: Interrupt enable */ + /* */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +} CMSDK_WATCHDOG_TypeDef; #define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */ @@ -1168,21 +1158,20 @@ typedef struct /** @addtogroup CMSDK_PL061 CMSDK APB GPIO @{ */ -typedef struct -{ +typedef struct { -__IO uint32_t DATA[256]; -__IO uint32_t DIR; -__IO uint32_t INTSENSE; -__IO uint32_t INTBOTHEDGE; -__IO uint32_t INTEVENT; -__IO uint32_t INTMASK; -__O uint32_t RAWINTSTAT; -__O uint32_t MASKINTSTAT; -__I uint32_t INTCLR; -__IO uint32_t MODECTRL; + __IO uint32_t DATA[256]; + __IO uint32_t DIR; + __IO uint32_t INTSENSE; + __IO uint32_t INTBOTHEDGE; + __IO uint32_t INTEVENT; + __IO uint32_t INTMASK; + __O uint32_t RAWINTSTAT; + __O uint32_t MASKINTSTAT; + __I uint32_t INTCLR; + __IO uint32_t MODECTRL; -}APBGPIO_TypeDef; +} APBGPIO_TypeDef; #define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */ #define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h index 6b2a5ac3d7..1e11483c3a 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h @@ -46,40 +46,39 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct -{ - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct { + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -107,58 +106,57 @@ typedef struct /* SCC Register declaration */ /******************************************************************************/ -typedef struct // -{ - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct { // + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -166,60 +164,59 @@ typedef struct // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf -{ - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct { + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -331,107 +327,106 @@ typedef struct /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct { + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -486,44 +481,43 @@ typedef struct /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct // SMSC LAN9220 -{ -__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; -__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct { // SMSC LAN9220 + __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; + __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; -__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) -__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) -__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) -__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) + __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) + __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) + __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) + __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) -__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) -__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) -__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) -__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) -__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) -__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) -__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) -__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) -__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) -__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) -__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) -__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) -__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) -__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) -__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) -__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) -__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) -__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) -__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) -__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) -__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) -__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) -__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) -__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) + __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) + __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) + __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) + __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) + __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) + __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) + __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) + __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) + __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) + __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) + __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) + __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) + __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) + __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) + __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) + __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) + __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) + __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) + __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) + __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) + __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) + __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) + __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) + __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h index 04fb9ba365..29bad23617 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/peripherallink.h @@ -37,17 +37,17 @@ #define __DEVICE_H #if defined CMSDK_CM0 - #include "CMSDK_CM0.h" /* device specific header file */ +#include "CMSDK_CM0.h" /* device specific header file */ #elif defined CMSDK_CM0plus - #include "CMSDK_CM0plus.h" /* device specific header file */ +#include "CMSDK_CM0plus.h" /* device specific header file */ #elif defined CMSDK_CM3 - #include "CMSDK_CM3.h" /* device specific header file */ +#include "CMSDK_CM3.h" /* device specific header file */ #elif defined CMSDK_CM4 - #include "CMSDK_CM4.h" /* device specific header file */ +#include "CMSDK_CM4.h" /* device specific header file */ #elif defined CMSDK_CM7 - #include "CMSDK_CM7.h" /* device specific header file */ +#include "CMSDK_CM7.h" /* device specific header file */ #else - #warning "no appropriate header file found!" +#warning "no appropriate header file found!" #endif #endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c index 81657dda17..401f9f69ac 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.c @@ -64,10 +64,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } @@ -80,17 +80,17 @@ void SystemCoreClockUpdate (void) * @brief Setup the microcontroller system. * Initialize the System. */ -void SystemInit (void) +void SystemInit(void) { - #if (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ - #endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */ + (3UL << 11 * 2)); /* set CP11 Full Access */ #endif - SystemCoreClock = __SYSTEM_CLOCK; +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h index 8208fd832c..7eddb44ba6 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/system_CMSDK_CM4.h @@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) * * @brief Setup the microcontroller system. * Initialize the System and update the SystemCoreClock variable. */ -extern void SystemInit (void); +extern void SystemInit(void); /** * Update SystemCoreClock variable @@ -67,7 +67,7 @@ extern void SystemInit (void); * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -extern void SystemCoreClockUpdate (void); +extern void SystemCoreClockUpdate(void); #ifdef __cplusplus } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h index 43b59b9316..2b82b87ef4 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/CMSDK_CM7.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file CMSDK_CM7.h * @brief CMSIS Core Peripheral Access Layer Header File for @@ -46,52 +46,51 @@ extern "C" { /* ------------------------- Interrupt Number Definition ------------------------ */ -typedef enum IRQn -{ -/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +typedef enum IRQn { + /* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ -/* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */ - UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ - PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ - SPI_IRQn = 11, /* SPI Interrupt */ - UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /* Ethernet Interrupt */ - I2S_IRQn = 14, /* I2S Interrupt */ - TSC_IRQn = 15, /* Touch Screen Interrupt */ - PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */ - PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */ - UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */ - UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */ - UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */ - UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */ - ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */ - SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */ - PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */ - PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */ - PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */ - PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */ - PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */ - PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */ - PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */ - PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */ + /* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */ + UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ + PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ + SPI_IRQn = 11, /* SPI Interrupt */ + UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /* Ethernet Interrupt */ + I2S_IRQn = 14, /* I2S Interrupt */ + TSC_IRQn = 15, /* Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -119,33 +118,32 @@ typedef enum IRQn /* ------------------- Start of section using anonymous unions ------------------ */ #if defined (__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined (__ICCARM__) - #pragma language=extended +#pragma language=extended #elif defined (__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TASKING__) - #pragma warning 586 +#pragma warning 586 #elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #else - #warning Not supported compiler type +#warning Not supported compiler type #endif /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ - __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; - __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ } CMSDK_UART_TypeDef; @@ -204,14 +202,13 @@ typedef struct /*----------------------------- Timer (TIMER) -------------------------------*/ -typedef struct -{ - __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ - __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ - __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; } CMSDK_TIMER_TypeDef; @@ -244,26 +241,25 @@ typedef struct /*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ - __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ - __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ - __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ - __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ - __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ - __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ - uint32_t RESERVED0; - __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ - __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ - __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ - __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ - __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ - __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ - __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ - uint32_t RESERVED1[945]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +typedef struct { + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ } CMSDK_DUALTIMER_BOTH_TypeDef; #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ @@ -339,15 +335,14 @@ typedef struct #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ -typedef struct -{ - __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ - __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ - __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ - __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ - __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ - __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ - __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +typedef struct { + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ } CMSDK_DUALTIMER_SINGLE_TypeDef; #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ @@ -388,28 +383,27 @@ typedef struct /*-------------------- General Purpose Input Output (GPIO) -------------------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ - __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ - uint32_t RESERVED0[2]; - __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ - __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ - __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ - __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ - __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ - __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ - __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ - __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ - __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ - __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ +typedef struct { + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ }; - uint32_t RESERVED1[241]; - __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ - __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ } CMSDK_GPIO_TypeDef; #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ @@ -462,13 +456,12 @@ typedef struct /*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ - __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ - __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ - __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ - __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +typedef struct { + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ } CMSDK_SYSCON_TypeDef; #define CMSDK_SYSCON_REMAP_Pos 0 @@ -503,26 +496,25 @@ typedef struct /*------------- PL230 uDMA (PL230) --------------------------------------*/ -typedef struct -{ - __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ - __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ - __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ - __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ - __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ - __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ - __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ - __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ - __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ - __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ - __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ - __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ - __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ - __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ - __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ - __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ - uint32_t RESERVED0[3]; - __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ +typedef struct { + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ } CMSDK_PL230_TypeDef; @@ -599,21 +591,20 @@ typedef struct /*------------------- Watchdog ----------------------------------------------*/ -typedef struct -{ +typedef struct { - __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ - __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ - __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ - __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ - uint32_t RESERVED0[762]; - __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ - uint32_t RESERVED1[191]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ -}CMSDK_WATCHDOG_TypeDef; + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +} CMSDK_WATCHDOG_TypeDef; #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ @@ -649,19 +640,19 @@ typedef struct /* -------------------- End of section using anonymous unions ------------------- */ #if defined (__CC_ARM) - #pragma pop +#pragma pop #elif defined (__ICCARM__) - /* leave anonymous unions enabled */ +/* leave anonymous unions enabled */ #elif defined (__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TASKING__) - #pragma warning restore +#pragma warning restore #elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #else - #warning Not supported compiler type +#warning Not supported compiler type #endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h index e438d840f6..2e44ab2207 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h * Release: Version 1.1 @@ -46,40 +46,39 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct -{ - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct { + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -107,58 +106,57 @@ typedef struct /* SCC Register declaration */ /******************************************************************************/ -typedef struct // -{ - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct { // + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -166,60 +164,59 @@ typedef struct // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf -{ - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -314,13 +311,12 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct { + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -331,107 +327,106 @@ typedef struct /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct -{ - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct { + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -486,44 +481,43 @@ typedef struct /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct // SMSC LAN9220 -{ -__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; -__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct { // SMSC LAN9220 + __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; + __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; -__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) -__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) -__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) -__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) + __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) + __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) + __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) + __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) -__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) -__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) -__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) -__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) -__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) -__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) -__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) -__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) -__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) -__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) -__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) -__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) -__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) -__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) -__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) -__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) -__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) -__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) -__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) -__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) -__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) -__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) -__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) -__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) + __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) + __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) + __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) + __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) + __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) + __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) + __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) + __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) + __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) + __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) + __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) + __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) + __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) + __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) + __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) + __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) + __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) + __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) + __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) + __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) + __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) + __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) + __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) + __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -592,9 +586,9 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h index 4576f5e32e..14160841bc 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * A generic CMSIS include header, pulling in MPS2 specifics *******************************************************************************/ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h index 7dd4ba9509..a564abfc18 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/cmsis_nvic.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ #ifndef MBED_CMSIS_NVIC_H diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h index b6663cf719..29bad23617 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/peripherallink.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * Name: Device.h * Purpose: Include the correct device header file @@ -37,17 +37,17 @@ #define __DEVICE_H #if defined CMSDK_CM0 - #include "CMSDK_CM0.h" /* device specific header file */ +#include "CMSDK_CM0.h" /* device specific header file */ #elif defined CMSDK_CM0plus - #include "CMSDK_CM0plus.h" /* device specific header file */ +#include "CMSDK_CM0plus.h" /* device specific header file */ #elif defined CMSDK_CM3 - #include "CMSDK_CM3.h" /* device specific header file */ +#include "CMSDK_CM3.h" /* device specific header file */ #elif defined CMSDK_CM4 - #include "CMSDK_CM4.h" /* device specific header file */ +#include "CMSDK_CM4.h" /* device specific header file */ #elif defined CMSDK_CM7 - #include "CMSDK_CM7.h" /* device specific header file */ +#include "CMSDK_CM7.h" /* device specific header file */ #else - #warning "no appropriate header file found!" +#warning "no appropriate header file found!" #endif #endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c index 23deb6640f..6e543668d1 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.c @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file system_CMSDK_CM7.c * @brief CMSIS Device System Source File for @@ -37,13 +37,13 @@ #if defined (CMSDK_CM7) - #include "CMSDK_CM7.h" +#include "CMSDK_CM7.h" #elif defined (CMSDK_CM7_SP) - #include "CMSDK_CM7_SP.h" +#include "CMSDK_CM7_SP.h" #elif defined (CMSDK_CM7_DP) - #include "CMSDK_CM7_DP.h" +#include "CMSDK_CM7_DP.h" #else - #error device not specified! +#error device not specified! #endif /*---------------------------------------------------------------------------- @@ -72,10 +72,10 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */ * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { - SystemCoreClock = __SYSTEM_CLOCK; + SystemCoreClock = __SYSTEM_CLOCK; } @@ -88,17 +88,17 @@ void SystemCoreClockUpdate (void) * @brief Setup the microcontroller system. * Initialize the System. */ -void SystemInit (void) +void SystemInit(void) { - #if (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ - #endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */ + (3UL << 11 * 2)); /* set CP11 Full Access */ #endif - SystemCoreClock = __SYSTEM_CLOCK; +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h index 24b7112c55..afe92f2b90 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/system_CMSDK_CM7.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. * ******************************************************************************* * @file system_CMSDK_CM7.h @@ -56,7 +56,7 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ * @brief Setup the microcontroller system. * Initialize the System and update the SystemCoreClock variable. */ -extern void SystemInit (void); +extern void SystemInit(void); /** * Update SystemCoreClock variable @@ -67,7 +67,7 @@ extern void SystemInit (void); * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ -extern void SystemCoreClockUpdate (void); +extern void SystemCoreClockUpdate(void); #ifdef __cplusplus } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c index 9df01717c8..7b9ca99862 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/analogin_api.c @@ -38,73 +38,77 @@ static const PinMap PinMap_ADC[] = { }; static const PinMap PinMap_SPI_SCLK[] = { - {ADC_SCLK , SPI_3, 0}, - {NC , NC , 0} + {ADC_SCLK, SPI_3, 0}, + {NC, NC, 0} }; static const PinMap PinMap_SPI_MOSI[] = { {ADC_MOSI, SPI_3, 0}, - {NC , NC , 0} + {NC, NC, 0} }; static const PinMap PinMap_SPI_MISO[] = { {ADC_MISO, SPI_3, 0}, - {NC , NC , 0} + {NC, NC, 0} }; static const PinMap PinMap_SPI_SSEL[] = { {ADC_SSEL, SPI_3, 0}, - {NC , NC , 0} + {NC, NC, 0} }; #define ADC_RANGE ADC_12BIT_RANGE int analog_spi_inited = 0; -void analogin_init(analogin_t *obj, PinName pin) { - +void analogin_init(analogin_t *obj, PinName pin) +{ + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - obj->pin = pin; - obj->pin_number = pin-600; - obj->address = (0x0000 | (pin-600)); - + MBED_ASSERT(obj->adc != (ADCName)NC); + obj->pin = pin; + obj->pin_number = pin - 600; + obj->address = (0x0000 | (pin - 600)); + SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI); - SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO); - SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK); - SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL); - SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso); - SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel); - obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl); - - if(analog_spi_inited == 0){ - obj->adc_spi->CR1 = 0; - obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16; - obj->adc_spi->CPSR = SSP_CPSR_DFLT; - obj->adc_spi->IMSC = 0x8; - obj->adc_spi->DMACR = 0; - obj->adc_spi->CR1 = SSP_CR1_SSE_Msk; - obj->adc_spi->ICR = 0x3; - analog_spi_inited = 1; + SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO); + SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK); + SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL); + SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso); + SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel); + obj->adc_spi = (MPS2_SSP_TypeDef *)pinmap_merge(adc_data, adc_cntl); + + if (analog_spi_inited == 0) { + obj->adc_spi->CR1 = 0; + obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16; + obj->adc_spi->CPSR = SSP_CPSR_DFLT; + obj->adc_spi->IMSC = 0x8; + obj->adc_spi->DMACR = 0; + obj->adc_spi->CR1 = SSP_CR1_SSE_Msk; + obj->adc_spi->ICR = 0x3; + analog_spi_inited = 1; } - - pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI); - pinmap_pinout(ADC_MISO, PinMap_SPI_MISO); - pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK); - pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL); - pinmap_pinout(pin, PinMap_ADC); + + pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI); + pinmap_pinout(ADC_MISO, PinMap_SPI_MISO); + pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK); + pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL); + pinmap_pinout(pin, PinMap_ADC); } -static inline uint32_t adc_read(analogin_t *obj) { +static inline uint32_t adc_read(analogin_t *obj) +{ return 0; } -float analogin_read(analogin_t *obj) { +float analogin_read(analogin_t *obj) +{ uint32_t value = adc_read(obj); return 0; } -uint16_t analogin_read_u16(analogin_t *obj) { +uint16_t analogin_read_u16(analogin_t *obj) +{ return 0; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h index b38cfffcf7..f7db3c293d 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h @@ -13,11 +13,11 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + // The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. // Check the 'features' section of the target description in 'targets.json' for more details. - - #ifndef MBED_DEVICE_H + +#ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c index 401c3bcdad..ee69baa865 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c @@ -38,14 +38,14 @@ *----------------------------------------------------------------------------*/ int ethernet_init() { - int error; + int error; error = 0; - if(smsc9220_check_id()) { + if (smsc9220_check_id()) { error = TRUE; } - if(smsc9220_soft_reset()) { + if (smsc9220_soft_reset()) { error = TRUE; } @@ -55,7 +55,7 @@ int ethernet_init() // threshold to defaults specified. SMSC9220->AFC_CFG = 0x006E3740; - if(smsc9220_wait_eeprom()) { + if (smsc9220_wait_eeprom()) { error = TRUE; } @@ -66,11 +66,11 @@ int ethernet_init() /* Configure MAC addresses here if needed. */ - if(smsc9220_check_phy()) { + if (smsc9220_check_phy()) { error = TRUE; } - if(smsc9220_reset_phy()) { + if (smsc9220_reset_phy()) { error = TRUE; return error; } @@ -81,7 +81,7 @@ int ethernet_init() unsigned short phyreset; phyreset = 0; smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); - if(phyreset & (1 << 15)) { + if (phyreset & (1 << 15)) { error = TRUE; return error; } @@ -93,7 +93,7 @@ int ethernet_init() /* Begin to establish link */ smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing. - // Although it's not so in the manual. + // Although it's not so in the manual. /* Interrupt threshold */ SMSC9220->FIFO_INT = 0xFF000000; @@ -118,20 +118,21 @@ int ethernet_init() /*---------------------------------------------------------------------------- Ethernet Device Uninitialize *----------------------------------------------------------------------------*/ -void ethernet_free() { +void ethernet_free() +{ } int ethernet_write(const char *data, int size) { - return 0; + return 0; } -int ethernet_send() +int ethernet_send() { - return 0; + return 0; } -int ethernet_receive() +int ethernet_receive() { return 0; } @@ -143,16 +144,17 @@ int ethernet_receive() // It is possible to use read multible times. // Each time read will start reading after the last read byte before. -int ethernet_read(char *data, int dlen) +int ethernet_read(char *data, int dlen) { return 0; } -void ethernet_address(char *mac) { +void ethernet_address(char *mac) +{ mbed_mac_address(mac); } -int ethernet_link(void) +int ethernet_link(void) { return 0; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c index 96e905d560..2da2b84e53 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_api.c @@ -17,121 +17,132 @@ #include "pinmap.h" // function to enable the GPIO pin -uint32_t gpio_set(PinName pin) { +uint32_t gpio_set(PinName pin) +{ return (1); } //function to initialise the gpio pin -// this links the board control bits for each pin +// this links the board control bits for each pin // with the object created for the pin -void gpio_init(gpio_t *obj, PinName pin) { - if(pin == NC){ return;} - else { +void gpio_init(gpio_t *obj, PinName pin) +{ + if (pin == NC) { + return; + } else { int pin_value = 0; obj->pin = pin; - if(pin <=15){ + if (pin <= 15) { pin_value = pin; - }else if (pin >= 16 && pin <= 31){ - pin_value = pin-16; - }else if (pin >= 32 && pin <= 47){ - pin_value = pin-32; - }else if (pin >= 48 && pin <= 51){ - pin_value = pin-48; - }else if (pin == 100 || pin == 101){ - pin_value = pin-100; - }else if (pin == 110 || pin == 111){ - pin_value = pin-110; - }else if (pin >= 200 && pin <= 207){ - pin_value = pin-200; - }else if (pin >= 210 && pin <= 217){ - pin_value = pin-210; - }else if (pin == 303){ - pin_value = pin-302; - }else if (pin == 307){ - pin_value = pin-307; - }else if (pin == 308){ - pin_value = pin-305; - }else if (pin == 309){ - pin_value = pin-305; - }else if (pin == 310){ - pin_value = pin-305; - }else if (pin == 311){ - pin_value = pin-305; - }else if (pin == 323){ - pin_value = pin-315; - }else if (pin == 334){ - pin_value = pin-325; - }else if (pin == 653){ - pin_value = pin-646; + } else if (pin >= 16 && pin <= 31) { + pin_value = pin - 16; + } else if (pin >= 32 && pin <= 47) { + pin_value = pin - 32; + } else if (pin >= 48 && pin <= 51) { + pin_value = pin - 48; + } else if (pin == 100 || pin == 101) { + pin_value = pin - 100; + } else if (pin == 110 || pin == 111) { + pin_value = pin - 110; + } else if (pin >= 200 && pin <= 207) { + pin_value = pin - 200; + } else if (pin >= 210 && pin <= 217) { + pin_value = pin - 210; + } else if (pin == 303) { + pin_value = pin - 302; + } else if (pin == 307) { + pin_value = pin - 307; + } else if (pin == 308) { + pin_value = pin - 305; + } else if (pin == 309) { + pin_value = pin - 305; + } else if (pin == 310) { + pin_value = pin - 305; + } else if (pin == 311) { + pin_value = pin - 305; + } else if (pin == 323) { + pin_value = pin - 315; + } else if (pin == 334) { + pin_value = pin - 325; + } else if (pin == 653) { + pin_value = pin - 646; } - + obj->mask = 0x1 << pin_value; obj->pin_number = pin; - if(pin <=15) { + if (pin <= 15) { obj->reg_data = &CMSDK_GPIO0->DATAOUT ; obj->reg_in = &CMSDK_GPIO0->DATA ; obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ; obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ; - } else if (pin >= 16 && pin <= 31){ + } else if (pin >= 16 && pin <= 31) { obj->reg_data = &CMSDK_GPIO1->DATAOUT ; obj->reg_in = &CMSDK_GPIO1->DATA ; obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ; obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ; - } else if (pin >= 32 && pin <= 47){ + } else if (pin >= 32 && pin <= 47) { obj->reg_data = &CMSDK_GPIO2->DATAOUT; obj->reg_in = &CMSDK_GPIO2->DATA; obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ; obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ; - } else if (pin >= 48 && pin <= 51){ + } else if (pin >= 48 && pin <= 51) { obj->reg_data = &CMSDK_GPIO3->DATAOUT; obj->reg_in = &CMSDK_GPIO3->DATA; obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ; obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ; - } else if (pin == 100 || pin == 101){ + } else if (pin == 100 || pin == 101) { obj->reg_data = &MPS2_FPGAIO->LED; //user leds obj->reg_in = &MPS2_FPGAIO->LED; - } else if (pin == 110 || pin == 111){ + } else if (pin == 110 || pin == 111) { obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches - }else if (pin >= 200 && pin <= 207){ + } else if (pin >= 200 && pin <= 207) { obj->reg_data = &MPS2_SCC->LEDS; //mcc leds obj->reg_in = &MPS2_SCC->LEDS; //mcc leds - }else if (pin >= 210 && pin <= 217){ + } else if (pin >= 210 && pin <= 217) { obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches - }else if (pin == 303 || pin == 307){ + } else if (pin == 303 || pin == 307) { obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307 - }else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){ + } else if (pin == 308 || pin == 309 || pin == 310 || pin == 311) { obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits - }else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653 + } else if (pin == 323 || pin == 334 || pin == 653) { //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653 obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits } - - if (pin == 323){ + + if (pin == 323) { CMSDK_GPIO0->ALTFUNCSET |= 0x1000; - }else if (pin == 334){ + } else if (pin == 334) { CMSDK_GPIO2->ALTFUNCSET |= 0x0040; - }else if (pin == 653){ + } else if (pin == 653) { CMSDK_GPIO1->ALTFUNCSET |= 0x0001; } } } -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->pin, mode); } -void gpio_dir(gpio_t *obj, PinDirection direction) { - if(obj->pin >= 0 && obj->pin <= 51) - { +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + if (obj->pin >= 0 && obj->pin <= 51) { switch (direction) { - case PIN_INPUT : *obj->reg_dirclr = obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + case PIN_INPUT : + *obj->reg_dirclr = obj->mask; + break; + case PIN_OUTPUT: + *obj->reg_dir |= obj->mask; + break; } - } else {return;} + } else { + return; + } } -int gpio_is_connected(const gpio_t *obj){ - if(obj->pin != (PinName)NC){ +int gpio_is_connected(const gpio_t *obj) +{ + if (obj->pin != (PinName)NC) { return 1; } else { return 0; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c index 0f6ebb6852..fbc0fc2f25 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c @@ -26,216 +26,381 @@ static uint32_t channel_ids[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; -static inline void handle_interrupt_in(uint32_t channel) { - uint32_t ch_bit = (1 << channel); - // Return immediately if: - // * The interrupt was already served - // * There is no user handler - // * It is a level interrupt, not an edge interrupt - if (ch_bit <16){ - if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; +static inline void handle_interrupt_in(uint32_t channel) +{ + uint32_t ch_bit = (1 << channel); + // Return immediately if: + // * The interrupt was already served + // * There is no user handler + // * It is a level interrupt, not an edge interrupt + if (ch_bit < 16) { + if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0)) { + return; + } if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); - CMSDK_GPIO_0->INTPOLSET = ch_bit; + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_0->INTPOLSET = ch_bit; } if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_ids[channel], IRQ_FALL); } CMSDK_GPIO_0->INTCLEAR = ch_bit; } - - if (ch_bit>=16) { - if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; + + if (ch_bit >= 16) { + if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0)) { + return; + } if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); - CMSDK_GPIO_1->INTPOLSET = ch_bit; + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_1->INTPOLSET = ch_bit; } if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_ids[channel], IRQ_FALL); } CMSDK_GPIO_1->INTCLEAR = ch_bit; } } -void gpio0_irq0(void) {handle_interrupt_in(0);} -void gpio0_irq1(void) {handle_interrupt_in(1);} -void gpio0_irq2(void) {handle_interrupt_in(2);} -void gpio0_irq3(void) {handle_interrupt_in(3);} -void gpio0_irq4(void) {handle_interrupt_in(4);} -void gpio0_irq5(void) {handle_interrupt_in(5);} -void gpio0_irq6(void) {handle_interrupt_in(6);} -void gpio0_irq7(void) {handle_interrupt_in(7);} -void gpio0_irq8(void) {handle_interrupt_in(8);} -void gpio0_irq9(void) {handle_interrupt_in(9);} -void gpio0_irq10(void) {handle_interrupt_in(10);} -void gpio0_irq11(void) {handle_interrupt_in(11);} -void gpio0_irq12(void) {handle_interrupt_in(12);} -void gpio0_irq13(void) {handle_interrupt_in(13);} -void gpio0_irq14(void) {handle_interrupt_in(14);} -void gpio0_irq15(void) {handle_interrupt_in(15);} -void gpio1_irq0(void) {handle_interrupt_in(16);} -void gpio1_irq1(void) {handle_interrupt_in(17);} -void gpio1_irq2(void) {handle_interrupt_in(18);} -void gpio1_irq3(void) {handle_interrupt_in(19);} -void gpio1_irq4(void) {handle_interrupt_in(20);} -void gpio1_irq5(void) {handle_interrupt_in(21);} -void gpio1_irq6(void) {handle_interrupt_in(22);} -void gpio1_irq7(void) {handle_interrupt_in(23);} -void gpio1_irq8(void) {handle_interrupt_in(24);} -void gpio1_irq9(void) {handle_interrupt_in(25);} -void gpio1_irq10(void) {handle_interrupt_in(26);} -void gpio1_irq11(void) {handle_interrupt_in(27);} -void gpio1_irq12(void) {handle_interrupt_in(28);} -void gpio1_irq13(void) {handle_interrupt_in(29);} -void gpio1_irq14(void) {handle_interrupt_in(30);} -void gpio1_irq15(void) {handle_interrupt_in(31);} +void gpio0_irq0(void) +{ + handle_interrupt_in(0); +} +void gpio0_irq1(void) +{ + handle_interrupt_in(1); +} +void gpio0_irq2(void) +{ + handle_interrupt_in(2); +} +void gpio0_irq3(void) +{ + handle_interrupt_in(3); +} +void gpio0_irq4(void) +{ + handle_interrupt_in(4); +} +void gpio0_irq5(void) +{ + handle_interrupt_in(5); +} +void gpio0_irq6(void) +{ + handle_interrupt_in(6); +} +void gpio0_irq7(void) +{ + handle_interrupt_in(7); +} +void gpio0_irq8(void) +{ + handle_interrupt_in(8); +} +void gpio0_irq9(void) +{ + handle_interrupt_in(9); +} +void gpio0_irq10(void) +{ + handle_interrupt_in(10); +} +void gpio0_irq11(void) +{ + handle_interrupt_in(11); +} +void gpio0_irq12(void) +{ + handle_interrupt_in(12); +} +void gpio0_irq13(void) +{ + handle_interrupt_in(13); +} +void gpio0_irq14(void) +{ + handle_interrupt_in(14); +} +void gpio0_irq15(void) +{ + handle_interrupt_in(15); +} +void gpio1_irq0(void) +{ + handle_interrupt_in(16); +} +void gpio1_irq1(void) +{ + handle_interrupt_in(17); +} +void gpio1_irq2(void) +{ + handle_interrupt_in(18); +} +void gpio1_irq3(void) +{ + handle_interrupt_in(19); +} +void gpio1_irq4(void) +{ + handle_interrupt_in(20); +} +void gpio1_irq5(void) +{ + handle_interrupt_in(21); +} +void gpio1_irq6(void) +{ + handle_interrupt_in(22); +} +void gpio1_irq7(void) +{ + handle_interrupt_in(23); +} +void gpio1_irq8(void) +{ + handle_interrupt_in(24); +} +void gpio1_irq9(void) +{ + handle_interrupt_in(25); +} +void gpio1_irq10(void) +{ + handle_interrupt_in(26); +} +void gpio1_irq11(void) +{ + handle_interrupt_in(27); +} +void gpio1_irq12(void) +{ + handle_interrupt_in(28); +} +void gpio1_irq13(void) +{ + handle_interrupt_in(29); +} +void gpio1_irq14(void) +{ + handle_interrupt_in(30); +} +void gpio1_irq15(void) +{ + handle_interrupt_in(31); +} -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) {return -1;} - else { - +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + if (pin == NC) { + return -1; + } else { + irq_handler = handler; - + int found_free_channel = 0; int i = 0; - for (i=0; ich = i; - found_free_channel = 1; - break; - } + for (i = 0; i < CHANNEL_NUM; i++) { + if (channel_ids[i] == 0) { + channel_ids[i] = id; + obj->ch = i; + found_free_channel = 1; + break; + } } - if (!found_free_channel) return -1; - - + if (!found_free_channel) { + return -1; + } + + /* To select a pin for any of the eight pin interrupts, write the pin number * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. * @see: mbed_capi/PinNames.h */ - if (pin <16) - { - CMSDK_GPIO_0->INTENSET |= (0x1 << pin); + if (pin < 16) { + CMSDK_GPIO_0->INTENSET |= (0x1 << pin); } - - if (pin >= 16) - { - CMSDK_GPIO_1->INTENSET |= (0x1 << pin); + + if (pin >= 16) { + CMSDK_GPIO_1->INTENSET |= (0x1 << pin); } void (*channels_irq)(void) = NULL; switch (obj->ch) { - case 0: channels_irq = &gpio0_irq0; break; - case 1: channels_irq = &gpio0_irq1; break; - case 2: channels_irq = &gpio0_irq2; break; - case 3: channels_irq = &gpio0_irq3; break; - case 4: channels_irq = &gpio0_irq4; break; - case 5: channels_irq = &gpio0_irq5; break; - case 6: channels_irq = &gpio0_irq6; break; - case 7: channels_irq = &gpio0_irq7; break; - case 8: channels_irq = &gpio0_irq8; break; - case 9: channels_irq = &gpio0_irq9; break; - case 10: channels_irq = &gpio0_irq10; break; - case 11: channels_irq = &gpio0_irq11; break; - case 12: channels_irq = &gpio0_irq12; break; - case 13: channels_irq = &gpio0_irq13; break; - case 14: channels_irq = &gpio0_irq14; break; - case 15: channels_irq = &gpio0_irq15; break; - case 16: channels_irq = &gpio1_irq0; break; - case 17: channels_irq = &gpio1_irq1; break; - case 18: channels_irq = &gpio1_irq2; break; - case 19: channels_irq = &gpio1_irq3; break; - case 20: channels_irq = &gpio1_irq4; break; - case 21: channels_irq = &gpio1_irq5; break; - case 22: channels_irq = &gpio1_irq6; break; - case 23: channels_irq = &gpio1_irq7; break; - case 24: channels_irq = &gpio1_irq8; break; - case 25: channels_irq = &gpio1_irq9; break; - case 26: channels_irq = &gpio1_irq10; break; - case 27: channels_irq = &gpio1_irq11; break; - case 28: channels_irq = &gpio1_irq12; break; - case 29: channels_irq = &gpio1_irq13; break; - case 30: channels_irq = &gpio1_irq14; break; - case 31: channels_irq = &gpio1_irq15; break; - + case 0: + channels_irq = &gpio0_irq0; + break; + case 1: + channels_irq = &gpio0_irq1; + break; + case 2: + channels_irq = &gpio0_irq2; + break; + case 3: + channels_irq = &gpio0_irq3; + break; + case 4: + channels_irq = &gpio0_irq4; + break; + case 5: + channels_irq = &gpio0_irq5; + break; + case 6: + channels_irq = &gpio0_irq6; + break; + case 7: + channels_irq = &gpio0_irq7; + break; + case 8: + channels_irq = &gpio0_irq8; + break; + case 9: + channels_irq = &gpio0_irq9; + break; + case 10: + channels_irq = &gpio0_irq10; + break; + case 11: + channels_irq = &gpio0_irq11; + break; + case 12: + channels_irq = &gpio0_irq12; + break; + case 13: + channels_irq = &gpio0_irq13; + break; + case 14: + channels_irq = &gpio0_irq14; + break; + case 15: + channels_irq = &gpio0_irq15; + break; + case 16: + channels_irq = &gpio1_irq0; + break; + case 17: + channels_irq = &gpio1_irq1; + break; + case 18: + channels_irq = &gpio1_irq2; + break; + case 19: + channels_irq = &gpio1_irq3; + break; + case 20: + channels_irq = &gpio1_irq4; + break; + case 21: + channels_irq = &gpio1_irq5; + break; + case 22: + channels_irq = &gpio1_irq6; + break; + case 23: + channels_irq = &gpio1_irq7; + break; + case 24: + channels_irq = &gpio1_irq8; + break; + case 25: + channels_irq = &gpio1_irq9; + break; + case 26: + channels_irq = &gpio1_irq10; + break; + case 27: + channels_irq = &gpio1_irq11; + break; + case 28: + channels_irq = &gpio1_irq12; + break; + case 29: + channels_irq = &gpio1_irq13; + break; + case 30: + channels_irq = &gpio1_irq14; + break; + case 31: + channels_irq = &gpio1_irq15; + break; + } NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); - + return 0; } } -void gpio_irq_free(gpio_irq_t *obj) { +void gpio_irq_free(gpio_irq_t *obj) +{ } -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - unsigned int ch_bit = (1 << obj->ch); - - // Clear interrupt - if (obj->ch <16) - { - if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) - { - CMSDK_GPIO_0->INTCLEAR = ch_bit; - } +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + unsigned int ch_bit = (1 << obj->ch); + + // Clear interrupt + if (obj->ch < 16) { + if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) { + CMSDK_GPIO_0->INTCLEAR = ch_bit; } - if (obj->ch >= 16) - { - if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) - { - CMSDK_GPIO_1->INTCLEAR = ch_bit; - } + } + if (obj->ch >= 16) { + if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) { + CMSDK_GPIO_1->INTCLEAR = ch_bit; } - - // Edge trigger - if (obj->ch <16) - { - CMSDK_GPIO_0->INTTYPESET &= ch_bit; - if (event == IRQ_RISE) { - CMSDK_GPIO_0->INTPOLSET |= ch_bit; - if (enable) { - CMSDK_GPIO_0->INTENSET |= ch_bit; - } else { - CMSDK_GPIO_0->INTENCLR |= ch_bit; - } - } else { - CMSDK_GPIO_0->INTPOLCLR |= ch_bit; - if (enable) { - CMSDK_GPIO_0->INTENSET |= ch_bit; - } else { - CMSDK_GPIO_0->INTENCLR |= ch_bit; - } - } + } + + // Edge trigger + if (obj->ch < 16) { + CMSDK_GPIO_0->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_0->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_0->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } } - if (obj->ch >= 16) - { - CMSDK_GPIO_1->INTTYPESET &= ch_bit; - if (event == IRQ_RISE) { - CMSDK_GPIO_1->INTPOLSET |= ch_bit; - if (enable) { - CMSDK_GPIO_1->INTENSET |= ch_bit; - } else { - CMSDK_GPIO_1->INTENCLR |= ch_bit; - } - } else { - CMSDK_GPIO_1->INTPOLCLR |= ch_bit; - if (enable) { - CMSDK_GPIO_1->INTENSET |= ch_bit; - } else { - CMSDK_GPIO_1->INTENCLR |= ch_bit; - } - } + } + if (obj->ch >= 16) { + CMSDK_GPIO_1->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_1->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_1->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } } + } } -void gpio_irq_enable(gpio_irq_t *obj) { - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +void gpio_irq_enable(gpio_irq_t *obj) +{ + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); } -void gpio_irq_disable(gpio_irq_t *obj) { - NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +void gpio_irq_disable(gpio_irq_t *obj) +{ + NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h index f6ba621d30..84db0c0022 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_object.h @@ -24,27 +24,29 @@ #ifdef __cplusplus extern "C" { #endif - + typedef struct { PinName pin; uint32_t mask; - uint32_t pin_number; - + uint32_t pin_number; + __IO uint32_t *reg_dir; - __IO uint32_t *reg_dirclr; + __IO uint32_t *reg_dirclr; __IO uint32_t *reg_data; __I uint32_t *reg_in; } gpio_t; -static inline void gpio_write(gpio_t *obj, int value) { - if (value){ - *obj->reg_data |= (obj->mask); - } else { - *obj->reg_data &= ~(obj->mask); - } +static inline void gpio_write(gpio_t *obj, int value) +{ + if (value) { + *obj->reg_data |= (obj->mask); + } else { + *obj->reg_data &= ~(obj->mask); + } } -static inline int gpio_read(gpio_t *obj) { +static inline int gpio_read(gpio_t *obj) +{ return ((*obj->reg_in & obj->mask) ? 1 : 0); } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c index b620c21d6d..4bd62b3585 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/i2c_api.c @@ -56,7 +56,7 @@ static const PinMap PinMap_I2C_SDA[] = { {AUD_SDA, I2C_1, 0}, {SHIELD_0_SDA, I2C_2, 0}, {SHIELD_1_SDA, I2C_3, 0}, - {NC , NC , 0} + {NC, NC, 0} }; static const PinMap PinMap_I2C_SCL[] = { @@ -64,24 +64,24 @@ static const PinMap PinMap_I2C_SCL[] = { {AUD_SCL, I2C_1, 0}, {SHIELD_0_SCL, I2C_2, 0}, {SHIELD_1_SCL, I2C_3, 0}, - {NC , NC, 0} + {NC, NC, 0} }; static inline void i2c_send_byte(i2c_t *obj, unsigned char c) { int loop; switch ((int)obj->i2c) { - case I2C_0: + case I2C_0: obj->i2c->CONTROLC = SCL; i2c_delay(TSC_TSU); - for (loop = 0; loop < 8; loop++) - { - if (c & (1 << (7 - loop))) + for (loop = 0; loop < 8; loop++) { + if (c & (1 << (7 - loop))) { obj->i2c->CONTROLS = SDA; - else + } else { obj->i2c->CONTROLC = SDA; - + } + i2c_delay(TSC_TSU); obj->i2c->CONTROLS = SCL; i2c_delay(TSC_TSU); @@ -91,17 +91,18 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c) obj->i2c->CONTROLS = SDA; i2c_delay(TSC_TSU); - break; + break; case I2C_1: for (loop = 0; loop < 8; loop++) { i2c_delay(AAIC_TSU); obj->i2c->CONTROLC = SCL; i2c_delay(AAIC_TSU); - if (c & (1 << (7 - loop))) + if (c & (1 << (7 - loop))) { obj->i2c->CONTROLS = SDA; - else + } else { obj->i2c->CONTROLC = SDA; - + } + i2c_delay(AAIC_TSU); obj->i2c->CONTROLS = SCL; i2c_delay(AAIC_TSU); @@ -111,19 +112,19 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c) i2c_delay(AAIC_TSU); obj->i2c->CONTROLS = SDA; i2c_delay(AAIC_TSU); - break; - case I2C_2: - case I2C_3: + break; + case I2C_2: + case I2C_3: obj->i2c->CONTROLC = SCL; i2c_delay(SHIELD_TSU); - for (loop = 0; loop < 8; loop++) - { - if (c & (1 << (7 - loop))) + for (loop = 0; loop < 8; loop++) { + if (c & (1 << (7 - loop))) { obj->i2c->CONTROLS = SDA; - else + } else { obj->i2c->CONTROLC = SDA; - + } + i2c_delay(SHIELD_TSU); obj->i2c->CONTROLS = SCL; i2c_delay(SHIELD_TSU); @@ -133,7 +134,7 @@ static inline void i2c_send_byte(i2c_t *obj, unsigned char c) obj->i2c->CONTROLS = SDA; i2c_delay(SHIELD_TSU); - break; + break; } } @@ -141,26 +142,26 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj) { int data_receive_byte, loop; switch ((int)obj->i2c) { - case I2C_0: + case I2C_0: obj->i2c->CONTROLS = SDA; i2c_delay(TSC_TSU); data_receive_byte = 0; - for (loop = 0; loop < 8; loop++) - { + for (loop = 0; loop < 8; loop++) { obj->i2c->CONTROLS = SCL; i2c_delay(TSC_TSU); - if ((obj->i2c->CONTROL & SDA)) + if ((obj->i2c->CONTROL & SDA)) { data_receive_byte += (1 << (7 - loop)); - + } + obj->i2c->CONTROLC = SCL; i2c_delay(TSC_TSU); } obj->i2c->CONTROLC = SDA; i2c_delay(TSC_TSU); - break; + break; case I2C_1: obj->i2c->CONTROLS = SDA; data_receive_byte = 0; @@ -171,9 +172,10 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj) i2c_delay(AAIC_TSU); obj->i2c->CONTROLS = SCL | SDA; i2c_delay(AAIC_TSU); - if ((obj->i2c->CONTROL & SDA)) + if ((obj->i2c->CONTROL & SDA)) { data_receive_byte += (1 << (7 - loop)); - + } + i2c_delay(AAIC_TSU); obj->i2c->CONTROLC = SCL; } @@ -181,28 +183,28 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj) i2c_delay(AAIC_TSU); obj->i2c->CONTROLC = SDA; i2c_delay(AAIC_TSU); - break; - case I2C_2: + break; + case I2C_2: case I2C_3: obj->i2c->CONTROLS = SDA; i2c_delay(SHIELD_TSU); data_receive_byte = 0; - for (loop = 0; loop < 8; loop++) - { + for (loop = 0; loop < 8; loop++) { obj->i2c->CONTROLS = SCL; i2c_delay(SHIELD_TSU); - if ((obj->i2c->CONTROL & SDA)) + if ((obj->i2c->CONTROL & SDA)) { data_receive_byte += (1 << (7 - loop)); - + } + obj->i2c->CONTROLC = SCL; i2c_delay(SHIELD_TSU); } obj->i2c->CONTROLC = SDA; i2c_delay(SHIELD_TSU); - break; + break; } return data_receive_byte; } @@ -212,10 +214,18 @@ static inline int i2c_receive_ack(i2c_t *obj) int nack; int delay_value; switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - case I2C_2: delay_value = SHIELD_TSU; break; - case I2C_3: delay_value = SHIELD_TSU; break; + case I2C_0: + delay_value = TSC_TSU; + break; + case I2C_1: + delay_value = AAIC_TSU; + break; + case I2C_2: + delay_value = SHIELD_TSU; + break; + case I2C_3: + delay_value = SHIELD_TSU; + break; } i2c_delay(delay_value); @@ -231,21 +241,30 @@ static inline int i2c_receive_ack(i2c_t *obj) i2c_delay(delay_value); obj->i2c->CONTROLS = SDA; i2c_delay(delay_value); - if(nack==0) + if (nack == 0) { return 1; + } return 0; } -static inline void i2c_send_nack(i2c_t *obj) +static inline void i2c_send_nack(i2c_t *obj) { int delay_value; switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - case I2C_2: delay_value = SHIELD_TSU; break; - case I2C_3: delay_value = SHIELD_TSU; break; + case I2C_0: + delay_value = TSC_TSU; + break; + case I2C_1: + delay_value = AAIC_TSU; + break; + case I2C_2: + delay_value = SHIELD_TSU; + break; + case I2C_3: + delay_value = SHIELD_TSU; + break; } i2c_delay(delay_value); @@ -262,14 +281,22 @@ static inline void i2c_send_nack(i2c_t *obj) } -static inline void i2c_send_ack(i2c_t *obj) +static inline void i2c_send_ack(i2c_t *obj) { int delay_value; switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - case I2C_2: delay_value = SHIELD_TSU; break; - case I2C_3: delay_value = SHIELD_TSU; break; + case I2C_0: + delay_value = TSC_TSU; + break; + case I2C_1: + delay_value = AAIC_TSU; + break; + case I2C_2: + delay_value = SHIELD_TSU; + break; + case I2C_3: + delay_value = SHIELD_TSU; + break; } i2c_delay(delay_value); @@ -288,33 +315,45 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); obj->i2c = (MPS2_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); - + if ((int)obj->i2c == NC) { error("I2C pin mapping failed"); } - + pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); - + switch ((int)obj->i2c) { - case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break; - case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000; - CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break; + case I2C_2: + CMSDK_GPIO0->ALTFUNCSET |= 0x8020; + break; + case I2C_3: + CMSDK_GPIO1->ALTFUNCSET |= 0x8000; + CMSDK_GPIO2->ALTFUNCSET |= 0x0200; + break; } - - + + } int i2c_start(i2c_t *obj) { int delay_value; switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - case I2C_2: delay_value = SHIELD_TSU; break; - case I2C_3: delay_value = SHIELD_TSU; break; + case I2C_0: + delay_value = TSC_TSU; + break; + case I2C_1: + delay_value = AAIC_TSU; + break; + case I2C_2: + delay_value = SHIELD_TSU; + break; + case I2C_3: + delay_value = SHIELD_TSU; + break; } - + i2c_delay(delay_value); obj->i2c->CONTROLS = SDA | SCL; i2c_delay(delay_value); @@ -328,12 +367,20 @@ int i2c_start_tsc(i2c_t *obj) { int delay_value; switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - case I2C_2: delay_value = SHIELD_TSU; break; - case I2C_3: delay_value = SHIELD_TSU; break; + case I2C_0: + delay_value = TSC_TSU; + break; + case I2C_1: + delay_value = AAIC_TSU; + break; + case I2C_2: + delay_value = SHIELD_TSU; + break; + case I2C_3: + delay_value = SHIELD_TSU; + break; } - + i2c_delay(delay_value); obj->i2c->CONTROLC = SDA; i2c_delay(delay_value); @@ -344,13 +391,21 @@ int i2c_start_tsc(i2c_t *obj) } int i2c_stop(i2c_t *obj) -{ +{ int delay_value; switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - case I2C_2: delay_value = SHIELD_TSU; break; - case I2C_3: delay_value = SHIELD_TSU; break; + case I2C_0: + delay_value = TSC_TSU; + break; + case I2C_1: + delay_value = AAIC_TSU; + break; + case I2C_2: + delay_value = SHIELD_TSU; + break; + case I2C_3: + delay_value = SHIELD_TSU; + break; } // Actual stop bit i2c_delay(delay_value); @@ -366,34 +421,35 @@ int i2c_stop(i2c_t *obj) -void i2c_frequency(i2c_t *obj, int hz) { +void i2c_frequency(i2c_t *obj, int hz) +{ } int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { unsigned int loop, rxdata; int sadr, ack, bytes_read; - rxdata=0; + rxdata = 0; switch ((int)obj->i2c) { - case I2C_0: - sadr = TSC_I2C_ADDR; + case I2C_0: + sadr = TSC_I2C_ADDR; break; - case I2C_1: - sadr = AAIC_I2C_ADDR; + case I2C_1: + sadr = AAIC_I2C_ADDR; break; - case I2C_2: - case I2C_3: + case I2C_2: + case I2C_3: sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR; break; - } + } bytes_read = 0; // Start bit i2c_start(obj); switch ((int)obj->i2c) { - case I2C_0: + case I2C_0: // Set serial and register address - i2c_send_byte(obj,sadr); + i2c_send_byte(obj, sadr); ack += i2c_receive_ack(obj); i2c_send_byte(obj, address); ack += i2c_receive_ack(obj); @@ -405,17 +461,15 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) i2c_start_tsc(obj); // Read from I2C address - i2c_send_byte(obj,sadr | 1); + i2c_send_byte(obj, sadr | 1); ack += i2c_receive_ack(obj); rxdata = (i2c_receive_byte(obj) & 0xFF); - data[((length-1)-bytes_read)] = (char)rxdata; + data[((length - 1) - bytes_read)] = (char)rxdata; bytes_read++; // Read multiple bytes - if ((length > 1) && (length < 5)) - { - for (loop = 1; loop <= (length - 1); loop++) - { + if ((length > 1) && (length < 5)) { + for (loop = 1; loop <= (length - 1); loop++) { // Send ACK i2c_send_ack(obj); @@ -423,15 +477,15 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) //rxdata = ((rxdata << 8) & 0xFFFFFF00); //rxdata |= (i2c_receive_byte(obj) & 0xFF); rxdata = i2c_receive_byte(obj); - data[(length-1)-bytes_read] = (char)rxdata; + data[(length - 1) - bytes_read] = (char)rxdata; bytes_read++; - + } } break; case I2C_1: // Set serial and register address - i2c_send_byte(obj,sadr); + i2c_send_byte(obj, sadr); ack += i2c_receive_ack(obj); i2c_send_byte(obj, address); ack += i2c_receive_ack(obj); @@ -441,21 +495,19 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) // Start bit i2c_start_tsc(obj); - // Fall through to read data + // Fall through to read data case I2C_2: case I2C_3: // Read from preset register address pointer - i2c_send_byte(obj,sadr | 1); + i2c_send_byte(obj, sadr | 1); ack += i2c_receive_ack(obj); rxdata = i2c_receive_byte(obj); data[bytes_read] = (char)rxdata; bytes_read++; // Read multiple bytes - if ((length > 1) && (length < 5)) - { - for (loop = 1; loop <= (length - 1); loop++) - { + if ((length > 1) && (length < 5)) { + for (loop = 1; loop <= (length - 1); loop++) { // Send ACK i2c_send_ack(obj); @@ -463,12 +515,12 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) rxdata = i2c_receive_byte(obj); data[loop] = (char)rxdata; bytes_read++; - + } } break; } - i2c_send_nack(obj); + i2c_send_nack(obj); i2c_stop(obj); // Actual stop bit @@ -477,57 +529,61 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int ack=0; + int ack = 0; int sadr; - char * ptr; + char *ptr; char addr; - ptr = (char*)data; - switch ((int)obj->i2c) - { - case I2C_0: + ptr = (char *)data; + switch ((int)obj->i2c) { + case I2C_0: sadr = TSC_I2C_ADDR; addr = address; break; - case I2C_1: - sadr = AAIC_I2C_ADDR; + case I2C_1: + sadr = AAIC_I2C_ADDR; addr = address; break; - case I2C_2: - case I2C_3: + case I2C_2: + case I2C_3: sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR; addr = *ptr++; break; - } - + } + // printf("adr = %x, reg = %x\n",sadr, address); i2c_start(obj); // Set serial and register address - i2c_send_byte(obj,sadr); + i2c_send_byte(obj, sadr); ack += i2c_receive_ack(obj); i2c_send_byte(obj, addr); ack += i2c_receive_ack(obj); - for(int i = 1; iport = port; obj->mask = mask; - - CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10)); + + CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10)); obj->reg_in = &port_reg->DATAOUT; obj->reg_dir = &port_reg->OUTENABLESET; obj->reg_dirclr = &port_reg->OUTENABLECLR; - + uint32_t i; // The function is set per pin: reuse gpio logic - for (i=0; i<16; i++) { - if (obj->mask & (1<mask & (1 << i)) { gpio_set(port_pin(obj->port, i)); } } - + port_dir(obj, dir); } -void port_mode(port_t *obj, PinMode mode) { +void port_mode(port_t *obj, PinMode mode) +{ uint32_t i; // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<mask & (1 << i)) { pin_mode(port_pin(obj->port, i), mode); } } } -void port_dir(port_t *obj, PinDirection dir) { +void port_dir(port_t *obj, PinDirection dir) +{ switch (dir) { - case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + case PIN_INPUT : + *obj->reg_dir &= ~obj->mask; + break; + case PIN_OUTPUT: + *obj->reg_dir |= obj->mask; + break; } } -void port_write(port_t *obj, int value) { +void port_write(port_t *obj, int value) +{ *obj->reg_in = value; } -int port_read(port_t *obj) { +int port_read(port_t *obj) +{ return (*obj->reg_in); } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c index 284c3affb5..c2bf2d3131 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c @@ -30,19 +30,19 @@ ******************************************************************************/ static const PinMap PinMap_UART_TX[] = { - {USBTX , UART_0, 0}, - {XB_TX , UART_1, 0}, - {SH0_TX , UART_2, 0}, - {SH1_TX , UART_3, 0}, - {NC , NC , 0} + {USBTX, UART_0, 0}, + {XB_TX, UART_1, 0}, + {SH0_TX, UART_2, 0}, + {SH1_TX, UART_3, 0}, + {NC, NC, 0} }; static const PinMap PinMap_UART_RX[] = { - {USBRX , UART_0, 0}, - {XB_RX , UART_1, 0}, - {SH0_RX , UART_2, 0}, - {SH1_RX , UART_3, 0}, - {NC , NC , 0} + {USBRX, UART_0, 0}, + {XB_RX, UART_1, 0}, + {SH0_RX, UART_2, 0}, + {SH1_RX, UART_3, 0}, + {NC, NC, 0} }; #define UART_NUM 4 @@ -60,9 +60,10 @@ struct serial_global_data_s { static struct serial_global_data_s uart_data[UART_NUM]; -void serial_init(serial_t *obj, PinName tx, PinName rx) { +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ int is_stdio_uart = 0; - + // determine the UART to use UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); @@ -70,300 +71,314 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { if ((int)uart == NC) { error("Serial pinout mapping failed"); } - + obj->uart = (CMSDK_UART_TypeDef *)uart; //set baud rate and enable Uart in normarl mode (RX and TX enabled) - switch (uart) - { - case UART_0: - { - CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration - if((int)uart_tx != NC) - { - CMSDK_UART0->CTRL |= 0x01; // TX enable - } else { - CMSDK_UART0->CTRL &= 0xFFFE; // TX disable - } - - - if((int)uart_rx != NC) - { - CMSDK_UART0->CTRL |= 0x02; // RX enable - } else { - CMSDK_UART0->CTRL &= 0xFFFD; // RX disable - } + switch (uart) { + case UART_0: { + CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration + if ((int)uart_tx != NC) { + CMSDK_UART0->CTRL |= 0x01; // TX enable + } else { + CMSDK_UART0->CTRL &= 0xFFFE; // TX disable + } - } - break; - case UART_1: //XBEE SOCKET UART - { - CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration - if((int)tx != NC) - { - CMSDK_UART1->CTRL = 0x1; // TX enable - CMSDK_GPIO1->ALTFUNCSET |= 0x0100; - } - if((int)rx != NC) - { - CMSDK_UART1->CTRL |= 0x2; // RX enable - CMSDK_GPIO1->ALTFUNCSET |= 0x0080; - } - } - break; - case UART_2: //Sheild0 UART - { - CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration - if((int)tx != NC) - { - CMSDK_UART3->CTRL = 0x1; // TX enable - CMSDK_GPIO0->ALTFUNCSET |= 0x0010; - } - if((int)rx != NC) - { - CMSDK_UART3->CTRL |= 0x2; // RX enable - CMSDK_GPIO0->ALTFUNCSET |= 0x0001; - } - } - break; - case UART_3: //Sheild1 UART - { - CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration - if((int)tx != NC) - { - CMSDK_UART4->CTRL = 0x1; // TX enable - CMSDK_GPIO1->ALTFUNCSET |= 0x4000; - } - if((int)rx != NC) - { - CMSDK_UART4->CTRL |= 0x2; // RX enable - CMSDK_GPIO1->ALTFUNCSET |= 0x0400; - } - } - break; + + if ((int)uart_rx != NC) { + CMSDK_UART0->CTRL |= 0x02; // RX enable + } else { + CMSDK_UART0->CTRL &= 0xFFFD; // RX disable + } + + } + break; + case UART_1: { //XBEE SOCKET UART + CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration + if ((int)tx != NC) { + CMSDK_UART1->CTRL = 0x1; // TX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0100; + } + if ((int)rx != NC) { + CMSDK_UART1->CTRL |= 0x2; // RX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0080; + } + } + break; + case UART_2: { //Sheild0 UART + CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration + if ((int)tx != NC) { + CMSDK_UART3->CTRL = 0x1; // TX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0010; + } + if ((int)rx != NC) { + CMSDK_UART3->CTRL |= 0x2; // RX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0001; + } + } + break; + case UART_3: { //Sheild1 UART + CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration + if ((int)tx != NC) { + CMSDK_UART4->CTRL = 0x1; // TX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x4000; + } + if ((int)rx != NC) { + CMSDK_UART4->CTRL |= 0x2; // RX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0400; + } + } + break; } // set default baud rate and format - serial_baud (obj, 9600); - + serial_baud(obj, 9600); + // pinout the chosen uart pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); - + switch (uart) { - case UART_0: obj->index = 0; break; - case UART_1: obj->index = 1; break; - case UART_2: obj->index = 2; break; - case UART_3: obj->index = 3; break; + case UART_0: + obj->index = 0; + break; + case UART_1: + obj->index = 1; + break; + case UART_2: + obj->index = 2; + break; + case UART_3: + obj->index = 3; + break; } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; serial_set_flow_control(obj, FlowControlNone, NC, NC); - + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); - + if (is_stdio_uart) { stdio_uart_inited = 1; memcpy(&stdio_uart, obj, sizeof(serial_t)); } } -void serial_free(serial_t *obj) { - uart_data[obj->index].serial_irq_id = 0; +void serial_free(serial_t *obj) +{ + uart_data[obj->index].serial_irq_id = 0; } // serial_baud // set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { +void serial_baud(serial_t *obj, int baudrate) +{ // The MPS2 has a simple divider to control the baud rate. The formula is: // // Baudrate = PCLK / BAUDDIV - // - // PCLK = 25 Mhz - // so for a desired baud rate of 9600 - // 25000000 / 9600 = 2604 + // + // PCLK = 25 Mhz + // so for a desired baud rate of 9600 + // 25000000 / 9600 = 2604 // //check to see if minimum baud value entered int baudrate_div = 0; baudrate_div = SystemCoreClock / baudrate; - if(baudrate >= 16){ - switch ((int)obj->uart) { - case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break; - case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break; - case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break; - case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break; - default: error("serial_baud"); break; - } + if (baudrate >= 16) { + switch ((int)obj->uart) { + case UART_0: + CMSDK_UART0->BAUDDIV = baudrate_div; + break; + case UART_1: + CMSDK_UART1->BAUDDIV = baudrate_div; + break; + case UART_2: + CMSDK_UART3->BAUDDIV = baudrate_div; + break; + case UART_3: + CMSDK_UART4->BAUDDIV = baudrate_div; + break; + default: + error("serial_baud"); + break; + } } else { error("serial_baud"); } } -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ } /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ -static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) { +static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) +{ SerialIrq irq_type; - switch (intstatus) - { - case 1: - { - irq_type = TxIrq; - } - break; + switch (intstatus) { + case 1: { + irq_type = TxIrq; + } + break; - case 2: - { - irq_type = RxIrq; - } - break; + case 2: { + irq_type = RxIrq; + } + break; - default: return; + default: + return; } /* End of Switch */ - if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) - { + if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) { gpio_write(&uart_data[index].sw_rts, 1); // Disable interrupt if it wasn't enabled by other part of the application - if (!uart_data[index].rx_irq_set_api) - { + if (!uart_data[index].rx_irq_set_api) { /* Disable Rx interrupt */ puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); } } - if (uart_data[index].serial_irq_id != 0) - { - if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) - { + if (uart_data[index].serial_irq_id != 0) { + if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) { irq_handler(uart_data[index].serial_irq_id, irq_type); } } - if( irq_type == TxIrq ) - { + if (irq_type == TxIrq) { /* Clear the TX interrupt Flag */ puart->INTCLEAR |= 0x01; - } - else - { + } else { /* Clear the Rx interupt Flag */ puart->INTCLEAR |= 0x02; } } -void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);} -void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);} -void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);} -void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);} +void uart0_irq() +{ + uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef *)CMSDK_UART0); +} +void uart1_irq() +{ + uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef *)CMSDK_UART1); +} +void uart2_irq() +{ + uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef *)CMSDK_UART3); +} +void uart3_irq() +{ + uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef *)CMSDK_UART4); +} -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ irq_handler = handler; uart_data[obj->index].serial_irq_id = id; } -static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { +static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) +{ /* Declare a variable of type IRQn, initialise to 0 */ IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; - switch ((int)obj->uart) - { - case UART_0: - { - irq_n = (( irq == TxIrq ) ? UARTTX0_IRQn : UARTRX0_IRQn); + switch ((int)obj->uart) { + case UART_0: { + irq_n = ((irq == TxIrq) ? UARTTX0_IRQn : UARTRX0_IRQn); vector = (uint32_t)&uart0_irq; } break; - case UART_1: - { - irq_n = (( irq == TxIrq ) ? UARTTX1_IRQn : UARTRX1_IRQn); + case UART_1: { + irq_n = ((irq == TxIrq) ? UARTTX1_IRQn : UARTRX1_IRQn); vector = (uint32_t)&uart1_irq; } break; - case UART_2: - { - irq_n = (( irq == TxIrq ) ? UARTTX3_IRQn : UARTRX3_IRQn); + case UART_2: { + irq_n = ((irq == TxIrq) ? UARTTX3_IRQn : UARTRX3_IRQn); vector = (uint32_t)&uart2_irq; } break; - case UART_3: - { - irq_n = (( irq == TxIrq ) ? UARTTX4_IRQn : UARTRX4_IRQn); - vector = (uint32_t)&uart3_irq; + case UART_3: { + irq_n = ((irq == TxIrq) ? UARTTX4_IRQn : UARTRX4_IRQn); + vector = (uint32_t)&uart3_irq; } break; } - if (enable) - { - if( irq == TxIrq ) - { + if (enable) { + if (irq == TxIrq) { /* Transmit IRQ, set appripriate enable */ /* set TX interrupt enable in CTRL REG */ obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; - } - else - { + } else { /* set Rx interrupt on in CTRL REG */ obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; } NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); - } - else - { /* Disable IRQ */ - + } else { + /* Disable IRQ */ + obj->uart->CTRL &= ~(1 << (irq + 2)); - NVIC_DisableIRQ(irq_n); + NVIC_DisableIRQ(irq_n); } } -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ serial_irq_set_internal(obj, irq, enable); } /****************************************************************************** * READ/WRITE ******************************************************************************/ -int serial_getc(serial_t *obj) { +int serial_getc(serial_t *obj) +{ while (serial_readable(obj) == 0); int data = obj->uart->DATA; return data; } -void serial_putc(serial_t *obj, int c) { +void serial_putc(serial_t *obj, int c) +{ while (serial_writable(obj) == 0); obj->uart->DATA = c; } -int serial_readable(serial_t *obj) { +int serial_readable(serial_t *obj) +{ return obj->uart->STATE & 0x2; } -int serial_writable(serial_t *obj) { +int serial_writable(serial_t *obj) +{ return !(obj->uart->STATE & 0x1); } -void serial_clear(serial_t *obj) { +void serial_clear(serial_t *obj) +{ obj->uart->DATA = 0x00; } -void serial_pinout_tx(PinName tx) { +void serial_pinout_tx(PinName tx) +{ pinmap_pinout(tx, PinMap_UART_TX); } -void serial_break_set(serial_t *obj) { +void serial_break_set(serial_t *obj) +{ } -void serial_break_clear(serial_t *obj) { +void serial_break_clear(serial_t *obj) +{ } -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c index b0b668ad44..debe460501 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_api.c @@ -23,12 +23,12 @@ #include "mbed_wait_api.h" static const PinMap PinMap_SPI_SCLK[] = { - {SCLK_SPI , SPI_0, 0}, - {CLCD_SCLK , SPI_1, 0}, - {ADC_SCLK , SPI_2, 0}, - {SHIELD_0_SPI_SCK , SPI_3, 0}, - {SHIELD_1_SPI_SCK , SPI_4, 0}, - {NC , NC , 0} + {SCLK_SPI, SPI_0, 0}, + {CLCD_SCLK, SPI_1, 0}, + {ADC_SCLK, SPI_2, 0}, + {SHIELD_0_SPI_SCK, SPI_3, 0}, + {SHIELD_1_SPI_SCK, SPI_4, 0}, + {NC, NC, 0} }; static const PinMap PinMap_SPI_MOSI[] = { @@ -37,7 +37,7 @@ static const PinMap PinMap_SPI_MOSI[] = { {ADC_MOSI, SPI_2, 0}, {SHIELD_0_SPI_MOSI, SPI_3, 0}, {SHIELD_1_SPI_MOSI, SPI_4, 0}, - {NC , NC , 0} + {NC, NC, 0} }; static const PinMap PinMap_SPI_MISO[] = { @@ -46,7 +46,7 @@ static const PinMap PinMap_SPI_MISO[] = { {ADC_MISO, SPI_2, 0}, {SHIELD_0_SPI_MISO, SPI_3, 0}, {SHIELD_1_SPI_MISO, SPI_4, 0}, - {NC , NC , 0} + {NC, NC, 0} }; static const PinMap PinMap_SPI_SSEL[] = { @@ -55,101 +55,118 @@ static const PinMap PinMap_SPI_SSEL[] = { {ADC_SSEL, SPI_2, 0}, {SHIELD_0_SPI_nCS, SPI_3, 0}, {SHIELD_1_SPI_nCS, SPI_4, 0}, - {NC , NC , 0} + {NC, NC, 0} }; static inline int ssp_disable(spi_t *obj); static inline int ssp_enable(spi_t *obj); -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - - int altfunction[4]; - // determine the SPI to use +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + + int altfunction[4]; + // determine the SPI to use SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + obj->spi = (MPS2_SSP_TypeDef *)pinmap_merge(spi_data, spi_cntl); if ((int)obj->spi == NC) { error("SPI pinout mapping failed"); } - + // enable power and clocking switch ((int)obj->spi) { - case (int)SPI_0: + case (int)SPI_0: obj->spi->CR1 = 0; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; - obj->spi->CPSR = SSP_CPSR_DFLT; - obj->spi->IMSC = 0x8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; obj->spi->DMACR = 0; obj->spi->CR1 = SSP_CR1_SSE_Msk; - obj->spi->ICR = 0x3; + obj->spi->ICR = 0x3; break; - case (int)SPI_1: - /* Configure SSP used for LCD */ + case (int)SPI_1: + /* Configure SSP used for LCD */ obj->spi->CR1 = 0; /* Synchronous serial port disable */ obj->spi->DMACR = 0; /* Disable FIFO DMA */ obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */ obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */ - (1ul << 1) ); /* Clear SSPRTINTR interrupt */ - obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */ - (0ul << 4) | /* Motorola frame format */ - (0ul << 6) | /* CPOL = 0 */ - (0ul << 7) | /* CPHA = 0 */ - (1ul << 8) ); /* Set serial clock rate */ - obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */ + (1ul << 1)); /* Clear SSPRTINTR interrupt */ + obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */ + (0ul << 4) | /* Motorola frame format */ + (0ul << 6) | /* CPOL = 0 */ + (0ul << 7) | /* CPHA = 0 */ + (1ul << 8)); /* Set serial clock rate */ + obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */ obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */ - (0ul << 2) ); /* Device configured as master */ + (0ul << 2)); /* Device configured as master */ break; - case (int)SPI_2: + case (int)SPI_2: obj->spi->CR1 = 0; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; - obj->spi->CPSR = SSP_CPSR_DFLT; - obj->spi->IMSC = 0x8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; obj->spi->DMACR = 0; obj->spi->CR1 = SSP_CR1_SSE_Msk; - obj->spi->ICR = 0x3; + obj->spi->ICR = 0x3; break; - case (int)SPI_3: + case (int)SPI_3: obj->spi->CR1 = 0; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; - obj->spi->CPSR = SSP_CPSR_DFLT; - obj->spi->IMSC = 0x8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; obj->spi->DMACR = 0; obj->spi->CR1 = SSP_CR1_SSE_Msk; - obj->spi->ICR = 0x3; + obj->spi->ICR = 0x3; break; - case (int)SPI_4: + case (int)SPI_4: obj->spi->CR1 = 0; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; - obj->spi->CPSR = SSP_CPSR_DFLT; - obj->spi->IMSC = 0x8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; obj->spi->DMACR = 0; obj->spi->CR1 = SSP_CR1_SSE_Msk; - obj->spi->ICR = 0x3; + obj->spi->ICR = 0x3; break; } - - if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} - if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} - if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} - if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} - + + if (mosi != NC) { + altfunction[0] = 1; + } else { + altfunction[0] = 0; + } + if (miso != NC) { + altfunction[1] = 1; + } else { + altfunction[1] = 0; + } + if (sclk != NC) { + altfunction[2] = 1; + } else { + altfunction[2] = 0; + } + if (ssel != NC) { + altfunction[3] = 1; + } else { + altfunction[3] = 0; + } + // enable alt function switch ((int)obj->spi) { - case (int)SPI_2: - CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]); + case (int)SPI_2: + CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2] << 3 | altfunction[0] << 2 | altfunction[1] << 1 | altfunction[3]); break; - case (int)SPI_3: - CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11); + case (int)SPI_3: + CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1] << 14 | altfunction[0] << 13 | altfunction[3] << 12 | altfunction[2] << 11); break; - case (int)SPI_4: - CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6); + case (int)SPI_4: + CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2] << 12 | altfunction[1] << 8 | altfunction[0] << 7 | altfunction[3] << 6); break; - } - + } + // set default format and frequency if (ssel == NC) { spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master @@ -157,7 +174,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave } spi_frequency(obj, 1000000); - + // enable the ssp channel ssp_enable(obj); @@ -172,57 +189,59 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel void spi_free(spi_t *obj) {} -void spi_format(spi_t *obj, int bits, int mode, int slave) { +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ ssp_disable(obj); if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { error("SPI format error"); } - + int polarity = (mode & 0x2) ? 1 : 0; int phase = (mode & 0x1) ? 1 : 0; - + // set it up int DSS = bits - 1; // DSS (data select size) int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity int SPH = (phase) ? 1 : 0; // SPH - clock out phase - + int FRF = 0; // FRF (frame format) = SPI uint32_t tmp = obj->spi->CR0; tmp &= ~(0xFFFF); tmp |= DSS << 0 - | FRF << 4 - | SPO << 6 - | SPH << 7; + | FRF << 4 + | SPO << 6 + | SPH << 7; obj->spi->CR0 = tmp; - + tmp = obj->spi->CR1; tmp &= ~(0xD); tmp |= 0 << 0 // LBM - loop back mode - off - | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave - | 0 << 3; // SOD - slave output disable - na + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na obj->spi->CR1 = tmp; - + ssp_enable(obj); } -void spi_frequency(spi_t *obj, int hz) { +void spi_frequency(spi_t *obj, int hz) +{ ssp_disable(obj); - + uint32_t PCLK = SystemCoreClock; - - int prescaler; - + + int prescaler; + for (prescaler = 2; prescaler <= 254; prescaler += 2) { int prescale_hz = PCLK / prescaler; - + // calculate the divider int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); - + // check we can support the divider if (divider < 256) { // prescaler obj->spi->CPSR = prescaler; - + // divider obj->spi->CR0 &= ~(0xFFFF << 8); obj->spi->CR0 |= (divider - 1) << 8; @@ -233,43 +252,52 @@ void spi_frequency(spi_t *obj, int hz) { error("Couldn't setup requested SPI frequency"); } -static inline int ssp_disable(spi_t *obj) { +static inline int ssp_disable(spi_t *obj) +{ return obj->spi->CR1 &= ~(1 << 1); } -static inline int ssp_enable(spi_t *obj) { +static inline int ssp_enable(spi_t *obj) +{ return obj->spi->CR1 |= SSP_CR1_SSE_Msk; } -static inline int ssp_readable(spi_t *obj) { +static inline int ssp_readable(spi_t *obj) +{ return obj->spi->SR & (1 << 2); } -static inline int ssp_writeable(spi_t *obj) { +static inline int ssp_writeable(spi_t *obj) +{ return obj->spi->SR & SSP_SR_BSY_Msk; } -static inline void ssp_write(spi_t *obj, int value) { +static inline void ssp_write(spi_t *obj, int value) +{ obj->spi->DR = value; while (ssp_writeable(obj)); } -static inline int ssp_read(spi_t *obj) { +static inline int ssp_read(spi_t *obj) +{ int read_DR = obj->spi->DR; return read_DR; } -static inline int ssp_busy(spi_t *obj) { +static inline int ssp_busy(spi_t *obj) +{ return (obj->spi->SR & (1 << 4)) ? (1) : (0); } -int spi_master_write(spi_t *obj, int value) { +int spi_master_write(spi_t *obj, int value) +{ ssp_write(obj, value); while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ return (ssp_read(obj)); } int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { + char *rx_buffer, int rx_length, char write_fill) +{ int total = (tx_length > rx_length) ? tx_length : rx_length; for (int i = 0; i < total; i++) { @@ -283,19 +311,23 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, return total; } -int spi_slave_receive(spi_t *obj) { +int spi_slave_receive(spi_t *obj) +{ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); } -int spi_slave_read(spi_t *obj) { +int spi_slave_read(spi_t *obj) +{ return obj->spi->DR; } -void spi_slave_write(spi_t *obj, int value) { +void spi_slave_write(spi_t *obj, int value) +{ while (ssp_writeable(obj) == 0) ; obj->spi->DR = value; } -int spi_busy(spi_t *obj) { +int spi_busy(spi_t *obj) +{ return ssp_busy(obj); } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h index ac76b34c6e..bb686eefa7 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h @@ -16,7 +16,7 @@ * File: apspi.h * Release: Version 2.0 * ---------------------------------------------------------------- - * + * * SSP interface Support * ===================== */ @@ -107,11 +107,11 @@ #define EERDSR_BP1 0x0008 // Block protect 1 #define EERDSR_WPEN 0x0080 // Write protect enable - /* ---------------------------------------------------------------- - * - * Color LCD Support - * ================= - */ +/* ---------------------------------------------------------------- +* +* Color LCD Support +* ================= +*/ // Color LCD Controller Internal Register addresses #define LSSPCS_BASE (0x4002804C) // LSSP chip select register diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c index 6ae74aea9c..04fc483601 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/us_ticker.c @@ -23,42 +23,49 @@ int us_ticker_inited = 0; -void us_ticker_init(void) { - if (us_ticker_inited) return; +void us_ticker_init(void) +{ + if (us_ticker_inited) { + return; + } us_ticker_inited = 1; - + US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER2->TimerControl = 0x00; // disable timer US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF; US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF; - + US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter - + US_TICKER_TIMER1->TimerControl |= 0x80; // enable counter US_TICKER_TIMER2->TimerControl |= 0x80; // enable counter - + NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); } -uint32_t us_ticker_read() { -uint32_t return_value = 0; - if (!us_ticker_inited) +uint32_t us_ticker_read() +{ + uint32_t return_value = 0; + if (!us_ticker_inited) { us_ticker_init(); - return_value = ((~US_TICKER_TIMER2->TimerValue)/25); + } + return_value = ((~US_TICKER_TIMER2->TimerValue) / 25); return return_value; } -void us_ticker_set_interrupt(timestamp_t timestamp) { - if (!us_ticker_inited) +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + if (!us_ticker_inited) { us_ticker_init(); + } - uint32_t delta = timestamp - us_ticker_read(); - // enable interrupt + uint32_t delta = timestamp - us_ticker_read(); + // enable interrupt US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode - US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value + US_TICKER_TIMER1->TimerLoad = (delta) * 25; //initialise the timer value US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer } @@ -68,14 +75,16 @@ void us_ticker_fire_interrupt(void) } -void us_ticker_disable_interrupt(void) { - +void us_ticker_disable_interrupt(void) +{ + US_TICKER_TIMER1->TimerControl &= 0xDF; US_TICKER_TIMER2->TimerControl &= 0xDF; } -void us_ticker_clear_interrupt(void) { +void us_ticker_clear_interrupt(void) +{ US_TICKER_TIMER1->TimerIntClr = 0x1; US_TICKER_TIMER2->TimerIntClr = 0x1; From bc03c20408f621caad3948b13d793ce5218cf0d6 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 21 May 2018 18:33:48 +0100 Subject: [PATCH 09/11] update targets.json remove redundant extra_lables --- targets/targets.json | 6 ------ 1 file changed, 6 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index d63395b9c7..1bc9986835 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -4018,7 +4018,6 @@ "inherits": ["ARM_FM"], "public": false, "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], - "extra_labels_add": ["FVP_MPS2"], "OUTPUT_EXT": "elf", "device_has": ["AACI", "ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"], "release_versions": ["5"] @@ -4026,31 +4025,26 @@ "FVP_MPS2_M0": { "inherits": ["FVP_MPS2"], "core": "Cortex-M0", - "extra_labels_add": ["FVP_MPS2_M0"], "macros": ["CMSDK_CM0","CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""] }, "FVP_MPS2_M0P": { "inherits": ["FVP_MPS2"], "core": "Cortex-M0+", - "extra_labels_add": ["FVP_MPS2_M0P"], "macros": ["CMSDK_CM0plus"] }, "FVP_MPS2_M3": { "inherits": ["FVP_MPS2"], "core": "Cortex-M3", - "extra_labels_add": ["FVP_MPS2_M3"], "macros": ["CMSDK_CM3"] }, "FVP_MPS2_M4": { "inherits": ["FVP_MPS2"], "core": "Cortex-M4", - "extra_labels_add": ["FVP_MPS2_M4"], "macros": ["CMSDK_CM4"] }, "FVP_MPS2_M7": { "inherits": ["FVP_MPS2"], "core": "Cortex-M7", - "extra_labels_add": ["FVP_MPS2_M7"], "macros": ["CMSDK_CM7"] } } From f35ba494ca7036810f9876c095dd7b1d8feac4cc Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 21 May 2018 18:43:37 +0100 Subject: [PATCH 10/11] remove empty lines and redundant variables --- .../TARGET_FVP_MPS2/SDK/ETH_MPS2.c | 10 +- .../TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c | 8 +- .../TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h | 566 ++++++++-------- .../TARGET_FVP_MPS2_M3/device/SMM_MPS2.h | 566 ++++++++-------- .../TARGET_FVP_MPS2_M4/device/SMM_MPS2.h | 560 ++++++++-------- .../TARGET_FVP_MPS2_M7/device/SMM_MPS2.h | 610 +++++++++--------- .../TARGET_ARM_FM/TARGET_FVP_MPS2/device.h | 19 - 7 files changed, 1168 insertions(+), 1171 deletions(-) diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c index 0e1c17d2f1..d0ded31e75 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c @@ -188,7 +188,7 @@ unsigned int smsc9220_read_id(void) return SMSC9220->ID_REV; } -// Initiates a soft reset, returns failure or success. +// Initiates a soft reset, returns 0 on success, or 1 on failure. unsigned int smsc9220_soft_reset(void) { int timedout; @@ -260,18 +260,14 @@ unsigned int smsc9220_check_phy(void) unsigned int smsc9220_reset_phy(void) { unsigned short read; - int error; - error = 0; if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { - error = 1; - return error; + return 1; } read |= (1 << 15); if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { - error = 1; - return error; + return 1; } return 0; } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c index 0b8b928e7d..f5032d241b 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c @@ -60,14 +60,11 @@ int smsc9220_check_id(void) int smsc9220_check_macaddress(void) { - int error; const unsigned int mac_valid_high = 0xC00A; const unsigned int mac_valid_low = 0x00F70200; unsigned int mac_low; unsigned int mac_high; - error = 0; - // Read current mac address. smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); @@ -82,11 +79,10 @@ int smsc9220_check_macaddress(void) if (mac_high != mac_valid_high || mac_low != mac_valid_low) { - error = TRUE; - return error; + return 1; } - return error; + return 0; } void smsc9220_print_mac_registers() diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h index 1e11483c3a..af11e0b478 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -590,9 +596,9 @@ typedef struct { // SMSC LAN9220 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h index 1e11483c3a..3b78c8b44f 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/SMM_MPS2.h @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -590,9 +596,9 @@ typedef struct { // SMSC LAN9220 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h index 1e11483c3a..6b2a5ac3d7 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h index 2e44ab2207..e438d840f6 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/SMM_MPS2.h @@ -2,32 +2,32 @@ * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h * Release: Version 1.1 @@ -46,39 +46,40 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct { - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions @@ -106,57 +107,58 @@ typedef struct { /* SCC Register declaration */ /******************************************************************************/ -typedef struct { // - __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT - // [31:1] : Reserved - // [0] 1 : REMAP BlockRam to ZBT - __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs - // [31:8] : Reserved - // [7:0] : MCC LEDs - uint32_t RESERVED0[1]; - __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches - // [31:8] : Reserved - // [7:0] : These bits indicate state of the MCC switches - __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision - // [31:4] : Reserved - // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B - uint32_t RESERVED1[35]; - __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register - // [31:0] : Data - __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register - // [31] : Start (generates interrupt on write to this bit) - // [30] : R/W access - // [29:26] : Reserved - // [25:20] : Function value - // [19:12] : Reserved - // [11:0] : Device (value of 0/1/2 for supported clocks) - __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information - // [31:2] : Reserved - // [1] : Error - // [0] : Complete - __IO uint32_t RESERVED2[20]; - __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register - // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked - // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked - // [15:1] : Reserved - // [0] : This bit indicates if all enabled DLLs are locked - uint32_t RESERVED3[957]; - __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register - // [31:24] : FPGA build number - // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) - // [19:11] : Reserved - // [10] : if “1” SCC_SW register has been implemented - // [9] : if “1” SCC_LED register has been implemented - // [8] : if “1” DLL lock register has been implemented - // [7:0] : number of SCC configuration register - __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image - // [31:24] : Implementer ID: 0x41 = ARM - // [23:20] : Application note IP variant number - // [19:16] : IP Architecture: 0x4 =AHB - // [15:4] : Primary part number: 386 = AN386 - // [3:0] : Application note IP revision number +typedef struct // +{ + __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT + // [31:1] : Reserved + // [0] 1 : REMAP BlockRam to ZBT + __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs + // [31:8] : Reserved + // [7:0] : MCC LEDs + uint32_t RESERVED0[1]; + __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches + // [31:8] : Reserved + // [7:0] : These bits indicate state of the MCC switches + __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision + // [31:4] : Reserved + // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B + uint32_t RESERVED1[35]; + __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register + // [31:0] : Data + __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register + // [31] : Start (generates interrupt on write to this bit) + // [30] : R/W access + // [29:26] : Reserved + // [25:20] : Function value + // [19:12] : Reserved + // [11:0] : Device (value of 0/1/2 for supported clocks) + __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information + // [31:2] : Reserved + // [1] : Error + // [0] : Complete + __IO uint32_t RESERVED2[20]; + __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register + // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked + // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked + // [15:1] : Reserved + // [0] : This bit indicates if all enabled DLLs are locked + uint32_t RESERVED3[957]; + __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register + // [31:24] : FPGA build number + // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) + // [19:11] : Reserved + // [10] : if “1” SCC_SW register has been implemented + // [9] : if “1” SCC_LED register has been implemented + // [8] : if “1” DLL lock register has been implemented + // [7:0] : number of SCC configuration register + __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image + // [31:24] : Implementer ID: 0x41 = ARM + // [23:20] : Application note IP variant number + // [19:16] : IP Architecture: 0x4 =AHB + // [15:4] : Primary part number: 386 = AN386 + // [3:0] : Application note IP revision number } MPS2_SCC_TypeDef; @@ -164,59 +166,60 @@ typedef struct { // /* SSP Peripheral declaration */ /******************************************************************************/ -typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf - __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 - // [31:16] : Reserved - // [15:8] : Serial clock rate - // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only - // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // [5:4] : Frame format - // [3:0] : Data Size Select - __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 - // [31:4] : Reserved - // [3] : Slave-mode output disable - // [2] : Master or slave mode select - // [1] : Synchronous serial port enable - // [0] : Loop back mode - __IO uint32_t DR; // Offset: 0x008 (R/W) Data register - // [31:16] : Reserved - // [15:0] : Transmit/Receive FIFO - __I uint32_t SR; // Offset: 0x00C (R/ ) Status register - // [31:5] : Reserved - // [4] : PrimeCell SSP busy flag - // [3] : Receive FIFO full - // [2] : Receive FIFO not empty - // [1] : Transmit FIFO not full - // [0] : Transmit FIFO empty - __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register - // [31:8] : Reserved - // [8:0] : Clock prescale divisor - __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register - // [31:4] : Reserved - // [3] : Transmit FIFO interrupt mask - // [2] : Receive FIFO interrupt mask - // [1] : Receive timeout interrupt mask - // [0] : Receive overrun interrupt mask - __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register - // [31:4] : Reserved - // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt - __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register - // [31:4] : Reserved - // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register - // [31:2] : Reserved - // [1] : Clears the SSPRTINTR interrupt - // [0] : Clears the SSPRORINTR interrupt - __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register - // [31:2] : Reserved - // [1] : Transmit DMA Enable - // [0] : Receive DMA Enable +typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf +{ + __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 + // [31:16] : Reserved + // [15:8] : Serial clock rate + // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only + // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // [5:4] : Frame format + // [3:0] : Data Size Select + __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 + // [31:4] : Reserved + // [3] : Slave-mode output disable + // [2] : Master or slave mode select + // [1] : Synchronous serial port enable + // [0] : Loop back mode + __IO uint32_t DR; // Offset: 0x008 (R/W) Data register + // [31:16] : Reserved + // [15:0] : Transmit/Receive FIFO + __I uint32_t SR; // Offset: 0x00C (R/ ) Status register + // [31:5] : Reserved + // [4] : PrimeCell SSP busy flag + // [3] : Receive FIFO full + // [2] : Receive FIFO not empty + // [1] : Transmit FIFO not full + // [0] : Transmit FIFO empty + __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register + // [31:8] : Reserved + // [8:0] : Clock prescale divisor + __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register + // [31:4] : Reserved + // [3] : Transmit FIFO interrupt mask + // [2] : Receive FIFO interrupt mask + // [1] : Receive timeout interrupt mask + // [0] : Receive overrun interrupt mask + __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register + // [31:4] : Reserved + // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt + __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register + // [31:4] : Reserved + // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register + // [31:2] : Reserved + // [1] : Clears the SSPRTINTR interrupt + // [0] : Clears the SSPRORINTR interrupt + __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register + // [31:2] : Reserved + // [1] : Transmit DMA Enable + // [0] : Receive DMA Enable } MPS2_SSP_TypeDef; @@ -311,12 +314,13 @@ typedef struct { // Document DDI0194G_ssp_pl022_r1p3_trm.pdf /* Audio and Touch Screen (I2C) Peripheral declaration */ /******************************************************************************/ -typedef struct { - union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) - }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -327,106 +331,107 @@ typedef struct { /* Audio I2S Peripheral declaration */ /******************************************************************************/ -typedef struct { - /*!< Offset: 0x000 CONTROL Register (R/W) */ - __IO uint32_t CONTROL; // CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error +typedef struct +{ + /*!< Offset: 0x000 CONTROL Register (R/W) */ + __IO uint32_t CONTROL; // CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 @@ -481,43 +486,44 @@ typedef struct { /* SMSC9220 Register Definitions */ /******************************************************************************/ -typedef struct { // SMSC LAN9220 - __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) - uint32_t RESERVED1[0x7]; - __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) - uint32_t RESERVED2[0x7]; +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; - __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) - __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) - __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) - __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) - __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) - __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) - __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) - __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) - uint32_t RESERVED3; // Reserved for future use (offset 0x60) - __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) - __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) - __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) - __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) - __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) - __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) - __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) - __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) - __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) - __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) - __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) - __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) - uint32_t RESERVED4; // Reserved for future use (offset 0x94) - __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) - __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) - __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) - __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) - __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) - __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) - __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) - __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) } SMSC9220_TypeDef; @@ -586,9 +592,9 @@ typedef struct { // SMSC LAN9220 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) -#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) -#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) -#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h index f7db3c293d..97ace26e8b 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/device.h @@ -20,24 +20,5 @@ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H - - - - - - - - - - - - - - - - - - #include "objects.h" - #endif From 304b5840402420aea26ffb5a05b8b9b5cae219f6 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Tue, 22 May 2018 11:24:50 +0100 Subject: [PATCH 11/11] remove ethernet driver as it is not compatible --- .../TARGET_FVP_MPS2/SDK/ETH_MPS2.c | 451 ------------------ .../TARGET_FVP_MPS2/SDK/ETH_MPS2.h | 65 --- .../TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c | 162 ------- .../TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h | 57 --- .../TARGET_FVP_MPS2/ethernet_api.c | 166 ------- 5 files changed, 901 deletions(-) delete mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c delete mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h delete mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c delete mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h delete mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c deleted file mode 100644 index d0ded31e75..0000000000 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.c +++ /dev/null @@ -1,451 +0,0 @@ -/* MPS2 Peripheral Library -* -* Copyright (c) 2006-2018 ARM Limited -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -*/ - -/* - * Code implementation file for the LAN Ethernet interface. - */ - -#include -#include "mbed_wait_api.h" -#include "ETH_MPS2.h" - -// SMSC9220 low-level operations -unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) -{ - unsigned int val, maccmd; - int timedout; - int error; - - error = 0; - val = SMSC9220->MAC_CSR_CMD; - if (!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation - maccmd = 0; - maccmd |= regoffset; - maccmd |= ((unsigned int)1 << 30); // Indicates read - maccmd |= ((unsigned int)1 << 31); // Start bit - SMSC9220->MAC_CSR_CMD = maccmd; // Start operation - - timedout = 50; - do { - val = SMSC9220->BYTE_TEST; // A no-op read. - wait_ms(1); - timedout--; - } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); - - if (!timedout) { - error = 1; - } else { - *data = SMSC9220->MAC_CSR_DATA; - } - } else { - *data = 0; - } - return error; -} - -unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data) -{ - unsigned int read, maccmd; - int timedout; - int error; - - error = 0; - read = SMSC9220->MAC_CSR_CMD; - if (!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation - SMSC9220->MAC_CSR_DATA = data; // Store data. - maccmd = 0; - maccmd |= regoffset; - maccmd &= ~((unsigned int)1 << 30); // Clear indicates write - maccmd |= ((unsigned int)1 << 31); // Indicate start of operation - SMSC9220->MAC_CSR_CMD = maccmd; - - timedout = 50; - do { - read = SMSC9220->BYTE_TEST; // A no-op read. - wait_ms(1); - timedout--; - } while (timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); - - if (!timedout) { - error = 1; - } - } else { - printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n"); - } - return error; -} - -unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) -{ - unsigned int val, phycmd; - int error; - int timedout; - - error = 0; - - smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); - - if (!(val & 1)) { // Not busy - phycmd = 0; - phycmd |= (1 << 11); // 1 to [15:11] - phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] - phycmd &= ~(1 << 1); // Clear [1] indicates read. - phycmd |= (1 << 0); // Set [0] indicates operation start - - smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); - - val = 0; - timedout = 50; - do { - wait_ms(1); - timedout--; - smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); - } while (timedout && (val & ((unsigned int)1 << 0))); - - if (!timedout) { - error = 1; - } else { - smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data); - } - - } else { - *data = 0; - } - return error; -} - -unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) -{ - unsigned int val, phycmd; - int error; - int timedout; - - error = 0; - - smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); - - if (!(val & 1)) { // Not busy - smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data - phycmd = 0; - phycmd |= (1 << 11); // 1 to [15:11] - phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] - phycmd |= (1 << 1); // Set [1] indicates write. - phycmd |= (1 << 0); // Set [0] indicates operation start - smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); // Start operation - - phycmd = 0; - timedout = 50; - - do { - - wait_ms(1); - timedout--; - smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd); - } while (timedout && (phycmd & (1 << 0))); - - if (!timedout) { - error = 1; - } - - } else { - printf("Warning: SMSC9220 MAC MII is busy. No data written.\n"); - } - return error; -} - -// Returns smsc9220 id. -unsigned int smsc9220_read_id(void) -{ - return SMSC9220->ID_REV; -} - -// Initiates a soft reset, returns 0 on success, or 1 on failure. -unsigned int smsc9220_soft_reset(void) -{ - int timedout; - - timedout = 10; - // Soft reset - SMSC9220->HW_CFG |= 1; - - do { - wait_ms(1); - timedout--; - } while (timedout && (SMSC9220->HW_CFG & 1)); - - if (!timedout) { - return 1; - } - - return 0; -} - -void smsc9220_set_txfifo(unsigned int val) -{ - // 2kb minimum, 14kb maximum - if (val < 2 || val > 14) { - return; - } - - SMSC9220->HW_CFG = val << 16; -} - - -unsigned int smsc9220_wait_eeprom(void) -{ - int timedout; - - timedout = 50; - - do { - wait_ms(1); - timedout--; - - } while (timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); - - if (!timedout) { - return 1; - } - - return 0; -} - -/* initialise irqs */ -void smsc9220_init_irqs(void) -{ - SMSC9220->INT_EN = 0x0; - SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts - SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable. -} - -unsigned int smsc9220_check_phy(void) -{ - unsigned short phyid1, phyid2; - - smsc9220_phy_regread(SMSC9220_PHY_ID1, &phyid1); - smsc9220_phy_regread(SMSC9220_PHY_ID2, &phyid2); - return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || - (phyid1 == 0x0 && phyid2 == 0x0)); -} - -unsigned int smsc9220_reset_phy(void) -{ - unsigned short read; - - if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { - return 1; - } - - read |= (1 << 15); - if (smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { - return 1; - } - return 0; -} - -/* Advertise all speeds and pause capabilities */ -void smsc9220_advertise_cap(void) -{ - unsigned short aneg_adv; - aneg_adv = 0; - - - smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); - aneg_adv |= 0xDE0; - - smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv); - smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); - return; -} - -void smsc9220_establish_link(void) -{ - unsigned short bcr; - - smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); - bcr |= (1 << 12) | (1 << 9); - smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr); - smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); - - { - unsigned int hw_cfg; - - hw_cfg = 0; - hw_cfg = SMSC9220->HW_CFG; - - hw_cfg &= 0xF0000; - hw_cfg |= (1 << 20); - SMSC9220->HW_CFG = hw_cfg; - } - - return; -} - -void smsc9220_enable_xmit(void) -{ - SMSC9220->TX_CFG = 0x2; // Enable trasmission - return; -} - -void smsc9220_enable_mac_xmit(void) -{ - unsigned int mac_cr; - - mac_cr = 0; - smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); - - mac_cr |= (1 << 3); // xmit enable - mac_cr |= (1 << 28); // Heartbeat disable - - smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); - return; -} - -void smsc9220_enable_mac_recv(void) -{ - unsigned int mac_cr; - - mac_cr = 0; - smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); - mac_cr |= (1 << 2); // Recv enable - smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); - - return; -} - - -unsigned int smsc9220_check_ready(void) -{ - return !(SMSC9220->PMT_CTRL & 1); -} - -/* Generate a soft irq */ -void smsc9220_set_soft_int(void) -{ - SMSC9220->INT_EN |= 0x80000000; -} - -/* clear soft irq */ -void smsc9220_clear_soft_int(void) -{ - SMSC9220->INT_STS |= 0x80000000; -} - - -unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) -{ - unsigned int rxfifo_inf; // Tells us the status of rx payload and status fifos. - unsigned int rxfifo_stat; - - unsigned int pktsize; - unsigned int dwords_to_read; - - rxfifo_inf = SMSC9220->RX_FIFO_INF; - - if (rxfifo_inf & 0xFFFF) { // If there's data - rxfifo_stat = SMSC9220->RX_STAT_PORT; - if (rxfifo_stat != 0) { // Fetch status of this packet - pktsize = ((rxfifo_stat >> 16) & 0x3FFF); - if (rxfifo_stat & (1 << 15)) { - printf("Error occured during receiving of packets on the bus.\n"); - return 1; - } else { - /* Below formula (recommended by SMSC9220 code) - * gives 1 more than required. This is perhaps because - * a last word is needed for not word aligned packets. - */ - dwords_to_read = (pktsize + 3) >> 2; - // PIO copy of data received: - while (dwords_to_read > 0) { - recvbuf[*index] = SMSC9220->RX_DATA_PORT; - (*index)++; - dwords_to_read--; - } - } - } else { - return 1; - } - } else { - return 1; - } - - rxfifo_stat = SMSC9220->RX_STAT_PORT; - rxfifo_inf = SMSC9220->RX_FIFO_INF; - - return 0; -} - - -// Does the actual transfer of data to FIFO, note it does no -// fifo availability checking. This should be done by caller. -// Assumes the whole frame is transferred at once as a single segment -void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length) -{ - unsigned int txcmd_a, txcmd_b; - unsigned int dwords_to_write; - volatile unsigned int dwritten; - unsigned int *pktptr; - volatile unsigned int xmit_stat, xmit_stat2, xmit_inf; - int i; - - pktptr = (unsigned int *) pkt; - txcmd_a = 0; - txcmd_b = 0; - - txcmd_a |= (1 << 12) | (1 << 13); // First and last segments - txcmd_a |= length & 0x7FF; // [10:0] contains length - - txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length - txcmd_b |= length & 0x7FF; // [10:0] also contains length - - - SMSC9220->TX_DATA_PORT = txcmd_a; - SMSC9220->TX_DATA_PORT = txcmd_b; - dwritten = dwords_to_write = (length + 3) >> 2; - - // PIO Copy to FIFO. Could replace this with DMA. - while (dwords_to_write > 0) { - SMSC9220->TX_DATA_PORT = *pktptr; - pktptr++; - dwords_to_write--; - } - - xmit_stat = SMSC9220->TX_STAT_PORT; - xmit_stat2 = SMSC9220->TX_STAT_PORT; - xmit_inf = SMSC9220->TX_FIFO_INF; - - if (xmit_stat2 != 0) { - for (i = 0; i < 6; i++) { - xmit_stat2 = SMSC9220->TX_STAT_PORT; - } - } -} diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h deleted file mode 100644 index 38e9d66610..0000000000 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/ETH_MPS2.h +++ /dev/null @@ -1,65 +0,0 @@ -/* MPS2 Peripheral Library -* -* Copyright (c) 2006-2018 ARM Limited -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _ETH_MPS2_H_ -#define _ETH_MPS2_H_ - -#include "SMM_MPS2.h" - -// Function declarations - -unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data); -unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data); -unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data); -unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data); - -unsigned int smsc9220_read_id(void); -unsigned int smsc9220_soft_reset(void); -void smsc9220_set_txfifo(unsigned int val); -unsigned int smsc9220_wait_eeprom(void); -void smsc9220_init_irqs(void); -unsigned int smsc9220_check_phy(void); -unsigned int smsc9220_reset_phy(void); - -void smsc9220_advertise_cap(void); -void smsc9220_establish_link(void); -void smsc9220_enable_xmit(void); -void smsc9220_enable_mac_xmit(void); -void smsc9220_enable_mac_recv(void); -unsigned int smsc9220_check_ready(void); -void smsc9220_set_soft_int(void); -void smsc9220_clear_soft_int(void); - -unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index); -void smsc9220_xmit_packet(unsigned char *pkt, unsigned int length); - -#endif diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c deleted file mode 100644 index f5032d241b..0000000000 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.c +++ /dev/null @@ -1,162 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "mps2_ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "ETH_MPS2.h" -#include "mbed_wait_api.h" - -#define TX_PKT_SIZE 256 -#define RX_PKT_SIZE 300 - -// Types -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 - - -int smsc9220_check_id(void) -{ - int error; - unsigned int id; - error = 0; - - id = smsc9220_read_id(); - - // If bottom and top halves of the word are the same - if (((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { - error = 1; - return error; - } - switch (((id >> 16) & 0xFFFF)) { - case 0x9220: - break; - - default: - error = 1; - break; - } - - return error; -} - -int smsc9220_check_macaddress(void) -{ - const unsigned int mac_valid_high = 0xC00A; - const unsigned int mac_valid_low = 0x00F70200; - unsigned int mac_low; - unsigned int mac_high; - - // Read current mac address. - smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); - smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); - - // Writing temporary address: - smsc9220_mac_regwrite(SMSC9220_MAC_ADDRH, mac_valid_high); - smsc9220_mac_regwrite(SMSC9220_MAC_ADDRL, mac_valid_low); - - // Verify write was correct: - smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); - smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); - - - if (mac_high != mac_valid_high || mac_low != mac_valid_low) { - return 1; - } - - return 0; -} - -void smsc9220_print_mac_registers() -{ - unsigned int read; - int i; - - i = 0; - read = 0; - - for (i = 1; i <= 0xC; i++) { - smsc9220_mac_regread(i, &read); - } - return; -} - - -void smsc9220_print_phy_registers() -{ - unsigned short read; - unsigned int i; - - i = 0; - read = 0; - for (i = 0; i <= 6; i++) { - smsc9220_phy_regread(i, &read); - } - smsc9220_phy_regread(i = 17, &read); - - smsc9220_phy_regread(i = 18, &read); - - smsc9220_phy_regread(i = 27, &read); - - smsc9220_phy_regread(i = 29, &read); - - smsc9220_phy_regread(i = 30, &read); - - smsc9220_phy_regread(i = 31, &read); - - return; -} - -/*---------------------------------------------------------------------------- - Ethernet Device initialize - *----------------------------------------------------------------------------*/ - -int ethernet_transmission(unsigned char *pkt, unsigned int length) -{ - smsc9220_xmit_packet(pkt, length); - return 0; -} - -int ethernet_reception(unsigned int *recvbuf, unsigned int *index) -{ - return smsc9220_recv_packet((unsigned int *)recvbuf, index); -} - -int ethernet_mac_address(char *mac) -{ - return smsc9220_check_macaddress(); -} - -unsigned int ethernet_check_ready(void) -{ - return smsc9220_check_ready(); -} - -unsigned int ethernet_intf() -{ - unsigned int txfifo_inf; - - txfifo_inf = SMSC9220->TX_FIFO_INF; - - return txfifo_inf; - -} - diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h deleted file mode 100644 index 33a9d83a58..0000000000 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/mps2_ethernet_api.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MPS2_ETHERNET_API_H -#define MPS2_ETHERNET_API_H - -#include "device.h" - -#if DEVICE_ETHERNET - -#ifdef __cplusplus -extern "C" { -#endif - -// Connection constants - -// send ethernet write buffer, returning the packet size sent -int ethernet_transmission(unsigned char *pkt, unsigned int length); - -// recieve from ethernet buffer, returning packet size, or 0 if no packet -int ethernet_reception(unsigned int *recvbuf, unsigned int *index); - -// get the ethernet address -int ethernet_mac_address(char *mac); - -unsigned int ethernet_check_ready(void); - -unsigned int ethernet_intf(void); - -int smsc9220_check_id(void); - -int smsc9220_check_macaddress(void); - -void smsc9220_print_mac_registers(void); -void smsc9220_print_phy_registers(void); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c deleted file mode 100644 index ee69baa865..0000000000 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/ethernet_api.c +++ /dev/null @@ -1,166 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "ethernet_api.h" -#include "mps2_ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "ETH_MPS2.h" -#include "mbed_wait_api.h" - -#define TX_PKT_SIZE 256 -#define RX_PKT_SIZE 300 - -// Types -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 - -/*---------------------------------------------------------------------------- - Ethernet Device initialize - *----------------------------------------------------------------------------*/ -int ethernet_init() -{ - int error; - error = 0; - - if (smsc9220_check_id()) { - error = TRUE; - } - - if (smsc9220_soft_reset()) { - error = TRUE; - } - - smsc9220_set_txfifo(5); - - // Sets automatic flow control thresholds, and backpressure - // threshold to defaults specified. - SMSC9220->AFC_CFG = 0x006E3740; - - if (smsc9220_wait_eeprom()) { - error = TRUE; - } - - // Configure GPIOs as LED outputs. - SMSC9220->GPIO_CFG = 0x70070000; - - smsc9220_init_irqs(); - - /* Configure MAC addresses here if needed. */ - - if (smsc9220_check_phy()) { - error = TRUE; - } - - if (smsc9220_reset_phy()) { - error = TRUE; - return error; - } - - wait_ms(100); - // Checking whether phy reset completed successfully. - { - unsigned short phyreset; - phyreset = 0; - smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); - if (phyreset & (1 << 15)) { - error = TRUE; - return error; - } - } - - /* Advertise capabilities */ - smsc9220_advertise_cap(); - - - /* Begin to establish link */ - smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing. - // Although it's not so in the manual. - - /* Interrupt threshold */ - SMSC9220->FIFO_INT = 0xFF000000; - - smsc9220_enable_mac_xmit(); - - smsc9220_enable_xmit(); - - SMSC9220->RX_CFG = 0; - - smsc9220_enable_mac_recv(); - - // Rx status FIFO level irq threshold - SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles - - // This sleep is compulsory otherwise txmit/receive will fail. - wait_ms(2000); - return error; - -} - -/*---------------------------------------------------------------------------- - Ethernet Device Uninitialize - *----------------------------------------------------------------------------*/ -void ethernet_free() -{ -} - -int ethernet_write(const char *data, int size) -{ - return 0; -} - -int ethernet_send() -{ - return 0; -} - -int ethernet_receive() -{ - return 0; -} - -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is -// possible to read bytes from this packet. -// Read will write up to size bytes into data. -// It is possible to use read multible times. -// Each time read will start reading after the last read byte before. - -int ethernet_read(char *data, int dlen) -{ - return 0; -} - -void ethernet_address(char *mac) -{ - mbed_mac_address(mac); -} - -int ethernet_link(void) -{ - return 0; -} - -void ethernet_set_link(int speed, int duplex) -{ - smsc9220_establish_link(); -} -