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Initialize the I2S PLL in the system startup.

pull/8/head
Joe Turner 2013-05-31 08:49:12 +01:00
parent 9e3cd7f379
commit a3fd58bf2b
1 changed files with 16 additions and 4 deletions
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20
libraries/mbed/vendor/STM/cmsis/STM32F407/system_stm32f4xx.c vendored
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@ -56,9 +56,9 @@
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
* HSE Frequency(Hz) | 8000000
*-----------------------------------------------------------------------------
* PLL_M | 25
* PLL_M | 8
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
@ -66,9 +66,9 @@
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
* PLLI2S_N | 271
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
* PLLI2S_R | 2
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
@ -161,6 +161,9 @@
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
#define PLLI2S_N 271
#define PLLI2S_R 2
/******************************************************************************/
/**
@ -396,6 +399,15 @@ static void SetSysClock(void)
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure the I2S PLL */
RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
/* Enable the I2S PLL */
RCC->CR |= RCC_CR_PLLI2SON;
/* Wait until the I2S PLL is ready */
while (!(RCC->CR & RCC_CR_PLLI2SRDY));
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;