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DISCO_L072CZ_LRWAN1: targets.json correction

pull/4356/head
arostm 2017-04-25 11:04:34 +02:00 committed by adbridge
parent 71505b3ca0
commit a1e78eab4c
1 changed files with 5 additions and 2 deletions
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7
targets/targets.json
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@ -1203,10 +1203,13 @@
"inherits": ["Target"],
"core": "Cortex-M0+",
"default_toolchain": "ARM",
"extra_labels": ["STM", "STM32L0", "STM32L072CZ"],
"extra_labels": ["STM", "STM32L0", "STM32L072CZ", "STM32L072xx"],
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"supported_form_factors": ["ARDUINO", "MORPHO"],
"macros": ["RTC_LSI=1"],
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"], "release_versions": ["2", "5"],
"detect_code": ["0833"],
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
"release_versions": ["2", "5"],
"device_name": "STM32L072CZ"
},
"DISCO_F746NG": {