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Merge pull request #3227 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.2.2
pull/3293/head mbed-os-5.2.2
Martin Kojtal 2016-11-08 16:02:35 +00:00 committed by GitHub
parent e2617cc0e1 639bd4fa28
commit a1c0840b3d
616 changed files with 127189 additions and 2236 deletions
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5
.travis.yml
View File

@ -7,6 +7,7 @@ script:
- python tools/test/pylint.py
- py.test tools/test/toolchains/api.py
- python tools/test/memap/memap_test.py
- python tools/project.py -S
- python tools/build_travis.py
before_install:
- sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded
@ -16,9 +17,7 @@ before_install:
- arm-none-eabi-gcc --version
- python --version
install:
- sudo pip install colorama
- sudo pip install prettytable
- sudo pip install jinja2
- sudo pip install -r requirements.txt
- sudo pip install pytest
- sudo pip install pylint
- sudo pip install hypothesis

4
TESTS/mbed_drivers/lp_timeout/main.cpp
View File

@ -118,7 +118,7 @@ void lp_timeout_500us(void)
}
status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
@ -134,7 +134,7 @@ Case cases[] = {
#endif /* DEVICE_SLEEP */
};
status_t greentea_test_setup(const size_t number_of_cases) {
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}

4
TESTS/mbed_hal/lp_ticker/main.cpp
View File

@ -133,7 +133,7 @@ void lp_ticker_5s(void)
lp_ticker_delay_us(5000000, LONG_TIMEOUT);
}
status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
@ -149,7 +149,7 @@ Case cases[] = {
#endif /* DEVICE_SLEEP */
};
status_t greentea_test_setup(const size_t number_of_cases) {
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "default_auto");
lp_ticker_data->interface->init();
return greentea_test_setup_handler(number_of_cases);

9
TESTS/mbedmicro-mbed/cpp/main.cpp
View File

@ -9,8 +9,10 @@ private:
const int pattern;
public:
Test(const char* _name) : name(_name), pattern(PATTERN_CHECK_VALUE) {
print("init");
Test(const char* _name, bool print_message=true) : name(_name), pattern(PATTERN_CHECK_VALUE) {
if (print_message) {
print("init");
}
}
void print(const char *message) {
@ -39,7 +41,7 @@ public:
};
/* Check C++ startup initialisation */
Test s("Static");
Test s("Static", false);
/* EXPECTED OUTPUT:
*******************
@ -59,6 +61,7 @@ int main (void) {
bool result = true;
for (;;)
{
s.print("init");
// Global stack object simple test
s.stack_test();
if (s.check_init() == false)

2
TESTS/mbedmicro-rtos-mbed/threads/main.cpp
View File

@ -25,6 +25,8 @@
#define STACK_SIZE 512
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#elif defined(TARGET_HI2110)
#define STACK_SIZE 512
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif

60
docs/exporters.md Normal file
View File

@ -0,0 +1,60 @@
# About the exporters
The mbed exporters are used to export your code to various 3rd party tools and IDEs. Each exporter implements a `generate` function that produces an IDE specific project file. Exporters benefit from [mbed build tools](https://github.com/ARMmbed/mbed-os/blob/master/docs/BUILDING.md#build-mbed-sdk-library-from-sources). However, instead of using your source and [config data](https://github.com/ARMmbed/mbed-os/blob/master/docs/config_system.md) to create an executable, we use that information to populate an IDE project file that will be configured to build, flash, and debug your code. You can find exporter implementations [here](https://github.com/ARMmbed/mbed-os/tree/master/tools/export).
## mbed-cli command
`mbed export -m [target] -i [IDE]`
# Adding export support for a target
If you have added new target to the mbed SDK, exporting will allow users to transition from mbed source code to the offline development environment of their choice. This functionality activates the use of your device for larger number of users.
## Eclipse and Make
Eclipse project export utilizes a generated Makefile for building. Other than target configuration within the [config system](https://github.com/ARMmbed/mbed-os/blob/master/docs/mbed_targets.md) for mbed build system support, there is no additional work to provide Make export.
### Available mbed-cli commands
`mbed export -m [target] -i [make_gcc_arm, make_iar, make_armc5, eclipse_gcc_arm, eclipse_iar, eclipse_armc5]`
## UVision and IAR
### CMSIS Packs
UVision and IAR both utilize [CMSIS packs](http://www.keil.com/pack/doc/CMSIS/Pack/html/index.html) to find target information necessary to create a valid project file.
We utilize the tool [ArmPackManager](https://github.com/ARMmbed/mbed-os/tree/master/tools/arm_pack_manager) to scrape [MDK5 Software Packs](https://www.keil.com/dd2/Pack/) for target information. This is achieved by parsing [http://www.keil.com/pack/index.idx](http://sadevicepacksprod.blob.core.windows.net/idxfile/index.idx). The relevant information in the [PDSC (Pack Description)](http://www.keil.com/pack/doc/CMSIS/Pack/html/_pack_format.html) retrieved from each URL in the index is stored in [index.json](https://github.com/ARMmbed/mbed-os/blob/master/tools/arm_pack_manager/index.json). A `.pdsc` file typically describes a family of devices. Each device is uniquely identified by its [device name](https://github.com/ARMmbed/mbed-os/blob/master/docs/mbed_targets.md#device_name). Thus, this name makes a natural key to associate a device with its information in `index.json`.
#### What's in a device name?
There is no reliable way to map an mbed alias like [NUCLEO_F030R8](https://github.com/ARMmbed/mbed-os/blob/master/targets/targets.json#L603) to its unique identifier, [STM32F030R8](https://github.com/ARMmbed/mbed-os/blob/master/targets/targets.json#L615), as it is listed in a CMSIS pack (and subsequently `index.json`). So, we added a [device name](https://github.com/ARMmbed/mbed-os/blob/master/docs/mbed_targets.md#device_name) field in `targets.json`. **This field is required for IAR or UVision exporter support**.
#### Code Usage
http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc is the PDSC that contains TEENSY_31 device (MK20DX256xxx7). It has been parsed by ArmPackManager and stored in `index.json`. The device information begins on line 156:
```xml
<device Dname="MK20DX256xxx7">
<processor Dfpu="0" Dmpu="0" Dendian="Little-endian" Dclock="72000000"/>
<compile header="Device\Include\MK20D7.h" define="MK20DX256xxx7"/>
<debug svd="SVD\MK20D7.svd"/>
<memory id="IROM1" start="0x00000000" size="0x40000" startup="1" default="1"/>
<memory id="IROM2" start="0x10000000" size="0x8000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x8000" init ="0" default="1"/>
<memory id="IRAM2" start="0x1FFF8000" size="0x8000" init ="0" default="0"/>
<algorithm name="Flash\MK_P256.FLM" start="0x00000000" size="0x40000" default="1"/>
<algorithm name="Flash\MK_D32_72MHZ.FLM" start="0x10000000" size="0x8000" default="1"/>
<book name="Documents\K20P100M72SF1RM.pdf" title="MK20DX256xxx7 Reference Manual"/>
<book name="Documents\K20P100M72SF1.pdf" title="MK20DX256xxx7 Data Sheet"/>
</device>
```
##### Uvision
The dname (device name) field on line 156 directly corresponds to that in the Uvision5 IDE target selection window. [`tools/export/uvision/uvision.tmpl`](https://github.com/ARMmbed/mbed-os/blob/master/tools/export/uvision/uvision.tmpl#L15), uses target information from these packs is used to generate valid Uvision5 projects. If the device name is not found, we use a generic ARM CPU target in Uvision5.
##### IAR
[`tools/export/iar/iar_definitions.json`](https://github.com/ARMmbed/mbed-os/blob/master/tools/export/iar/iar_definitions.json) utilizes this device name to store information necessary to set the target in an IAR project.

3
docs/mbed_targets.md
View File

@ -164,6 +164,5 @@ The hook code can look quite different between different targets. Take a look at
This property is used to pass necessary data for exporting the mbed code to various 3rd party tools and IDEs.
This is possible because the device name corresponds to a field in publicly hosted CMSIS packs. These packs hold target properties. [This](http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc) is the pdsc that contains TEENSY_31 device (MK20DX256xxx7). The device information begins on line 156. The dname (device name) field on line 156 directly corresponds to that in the Uvision5 IDE target selection window. Beginning on line 15 of `tools/export/uvision/uvision.tmpl`, target information from these packs is used to generate valid Uvision5 projects. If the device name is not found, we use a generic ARM CPU target in Uvision5.
`tools/export/iar/iar_definitions.json` utilizes this device name to store information necessary to set the target in an IAR project.
Please see [exporters.md](exporters.md) for information about this field.

4
docs/testing_mbed_OS_5.md
View File

@ -78,7 +78,9 @@ The full build process is:
When building an mbed application, the presence of a `mbed_app.json` file allows you to set or override different config settings from libraries and targets. However, because the tests share a common build, this can cause issues when tests have different configurations that affect the OS.
If you need to use app config, this must be set via the `--app-config` option when calling `mbed test`. **If this option is not specified, the build system will ignore all `mbed_app.json` files and use the default config values.**
The build system will look for an `mbed_app.json` file in your shared project files (any directory not inside of a `TESTS` folder). If this is found, this configuration file will be used for both the non-test code as well as each test case inside your project's source tree. If there is more than one `mbed_app.json` files in the source tree, the config system will error.
If you need to test with multiple configurations, then you can use the `--app-config` option. This will override the search for an `mbed_app.json` file and use the config file you specify for the build.
### Running tests

14
features/FEATURE_LWIP/lwip-interface/EthernetInterface.cpp
View File

@ -24,22 +24,22 @@ EthernetInterface::EthernetInterface()
{
}
int EthernetInterface::set_network(const char *ip_address, const char *netmask, const char *gateway)
nsapi_error_t EthernetInterface::set_network(const char *ip_address, const char *netmask, const char *gateway)
{
_dhcp = false;
strncpy(_ip_address, ip_address ? ip_address : "", sizeof(_ip_address));
strncpy(_netmask, netmask ? netmask : "", sizeof(_netmask));
strncpy(_gateway, gateway ? gateway : "", sizeof(_gateway));
return 0;
return NSAPI_ERROR_OK;
}
int EthernetInterface::set_dhcp(bool dhcp)
nsapi_error_t EthernetInterface::set_dhcp(bool dhcp)
{
_dhcp = dhcp;
return 0;
return NSAPI_ERROR_OK;
}
int EthernetInterface::connect()
nsapi_error_t EthernetInterface::connect()
{
return mbed_lwip_bringup(_dhcp,
_ip_address[0] ? _ip_address : 0,
@ -47,7 +47,7 @@ int EthernetInterface::connect()
_gateway[0] ? _gateway : 0);
}
int EthernetInterface::disconnect()
nsapi_error_t EthernetInterface::disconnect()
{
return mbed_lwip_bringdown();
}
@ -63,7 +63,7 @@ const char *EthernetInterface::get_ip_address()
return _ip_address;
}
return 0;
return NULL;
}
const char *EthernetInterface::get_netmask()

9
features/FEATURE_LWIP/lwip-interface/EthernetInterface.h
View File

@ -46,7 +46,8 @@ public:
* @param gateway Null-terminated representation of the local gateway
* @return 0 on success, negative error code on failure
*/
virtual int set_network(const char *ip_address, const char *netmask, const char *gateway);
virtual nsapi_error_t set_network(
const char *ip_address, const char *netmask, const char *gateway);
/** Enable or disable DHCP on the network
*
@ -55,17 +56,17 @@ public:
* @param dhcp False to disable dhcp (defaults to enabled)
* @return 0 on success, negative error code on failure
*/
virtual int set_dhcp(bool dhcp);
virtual nsapi_error_t set_dhcp(bool dhcp);
/** Start the interface
* @return 0 on success, negative on failure
*/
virtual int connect();
virtual nsapi_error_t connect();
/** Stop the interface
* @return 0 on success, negative on failure
*/
virtual int disconnect();
virtual nsapi_error_t disconnect();
/** Get the local MAC address
*

5
features/FEATURE_LWIP/lwip-interface/emac_stack_lwip.cpp
View File

@ -47,6 +47,11 @@ void emac_stack_mem_free(emac_stack_t* stack, emac_stack_mem_t *mem)
pbuf_free((struct pbuf*)mem);
}
void emac_stack_mem_copy(emac_stack_t* stack, emac_stack_mem_t *to, emac_stack_mem_t *from)
{
pbuf_copy((struct pbuf*)to, (struct pbuf*)from);
}
void *emac_stack_mem_ptr(emac_stack_t* stack, emac_stack_mem_t *mem)
{
return ((struct pbuf*)mem)->payload;

24
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/k64f_emac.c
View File

@ -102,24 +102,22 @@ static void update_read_buffer(uint8_t *buf)
*/
static void k64f_tx_reclaim(struct k64f_enetdata *k64f_enet)
{
uint8_t i = 0 ;
/* Get exclusive access */
sys_mutex_lock(&k64f_enet->TXLockMutex);
i = k64f_enet->tx_consume_index;
// Traverse all descriptors, looking for the ones modified by the uDMA
while((i != k64f_enet->tx_produce_index) && (!(g_handle.txBdDirty->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK))) {
pbuf_free(tx_buff[i]);
while((k64f_enet->tx_consume_index != k64f_enet->tx_produce_index) &&
(!(g_handle.txBdDirty->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK))) {
pbuf_free(tx_buff[k64f_enet->tx_consume_index % ENET_TX_RING_LEN]);
if (g_handle.txBdDirty->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
g_handle.txBdDirty = g_handle.txBdBase;
else
g_handle.txBdDirty++;
i = (i + 1) % ENET_TX_RING_LEN;
k64f_enet->tx_consume_index += 1;
osSemaphoreRelease(k64f_enet->xTXDCountSem.id);
}
k64f_enet->tx_consume_index = i;
/* Restore access */
sys_mutex_unlock(&k64f_enet->TXLockMutex);
}
@ -524,17 +522,17 @@ static err_t k64f_low_level_output(struct netif *netif, struct pbuf *p)
dst += q->len;
}
/* Wait until a descriptor is available for the transfer. */
/* THIS WILL BLOCK UNTIL THERE ARE A DESCRIPTOR AVAILABLE */
while (g_handle.txBdCurrent->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
osSemaphoreWait(k64f_enet->xTXDCountSem.id, osWaitForever);
/* Check if a descriptor is available for the transfer. */
int32_t count = osSemaphoreWait(k64f_enet->xTXDCountSem.id, 0);
if (count < 1)
return ERR_BUF;
/* Get exclusive access */
sys_mutex_lock(&k64f_enet->TXLockMutex);
/* Save the buffer so that it can be freed when transmit is done */
tx_buff[k64f_enet->tx_produce_index] = temp_pbuf;
k64f_enet->tx_produce_index = (k64f_enet->tx_produce_index + 1) % ENET_TX_RING_LEN;
tx_buff[k64f_enet->tx_produce_index % ENET_TX_RING_LEN] = temp_pbuf;
k64f_enet->tx_produce_index += 1;
/* Setup transfers */
g_handle.txBdCurrent->buffer = psend;

7
features/FEATURE_LWIP/lwip-interface/lwip-sys/arch/cc.h
View File

@ -54,7 +54,12 @@ typedef uintptr_t mem_ptr_t;
#define SZT_F "uz"
/* ARM/LPC17xx is little endian only */
#if !defined(BYTE_ORDER) || (BYTE_ORDER != LITTLE_ENDIAN && BYTE_ORDER != BIG_ENDIAN)
#ifdef BYTE_ORDER
#undef BYTE_ORDER
#endif
#define BYTE_ORDER LITTLE_ENDIAN
#endif
/* Use LWIP error codes */
#define LWIP_PROVIDE_ERRNO
@ -92,7 +97,7 @@ typedef uintptr_t mem_ptr_t;
#define LWIP_CHKSUM_ALGORITHM 0
void* thumb2_memcpy(void* pDest, const void* pSource, size_t length);
u16_t thumb2_checksum(void* pData, int length);
u16_t thumb2_checksum(const void* pData, int length);
#else
/* Used with IP headers only */
#define LWIP_CHKSUM_ALGORITHM 1

1
features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_pbuf.c
View File

@ -1179,6 +1179,7 @@ pbuf_coalesce(struct pbuf *p, pbuf_layer layer)
return p;
}
err = pbuf_copy(q, p);
LWIP_UNUSED_ARG(err);
LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
pbuf_free(p);
return q;

40
features/FEATURE_LWIP/lwip-interface/lwip_stack.c
View File

@ -326,7 +326,7 @@ const char *mbed_lwip_get_mac_address(void)
return lwip_mac_address[0] ? lwip_mac_address : 0;
}
char *mbed_lwip_get_ip_address(char *buf, int buflen)
char *mbed_lwip_get_ip_address(char *buf, nsapi_size_t buflen)
{
const ip_addr_t *addr = mbed_lwip_get_ip_addr(true, &lwip_netif);
if (!addr) {
@ -345,7 +345,7 @@ char *mbed_lwip_get_ip_address(char *buf, int buflen)
return NULL;
}
const char *mbed_lwip_get_netmask(char *buf, int buflen)
const char *mbed_lwip_get_netmask(char *buf, nsapi_size_t buflen)
{
#if LWIP_IPV4
const ip4_addr_t *addr = netif_ip4_netmask(&lwip_netif);
@ -359,7 +359,7 @@ const char *mbed_lwip_get_netmask(char *buf, int buflen)
#endif
}
char *mbed_lwip_get_gateway(char *buf, int buflen)
char *mbed_lwip_get_gateway(char *buf, nsapi_size_t buflen)
{
#if LWIP_IPV4
const ip4_addr_t *addr = netif_ip4_gw(&lwip_netif);
@ -373,7 +373,7 @@ char *mbed_lwip_get_gateway(char *buf, int buflen)
#endif
}
int mbed_lwip_init(emac_interface_t *emac)
nsapi_error_t mbed_lwip_init(emac_interface_t *emac)
{
// Check if we've already brought up lwip
if (!mbed_lwip_get_mac_address()) {
@ -409,7 +409,7 @@ int mbed_lwip_init(emac_interface_t *emac)
return NSAPI_ERROR_OK;
}
int mbed_lwip_bringup(bool dhcp, const char *ip, const char *netmask, const char *gw)
nsapi_error_t mbed_lwip_bringup(bool dhcp, const char *ip, const char *netmask, const char *gw)
{
// Check if we've already connected
if (lwip_connected) {
@ -509,7 +509,7 @@ int mbed_lwip_bringup(bool dhcp, const char *ip, const char *netmask, const char
return 0;
}
int mbed_lwip_bringdown(void)
nsapi_error_t mbed_lwip_bringdown(void)
{
// Check if we've connected
if (!lwip_connected) {
@ -533,7 +533,7 @@ int mbed_lwip_bringdown(void)
}
/* LWIP error remapping */
static int mbed_lwip_err_remap(err_t err) {
static nsapi_error_t mbed_lwip_err_remap(err_t err) {
switch (err) {
case ERR_OK:
case ERR_CLSD:
@ -559,7 +559,7 @@ static int mbed_lwip_err_remap(err_t err) {
}
/* LWIP network stack implementation */
static int mbed_lwip_gethostbyname(nsapi_stack_t *stack, const char *host, nsapi_addr_t *addr, nsapi_version_t version)
static nsapi_error_t mbed_lwip_gethostbyname(nsapi_stack_t *stack, const char *host, nsapi_addr_t *addr, nsapi_version_t version)
{
ip_addr_t lwip_addr;
@ -600,7 +600,7 @@ static int mbed_lwip_gethostbyname(nsapi_stack_t *stack, const char *host, nsapi
return 0;
}
static int mbed_lwip_socket_open(nsapi_stack_t *stack, nsapi_socket_t *handle, nsapi_protocol_t proto)
static nsapi_error_t mbed_lwip_socket_open(nsapi_stack_t *stack, nsapi_socket_t *handle, nsapi_protocol_t proto)
{
// check if network is connected
if (!lwip_connected) {
@ -643,7 +643,7 @@ static int mbed_lwip_socket_open(nsapi_stack_t *stack, nsapi_socket_t *handle, n
return 0;
}
static int mbed_lwip_socket_close(nsapi_stack_t *stack, nsapi_socket_t handle)
static nsapi_error_t mbed_lwip_socket_close(nsapi_stack_t *stack, nsapi_socket_t handle)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
@ -652,7 +652,7 @@ static int mbed_lwip_socket_close(nsapi_stack_t *stack, nsapi_socket_t handle)
return mbed_lwip_err_remap(err);
}
static int mbed_lwip_socket_bind(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t addr, uint16_t port)
static nsapi_error_t mbed_lwip_socket_bind(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t addr, uint16_t port)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
ip_addr_t ip_addr;
@ -670,7 +670,7 @@ static int mbed_lwip_socket_bind(nsapi_stack_t *stack, nsapi_socket_t handle, ns
return mbed_lwip_err_remap(err);
}
static int mbed_lwip_socket_listen(nsapi_stack_t *stack, nsapi_socket_t handle, int backlog)
static nsapi_error_t mbed_lwip_socket_listen(nsapi_stack_t *stack, nsapi_socket_t handle, int backlog)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
@ -678,7 +678,7 @@ static int mbed_lwip_socket_listen(nsapi_stack_t *stack, nsapi_socket_t handle,
return mbed_lwip_err_remap(err);
}
static int mbed_lwip_socket_connect(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t addr, uint16_t port)
static nsapi_error_t mbed_lwip_socket_connect(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t addr, uint16_t port)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
ip_addr_t ip_addr;
@ -694,7 +694,7 @@ static int mbed_lwip_socket_connect(nsapi_stack_t *stack, nsapi_socket_t handle,
return mbed_lwip_err_remap(err);
}
static int mbed_lwip_socket_accept(nsapi_stack_t *stack, nsapi_socket_t server, nsapi_socket_t *handle, nsapi_addr_t *addr, uint16_t *port)
static nsapi_error_t mbed_lwip_socket_accept(nsapi_stack_t *stack, nsapi_socket_t server, nsapi_socket_t *handle, nsapi_addr_t *addr, uint16_t *port)
{
struct lwip_socket *s = (struct lwip_socket *)server;
struct lwip_socket *ns = mbed_lwip_arena_alloc();
@ -718,7 +718,7 @@ static int mbed_lwip_socket_accept(nsapi_stack_t *stack, nsapi_socket_t server,
return 0;
}
static int mbed_lwip_socket_send(nsapi_stack_t *stack, nsapi_socket_t handle, const void *data, unsigned size)
static nsapi_size_or_error_t mbed_lwip_socket_send(nsapi_stack_t *stack, nsapi_socket_t handle, const void *data, nsapi_size_t size)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
size_t bytes_written = 0;
@ -728,10 +728,10 @@ static int mbed_lwip_socket_send(nsapi_stack_t *stack, nsapi_socket_t handle, co
return mbed_lwip_err_remap(err);
}
return (int)bytes_written;
return (nsapi_size_or_error_t)bytes_written;
}
static int mbed_lwip_socket_recv(nsapi_stack_t *stack, nsapi_socket_t handle, void *data, unsigned size)
static nsapi_size_or_error_t mbed_lwip_socket_recv(nsapi_stack_t *stack, nsapi_socket_t handle, void *data, nsapi_size_t size)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
@ -755,7 +755,7 @@ static int mbed_lwip_socket_recv(nsapi_stack_t *stack, nsapi_socket_t handle, vo
return recv;
}
static int mbed_lwip_socket_sendto(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t addr, uint16_t port, const void *data, unsigned size)
static nsapi_size_or_error_t mbed_lwip_socket_sendto(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t addr, uint16_t port, const void *data, nsapi_size_t size)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
ip_addr_t ip_addr;
@ -780,7 +780,7 @@ static int mbed_lwip_socket_sendto(nsapi_stack_t *stack, nsapi_socket_t handle,
return size;
}
static int mbed_lwip_socket_recvfrom(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t *addr, uint16_t *port, void *data, unsigned size)
static nsapi_size_or_error_t mbed_lwip_socket_recvfrom(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t *addr, uint16_t *port, void *data, nsapi_size_t size)
{
struct lwip_socket *s = (struct lwip_socket *)handle;
struct netbuf *buf;
@ -799,7 +799,7 @@ static int mbed_lwip_socket_recvfrom(nsapi_stack_t *stack, nsapi_socket_t handle
return recv;
}
static int mbed_lwip_setsockopt(nsapi_stack_t *stack, nsapi_socket_t handle, int level, int optname, const void *optval, unsigned optlen)
static nsapi_error_t mbed_lwip_setsockopt(nsapi_stack_t *stack, nsapi_socket_t handle, int level, int optname, const void *optval, unsigned optlen)
{
struct lwip_socket *s = (struct lwip_socket *)handle;

6
features/FEATURE_LWIP/lwip-interface/lwip_stack.h
View File

@ -25,9 +25,9 @@ extern "C" {
#endif
// Access to lwip through the nsapi
int mbed_lwip_init(emac_interface_t *emac);
int mbed_lwip_bringup(bool dhcp, const char *ip, const char *netmask, const char *gw);
int mbed_lwip_bringdown(void);
nsapi_error_t mbed_lwip_init(emac_interface_t *emac);
nsapi_error_t mbed_lwip_bringup(bool dhcp, const char *ip, const char *netmask, const char *gw);
nsapi_error_t mbed_lwip_bringdown(void);
const char *mbed_lwip_get_mac_address(void);
char *mbed_lwip_get_ip_address(char *buf, int buflen);

42
features/FEATURE_LWIP/lwip-interface/lwipopts.h
View File

@ -105,12 +105,54 @@
#define LWIP_RAM_HEAP_POINTER lwip_ram_heap
// Number of pool pbufs.
// Each requires 684 bytes of RAM.
#ifndef PBUF_POOL_SIZE
#define PBUF_POOL_SIZE 5
#endif
// One tcp_pcb_listen is needed for each TCPServer.
// Each requires 72 bytes of RAM.
#ifdef MBED_CONF_LWIP_TCP_SERVER_MAX
#define MEMP_NUM_TCP_PCB_LISTEN MBED_CONF_LWIP_TCP_SERVER_MAX
#else
#define MEMP_NUM_TCP_PCB_LISTEN 4
#endif
// One is tcp_pcb needed for each TCPSocket.
// Each requires 196 bytes of RAM.
#ifdef MBED_CONF_LWIP_TCP_SOCKET_MAX
#define MEMP_NUM_TCP_PCB MBED_CONF_LWIP_TCP_SOCKET_MAX
#else
#define MEMP_NUM_TCP_PCB 4
#endif
// One udp_pcb is needed for each UDPSocket.
// Each requires 84 bytes of RAM (total rounded to multiple of 512).
#ifdef MBED_CONF_LWIP_UDP_SOCKET_MAX
#define MEMP_NUM_UDP_PCB MBED_CONF_LWIP_UDP_SOCKET_MAX
#else
#define MEMP_NUM_UDP_PCB 4
#endif
// Number of non-pool pbufs.
// Each requires 92 bytes of RAM.
#ifndef MEMP_NUM_PBUF
#define MEMP_NUM_PBUF 8
#endif
// Each netbuf requires 64 bytes of RAM.
#ifndef MEMP_NUM_NETBUF
#define MEMP_NUM_NETBUF 8
#endif
// One netconn is needed for each UDPSocket, TCPSocket or TCPServer.
// Each requires 236 bytes of RAM (total rounded to multiple of 512).
#ifdef MBED_CONF_LWIP_SOCKET_MAX
#define MEMP_NUM_NETCONN MBED_CONF_LWIP_SOCKET_MAX
#else
#define MEMP_NUM_NETCONN 4
#endif
#define TCP_QUEUE_OOSEQ 0
#define TCP_OVERSIZE 0

16
features/FEATURE_LWIP/lwip-interface/mbed_lib.json
View File

@ -16,6 +16,22 @@
"addr-timeout": {
"help": "On dual stack system how long to wait preferred stack's address in seconds",
"value": 5
},
"socket-max": {
"help": "Maximum number of open TCPServer, TCPSocket and UDPSocket instances allowed, including one used internally for DNS. Each requires 236 bytes of pre-allocated RAM",
"value": 4
},
"tcp-server-max": {
"help": "Maximum number of open TCPServer instances allowed. Each requires 72 bytes of pre-allocated RAM",
"value": 4
},
"tcp-socket-max": {
"help": "Maximum number of open TCPSocket instances allowed. Each requires 196 bytes of pre-allocated RAM",
"value": 4
},
"udp-socket-max": {
"help": "Maximum number of open UDPSocket instances allowed, including one used internally for DNS. Each requires 84 bytes of pre-allocated RAM",
"value": 4
}
}
}

2
features/frameworks/greentea-client/source/test_env.cpp
View File

@ -533,7 +533,7 @@ enum Token {
*
*/
static int _get_char() {
return getchar();
return greentea_serial->getc();
}
/**

1
features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md
View File

@ -54,6 +54,7 @@ An example of the configuration file:
| 6lowpan-nd-channel-mask | number [0-0x07fff800] | Channel mask, bit-mask of channels to use |
| 6lowpan-nd-channel-page | number [0, 2] | 0 for 2,4 GHz and 2 for sub-GHz radios |
| 6lowpan-nd-channel | number [0-27] | RF channel to use when `channel_mask` is not defined |
| 6lowpan-nd-panid-filter | number [0-0xffff] | Beacon PAN ID filter, 0xffff means no filtering |
| 6lowpan-nd-security-mode | "NONE" or "PSK" | To use either no security, or Pre shared network key |
| 6lowpan-nd-psk-key-id | number | PSK key id when PSK is enabled |
| 6lowpan-nd-psk-key | byte array [16] | Pre shared network key |

1
features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json
View File

@ -5,6 +5,7 @@
"6lowpan-nd-channel-mask": "(1<<12)",
"6lowpan-nd-channel-page": 0,
"6lowpan-nd-channel": 12,
"6lowpan-nd-panid-filter": "0xffff",
"6lowpan-nd-security-mode": "NONE",
"6lowpan-nd-psk-key-id": 1,
"6lowpan-nd-psk-key": "{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf}",

6
features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/include/static_config.h
View File

@ -100,6 +100,12 @@ extern "C" {
#define MBED_MESH_API_6LOWPAN_ND_SEC_LEVEL 5
#endif
#if defined MBED_CONF_MBED_MESH_API_6LOWPAN_ND_PANID_FILTER
#define MBED_MESH_API_6LOWPAN_ND_PANID_FILTER MBED_CONF_MBED_MESH_API_6LOWPAN_ND_PANID_FILTER
#else
#define MBED_MESH_API_6LOWPAN_ND_PANID_FILTER 0xffff
#endif
/* Thread configuration */
// PSKd, must be longer than 6
#ifdef YOTTA_CFG_MBED_MESH_API_THREAD_PSKD

4
features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c
View File

@ -263,6 +263,10 @@ void nd_tasklet_configure_and_connect_to_network(void)
arm_nwk_6lowpan_link_nwk_id_filter_for_nwk_scan(
tasklet_data_ptr->network_interface_id, NULL);
arm_nwk_6lowpan_link_panid_filter_for_nwk_scan(
tasklet_data_ptr->network_interface_id,
MBED_MESH_API_6LOWPAN_ND_PANID_FILTER);
status = arm_nwk_interface_up(tasklet_data_ptr->network_interface_id);
if (status >= 0) {
tasklet_data_ptr->tasklet_state = TASKLET_STATE_BOOTSTRAP_STARTED;

87
features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp
View File

@ -28,7 +28,6 @@
#include "mesh_system.h" // from inside mbed-mesh-api
#include "socket_api.h"
#include "net_interface.h"
#include "ip6string.h"
// Uncomment to enable trace
//#define HAVE_DEBUG
#include "ns_trace.h"
@ -110,7 +109,7 @@ private:
static NanostackSocket * socket_tbl[NS_INTERFACE_SOCKETS_MAX];
static int map_mesh_error(mesh_error_t err)
static nsapi_error_t map_mesh_error(mesh_error_t err)
{
switch (err) {
case MESH_ERROR_NONE: return 0;
@ -126,16 +125,13 @@ static void convert_mbed_addr_to_ns(ns_address_t *ns_addr,
{
ns_addr->type = ADDRESS_IPV6;
ns_addr->identifier = s_addr->get_port();
const char *str = s_addr->get_ip_address();
stoip6(str, strlen(str), ns_addr->address);
memcpy(ns_addr->address, s_addr->get_ip_bytes(), 16);
}
static void convert_ns_addr_to_mbed(SocketAddress *s_addr, const ns_address_t *ns_addr)
{
char str[40];
ip6tos(ns_addr->address, str);
s_addr->set_port(ns_addr->identifier);
s_addr->set_ip_address(str);
s_addr->set_ip_bytes(ns_addr->address, NSAPI_IPv6);
}
void* NanostackSocket::operator new(std::size_t sz) {
@ -167,7 +163,7 @@ NanostackSocket::~NanostackSocket()
close();
}
if (socket_id >= 0) {
int ret = socket_free(socket_id);
nsapi_error_t ret = socket_free(socket_id);
MBED_ASSERT(0 == ret);
MBED_ASSERT(socket_tbl[socket_id] == this);
socket_tbl[socket_id] = NULL;
@ -209,7 +205,7 @@ void NanostackSocket::close()
MBED_ASSERT(mode != SOCKET_MODE_CLOSED);
if (socket_id >= 0) {
int ret = socket_close(socket_id, (addr_valid ? &ns_address : NULL));
nsapi_error_t ret = socket_close(socket_id, (addr_valid ? &ns_address : NULL));
MBED_ASSERT(0 == ret);
} else {
MBED_ASSERT(SOCKET_MODE_UNOPENED == mode);
@ -466,7 +462,7 @@ MeshInterfaceNanostack::MeshInterfaceNanostack(NanostackRfPhy *phy)
// Nothing to do
}
int MeshInterfaceNanostack::initialize(NanostackRfPhy *phy)
nsapi_error_t MeshInterfaceNanostack::initialize(NanostackRfPhy *phy)
{
if (this->phy != NULL) {
error("Phy already set");
@ -486,7 +482,7 @@ void MeshInterfaceNanostack::mesh_network_handler(mesh_connection_status_t statu
nanostack_unlock();
}
int MeshInterfaceNanostack::register_rf()
nsapi_error_t MeshInterfaceNanostack::register_rf()
{
nanostack_lock();
@ -504,7 +500,7 @@ int MeshInterfaceNanostack::register_rf()
return 0;
}
int MeshInterfaceNanostack::actual_connect()
nsapi_error_t MeshInterfaceNanostack::actual_connect()
{
nanostack_assert_locked();
@ -532,7 +528,7 @@ NetworkStack * MeshInterfaceNanostack::get_stack()
return NanostackInterface::get_stack();
}
int MeshInterfaceNanostack::disconnect()
nsapi_error_t MeshInterfaceNanostack::disconnect()
{
nanostack_lock();
@ -562,7 +558,7 @@ const char *MeshInterfaceNanostack::get_mac_address()
return mac_addr_str;
}
int ThreadInterface::connect()
nsapi_error_t ThreadInterface::connect()
{
// initialize mesh networking resources, memory, timers, etc...
mesh_system_init();
@ -586,14 +582,14 @@ int ThreadInterface::connect()
nanostack_unlock();
return map_mesh_error(status);
}
int ret = this->actual_connect();
nsapi_error_t ret = this->actual_connect();
nanostack_unlock();
return ret;
}
int LoWPANNDInterface::connect()
nsapi_error_t LoWPANNDInterface::connect()
{
// initialize mesh networking resources, memory, timers, etc...
mesh_system_init();
@ -617,7 +613,7 @@ int LoWPANNDInterface::connect()
nanostack_unlock();
return map_mesh_error(status);
}
int ret = this->actual_connect();
nsapi_error_t ret = this->actual_connect();
nanostack_unlock();
@ -646,7 +642,7 @@ const char * NanostackInterface::get_ip_address()
return NULL;
}
int NanostackInterface::socket_open(void **handle, nsapi_protocol_t protocol)
nsapi_error_t NanostackInterface::socket_open(void **handle, nsapi_protocol_t protocol)
{
// Validate parameters
if (NULL == handle) {
@ -687,7 +683,7 @@ int NanostackInterface::socket_open(void **handle, nsapi_protocol_t protocol)
return 0;
}
int NanostackInterface::socket_close(void *handle)
nsapi_error_t NanostackInterface::socket_close(void *handle)
{
// Validate parameters
NanostackSocket * socket = static_cast<NanostackSocket *>(handle);
@ -707,7 +703,7 @@ int NanostackInterface::socket_close(void *handle)
}
int NanostackInterface::socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned int size)
nsapi_size_or_error_t NanostackInterface::socket_sendto(void *handle, const SocketAddress &address, const void *data, nsapi_size_t size)
{
// Validate parameters
NanostackSocket * socket = static_cast<NanostackSocket *>(handle);
@ -716,9 +712,13 @@ int NanostackInterface::socket_sendto(void *handle, const SocketAddress &address
return NSAPI_ERROR_NO_SOCKET;
}
if (address.get_ip_version() != NSAPI_IPv6) {
return NSAPI_ERROR_UNSUPPORTED;
}
nanostack_lock();
int ret;
nsapi_size_or_error_t ret;
if (socket->closed()) {
ret = NSAPI_ERROR_NO_CONNECTION;
} else if (NANOSTACK_SOCKET_TCP == socket->proto) {
@ -758,7 +758,7 @@ int NanostackInterface::socket_sendto(void *handle, const SocketAddress &address
return ret;
}
int NanostackInterface::socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size)
nsapi_size_or_error_t NanostackInterface::socket_recvfrom(void *handle, SocketAddress *address, void *buffer, nsapi_size_t size)
{
// Validate parameters
NanostackSocket * socket = static_cast<NanostackSocket *>(handle);
@ -777,7 +777,7 @@ int NanostackInterface::socket_recvfrom(void *handle, SocketAddress *address, vo
nanostack_lock();
int ret;
nsapi_size_or_error_t ret;
if (socket->closed()) {
ret = NSAPI_ERROR_NO_CONNECTION;
} else if (NANOSTACK_SOCKET_TCP == socket->proto) {
@ -796,7 +796,7 @@ int NanostackInterface::socket_recvfrom(void *handle, SocketAddress *address, vo
return ret;
}
int NanostackInterface::socket_bind(void *handle, const SocketAddress &address)
nsapi_error_t NanostackInterface::socket_bind(void *handle, const SocketAddress &address)
{
// Validate parameters
NanostackSocket * socket = static_cast<NanostackSocket *>(handle);
@ -805,14 +805,25 @@ int NanostackInterface::socket_bind(void *handle, const SocketAddress &address)
return NSAPI_ERROR_NO_SOCKET;
}
const void *addr_field;
switch (address.get_ip_version()) {
case NSAPI_IPv6:
addr_field = address.get_ip_bytes();
break;
case NSAPI_UNSPEC:
addr_field = &ns_in6addr_any;
break;
default:
return NSAPI_ERROR_UNSUPPORTED;
}
nanostack_lock();
ns_address_t ns_address;
ns_address.type = ADDRESS_IPV6;
memset(ns_address.address, 0, sizeof ns_address.address);
memcpy(ns_address.address, addr_field, sizeof ns_address.address);
ns_address.identifier = address.get_port();
int ret = NSAPI_ERROR_DEVICE_ERROR;
nsapi_error_t ret = NSAPI_ERROR_DEVICE_ERROR;
if (0 == ::socket_bind(socket->socket_id, &ns_address)) {
socket->set_bound();
ret = 0;
@ -825,22 +836,22 @@ int NanostackInterface::socket_bind(void *handle, const SocketAddress &address)
return ret;
}
int NanostackInterface::setsockopt(void *handle, int level, int optname, const void *optval, unsigned optlen)
nsapi_error_t NanostackInterface::setsockopt(void *handle, int level, int optname, const void *optval, unsigned optlen)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NanostackInterface::getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen)
nsapi_error_t NanostackInterface::getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NanostackInterface::socket_listen(void *handle, int backlog)
nsapi_error_t NanostackInterface::socket_listen(void *handle, int backlog)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NanostackInterface::socket_connect(void *handle, const SocketAddress &addr)
nsapi_error_t NanostackInterface::socket_connect(void *handle, const SocketAddress &addr)
{
// Validate parameters
NanostackSocket * socket = static_cast<NanostackSocket *>(handle);
@ -849,9 +860,13 @@ int NanostackInterface::socket_connect(void *handle, const SocketAddress &addr)
return NSAPI_ERROR_NO_SOCKET;
}
if (addr.get_ip_version() != NSAPI_IPv6) {
return NSAPI_ERROR_UNSUPPORTED;
}
nanostack_lock();
int ret;
nsapi_error_t ret;
ns_address_t ns_addr;
int random_port = socket->is_bound() ? 0 : 1;
convert_mbed_addr_to_ns(&ns_addr, &addr);
@ -869,12 +884,12 @@ int NanostackInterface::socket_connect(void *handle, const SocketAddress &addr)
return ret;
}
int NanostackInterface::socket_accept(void *server, void **handle, SocketAddress *address)
nsapi_error_t NanostackInterface::socket_accept(void *server, void **handle, SocketAddress *address)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NanostackInterface::socket_send(void *handle, const void *p, unsigned size)
nsapi_size_or_error_t NanostackInterface::socket_send(void *handle, const void *p, nsapi_size_t size)
{
// Validate parameters
NanostackSocket * socket = static_cast<NanostackSocket *>(handle);
@ -885,7 +900,7 @@ int NanostackInterface::socket_send(void *handle, const void *p, unsigned size)
nanostack_lock();
int ret;
nsapi_size_or_error_t ret;
if (socket->closed()) {
ret = NSAPI_ERROR_NO_CONNECTION;
} else if (socket->is_connecting()) {
@ -918,7 +933,7 @@ int NanostackInterface::socket_send(void *handle, const void *p, unsigned size)
return ret;
}
int NanostackInterface::socket_recv(void *handle, void *data, unsigned size)
nsapi_size_or_error_t NanostackInterface::socket_recv(void *handle, void *data, nsapi_size_t size)
{
// Validate parameters
NanostackSocket * socket = static_cast<NanostackSocket *>(handle);
@ -929,7 +944,7 @@ int NanostackInterface::socket_recv(void *handle, void *data, unsigned size)
nanostack_lock();
int ret;
nsapi_size_or_error_t ret;
if (socket->closed()) {
ret = NSAPI_ERROR_NO_CONNECTION;
} else if (socket->data_available()) {

38
features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h
View File

@ -37,7 +37,7 @@ protected:
* @param proto Protocol of socket to open, NSAPI_TCP or NSAPI_UDP
* @return 0 on success, negative error code on failure
*/
virtual int socket_open(void **handle, nsapi_protocol_t proto);
virtual nsapi_error_t socket_open(void **handle, nsapi_protocol_t proto);
/** Close the socket
*
@ -47,7 +47,7 @@ protected:
* @param handle Socket handle
* @return 0 on success, negative error code on failure
*/
virtual int socket_close(void *handle);
virtual nsapi_error_t socket_close(void *handle);
/** Bind a specific address to a socket
*
@ -58,7 +58,7 @@ protected:
* @param address Local address to bind
* @return 0 on success, negative error code on failure.
*/
virtual int socket_bind(void *handle, const SocketAddress &address);
virtual nsapi_error_t socket_bind(void *handle, const SocketAddress &address);
/** Listen for connections on a TCP socket
*
@ -70,7 +70,7 @@ protected:
* simultaneously
* @return 0 on success, negative error code on failure
*/
virtual int socket_listen(void *handle, int backlog);
virtual nsapi_error_t socket_listen(void *handle, int backlog);
/** Connects TCP socket to a remote host
*
@ -81,7 +81,7 @@ protected:
* @param address The SocketAddress of the remote host
* @return 0 on success, negative error code on failure
*/
virtual int socket_connect(void *handle, const SocketAddress &address);
virtual nsapi_error_t socket_connect(void *handle, const SocketAddress &address);
/** Accepts a connection on a TCP socket
*
@ -101,7 +101,7 @@ protected:
* @param address Destination for the remote address or NULL
* @return 0 on success, negative error code on failure
*/
virtual int socket_accept(void *handle, void **server, SocketAddress *address);
virtual nsapi_error_t socket_accept(void *handle, void **server, SocketAddress *address);
/** Send data over a TCP socket
*
@ -117,7 +117,7 @@ protected:
* @return Number of sent bytes on success, negative error
* code on failure
*/
virtual int socket_send(void *handle, const void *data, unsigned size);
virtual nsapi_size_or_error_t socket_send(void *handle, const void *data, nsapi_size_t size);
/** Receive data over a TCP socket
*
@ -133,7 +133,7 @@ protected:
* @return Number of received bytes on success, negative error
* code on failure
*/
virtual int socket_recv(void *handle, void *data, unsigned size);
virtual nsapi_size_or_error_t socket_recv(void *handle, void *data, nsapi_size_t size);
/** Send a packet over a UDP socket
*
@ -150,7 +150,7 @@ protected:
* @return Number of sent bytes on success, negative error
* code on failure
*/
virtual int socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size);
virtual nsapi_size_or_error_t socket_sendto(void *handle, const SocketAddress &address, const void *data, nsapi_size_t size);
/** Receive a packet over a UDP socket
*
@ -167,7 +167,7 @@ protected:
* @return Number of received bytes on success, negative error
* code on failure
*/
virtual int socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size);
virtual nsapi_size_or_error_t socket_recvfrom(void *handle, SocketAddress *address, void *buffer, nsapi_size_t size);
/** Register a callback on state change of the socket
*
@ -197,7 +197,7 @@ protected:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual int setsockopt(void *handle, int level, int optname, const void *optval, unsigned optlen);
virtual nsapi_error_t setsockopt(void *handle, int level, int optname, const void *optval, unsigned optlen);
/* Get stack-specific socket options
*
@ -212,7 +212,7 @@ protected:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual int getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen);
virtual nsapi_error_t getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen);
private:
static NanostackInterface * _ns_interface;
@ -228,19 +228,19 @@ public:
*
* @return 0 on success, negative on failure
*/
virtual int initialize(NanostackRfPhy *phy);
virtual nsapi_error_t initialize(NanostackRfPhy *phy);
/** Start the interface
*
* @return 0 on success, negative on failure
*/
virtual int connect() = 0;
virtual nsapi_error_t connect() = 0;
/** Stop the interface
*
* @return 0 on success, negative on failure
*/
virtual int disconnect();
virtual nsapi_error_t disconnect();
/** Get the internally stored IP address
/return IP address of the interface or null if not yet connected
@ -255,8 +255,8 @@ public:
protected:
MeshInterfaceNanostack();
MeshInterfaceNanostack(NanostackRfPhy *phy);
int register_rf();
int actual_connect();
nsapi_error_t register_rf();
nsapi_error_t actual_connect();
virtual NetworkStack * get_stack(void);
void mesh_network_handler(mesh_connection_status_t status);
@ -287,7 +287,7 @@ public:
}
int connect();
nsapi_error_t connect();
protected:
Mesh6LoWPAN_ND *get_mesh_api() const { return static_cast<Mesh6LoWPAN_ND *>(mesh_api); }
private:
@ -312,7 +312,7 @@ public:
}
int connect();
nsapi_error_t connect();
protected:
MeshThread *get_mesh_api() const { return static_cast<MeshThread *>(mesh_api); }
private:

11
features/netsocket/CellularInterface.h
View File

@ -39,8 +39,10 @@ public:
* @param apn Optional name of the network to connect to
* @param user Optional username for the APN
* @param pass Optional password fot the APN
* @return 0 on success, negative error code on failure
*/
virtual int set_credentials(const char *apn, const char *user = 0, const char *pass = 0) = 0;
virtual nsapi_error_t set_credentials(const char *apn,
const char *username = 0, const char *password = 0) = 0;
/** Start the interface
*
@ -49,7 +51,8 @@ public:
* @param password Optional password for your APN
* @return 0 on success, negative error code on failure
*/
virtual int connect(const char *apn, const char *username = 0, const char *password = 0) = 0;
virtual nsapi_error_t connect(const char *apn,
const char *username = 0, const char *password = 0) = 0;
/** Start the interface
*
@ -57,13 +60,13 @@ public:
*
* @return 0 on success, negative error code on failure
*/
virtual int connect() = 0;
virtual nsapi_error_t connect() = 0;
/** Stop the interface
*
* @return 0 on success, negative error code on failure
*/
virtual int disconnect() = 0;
virtual nsapi_error_t disconnect() = 0;
};

10
features/netsocket/NetworkInterface.cpp
View File

@ -40,27 +40,27 @@ const char *NetworkInterface::get_gateway()
return 0;
}
int NetworkInterface::set_network(const char *ip_address, const char *netmask, const char *gateway)
nsapi_error_t NetworkInterface::set_network(const char *ip_address, const char *netmask, const char *gateway)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NetworkInterface::set_dhcp(bool dhcp)
nsapi_error_t NetworkInterface::set_dhcp(bool dhcp)
{
if (!dhcp) {
return NSAPI_ERROR_UNSUPPORTED;
} else {
return 0;
return NSAPI_ERROR_OK;
}
}
// DNS operations go through the underlying stack by default
int NetworkInterface::gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version)
nsapi_error_t NetworkInterface::gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version)
{
return get_stack()->gethostbyname(name, address, version);
}
int NetworkInterface::add_dns_server(const SocketAddress &address)
nsapi_error_t NetworkInterface::add_dns_server(const SocketAddress &address)
{
return get_stack()->add_dns_server(address);
}

14
features/netsocket/NetworkInterface.h
View File

@ -78,7 +78,8 @@ public:
* @param gateway Null-terminated representation of the local gateway
* @return 0 on success, negative error code on failure
*/
virtual int set_network(const char *ip_address, const char *netmask, const char *gateway);
virtual nsapi_error_t set_network(
const char *ip_address, const char *netmask, const char *gateway);
/** Enable or disable DHCP on the network
*
@ -89,19 +90,19 @@ public:
* @param dhcp True to enable DHCP
* @return 0 on success, negative error code on failure
*/
virtual int set_dhcp(bool dhcp);
virtual nsapi_error_t set_dhcp(bool dhcp);
/** Start the interface
*
* @return 0 on success, negative error code on failure
*/
virtual int connect() = 0;
virtual nsapi_error_t connect() = 0;
/** Stop the interface
*
* @return 0 on success, negative error code on failure
*/
virtual int disconnect() = 0;
virtual nsapi_error_t disconnect() = 0;
/** Translates a hostname to an IP address with specific version
*
@ -117,14 +118,15 @@ public:
* version is chosen by the stack (defaults to NSAPI_UNSPEC)
* @return 0 on success, negative error code on failure
*/
virtual int gethostbyname(const char *host, SocketAddress *address, nsapi_version_t version = NSAPI_UNSPEC);
virtual nsapi_error_t gethostbyname(const char *host,
SocketAddress *address, nsapi_version_t version = NSAPI_UNSPEC);
/** Add a domain name server to list of servers to query
*
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
virtual int add_dns_server(const SocketAddress &address);
virtual nsapi_error_t add_dns_server(const SocketAddress &address);
protected:
friend class Socket;

61
features/netsocket/NetworkStack.cpp
View File

@ -22,7 +22,7 @@
// Default NetworkStack operations
int NetworkStack::gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version)
nsapi_error_t NetworkStack::gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version)
{
// check for simple ip addresses
if (address->set_ip_address(name)) {
@ -30,33 +30,42 @@ int NetworkStack::gethostbyname(const char *name, SocketAddress *address, nsapi_
return NSAPI_ERROR_DNS_FAILURE;
}
return 0;
return NSAPI_ERROR_OK;
}
// if the version is unspecified, try to guess the version from the
// ip address of the underlying stack
if (version == NSAPI_UNSPEC) {
SocketAddress testaddress;
if (testaddress.set_ip_address(this->get_ip_address())) {
version = testaddress.get_ip_version();
}
}
return nsapi_dns_query(this, name, address, version);
}
int NetworkStack::add_dns_server(const SocketAddress &address)
nsapi_error_t NetworkStack::add_dns_server(const SocketAddress &address)
{
return nsapi_dns_add_server(address);
}
int NetworkStack::setstackopt(int level, int optname, const void *optval, unsigned optlen)
nsapi_error_t NetworkStack::setstackopt(int level, int optname, const void *optval, unsigned optlen)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NetworkStack::getstackopt(int level, int optname, void *optval, unsigned *optlen)
nsapi_error_t NetworkStack::getstackopt(int level, int optname, void *optval, unsigned *optlen)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NetworkStack::setsockopt(void *handle, int level, int optname, const void *optval, unsigned optlen)
nsapi_error_t NetworkStack::setsockopt(void *handle, int level, int optname, const void *optval, unsigned optlen)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int NetworkStack::getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen)
nsapi_error_t NetworkStack::getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen)
{
return NSAPI_ERROR_UNSUPPORTED;
}
@ -90,19 +99,19 @@ public:
return address->get_ip_address();
}
virtual int gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version)
virtual nsapi_error_t gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version)
{
if (!_stack_api()->gethostbyname) {
return NetworkStack::gethostbyname(name, address, version);
}
nsapi_addr_t addr = {NSAPI_UNSPEC, 0};
int err = _stack_api()->gethostbyname(_stack(), name, &addr, version);
nsapi_error_t err = _stack_api()->gethostbyname(_stack(), name, &addr, version);
address->set_addr(addr);
return err;
}
virtual int add_dns_server(const SocketAddress &address)
virtual nsapi_error_t add_dns_server(const SocketAddress &address)
{
if (!_stack_api()->add_dns_server) {
return NetworkStack::add_dns_server(address);
@ -111,7 +120,7 @@ public:
return _stack_api()->add_dns_server(_stack(), address.get_addr());
}
virtual int setstackopt(int level, int optname, const void *optval, unsigned optlen)
virtual nsapi_error_t setstackopt(int level, int optname, const void *optval, unsigned optlen)
{
if (!_stack_api()->setstackopt) {
return NSAPI_ERROR_UNSUPPORTED;
@ -120,7 +129,7 @@ public:
return _stack_api()->setstackopt(_stack(), level, optname, optval, optlen);
}
virtual int getstackopt(int level, int optname, void *optval, unsigned *optlen)
virtual nsapi_error_t getstackopt(int level, int optname, void *optval, unsigned *optlen)
{
if (!_stack_api()->getstackopt) {
return NSAPI_ERROR_UNSUPPORTED;
@ -130,7 +139,7 @@ public:
}
protected:
virtual int socket_open(nsapi_socket_t *socket, nsapi_protocol_t proto)
virtual nsapi_error_t socket_open(nsapi_socket_t *socket, nsapi_protocol_t proto)
{
if (!_stack_api()->socket_open) {
return NSAPI_ERROR_UNSUPPORTED;
@ -139,7 +148,7 @@ protected:
return _stack_api()->socket_open(_stack(), socket, proto);
}
virtual int socket_close(nsapi_socket_t socket)
virtual nsapi_error_t socket_close(nsapi_socket_t socket)
{
if (!_stack_api()->socket_close) {
return NSAPI_ERROR_UNSUPPORTED;
@ -148,7 +157,7 @@ protected:
return _stack_api()->socket_close(_stack(), socket);
}
virtual int socket_bind(nsapi_socket_t socket, const SocketAddress &address)
virtual nsapi_error_t socket_bind(nsapi_socket_t socket, const SocketAddress &address)
{
if (!_stack_api()->socket_bind) {
return NSAPI_ERROR_UNSUPPORTED;
@ -157,7 +166,7 @@ protected:
return _stack_api()->socket_bind(_stack(), socket, address.get_addr(), address.get_port());
}
virtual int socket_listen(nsapi_socket_t socket, int backlog)
virtual nsapi_error_t socket_listen(nsapi_socket_t socket, int backlog)
{
if (!_stack_api()->socket_listen) {
return NSAPI_ERROR_UNSUPPORTED;
@ -166,7 +175,7 @@ protected:
return _stack_api()->socket_listen(_stack(), socket, backlog);
}
virtual int socket_connect(nsapi_socket_t socket, const SocketAddress &address)
virtual nsapi_error_t socket_connect(nsapi_socket_t socket, const SocketAddress &address)
{
if (!_stack_api()->socket_connect) {
return NSAPI_ERROR_UNSUPPORTED;
@ -175,7 +184,7 @@ protected:
return _stack_api()->socket_connect(_stack(), socket, address.get_addr(), address.get_port());
}
virtual int socket_accept(nsapi_socket_t server, nsapi_socket_t *socket, SocketAddress *address)
virtual nsapi_error_t socket_accept(nsapi_socket_t server, nsapi_socket_t *socket, SocketAddress *address)
{
if (!_stack_api()->socket_accept) {
return NSAPI_ERROR_UNSUPPORTED;
@ -184,7 +193,7 @@ protected:
nsapi_addr_t addr = {NSAPI_IPv4, 0};
uint16_t port = 0;
int err = _stack_api()->socket_accept(_stack(), server, socket, &addr, &port);
nsapi_error_t err = _stack_api()->socket_accept(_stack(), server, socket, &addr, &port);
if (address) {
address->set_addr(addr);
@ -194,7 +203,7 @@ protected:
return err;
}
virtual int socket_send(nsapi_socket_t socket, const void *data, unsigned size)
virtual nsapi_size_or_error_t socket_send(nsapi_socket_t socket, const void *data, nsapi_size_t size)
{
if (!_stack_api()->socket_send) {
return NSAPI_ERROR_UNSUPPORTED;
@ -203,7 +212,7 @@ protected:
return _stack_api()->socket_send(_stack(), socket, data, size);
}
virtual int socket_recv(nsapi_socket_t socket, void *data, unsigned size)
virtual nsapi_size_or_error_t socket_recv(nsapi_socket_t socket, void *data, nsapi_size_t size)
{
if (!_stack_api()->socket_recv) {
return NSAPI_ERROR_UNSUPPORTED;
@ -212,7 +221,7 @@ protected:
return _stack_api()->socket_recv(_stack(), socket, data, size);
}
virtual int socket_sendto(nsapi_socket_t socket, const SocketAddress &address, const void *data, unsigned size)
virtual nsapi_size_or_error_t socket_sendto(nsapi_socket_t socket, const SocketAddress &address, const void *data, nsapi_size_t size)
{
if (!_stack_api()->socket_sendto) {
return NSAPI_ERROR_UNSUPPORTED;
@ -221,7 +230,7 @@ protected:
return _stack_api()->socket_sendto(_stack(), socket, address.get_addr(), address.get_port(), data, size);
}
virtual int socket_recvfrom(nsapi_socket_t socket, SocketAddress *address, void *data, unsigned size)
virtual nsapi_size_or_error_t socket_recvfrom(nsapi_socket_t socket, SocketAddress *address, void *data, nsapi_size_t size)
{
if (!_stack_api()->socket_recvfrom) {
return NSAPI_ERROR_UNSUPPORTED;
@ -230,7 +239,7 @@ protected:
nsapi_addr_t addr = {NSAPI_IPv4, 0};
uint16_t port = 0;
int err = _stack_api()->socket_recvfrom(_stack(), socket, &addr, &port, data, size);
nsapi_size_or_error_t err = _stack_api()->socket_recvfrom(_stack(), socket, &addr, &port, data, size);
if (address) {
address->set_addr(addr);
@ -249,7 +258,7 @@ protected:
return _stack_api()->socket_attach(_stack(), socket, callback, data);
}
virtual int setsockopt(nsapi_socket_t socket, int level, int optname, const void *optval, unsigned optlen)
virtual nsapi_error_t setsockopt(nsapi_socket_t socket, int level, int optname, const void *optval, unsigned optlen)
{
if (!_stack_api()->setsockopt) {
return NSAPI_ERROR_UNSUPPORTED;
@ -258,7 +267,7 @@ protected:
return _stack_api()->setsockopt(_stack(), socket, level, optname, optval, optlen);
}
virtual int getsockopt(nsapi_socket_t socket, int level, int optname, void *optval, unsigned *optlen)
virtual nsapi_error_t getsockopt(nsapi_socket_t socket, int level, int optname, void *optval, unsigned *optlen)
{
if (!_stack_api()->getsockopt) {
return NSAPI_ERROR_UNSUPPORTED;

40
features/netsocket/NetworkStack.h
View File

@ -58,14 +58,15 @@ public:
* version is chosen by the stack (defaults to NSAPI_UNSPEC)
* @return 0 on success, negative error code on failure
*/
virtual int gethostbyname(const char *host, SocketAddress *address, nsapi_version_t version = NSAPI_UNSPEC);
virtual nsapi_error_t gethostbyname(const char *host,
SocketAddress *address, nsapi_version_t version = NSAPI_UNSPEC);
/** Add a domain name server to list of servers to query
*
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
virtual int add_dns_server(const SocketAddress &address);
virtual nsapi_error_t add_dns_server(const SocketAddress &address);
/* Set stack-specific stack options
*
@ -79,7 +80,7 @@ public:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual int setstackopt(int level, int optname, const void *optval, unsigned optlen);
virtual nsapi_error_t setstackopt(int level, int optname, const void *optval, unsigned optlen);
/* Get stack-specific stack options
*
@ -93,7 +94,7 @@ public:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual int getstackopt(int level, int optname, void *optval, unsigned *optlen);
virtual nsapi_error_t getstackopt(int level, int optname, void *optval, unsigned *optlen);
protected:
friend class Socket;
@ -113,7 +114,7 @@ protected:
* @param proto Protocol of socket to open, NSAPI_TCP or NSAPI_UDP
* @return 0 on success, negative error code on failure
*/
virtual int socket_open(nsapi_socket_t *handle, nsapi_protocol_t proto) = 0;
virtual nsapi_error_t socket_open(nsapi_socket_t *handle, nsapi_protocol_t proto) = 0;
/** Close the socket
*
@ -123,7 +124,7 @@ protected:
* @param handle Socket handle
* @return 0 on success, negative error code on failure
*/
virtual int socket_close(nsapi_socket_t handle) = 0;
virtual nsapi_error_t socket_close(nsapi_socket_t handle) = 0;
/** Bind a specific address to a socket
*
@ -134,7 +135,7 @@ protected:
* @param address Local address to bind
* @return 0 on success, negative error code on failure.
*/
virtual int socket_bind(nsapi_socket_t handle, const SocketAddress &address) = 0;
virtual nsapi_error_t socket_bind(nsapi_socket_t handle, const SocketAddress &address) = 0;
/** Listen for connections on a TCP socket
*
@ -146,7 +147,7 @@ protected:
* simultaneously
* @return 0 on success, negative error code on failure
*/
virtual int socket_listen(nsapi_socket_t handle, int backlog) = 0;
virtual nsapi_error_t socket_listen(nsapi_socket_t handle, int backlog) = 0;
/** Connects TCP socket to a remote host
*
@ -157,7 +158,7 @@ protected:
* @param address The SocketAddress of the remote host
* @return 0 on success, negative error code on failure
*/
virtual int socket_connect(nsapi_socket_t handle, const SocketAddress &address) = 0;
virtual nsapi_error_t socket_connect(nsapi_socket_t handle, const SocketAddress &address) = 0;
/** Accepts a connection on a TCP socket
*
@ -177,7 +178,8 @@ protected:
* @param address Destination for the remote address or NULL
* @return 0 on success, negative error code on failure
*/
virtual int socket_accept(nsapi_socket_t server, nsapi_socket_t *handle, SocketAddress *address=0) = 0;
virtual nsapi_error_t socket_accept(nsapi_socket_t server,
nsapi_socket_t *handle, SocketAddress *address=0) = 0;
/** Send data over a TCP socket
*
@ -193,7 +195,8 @@ protected:
* @return Number of sent bytes on success, negative error
* code on failure
*/
virtual int socket_send(nsapi_socket_t handle, const void *data, unsigned size) = 0;
virtual nsapi_size_or_error_t socket_send(nsapi_socket_t handle,
const void *data, nsapi_size_t size) = 0;
/** Receive data over a TCP socket
*
@ -209,7 +212,8 @@ protected:
* @return Number of received bytes on success, negative error
* code on failure
*/
virtual int socket_recv(nsapi_socket_t handle, void *data, unsigned size) = 0;
virtual nsapi_size_or_error_t socket_recv(nsapi_socket_t handle,
void *data, nsapi_size_t size) = 0;
/** Send a packet over a UDP socket
*
@ -226,7 +230,8 @@ protected:
* @return Number of sent bytes on success, negative error
* code on failure
*/
virtual int socket_sendto(nsapi_socket_t handle, const SocketAddress &address, const void *data, unsigned size) = 0;
virtual nsapi_size_or_error_t socket_sendto(nsapi_socket_t handle, const SocketAddress &address,
const void *data, nsapi_size_t size) = 0;
/** Receive a packet over a UDP socket
*
@ -243,7 +248,8 @@ protected:
* @return Number of received bytes on success, negative error
* code on failure
*/
virtual int socket_recvfrom(nsapi_socket_t handle, SocketAddress *address, void *buffer, unsigned size) = 0;
virtual nsapi_size_or_error_t socket_recvfrom(nsapi_socket_t handle, SocketAddress *address,
void *buffer, nsapi_size_t size) = 0;
/** Register a callback on state change of the socket
*
@ -273,7 +279,8 @@ protected:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual int setsockopt(nsapi_socket_t handle, int level, int optname, const void *optval, unsigned optlen);
virtual nsapi_error_t setsockopt(nsapi_socket_t handle, int level,
int optname, const void *optval, unsigned optlen);
/* Get stack-specific socket options
*
@ -288,7 +295,8 @@ protected:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual int getsockopt(nsapi_socket_t handle, int level, int optname, void *optval, unsigned *optlen);
virtual nsapi_error_t getsockopt(nsapi_socket_t handle, int level,
int optname, void *optval, unsigned *optlen);
};

26
features/netsocket/Socket.cpp
View File

@ -24,7 +24,7 @@ Socket::Socket()
{
}
int Socket::open(NetworkStack *stack)
nsapi_error_t Socket::open(NetworkStack *stack)
{
_lock.lock();
@ -35,7 +35,7 @@ int Socket::open(NetworkStack *stack)
_stack = stack;
nsapi_socket_t socket;
int err = _stack->socket_open(&socket, get_proto());
nsapi_error_t err = _stack->socket_open(&socket, get_proto());
if (err) {
_lock.unlock();
return err;
@ -46,14 +46,14 @@ int Socket::open(NetworkStack *stack)
_stack->socket_attach(_socket, Callback<void()>::thunk, &_event);
_lock.unlock();
return 0;
return NSAPI_ERROR_OK;
}
int Socket::close()
nsapi_error_t Socket::close()
{
_lock.lock();
int ret = 0;
nsapi_error_t ret = NSAPI_ERROR_OK;
if (_socket) {
_stack->socket_attach(_socket, 0, 0);
nsapi_socket_t socket = _socket;
@ -69,24 +69,24 @@ int Socket::close()
return ret;
}
int Socket::bind(uint16_t port)
nsapi_error_t Socket::bind(uint16_t port)
{
// Underlying bind is thread safe
SocketAddress addr(0, port);
return bind(addr);
}
int Socket::bind(const char *address, uint16_t port)
nsapi_error_t Socket::bind(const char *address, uint16_t port)
{
// Underlying bind is thread safe
SocketAddress addr(address, port);
return bind(addr);
}
int Socket::bind(const SocketAddress &address)
nsapi_error_t Socket::bind(const SocketAddress &address)
{
_lock.lock();
int ret;
nsapi_error_t ret;
if (!_socket) {
ret = NSAPI_ERROR_NO_SOCKET;
@ -117,10 +117,10 @@ void Socket::set_timeout(int timeout)
_lock.unlock();
}
int Socket::setsockopt(int level, int optname, const void *optval, unsigned optlen)
nsapi_error_t Socket::setsockopt(int level, int optname, const void *optval, unsigned optlen)
{
_lock.lock();
int ret;
nsapi_error_t ret;
if (!_socket) {
ret = NSAPI_ERROR_NO_SOCKET;
@ -132,10 +132,10 @@ int Socket::setsockopt(int level, int optname, const void *optval, unsigned optl
return ret;
}
int Socket::getsockopt(int level, int optname, void *optval, unsigned *optlen)
nsapi_error_t Socket::getsockopt(int level, int optname, void *optval, unsigned *optlen)
{
_lock.lock();
int ret;
nsapi_error_t ret;
if (!_socket) {
ret = NSAPI_ERROR_NO_SOCKET;

16
features/netsocket/Socket.h
View File

@ -46,10 +46,10 @@ public:
* @param stack Network stack as target for socket
* @return 0 on success, negative error code on failure
*/
int open(NetworkStack *stack);
nsapi_error_t open(NetworkStack *stack);
template <typename S>
int open(S *stack) {
nsapi_error_t open(S *stack) {
return open(nsapi_create_stack(stack));
}
@ -60,7 +60,7 @@ public:
*
* @return 0 on success, negative error code on failure
*/
int close();
nsapi_error_t close();
/** Bind a specific address to a socket
*
@ -70,7 +70,7 @@ public:
* @param port Local port to bind
* @return 0 on success, negative error code on failure.
*/
int bind(uint16_t port);
nsapi_error_t bind(uint16_t port);
/** Bind a specific address to a socket
*
@ -81,7 +81,7 @@ public:
* @param port Local port to bind
* @return 0 on success, negative error code on failure.
*/
int bind(const char *address, uint16_t port);
nsapi_error_t bind(const char *address, uint16_t port);
/** Bind a specific address to a socket
*
@ -91,7 +91,7 @@ public:
* @param address Local address to bind
* @return 0 on success, negative error code on failure.
*/
int bind(const SocketAddress &address);
nsapi_error_t bind(const SocketAddress &address);
/** Set blocking or non-blocking mode of the socket
*
@ -132,7 +132,7 @@ public:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
int setsockopt(int level, int optname, const void *optval, unsigned optlen);
nsapi_error_t setsockopt(int level, int optname, const void *optval, unsigned optlen);
/* Get stack-specific socket options
*
@ -146,7 +146,7 @@ public:
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
int getsockopt(int level, int optname, void *optval, unsigned *optlen);
nsapi_error_t getsockopt(int level, int optname, void *optval, unsigned *optlen);
/** Register a callback on state change of the socket
*

2
features/netsocket/SocketAddress.cpp
View File

@ -290,6 +290,8 @@ bool operator==(const SocketAddress &a, const SocketAddress &b)
} else if (a._addr.version == NSAPI_IPv6) {
return memcmp(a._addr.bytes, b._addr.bytes, NSAPI_IPv6_BYTES) == 0;
}
MBED_UNREACHABLE;
}
bool operator!=(const SocketAddress &a, const SocketAddress &b)

8
features/netsocket/TCPServer.cpp
View File

@ -32,10 +32,10 @@ nsapi_protocol_t TCPServer::get_proto()
return NSAPI_TCP;
}
int TCPServer::listen(int backlog)
nsapi_error_t TCPServer::listen(int backlog)
{
_lock.lock();
int ret;
nsapi_error_t ret;
if (!_socket) {
ret = NSAPI_ERROR_NO_SOCKET;
@ -47,10 +47,10 @@ int TCPServer::listen(int backlog)
return ret;
}
int TCPServer::accept(TCPSocket *connection, SocketAddress *address)
nsapi_error_t TCPServer::accept(TCPSocket *connection, SocketAddress *address)
{
_lock.lock();
int ret;
nsapi_error_t ret;
while (true) {
if (!_socket) {

4
features/netsocket/TCPServer.h
View File

@ -66,7 +66,7 @@ public:
* simultaneously, defaults to 1
* @return 0 on success, negative error code on failure
*/
int listen(int backlog = 1);
nsapi_error_t listen(int backlog = 1);
/** Accepts a connection on a TCP socket
*
@ -82,7 +82,7 @@ public:
* @param address Destination for the remote address or NULL
* @return 0 on success, negative error code on failure
*/
int accept(TCPSocket *connection, SocketAddress *address = NULL);
nsapi_error_t accept(TCPSocket *connection, SocketAddress *address = NULL);
protected:
virtual nsapi_protocol_t get_proto();

20
features/netsocket/TCPSocket.cpp
View File

@ -34,10 +34,10 @@ nsapi_protocol_t TCPSocket::get_proto()
return NSAPI_TCP;
}
int TCPSocket::connect(const SocketAddress &address)
nsapi_error_t TCPSocket::connect(const SocketAddress &address)
{
_lock.lock();
int ret;
nsapi_error_t ret;
if (!_socket) {
ret = NSAPI_ERROR_NO_SOCKET;
@ -49,10 +49,10 @@ int TCPSocket::connect(const SocketAddress &address)
return ret;
}
int TCPSocket::connect(const char *host, uint16_t port)
nsapi_error_t TCPSocket::connect(const char *host, uint16_t port)
{
SocketAddress address;
int err = _stack->gethostbyname(host, &address);
nsapi_error_t err = _stack->gethostbyname(host, &address);
if (err) {
return NSAPI_ERROR_DNS_FAILURE;
}
@ -63,10 +63,10 @@ int TCPSocket::connect(const char *host, uint16_t port)
return connect(address);
}
int TCPSocket::send(const void *data, unsigned size)
nsapi_size_or_error_t TCPSocket::send(const void *data, nsapi_size_t size)
{
_lock.lock();
int ret;
nsapi_size_or_error_t ret;
// If this assert is hit then there are two threads
// performing a send at the same time which is undefined
@ -81,7 +81,7 @@ int TCPSocket::send(const void *data, unsigned size)
}
_pending = 0;
int sent = _stack->socket_send(_socket, data, size);
nsapi_size_or_error_t sent = _stack->socket_send(_socket, data, size);
if ((0 == _timeout) || (NSAPI_ERROR_WOULD_BLOCK != sent)) {
ret = sent;
break;
@ -107,10 +107,10 @@ int TCPSocket::send(const void *data, unsigned size)
return ret;
}
int TCPSocket::recv(void *data, unsigned size)
nsapi_size_or_error_t TCPSocket::recv(void *data, nsapi_size_t size)
{
_lock.lock();
int ret;
nsapi_size_or_error_t ret;
// If this assert is hit then there are two threads
// performing a recv at the same time which is undefined
@ -125,7 +125,7 @@ int TCPSocket::recv(void *data, unsigned size)
}
_pending = 0;
int recv = _stack->socket_recv(_socket, data, size);
nsapi_size_or_error_t recv = _stack->socket_recv(_socket, data, size);
if ((0 == _timeout) || (NSAPI_ERROR_WOULD_BLOCK != recv)) {
ret = recv;
break;

8
features/netsocket/TCPSocket.h
View File

@ -66,7 +66,7 @@ public:
* @param port Port of the remote host
* @return 0 on success, negative error code on failure
*/
int connect(const char *host, uint16_t port);
nsapi_error_t connect(const char *host, uint16_t port);
/** Connects TCP socket to a remote host
*
@ -76,7 +76,7 @@ public:
* @param address The SocketAddress of the remote host
* @return 0 on success, negative error code on failure
*/
int connect(const SocketAddress &address);
nsapi_error_t connect(const SocketAddress &address);
/** Send data over a TCP socket
*
@ -92,7 +92,7 @@ public:
* @return Number of sent bytes on success, negative error
* code on failure
*/
int send(const void *data, unsigned size);
nsapi_size_or_error_t send(const void *data, nsapi_size_t size);
/** Receive data over a TCP socket
*
@ -108,7 +108,7 @@ public:
* @return Number of received bytes on success, negative error
* code on failure
*/
int recv(void *data, unsigned size);
nsapi_size_or_error_t recv(void *data, nsapi_size_t size);
protected:
friend class TCPServer;

16
features/netsocket/UDPSocket.cpp
View File

@ -34,10 +34,10 @@ nsapi_protocol_t UDPSocket::get_proto()
return NSAPI_UDP;
}
int UDPSocket::sendto(const char *host, uint16_t port, const void *data, unsigned size)
nsapi_size_or_error_t UDPSocket::sendto(const char *host, uint16_t port, const void *data, nsapi_size_t size)
{
SocketAddress address;
int err = _stack->gethostbyname(host, &address);
nsapi_size_or_error_t err = _stack->gethostbyname(host, &address);
if (err) {
return NSAPI_ERROR_DNS_FAILURE;
}
@ -48,10 +48,10 @@ int UDPSocket::sendto(const char *host, uint16_t port, const void *data, unsigne
return sendto(address, data, size);
}
int UDPSocket::sendto(const SocketAddress &address, const void *data, unsigned size)
nsapi_size_or_error_t UDPSocket::sendto(const SocketAddress &address, const void *data, nsapi_size_t size)
{
_lock.lock();
int ret;
nsapi_size_or_error_t ret;
// If this assert is hit then there are two threads
// performing a send at the same time which is undefined
@ -66,7 +66,7 @@ int UDPSocket::sendto(const SocketAddress &address, const void *data, unsigned s
}
_pending = 0;
int sent = _stack->socket_sendto(_socket, address, data, size);
nsapi_size_or_error_t sent = _stack->socket_sendto(_socket, address, data, size);
if ((0 == _timeout) || (NSAPI_ERROR_WOULD_BLOCK != sent)) {
ret = sent;
break;
@ -92,10 +92,10 @@ int UDPSocket::sendto(const SocketAddress &address, const void *data, unsigned s
return ret;
}
int UDPSocket::recvfrom(SocketAddress *address, void *buffer, unsigned size)
nsapi_size_or_error_t UDPSocket::recvfrom(SocketAddress *address, void *buffer, nsapi_size_t size)
{
_lock.lock();
int ret;
nsapi_size_or_error_t ret;
// If this assert is hit then there are two threads
// performing a recv at the same time which is undefined
@ -110,7 +110,7 @@ int UDPSocket::recvfrom(SocketAddress *address, void *buffer, unsigned size)
}
_pending = 0;
int recv = _stack->socket_recvfrom(_socket, address, buffer, size);
nsapi_size_or_error_t recv = _stack->socket_recvfrom(_socket, address, buffer, size);
if ((0 == _timeout) || (NSAPI_ERROR_WOULD_BLOCK != recv)) {
ret = recv;
break;

9
features/netsocket/UDPSocket.h
View File

@ -74,7 +74,8 @@ public:
* @return Number of sent bytes on success, negative error
* code on failure
*/
int sendto(const char *host, uint16_t port, const void *data, unsigned size);
nsapi_size_or_error_t sendto(const char *host, uint16_t port,
const void *data, nsapi_size_t size);
/** Send a packet over a UDP socket
*
@ -91,7 +92,8 @@ public:
* @return Number of sent bytes on success, negative error
* code on failure
*/
int sendto(const SocketAddress &address, const void *data, unsigned size);
nsapi_size_or_error_t sendto(const SocketAddress &address,
const void *data, nsapi_size_t size);
/** Receive a packet over a UDP socket
*
@ -108,7 +110,8 @@ public:
* @return Number of received bytes on success, negative error
* code on failure
*/
int recvfrom(SocketAddress *address, void *data, unsigned size);
nsapi_size_or_error_t recvfrom(SocketAddress *address,
void *data, nsapi_size_t size);
protected:
virtual nsapi_protocol_t get_proto();

19
features/netsocket/WiFiInterface.h
View File

@ -44,14 +44,15 @@ public:
* (defaults to NSAPI_SECURITY_NONE)
* @return 0 on success, or error code on failure
*/
virtual int set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE) = 0;
virtual nsapi_error_t set_credentials(const char *ssid, const char *pass,
nsapi_security_t security = NSAPI_SECURITY_NONE) = 0;
/** Set the WiFi network channel
*
* @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
* @return 0 on success, or error code on failure
*/
virtual int set_channel(uint8_t channel) = 0;
virtual nsapi_error_t set_channel(uint8_t channel) = 0;
/** Gets the current radio signal strength for active connection
*
@ -70,9 +71,8 @@ public:
* @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
* @return 0 on success, or error code on failure
*/
virtual int connect(const char *ssid, const char *pass,
nsapi_security_t security = NSAPI_SECURITY_NONE,
uint8_t channel = 0) = 0;
virtual nsapi_error_t connect(const char *ssid, const char *pass,
nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0) = 0;
/** Start the interface
*
@ -81,13 +81,13 @@ public:
*
* @return 0 on success, negative error code on failure
*/
virtual int connect() = 0;
virtual nsapi_error_t connect() = 0;
/** Stop the interface
*
* @return 0 on success, or error code on failure
*/
virtual int disconnect() = 0;
virtual nsapi_error_t disconnect() = 0;
/** Scan for available networks
*
@ -99,10 +99,11 @@ public:
* @param ap Pointer to allocated array to store discovered AP
* @param count Size of allocated @a res array, or 0 to only count available AP
* @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0)
* @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error
* @return Number of entries in @a, or if @a count was 0 number of available networks,
* negative on error
* see @a nsapi_error
*/
virtual int scan(WiFiAccessPoint *res, unsigned count) = 0;
virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, nsapi_size_t count) = 0;
};
#endif

9
features/netsocket/emac_stack_mem.h
View File

@ -49,6 +49,15 @@ emac_stack_mem_t *emac_stack_mem_alloc(emac_stack_t* stack, uint32_t size, uint3
*/
void emac_stack_mem_free(emac_stack_t* stack, emac_stack_mem_t *mem);
/**
* Copy memory
*
* @param stack Emac stack context
* @param to Memory to copy to
* @param from Memory to copy from
*/
void emac_stack_mem_copy(emac_stack_t* stack, emac_stack_mem_t *to, emac_stack_mem_t *from);
/**
* Return pointer to the payload
*

48
features/netsocket/nsapi_dns.cpp
View File

@ -31,21 +31,23 @@
#define DNS_SERVERS_SIZE 5
nsapi_addr_t dns_servers[DNS_SERVERS_SIZE] = {
{NSAPI_IPv4, {8, 8, 8, 8}},
{NSAPI_IPv4, {209, 244, 0, 3}},
{NSAPI_IPv4, {84, 200, 69, 80}},
{NSAPI_IPv4, {8, 26, 56, 26}},
{NSAPI_IPv4, {208, 67, 222, 222}},
{NSAPI_IPv4, {8, 8, 8, 8}}, // Google
{NSAPI_IPv4, {209, 244, 0, 3}}, // Level 3
{NSAPI_IPv4, {84, 200, 69, 80}}, // DNS.WATCH
{NSAPI_IPv6, {0x20,0x01, 0x48,0x60, 0x48,0x60, 0,0, // Google
0,0, 0,0, 0,0, 0x88,0x88}},
{NSAPI_IPv6, {0x20,0x01, 0x16,0x08, 0,0x10, 0,0x25, // DNS.WATCH
0,0, 0,0, 0x1c,0x04, 0xb1,0x2f}},
};
// DNS server configuration
extern "C" int nsapi_dns_add_server(nsapi_addr_t addr)
extern "C" nsapi_error_t nsapi_dns_add_server(nsapi_addr_t addr)
{
memmove(&dns_servers[1], &dns_servers[0],
(DNS_SERVERS_SIZE-1)*sizeof(nsapi_addr_t));
dns_servers[0] = addr;
return 0;
return NSAPI_ERROR_OK;
}
@ -193,7 +195,7 @@ static int dns_scan_response(const uint8_t **p, nsapi_addr_t *addr, unsigned add
}
// core query function
static int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
static nsapi_size_or_error_t nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
nsapi_addr_t *addr, unsigned addr_count, nsapi_version_t version)
{
// check for valid host name
@ -217,7 +219,7 @@ static int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
return NSAPI_ERROR_NO_MEMORY;
}
int result = NSAPI_ERROR_DNS_FAILURE;
nsapi_size_or_error_t result = NSAPI_ERROR_DNS_FAILURE;
// check against each dns server
for (unsigned i = 0; i < DNS_SERVERS_SIZE; i++) {
@ -226,11 +228,9 @@ static int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
dns_append_question(&question, host, version);
err = socket.sendto(SocketAddress(dns_servers[i], 53), packet, DNS_BUFFER_SIZE);
if (err == NSAPI_ERROR_WOULD_BLOCK) {
// send may fail for various reasons, including wrong address type - move on
if (err < 0) {
continue;
} else if (err < 0) {
result = err;
break;
}
// recv the response
@ -265,18 +265,18 @@ static int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
}
// convenience functions for other forms of queries
extern "C" int nsapi_dns_query_multiple(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, unsigned addr_count, nsapi_version_t version)
extern "C" nsapi_size_or_error_t nsapi_dns_query_multiple(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, nsapi_size_t addr_count, nsapi_version_t version)
{
NetworkStack *nstack = nsapi_create_stack(stack);
return nsapi_dns_query_multiple(nstack, host, addr, addr_count, version);
}
int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
SocketAddress *addresses, unsigned addr_count, nsapi_version_t version)
nsapi_size_or_error_t nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
SocketAddress *addresses, nsapi_size_t addr_count, nsapi_version_t version)
{
nsapi_addr_t *addrs = new nsapi_addr_t[addr_count];
int result = nsapi_dns_query_multiple(stack, host, addrs, addr_count, version);
nsapi_size_or_error_t result = nsapi_dns_query_multiple(stack, host, addrs, addr_count, version);
if (result > 0) {
for (int i = 0; i < result; i++) {
@ -288,19 +288,19 @@ int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
return result;
}
extern "C" int nsapi_dns_query(nsapi_stack_t *stack, const char *host,
extern "C" nsapi_error_t nsapi_dns_query(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, nsapi_version_t version)
{
NetworkStack *nstack = nsapi_create_stack(stack);
int result = nsapi_dns_query_multiple(nstack, host, addr, 1, version);
return (result > 0) ? 0 : result;
nsapi_size_or_error_t result = nsapi_dns_query_multiple(nstack, host, addr, 1, version);
return (nsapi_error_t)((result > 0) ? 0 : result);
}
int nsapi_dns_query(NetworkStack *stack, const char *host,
nsapi_error_t nsapi_dns_query(NetworkStack *stack, const char *host,
SocketAddress *address, nsapi_version_t version)
{
nsapi_addr_t addr;
int result = nsapi_dns_query_multiple(stack, host, &addr, 1, version);
nsapi_size_or_error_t result = nsapi_dns_query_multiple(stack, host, &addr, 1, version);
address->set_addr(addr);
return (result > 0) ? 0 : result;
return (nsapi_error_t)((result > 0) ? 0 : result);
}

32
features/netsocket/nsapi_dns.h
View File

@ -37,7 +37,7 @@
* @return 0 on success, negative error code on failure
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
int nsapi_dns_query(nsapi_stack_t *stack, const char *host,
nsapi_error_t nsapi_dns_query(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, nsapi_version_t version);
/** Query a domain name server for multiple IP address of a given hostname
@ -50,15 +50,15 @@ int nsapi_dns_query(nsapi_stack_t *stack, const char *host,
* @return Number of addresses found on success, negative error code on failure
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
int nsapi_dns_query_multiple(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, unsigned addr_count, nsapi_version_t version);
nsapi_size_or_error_t nsapi_dns_query_multiple(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, nsapi_size_t addr_count, nsapi_version_t version);
/** Add a domain name server to list of servers to query
*
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
int nsapi_dns_add_server(nsapi_addr_t addr);
nsapi_error_t nsapi_dns_add_server(nsapi_addr_t addr);
#else
@ -73,7 +73,7 @@ int nsapi_dns_add_server(nsapi_addr_t addr);
* @return 0 on success, negative error code on failure
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
int nsapi_dns_query(NetworkStack *stack, const char *host,
nsapi_error_t nsapi_dns_query(NetworkStack *stack, const char *host,
SocketAddress *addr, nsapi_version_t version = NSAPI_IPv4);
/** Query a domain name server for an IP address of a given hostname
@ -85,7 +85,7 @@ int nsapi_dns_query(NetworkStack *stack, const char *host,
* @return 0 on success, negative error code on failure
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
extern "C" int nsapi_dns_query(nsapi_stack_t *stack, const char *host,
extern "C" nsapi_error_t nsapi_dns_query(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, nsapi_version_t version = NSAPI_IPv4);
/** Query a domain name server for an IP address of a given hostname
@ -98,7 +98,7 @@ extern "C" int nsapi_dns_query(nsapi_stack_t *stack, const char *host,
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
template <typename S>
int nsapi_dns_query(S *stack, const char *host,
nsapi_error_t nsapi_dns_query(S *stack, const char *host,
SocketAddress *addr, nsapi_version_t version = NSAPI_IPv4)
{
return nsapi_dns_query(nsapi_create_stack(stack), host, addr, version);
@ -114,8 +114,8 @@ int nsapi_dns_query(S *stack, const char *host,
* @return Number of addresses found on success, negative error code on failure
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
SocketAddress *addr, unsigned addr_count, nsapi_version_t version = NSAPI_IPv4);
nsapi_size_or_error_t nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
SocketAddress *addr, nsapi_size_t addr_count, nsapi_version_t version = NSAPI_IPv4);
/** Query a domain name server for multiple IP address of a given hostname
*
@ -127,8 +127,8 @@ int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
* @return Number of addresses found on success, negative error code on failure
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
extern "C" int nsapi_dns_query_multiple(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, unsigned addr_count, nsapi_version_t version = NSAPI_IPv4);
extern "C" nsapi_size_or_error_t nsapi_dns_query_multiple(nsapi_stack_t *stack, const char *host,
nsapi_addr_t *addr, nsapi_size_t addr_count, nsapi_version_t version = NSAPI_IPv4);
/** Query a domain name server for multiple IP address of a given hostname
*
@ -141,8 +141,8 @@ extern "C" int nsapi_dns_query_multiple(nsapi_stack_t *stack, const char *host,
* NSAPI_ERROR_DNS_FAILURE indicates the host could not be found
*/
template <typename S>
int nsapi_dns_query_multiple(S *stack, const char *host,
SocketAddress *addr, unsigned addr_count, nsapi_version_t version = NSAPI_IPv4)
nsapi_size_or_error_t nsapi_dns_query_multiple(S *stack, const char *host,
SocketAddress *addr, nsapi_size_t addr_count, nsapi_version_t version = NSAPI_IPv4)
{
return nsapi_dns_query_multiple(nsapi_create_stack(stack),
host, addr, addr_count, version);
@ -153,14 +153,14 @@ int nsapi_dns_query_multiple(S *stack, const char *host,
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
extern "C" int nsapi_dns_add_server(nsapi_addr_t addr);
extern "C" nsapi_error_t nsapi_dns_add_server(nsapi_addr_t addr);
/** Add a domain name server to list of servers to query
*
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
static inline int nsapi_dns_add_server(const SocketAddress &address)
static inline nsapi_error_t nsapi_dns_add_server(const SocketAddress &address)
{
return nsapi_dns_add_server(address.get_addr());
}
@ -170,7 +170,7 @@ static inline int nsapi_dns_add_server(const SocketAddress &address)
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
static inline int nsapi_dns_add_server(const char *address)
static inline nsapi_error_t nsapi_dns_add_server(const char *address)
{
return nsapi_dns_add_server(SocketAddress(address));
}

69
features/netsocket/nsapi_types.h
View File

@ -34,7 +34,7 @@ extern "C" {
*
* @enum nsapi_error_t
*/
typedef enum nsapi_error {
enum nsapi_error {
NSAPI_ERROR_OK = 0, /*!< no error */
NSAPI_ERROR_WOULD_BLOCK = -3001, /*!< no data is not available but call is non-blocking */
NSAPI_ERROR_UNSUPPORTED = -3002, /*!< unsupported functionality */
@ -48,7 +48,25 @@ typedef enum nsapi_error {
NSAPI_ERROR_DHCP_FAILURE = -3010, /*!< DHCP failed to complete successfully */
NSAPI_ERROR_AUTH_FAILURE = -3011, /*!< connection to access point failed */
NSAPI_ERROR_DEVICE_ERROR = -3012, /*!< failure interfacing with the network processor */
} nsapi_error_t;
};
/** Type used to represent error codes
*
* This is a separate type from enum nsapi_error to avoid breaking
* compatibility in type-sensitive overloads
*/
typedef signed int nsapi_error_t;
/** Type used to represent the size of data passed through sockets
*/
typedef unsigned int nsapi_size_t;
/** Type used to represent either a size or error pased through sockets
*
* A valid nsapi_size_or_error_t is either a non-negative size or a
* negative error code from the nsapi_error_t
*/
typedef signed int nsapi_size_or_error_t;
/** Enum of encryption types
*
@ -233,14 +251,14 @@ typedef struct nsapi_stack_api
* @param version Address family
* @return 0 on success, negative error code on failure
*/
int (*gethostbyname)(nsapi_stack_t *stack, const char *host, nsapi_addr_t *addr, nsapi_version_t version);
nsapi_error_t (*gethostbyname)(nsapi_stack_t *stack, const char *host, nsapi_addr_t *addr, nsapi_version_t version);
/** Add a domain name server to list of servers to query
*
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
int (*add_dns_server)(nsapi_stack_t *stack, nsapi_addr_t addr);
nsapi_error_t (*add_dns_server)(nsapi_stack_t *stack, nsapi_addr_t addr);
/* Set stack-specific stack options
*
@ -255,7 +273,8 @@ typedef struct nsapi_stack_api
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
int (*setstackopt)(nsapi_stack_t *stack, int level, int optname, const void *optval, unsigned optlen);
nsapi_error_t (*setstackopt)(nsapi_stack_t *stack, int level,
int optname, const void *optval, unsigned optlen);
/* Get stack-specific stack options
*
@ -270,7 +289,8 @@ typedef struct nsapi_stack_api
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
int (*getstackopt)(nsapi_stack_t *stack, int level, int optname, void *optval, unsigned *optlen);
nsapi_error_t (*getstackopt)(nsapi_stack_t *stack, int level,
int optname, void *optval, unsigned *optlen);
/** Opens a socket
*
@ -285,7 +305,8 @@ typedef struct nsapi_stack_api
* @param proto Protocol of socket to open, NSAPI_TCP or NSAPI_UDP
* @return 0 on success, negative error code on failure
*/
int (*socket_open)(nsapi_stack_t *stack, nsapi_socket_t *socket, nsapi_protocol_t proto);
nsapi_error_t (*socket_open)(nsapi_stack_t *stack, nsapi_socket_t *socket,
nsapi_protocol_t proto);
/** Close the socket
*
@ -296,7 +317,7 @@ typedef struct nsapi_stack_api
* @param socket Socket handle
* @return 0 on success, negative error code on failure
*/
int (*socket_close)(nsapi_stack_t *stack, nsapi_socket_t socket);
nsapi_error_t (*socket_close)(nsapi_stack_t *stack, nsapi_socket_t socket);
/** Bind a specific address to a socket
*
@ -309,7 +330,8 @@ typedef struct nsapi_stack_api
* @param port Local port to bind
* @return 0 on success, negative error code on failure.
*/
int (*socket_bind)(nsapi_stack_t *stack, nsapi_socket_t socket, nsapi_addr_t addr, uint16_t port);
nsapi_error_t (*socket_bind)(nsapi_stack_t *stack, nsapi_socket_t socket,
nsapi_addr_t addr, uint16_t port);
/** Listen for connections on a TCP socket
*
@ -322,7 +344,7 @@ typedef struct nsapi_stack_api
* simultaneously
* @return 0 on success, negative error code on failure
*/
int (*socket_listen)(nsapi_stack_t *stack, nsapi_socket_t socket, int backlog);
nsapi_error_t (*socket_listen)(nsapi_stack_t *stack, nsapi_socket_t socket, int backlog);
/** Connects TCP socket to a remote host
*
@ -335,7 +357,8 @@ typedef struct nsapi_stack_api
* @param port The port of the remote host
* @return 0 on success, negative error code on failure
*/
int (*socket_connect)(nsapi_stack_t *stack, nsapi_socket_t socket, nsapi_addr_t addr, uint16_t port);
nsapi_error_t (*socket_connect)(nsapi_stack_t *stack, nsapi_socket_t socket,
nsapi_addr_t addr, uint16_t port);
/** Accepts a connection on a TCP socket
*
@ -357,7 +380,8 @@ typedef struct nsapi_stack_api
* @param port Destination for the port of the remote host
* @return 0 on success, negative error code on failure
*/
int (*socket_accept)(nsapi_stack_t *stack, nsapi_socket_t server, nsapi_socket_t *socket, nsapi_addr_t *addr, uint16_t *port);
nsapi_error_t (*socket_accept)(nsapi_stack_t *stack, nsapi_socket_t server,
nsapi_socket_t *socket, nsapi_addr_t *addr, uint16_t *port);
/** Send data over a TCP socket
*
@ -374,7 +398,8 @@ typedef struct nsapi_stack_api
* @return Number of sent bytes on success, negative error
* code on failure
*/
int (*socket_send)(nsapi_stack_t *stack, nsapi_socket_t socket, const void *data, unsigned size);
nsapi_size_or_error_t (*socket_send)(nsapi_stack_t *stack, nsapi_socket_t socket,
const void *data, nsapi_size_t size);
/** Receive data over a TCP socket
*
@ -391,7 +416,8 @@ typedef struct nsapi_stack_api
* @return Number of received bytes on success, negative error
* code on failure
*/
int (*socket_recv)(nsapi_stack_t *stack, nsapi_socket_t socket, void *data, unsigned size);
nsapi_size_or_error_t (*socket_recv)(nsapi_stack_t *stack, nsapi_socket_t socket,
void *data, nsapi_size_t size);
/** Send a packet over a UDP socket
*
@ -410,7 +436,8 @@ typedef struct nsapi_stack_api
* @return Number of sent bytes on success, negative error
* code on failure
*/
int (*socket_sendto)(nsapi_stack_t *stack, nsapi_socket_t socket, nsapi_addr_t addr, uint16_t port, const void *data, unsigned size);
nsapi_size_or_error_t (*socket_sendto)(nsapi_stack_t *stack, nsapi_socket_t socket,
nsapi_addr_t addr, uint16_t port, const void *data, nsapi_size_t size);
/** Receive a packet over a UDP socket
*
@ -429,7 +456,8 @@ typedef struct nsapi_stack_api
* @return Number of received bytes on success, negative error
* code on failure
*/
int (*socket_recvfrom)(nsapi_stack_t *stack, nsapi_socket_t socket, nsapi_addr_t *addr, uint16_t *port, void *buffer, unsigned size);
nsapi_size_or_error_t (*socket_recvfrom)(nsapi_stack_t *stack, nsapi_socket_t socket,
nsapi_addr_t *addr, uint16_t *port, void *buffer, nsapi_size_t size);
/** Register a callback on state change of the socket
*
@ -445,7 +473,8 @@ typedef struct nsapi_stack_api
* @param callback Function to call on state change
* @param data Argument to pass to callback
*/
void (*socket_attach)(nsapi_stack_t *stack, nsapi_socket_t socket, void (*callback)(void *), void *data);
void (*socket_attach)(nsapi_stack_t *stack, nsapi_socket_t socket,
void (*callback)(void *), void *data);
/* Set stack-specific socket options
*
@ -461,7 +490,8 @@ typedef struct nsapi_stack_api
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
int (*setsockopt)(nsapi_stack_t *stack, nsapi_socket_t socket, int level, int optname, const void *optval, unsigned optlen);
nsapi_error_t (*setsockopt)(nsapi_stack_t *stack, nsapi_socket_t socket, int level,
int optname, const void *optval, unsigned optlen);
/* Get stack-specific socket options
*
@ -477,7 +507,8 @@ typedef struct nsapi_stack_api
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
int (*getsockopt)(nsapi_stack_t *stack, nsapi_socket_t socket, int level, int optname, void *optval, unsigned *optlen);
nsapi_error_t (*getsockopt)(nsapi_stack_t *stack, nsapi_socket_t socket, int level,
int optname, void *optval, unsigned *optlen);
} nsapi_stack_api_t;

2
features/storage/FEATURE_STORAGE/TESTS/flash_journal/basicAPI/basicAPI.cpp
View File

@ -1055,7 +1055,7 @@ void test_crc32()
#ifndef AVOID_GREENTEA
// Custom setup handler required for proper Greentea support
status_t greentea_setup(const size_t number_of_cases)
utest::v1::status_t greentea_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(60, "default_auto");
// Call the default reporting function

2
features/storage/FEATURE_STORAGE/TESTS/storage-volume-manager/basicAPI/basicAPI.cpp
View File

@ -56,7 +56,7 @@ static int32_t virtualVolumeCallbackStatus;
#ifndef AVOID_GREENTEA
// Custom setup handler required for proper Greentea support
status_t greentea_setup(const size_t number_of_cases)
utest::v1::status_t greentea_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(30, "default_auto");
// Call the default reporting function

7
features/storage/FEATURE_STORAGE/cfstore/source/cfstore_svm.cpp
View File

@ -29,8 +29,13 @@
* so it can be called by the C-HAL implementation configuration_store.c
*/
#ifndef CFSTORE_SVM_VOL_01_START_OFFSET
#define CFSTORE_SVM_VOL_01_START_OFFSET 0x80000UL
#endif
#ifndef CFSTORE_SVM_VOL_01_SIZE
#define CFSTORE_SVM_VOL_01_SIZE 0x80000UL
#endif
#ifdef CFSTORE_CONFIG_BACKEND_FLASH_ENABLED
extern ARM_DRIVER_STORAGE ARM_Driver_Storage_MTD_K64F;
@ -39,7 +44,7 @@ static ARM_DRIVER_STORAGE *cfstore_svm_storage_drv = &ARM_Driver_Storage_MTD_K64
#endif /* CFSTORE_CONFIG_BACKEND_FLASH_ENABLED */
/* the storage volume manager instance used to generate virtual mtd descriptors */
static StorageVolumeManager volumeManager;
StorageVolumeManager volumeManager;
/* used only for the initialization of the volume-manager. */
static void cfstore_svm_volume_manager_initialize_callback(int32_t status)

25
features/unsupported/USBDevice/USBDevice/USBHAL_KL25Z.cpp
View File

@ -18,6 +18,9 @@
#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
#if defined(TARGET_KSDK2_MCUS)
#include "fsl_common.h"
#endif
#include "USBHAL.h"
USBHAL * USBHAL::instance;
@ -65,7 +68,8 @@ typedef struct BDT {
// there are:
// * 16 bidirectionnal endpt -> 32 physical endpt
// * as there are ODD and EVEN buffer -> 32*2 bdt
__attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
MBED_ALIGN(512) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2]; // 512 bytes aligned!
uint8_t * endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2];
uint8_t * endpoint_buffer_iso[2*2];
@ -86,7 +90,7 @@ USBHAL::USBHAL(void) {
// Disable IRQ
NVIC_DisableIRQ(USB0_IRQn);
#if defined(TARGET_K64F)
#if (defined(FSL_FEATURE_SOC_MPU_COUNT) && (FSL_FEATURE_SOC_MPU_COUNT > 0U))
MPU->CESR=0;
#endif
// fill in callback array
@ -121,18 +125,9 @@ USBHAL::USBHAL(void) {
epCallback[28] = &USBHAL::EP15_OUT_callback;
epCallback[29] = &USBHAL::EP15_IN_callback;
#if defined(TARGET_KL43Z)
#if defined(TARGET_KL43Z) || defined(TARGET_K22F) || defined(TARGET_K64F)
// enable USBFS clock
SIM->SCGC4 |= SIM_SCGC4_USBFS_MASK;
// enable the IRC48M clock
USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
// enable the USB clock recovery tuning
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
// choose usb src clock
SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
#else
// choose usb src as PLL
SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
@ -148,10 +143,6 @@ USBHAL::USBHAL(void) {
NVIC_EnableIRQ(USB0_IRQn);
// USB Module Configuration
// Reset USB Module
USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
// Set BDT Base Register
USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);

42
features/unsupported/tests/mbed/digitalin_digitalout/main.cpp
View File

@ -9,37 +9,21 @@ DigitalIn in(dp2);
// port pin), D1 is used as USBTX
DigitalOut out(D7);
DigitalIn in(D2);
#elif defined(TARGET_STM) && defined(TARGET_FF_ARDUINO)
// TARGET_FF_ARDUINO cannot be used
// D0 is used as USBRX for some NUCLEO64
// D7 is not used for some NUCLEO32
DigitalOut out(D9);
DigitalIn in(D2);
#elif defined(TARGET_DISCO_F469NI)
DigitalOut out(PB_1);
DigitalIn in(PG_9);
#elif defined(TARGET_DISCO_L053C8) || \
defined(TARGET_DISCO_F334C8)
DigitalOut out(PA_15);
DigitalIn in(PA_8);
#elif defined(TARGET_NUCLEO_F030R8) || \
defined(TARGET_NUCLEO_F070RB) || \
defined(TARGET_NUCLEO_F072RB) || \
defined(TARGET_NUCLEO_F091RC) || \
defined(TARGET_NUCLEO_F103RB) || \
defined(TARGET_NUCLEO_F302R8) || \
defined(TARGET_NUCLEO_F303RE) || \
defined(TARGET_NUCLEO_F334R8) || \
defined(TARGET_NUCLEO_F401RE) || \
defined(TARGET_NUCLEO_F410RB) || \
defined(TARGET_NUCLEO_F411RE) || \
defined(TARGET_NUCLEO_F429ZI) || \
defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_NUCLEO_F446ZE) || \
defined(TARGET_NUCLEO_L053R8) || \
defined(TARGET_NUCLEO_L073RZ) || \
defined(TARGET_NUCLEO_L152RE)
DigitalOut out(PC_7);
DigitalIn in(PB_8);
#elif defined(TARGET_NUCLEO_F031K6) || \
defined(TARGET_NUCLEO_F042K6) || \
defined(TARGET_NUCLEO_L011K4) || \
defined(TARGET_NUCLEO_L031K6)
DigitalOut out(A4);
DigitalIn in(A5);
#elif defined(TARGET_DISCO_L476VG)
DigitalOut out(PA_1);
DigitalIn in(PA_2);
#elif defined(TARGET_ARCH_MAX) || \
defined(TARGET_DISCO_F407VG) || \

38
features/unsupported/tests/mbed/digitalinout/main.cpp
View File

@ -10,31 +10,21 @@ DigitalInOut d2(dp2);
DigitalInOut d1(D2);
DigitalInOut d2(D7);
#elif defined(TARGET_NUCLEO_F030R8) || \
defined(TARGET_NUCLEO_F070RB) || \
defined(TARGET_NUCLEO_F072RB) || \
defined(TARGET_NUCLEO_F091RC) || \
defined(TARGET_NUCLEO_F103RB) || \
defined(TARGET_NUCLEO_F302R8) || \
defined(TARGET_NUCLEO_F303RE) || \
defined(TARGET_NUCLEO_F334R8) || \
defined(TARGET_NUCLEO_F401RE) || \
defined(TARGET_NUCLEO_F410RB) || \
defined(TARGET_NUCLEO_F411RE) || \
defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_NUCLEO_F446ZE) || \
defined(TARGET_NUCLEO_L053R8) || \
defined(TARGET_NUCLEO_L073RZ) || \
defined(TARGET_NUCLEO_L152RE)
DigitalInOut d1(PC_7);
DigitalInOut d2(PB_8);
#elif defined(TARGET_STM) && defined(TARGET_FF_ARDUINO)
// TARGET_FF_ARDUINO cannot be used
// D0 is used as USBRX for some NUCLEO64
// D7 is not used for some NUCLEO32
DigitalInOut d1(D9);
DigitalInOut d2(D2);
#elif defined(TARGET_NUCLEO_F031K6) || \
defined(TARGET_NUCLEO_F042K6) || \
defined(TARGET_NUCLEO_L011K4) || \
defined(TARGET_NUCLEO_L031K6)
DigitalInOut d1(A4);
DigitalInOut d2(A5);
#elif defined(TARGET_DISCO_L053C8) || \
defined(TARGET_DISCO_F334C8)
DigitalInOut d1(PA_15);
DigitalInOut d2(PA_8);
#elif defined(TARGET_DISCO_L476VG)
DigitalInOut d1(PA_1);
DigitalInOut d2(PA_2);
#elif defined(TARGET_ARCH_MAX) || \
defined(TARGET_DISCO_F407VG) || \

1
features/unsupported/tests/mbed/echo/main.cpp
View File

@ -15,6 +15,7 @@ int main() {
MBED_HOSTTEST_SELECT(echo);
MBED_HOSTTEST_DESCRIPTION(Serial Echo at 115200);
MBED_HOSTTEST_START("MBED_A9");
wait(0.5); // wait for characters to finish transmitting
Serial pc(TXPIN, RXPIN);
pc.baud(115200);

78
features/unsupported/tests/mbed/i2c_master_slave/main.cpp
View File

@ -2,29 +2,79 @@
#include "test_env.h"
#include <stdio.h>
#if !DEVICE_I2C
#error [NOT_SUPPORTED] I2C is not supported
#endif
#if !DEVICE_I2CSLAVE
#error [NOT_SUPPORTED] I2C Slave is not supported
#endif
#if defined(TARGET_NUCLEO_F031K6) || \
defined (TARGET_NUCLEO_L011K4) || \
defined (TARGET_NUCLEO_L031K6) || \
defined (TARGET_DISCO_F746NG) || \
defined (TARGET_DISCO_L476VG) || \
defined (TARGET_NUCLEO_F303K8) || \
defined (TARGET_NUCLEO_F334R8) || \
defined (TARGET_DISCO_F334C8) || \
defined (TARGET_NUCLEO_F042K6)
#error [NOT_SUPPORTED] Target has only one I2C instance
#endif
#define ADDR (0xA0)
#define FREQ 100000
// ********************************************************
// This tests data transfer between two I2C interfaces on
// the same chip, one configured as master, the other as
// slave. Works on:
//
// *LPC1768 mbed
// p28 <-> p9
// p27 <-> p10
// pull-up resistors on both lines
// *STM32F4 boards
// cf below for wiring
// slave.
//
// Wiring: connect master SCL to slave SCL, and master SDA to slave SDA
// ********************************************************
#if defined(TARGET_NUCLEO_F411RE) || defined (TARGET_NUCLEO_F446RE) || defined (TARGET_NUCLEO_F410RB) || defined (TARGET_NUCLEO_F401RE)
I2C master(PB_9, PB_8); // I2C_1 (Arduino: D14/D15)
I2CSlave slave(PB_3, PB_10); // I2C_2 (Arduino: D3/D6)
#elif defined (TARGET_NUCLEO_F429ZI) || defined (TARGET_DISCO_F429ZI) || defined (TARGET_NUCLEO_F446ZE)
I2C master(PB_9, PB_8); // I2C_1 (Arduino: D14/D15)
I2CSlave slave(PB_11, PB_10); // I2C_2
#if defined (TARGET_DISCO_F429ZI) || \
defined (TARGET_DISCO_L053C8)
I2C master(PB_9, PB_8);
#elif defined(TARGET_FF_ARDUINO)
I2C master(D14, D15); // I2C_SDA, I2C_SCL
#endif
#if defined (TARGET_NUCLEO_F429ZI) || \
defined (TARGET_NUCLEO_F767ZI) || \
defined (TARGET_NUCLEO_L053R8) || \
defined (TARGET_NUCLEO_L073RZ) || \
defined (TARGET_NUCLEO_L152RE) || \
defined (TARGET_NUCLEO_L476RG) || \
defined (TARGET_NUCLEO_F207ZG) || \
defined (TARGET_NUCLEO_F103RB) || \
defined (TARGET_NUCLEO_F091RC) || \
defined (TARGET_DISCO_F429ZI) || \
defined (TARGET_DISCO_F469NI) || \
defined (TARGET_DISCO_L053C8) || \
defined (TARGET_NUCLEO_F446ZE)
I2CSlave slave(PB_11, PB_10);
#elif defined (TARGET_NUCLEO_F303RE) || \
defined (TARGET_NUCLEO_F302R8)
I2CSlave slave(D2, D8);
#elif defined (TARGET_NUCLEO_F303ZE)
I2CSlave slave(PC_9, PA_8);
#elif defined (TARGET_NUCLEO_F746ZG)
I2CSlave slave(D2, D4);
#elif defined (TARGET_NUCLEO_F030R8) || \
defined (TARGET_NUCLEO_F070RB) || \
defined (TARGET_NUCLEO_F072RB)
I2CSlave slave(PB_11, D6);
#else
I2CSlave slave(D3, D6);
#endif
int main()

34
features/unsupported/tests/mbed/i2c_master_slave_asynch/main.cpp
View File

@ -2,6 +2,18 @@
#include "test_env.h"
#include <stdio.h>
#if !DEVICE_I2C
#error [NOT_SUPPORTED] I2C is not supported
#endif
#if !DEVICE_I2CSLAVE
#error [NOT_SUPPORTED] I2C Slave is not supported
#endif
#if !DEVICE_I2C_ASYNCH
#error [NOT_SUPPORTED] I2C Async is not supported
#endif
#define ADDR (0x90)
#define FREQ 100000
#define SIZE 10
@ -11,15 +23,23 @@
// the same chip, one configured as master, the other as
// slave.
//
// Wiring: cf below
// Wiring: connect master SCL to slave SCL, and master SDA to slave SDA
// ********************************************************
#if defined (TARGET_NUCLEO_F411RE) || defined (TARGET_NUCLEO_F446RE) || defined (TARGET_NUCLEO_F410RB) || defined (TARGET_NUCLEO_F401RE)
I2C master(PB_9, PB_8); // I2C_1 (Arduino: D14/D15)
I2CSlave slave(PB_3, PB_10); // I2C_2 (Arduino: D3/D6)
#elif defined (TARGET_NUCLEO_F429ZI) || defined (TARGET_DISCO_F429ZI) || defined (TARGET_NUCLEO_F446ZE)
I2C master(PB_9, PB_8); // I2C_1 (Arduino: D14/D15)
I2CSlave slave(PB_11, PB_10); // I2C_2
#if defined (TARGET_DISCO_F429ZI)
I2C master(PB_9, PB_8);
#elif defined(TARGET_FF_ARDUINO)
I2C master(D14, D15); // I2C_SDA, I2C_SCL
#endif
#if defined (TARGET_NUCLEO_F429ZI) || \
defined (TARGET_DISCO_F429ZI) || \
defined (TARGET_NUCLEO_F446ZE)
I2CSlave slave(PB_11, PB_10);
#else
I2CSlave slave(D3, D6);
#endif
volatile int why;

39
features/unsupported/tests/mbed/interruptin/main.cpp
View File

@ -39,32 +39,21 @@ void in_handler() {
#define PIN_IN (p11)
#define PIN_OUT (p12)
#elif defined(TARGET_NUCLEO_F030R8) || \
defined(TARGET_NUCLEO_F070RB) || \
defined(TARGET_NUCLEO_F072RB) || \
defined(TARGET_NUCLEO_F091RC) || \
defined(TARGET_NUCLEO_F103RB) || \
defined(TARGET_NUCLEO_F302R8) || \
defined(TARGET_NUCLEO_F303RE) || \
defined(TARGET_NUCLEO_F334R8) || \
defined(TARGET_NUCLEO_F401RE) || \
defined(TARGET_NUCLEO_F410RB) || \
defined(TARGET_NUCLEO_F411RE) || \
defined(TARGET_NUCLEO_F429ZI) || \
defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_NUCLEO_F446ZE) || \
defined(TARGET_NUCLEO_L053R8) || \
defined(TARGET_NUCLEO_L073RZ) || \
defined(TARGET_NUCLEO_L152RE)
#define PIN_IN PB_8
#define PIN_OUT PC_7
#elif defined(TARGET_STM) && defined(TARGET_FF_ARDUINO)
// TARGET_FF_ARDUINO cannot be used
// D0 is used as USBRX for some NUCLEO64
// D7 is not used for some NUCLEO32
#define PIN_OUT D2
#define PIN_IN D9
#elif defined(TARGET_NUCLEO_F031K6) || \
defined(TARGET_NUCLEO_F042K6) || \
defined(TARGET_NUCLEO_L011K4) || \
defined(TARGET_NUCLEO_L031K6)
#define PIN_IN A4
#define PIN_OUT A5
#elif defined(TARGET_DISCO_L053C8) || \
defined(TARGET_DISCO_F334C8)
#define PIN_OUT PA_15
#define PIN_IN PA_8
#elif defined(TARGET_DISCO_L476VG)
#define PIN_OUT PA_1
#define PIN_IN PA_2
#elif defined(TARGET_ARCH_MAX) || \
defined(TARGET_DISCO_F407VG) || \

2
features/unsupported/tests/mbed/sd/main.cpp
View File

@ -5,7 +5,7 @@
#if defined(TARGET_KL25Z)
SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd");
#elif defined(TARGET_KL46Z)
#elif defined(TARGET_KL46Z) || defined(TARGET_KL43Z)
SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd");
#elif defined(TARGET_K64F) || defined(TARGET_K66F)

2
features/unsupported/tests/mbed/sd_perf_fatfs/main.cpp
View File

@ -7,7 +7,7 @@
#if defined(TARGET_KL25Z)
SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd");
#elif defined(TARGET_KL46Z)
#elif defined(TARGET_KL46Z) || defined(TARGET_KL43Z)
SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd");
#elif defined(TARGET_K64F) || defined(TARGET_K66F)

2
features/unsupported/tests/mbed/sd_perf_fhandle/main.cpp
View File

@ -7,7 +7,7 @@
#if defined(TARGET_KL25Z)
SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd");
#elif defined(TARGET_KL46Z)
#elif defined(TARGET_KL46Z) || defined(TARGET_KL43Z)
SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd");
#elif defined(TARGET_K64F) || defined(TARGET_K66F)

2
features/unsupported/tests/mbed/sd_perf_stdio/main.cpp
View File

@ -7,7 +7,7 @@
#if defined(TARGET_KL25Z)
SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd");
#elif defined(TARGET_KL46Z)
#elif defined(TARGET_KL46Z) || defined(TARGET_KL43Z)
SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd");
#elif defined(TARGET_K64F) || defined(TARGET_K66F)

3
features/unsupported/tests/mbed/serial_nc_rx/main.cpp
View File

@ -15,6 +15,7 @@ int main() {
// This should be true, sync the start of test
if (c == 'S') {
pc->printf("RX OK - Start NC test\r\n");
wait(0.25); // wait for characters to finish transmitting
// disconnect TX and get char
delete pc;
@ -25,11 +26,13 @@ int main() {
delete pc;
pc = new Serial(USBTX, NC);
pc->printf("RX OK - Expected\r\n");
wait(0.25); // wait for characters to finish transmitting
c = pc->getc();
// This should be false/not get here
if (c == 'U') {
pc->printf("RX OK - Unexpected\r\n");
wait(0.25); // wait for characters to finish transmitting
}
}
delete pc;

5
features/unsupported/tests/mbed/serial_nc_tx/main.cpp
View File

@ -17,15 +17,16 @@ int main() {
if (c == 'S') {
Serial *pc = new Serial(USBTX, NC);
pc->printf("TX OK - Expected\r\n");
wait(0.5); // wait for characters to finish transmitting
delete pc;
pc = new Serial(NC, USBRX);
pc->printf("TX OK - Unexpected\r\n");
wait(0.5); // wait for characters to finish transmitting
delete pc;
}
while (1) {
}
}

2
mbed.h
View File

@ -16,7 +16,7 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 128
#define MBED_LIBRARY_VERSION 129
#if MBED_CONF_RTOS_PRESENT
#include "rtos/rtos.h"

113
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralNames.h Normal file
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@ -0,0 +1,113 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
} RTCName;
typedef enum {
LPUART_0 = 0,
LPUART_1 = 1,
LPUART_2 = 2,
LPUART_3 = 3,
LPUART_4 = 4,
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART LPUART_4
/* LPTMR interrupt is defined differently in K82F */
#define LPTMR0_IRQn LPTMR0_LPTMR1_IRQn
typedef enum {
I2C_0 = 0,
I2C_1 = 1,
I2C_2 = 2,
I2C_3 = 3,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
PWM_11 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
PWM_12 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
PWM_13 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
PWM_14 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
PWM_15 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
PWM_16 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
PWM_17 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
PWM_18 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
PWM_19 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
PWM_20 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
} PWMName;
#define ADC_INSTANCE_SHIFT 8
#define ADC_B_CHANNEL_SHIFT 5
typedef enum {
ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4,
ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5,
ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6,
ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7,
ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
ADC0_SE10 = (0 << ADC_INSTANCE_SHIFT) | 10,
ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11,
ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1 = 1,
SPI_2 = 2,
} SPIName;
#ifdef __cplusplus
}
#endif
#endif

267
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralPins.c Normal file
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@ -0,0 +1,267 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************RTC***************/
const PinMap PinMap_RTC[] = {
{NC, OSC32KCLK, 0},
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PTE16, ADC0_SE4a, 0},
{PTE17, ADC0_SE5a, 0},
{PTE18, ADC0_SE6a, 0},
{PTE19, ADC0_SE7a, 0},
{PTB0, ADC0_SE8, 0},
{PTB1, ADC0_SE9, 0},
{PTA7, ADC0_SE10, 0},
{PTA8, ADC0_SE11, 0},
{PTB2, ADC0_SE12, 0},
{PTB3, ADC0_SE13, 0},
{PTC0, ADC0_SE14, 0},
{PTC1, ADC0_SE15, 0},
{PTC2, ADC0_SE4b, 0},
{PTD1, ADC0_SE5b, 0},
{PTD5, ADC0_SE6b, 0},
{PTD6, ADC0_SE7b, 0},
{NC , NC , 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{DAC0_OUT, DAC_0, 0},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTE0, I2C_1, 6},
{PTE10, I2C_3, 2},
{PTE18, I2C_0, 4},
{PTA21, I2C_0, 2},
{PTA1, I2C_3, 4},
{PTA7, I2C_2, 2},
{PTA10, I2C_2, 2},
{PTB1, I2C_0, 2},
{PTB3, I2C_0, 2},
{PTB11, I2C_2, 4},
{PTC11, I2C_1, 2},
{PTD3, I2C_0, 7},
{PTD9, I2C_0, 2},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTE1, I2C_1, 6},
{PTE11, I2C_3, 2},
{PTE19, I2C_0, 4},
{PTA20, I2C_0, 2},
{PTA2, I2C_3, 4},
{PTA6, I2C_2, 2},
{PTA11, I2C_2, 2},
{PTB0, I2C_0, 2},
{PTB2, I2C_0, 2},
{PTB10, I2C_2, 4},
{PTC10, I2C_1, 2},
{PTD2, I2C_0, 7},
{PTD8, I2C_0, 2},
{NC , NC , 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PTE0, LPUART_1, 3},
{PTE4, LPUART_3, 3},
{PTE12, LPUART_2, 3},
{PTE16, LPUART_2, 3},
{PTA20, LPUART_4, 3},
{PTA2, LPUART_0, 2},
{PTA14, LPUART_0, 3},
{PTB11, LPUART_3, 3},
{PTB17, LPUART_0, 3},
{PTC4, LPUART_1, 3},
{PTC15, LPUART_4, 3},
{PTC17, LPUART_3, 3},
{PTD3, LPUART_2, 3},
{PTD7, LPUART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTE1, LPUART_1, 3},
{PTE5, LPUART_3, 3},
{PTE13, LPUART_2, 3},
{PTE17, LPUART_2, 3},
{PTA21, LPUART_4, 3},
{PTA1, LPUART_0, 2},
{PTA15, LPUART_0, 3},
{PTB10, LPUART_3, 3},
{PTB16, LPUART_0, 3},
{PTC3, LPUART_1, 3},
{PTC14, LPUART_4, 3},
{PTC16, LPUART_3, 3},
{PTD2, LPUART_2, 3},
{PTD6, LPUART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_CTS[] = {
{PTE2, LPUART_1, 3},
{PTE6, LPUART_3, 3},
{PTE18, LPUART_2, 3},
{PTA0, LPUART_0, 2},
{PTA16, LPUART_0, 3},
{PTB3, LPUART_0, 3},
{PTB9, LPUART_3, 3},
{PTC2, LPUART_1, 3},
{PTC13, LPUART_4, 3},
{PTC19, LPUART_3, 3},
{PTD1, LPUART_2, 3},
{PTD5, LPUART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RTS[] = {
{PTE3, LPUART_1, 3},
{PTE7, LPUART_3, 3},
{PTE19, LPUART_2, 3},
{PTA3, LPUART_0, 2},
{PTA17, LPUART_0, 3},
{PTB2, LPUART_0, 3},
{PTB8, LPUART_3, 3},
{PTC1, LPUART_1, 3},
{PTC12, LPUART_4, 3},
{PTC18, LPUART_3, 3},
{PTD0, LPUART_2, 3},
{PTD4, LPUART_0, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{PTE1, SPI_1, 2},
{PTE2, SPI_1, 7},
{PTE7, SPI_2, 2},
{PTE17, SPI_0, 2},
{PTA15, SPI_0, 2},
{PTB11, SPI_1, 2},
{PTB21, SPI_2, 2},
{PTC5, SPI_0, 2},
{PTD1, SPI_0, 2},
{PTD5, SPI_1, 7},
{PTD12, SPI_2, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PTE2, SPI_1, 2},
{PTE3, SPI_1, 7},
{PTE8, SPI_2, 3},
{PTE18, SPI_0, 2},
{PTA16, SPI_0, 2},
{PTB16, SPI_1, 2},
{PTB16, SPI_1, 2},
{PTB22, SPI_2, 2},
{PTC6, SPI_0, 2},
{PTD2, SPI_0, 2},
{PTD6, SPI_1, 7},
{PTD13, SPI_2, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PTE1, SPI_1, 7},
{PTE4, SPI_1, 2},
{PTE10, SPI_2, 3},
{PTE19, SPI_0, 2},
{PTA17, SPI_0, 2},
{PTB17, SPI_1, 2},
{PTB23, SPI_2, 2},
{PTC7, SPI_0, 2},
{PTD3, SPI_0, 2},
{PTD7, SPI_1, 7},
{PTD14, SPI_2, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PTE5, SPI_1, 2},
{PTE11, SPI_2, 3},
{PTE16, SPI_0, 2},
{PTA14, SPI_0, 2},
{PTB10, SPI_1, 2},
{PTB20, SPI_2, 2},
{PTC4, SPI_0, 2},
{PTD0, SPI_0, 2},
{PTD4, SPI_1, 7},
{PTD11, SPI_2, 2},
{NC , NC , 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
/* FTM 0 */
{PTA0, PWM_6, 3},
{PTA1, PWM_7, 3},
{PTA2, PWM_8, 3},
{PTA3, PWM_1, 3},
{PTA4, PWM_2, 3},
{PTA5, PWM_3, 3},
{PTA6, PWM_4, 3},
{PTA7, PWM_5, 3},
{PTC1, PWM_1, 4},
{PTC2, PWM_2, 4},
{PTC3, PWM_3, 4},
{PTC4, PWM_4, 4},
{PTC5, PWM_3, 7},
{PTD4, PWM_5, 4},
{PTD5, PWM_6, 4},
{PTD6, PWM_7, 4},
{PTD7, PWM_8, 4},
/* FTM 1 */
{PTA8, PWM_9, 3},
{PTA9, PWM_10, 3},
{PTA12, PWM_9, 3},
{PTA13, PWM_10, 3},
{PTB0, PWM_9, 3},
{PTB1, PWM_10, 3},
/* FTM 2 */
{PTA10, PWM_11, 3},
{PTA11, PWM_12, 3},
{PTB18, PWM_11, 3},
{PTB19, PWM_12, 3},
/* FTM 3 */
{PTE5, PWM_13, 6},
{PTE6, PWM_14, 6},
{PTE7, PWM_15, 6},
{PTE8, PWM_16, 6},
{PTE9, PWM_17, 6},
{PTE10, PWM_18, 6},
{PTE11, PWM_19, 6},
{PTE12, PWM_20, 6},
{PTC8, PWM_17, 3},
{PTC9, PWM_18, 3},
{PTC10, PWM_19, 3},
{PTC11, PWM_20, 3},
{PTD0, PWM_13, 4},
{PTD1, PWM_14, 4},
{PTD2, PWM_15, 4},
{PTD3, PWM_16, 4},
{NC , NC , 0}
};

188
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/TARGET_FRDM/PinNames.h Normal file
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@ -0,0 +1,188 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define GPIO_PORT_SHIFT 12
typedef enum {
PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
PTA10 = (0 << GPIO_PORT_SHIFT | 10 ),
PTA11 = (0 << GPIO_PORT_SHIFT | 11 ),
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
PTA20 = (0 << GPIO_PORT_SHIFT | 20),
PTA21 = (0 << GPIO_PORT_SHIFT | 21),
PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
PTC16 = (2 << GPIO_PORT_SHIFT | 16),
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
PTC18 = (2 << GPIO_PORT_SHIFT | 18),
PTC19 = (2 << GPIO_PORT_SHIFT | 19),
PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
PTD11 = (3 << GPIO_PORT_SHIFT | 11),
PTD12 = (3 << GPIO_PORT_SHIFT | 12),
PTD13 = (3 << GPIO_PORT_SHIFT | 13),
PTD14 = (3 << GPIO_PORT_SHIFT | 14),
PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
LED_RED = PTC8,
LED_GREEN = PTC9,
LED_BLUE = PTC10,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_RED,
//Push buttons
SW2 = PTA4,
SW3 = PTC6,
// USB Pins
USBTX = PTC15,
USBRX = PTC14,
// Arduino Headers
D0 = PTB16,
D1 = PTB17,
D2 = PTC12,
D3 = PTD0,
D4 = PTC11,
D5 = PTC10,
D6 = PTC8,
D7 = PTC9,
D8 = PTC3,
D9 = PTC5,
D10 = PTD4,
D11 = PTD2,
D12 = PTD3,
D13 = PTD1,
D14 = PTA1,
D15 = PTA2,
I2C_SCL = D15,
I2C_SDA = D14,
A0 = PTB0,
A1 = PTB1,
A2 = PTC1,
A3 = PTC2,
A4 = PTB3,
A5 = PTB2,
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

0
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h → targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/TARGET_FRDM/device.h
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164
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/TARGET_FRDM/fsl_clock_config.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_common.h"
#include "fsl_smc.h"
#include "fsl_clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
* Code
******************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
* and flash clock are in allowed range during clock mode switch.
*
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
*
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
* internal reference clock(MCGIRCLK). Follow the steps to setup:
*
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
*
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
* explicitly to setup MCGIRCLK.
*
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
* if the target mode is not FLL mode, the FLL is disabled.
*
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
*
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
*/
void BOARD_BootClockVLPR(void)
{
const sim_clock_config_t simConfig = {
.pllFllSel = 3U, .pllFllDiv = 0U, .pllFllFrac = 0U, .er32kSrc = 2U, .clkdiv1 = 0x00040000U,
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x04U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, .pllFllDiv = 0U, .pllFllFrac = 0U, .er32kSrc = 2U, .clkdiv1 = 0x01140000U,
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0U);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 120000000U;
}
void BOARD_BootClockHSRUN(void)
{
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x09U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, .pllFllDiv = 0U, .pllFllFrac = 0U, .er32kSrc = 2U, .clkdiv1 = 0x01150000U,
};
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0U);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 150000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}

55
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/TARGET_FRDM/fsl_clock_config.h Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
/*******************************************************************************
* DEFINITION
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 12000000U
#define BOARD_XTAL32K_CLK_HZ 32768U
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
void BOARD_InitOsc0(void);
void BOARD_BootClockVLPR(void);
void BOARD_BootClockRUN(void);
void BOARD_BootClockHSRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

39
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "fsl_clock_config.h"
// called before main
void mbed_sdk_init()
{
BOARD_BootClockRUN();
}
// Change the NMI pin to an input. This allows NMI pin to
// be used as a low power mode wakeup. The application will
// need to change the pin back to NMI_b or wakeup only occurs once!
void NMI_Handler(void)
{
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}
// Enable the RTC oscillator if available on the board
void rtc_setup_oscillator(RTC_Type *base)
{
/* Enable the RTC oscillator */
RTC->CR |= RTC_CR_OSCE_MASK;
}

15528
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/MK82F25615.h Normal file
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targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/MK82F25615_features.h Normal file
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127
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/MK82FN256xxx15.sct Normal file
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#! armcc -E
/*
** ###################################################################
** Processors: MK82FN256CAx15
** MK82FN256VDC15
** MK82FN256VLL15
** MK82FN256VLQ15
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
** Version: rev. 1.2, 2015-07-29
** Build: b160406
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
#define __ram_vector_table__ 1
/* Heap 1/4 of ram and stack 1/8 */
#define __stack_size__ 0x8000
#define __heap_size__ 0x10000
#if (defined(__ram_vector_table__))
#define __ram_vector_table_size__ 0x000003C0
#else
#define __ram_vector_table_size__ 0x00000000
#endif
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x000003C0
#define m_bootloader_config_start 0x000003C0
#define m_bootloader_config_size 0x00000040
#define m_flash_config_start 0x00000400
#define m_flash_config_size 0x00000010
#define m_text_start 0x00000410
#define m_text_size 0x0003FBF0
#define m_interrupts_ram_start 0x1FFF0000
#define m_interrupts_ram_size __ram_vector_table_size__
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
#define m_data_size (0x00010000 - m_interrupts_ram_size)
#define m_data_2_start 0x20000000
#define m_data_2_size 0x00030000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_bootloader_config m_bootloader_config_start FIXED m_bootloader_config_size { ; load address = execution address
* (BootloaderConfig)
}
ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (FlashConfig)
}
ER_m_text m_text_start m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__ram_vector_table__))
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
}
#else
VECTOR_RAM m_interrupts_start EMPTY 0 {
}
#endif
RW_m_data m_data_start m_data_size { ; RW data
.ANY (+RW +ZI)
}
RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 ImageLimit(RW_m_data_2) { ; Heap region growing up
}
}

965
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/startup_MK82F25615.S Normal file
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; * ---------------------------------------------------------------------------------------
; * @file: startup_MK82F25615.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
; * MK82F25615
; * @version: 1.0
; * @date: 2015-4-9
; * @build: b151210
; * ---------------------------------------------------------------------------------------
; *
; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without modification,
; * are permitted provided that the following conditions are met:
; *
; * o Redistributions of source code must retain the above copyright notice, this list
; * of conditions and the following disclaimer.
; *
; * o Redistributions in binary form must reproduce the above copyright notice, this
; * list of conditions and the following disclaimer in the documentation and/or
; * other materials provided with the distribution.
; *
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
; * contributors may be used to endorse or promote products derived from this
; * software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
__initial_sp EQU 0x20030000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA channel 0,16 transfer complete
DCD DMA1_DMA17_IRQHandler ;DMA channel 1,17 transfer complete
DCD DMA2_DMA18_IRQHandler ;DMA channel 2,18 transfer complete
DCD DMA3_DMA19_IRQHandler ;DMA channel 3,19 transfer complete
DCD DMA4_DMA20_IRQHandler ;DMA channel 4,20 transfer complete
DCD DMA5_DMA21_IRQHandler ;DMA channel 5,21 transfer complete
DCD DMA6_DMA22_IRQHandler ;DMA channel 6,22 transfer complete
DCD DMA7_DMA23_IRQHandler ;DMA channel 7,23 transfer complete
DCD DMA8_DMA24_IRQHandler ;DMA channel 8,24 transfer complete
DCD DMA9_DMA25_IRQHandler ;DMA channel 9,25 transfer complete
DCD DMA10_DMA26_IRQHandler ;DMA channel 10,26 transfer complete
DCD DMA11_DMA27_IRQHandler ;DMA channel 11,27 transfer complete
DCD DMA12_DMA28_IRQHandler ;DMA channel 12,28 transfer complete
DCD DMA13_DMA29_IRQHandler ;DMA channel 13,29 transfer complete
DCD DMA14_DMA30_IRQHandler ;DMA channel 14,30 transfer complete
DCD DMA15_DMA31_IRQHandler ;DMA channel 15,31 transfer complete
DCD DMA_Error_IRQHandler ;DMA channel 0 - 31 error
DCD MCM_IRQHandler ;MCM normal interrupt
DCD FTFA_IRQHandler ;FTFA command complete
DCD Read_Collision_IRQHandler ;FTFA read collision
DCD LVD_LVW_IRQHandler ;PMC controller low-voltage detect, low-voltage warning
DCD LLWU_IRQHandler ;Low leakage wakeup unit
DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM
DCD TRNG0_IRQHandler ;True randon number generator
DCD I2C0_IRQHandler ;Inter-integrated circuit 0
DCD I2C1_IRQHandler ;Inter-integrated circuit 1
DCD SPI0_IRQHandler ;Serial peripheral Interface 0
DCD SPI1_IRQHandler ;Serial peripheral Interface 1
DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt
DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt
DCD LPUART0_IRQHandler ;LPUART0 receive/transmit/error interrupt
DCD LPUART1_IRQHandler ;LPUART1 receive/transmit/error interrupt
DCD LPUART2_IRQHandler ;LPUART2 receive/transmit/error interrupt
DCD LPUART3_IRQHandler ;LPUART3 receive/transmit/error interrupt
DCD LPUART4_IRQHandler ;LPUART4 receive/transmit/error interrupt
DCD Reserved51_IRQHandler ;Reserved interrupt
DCD Reserved52_IRQHandler ;Reserved interrupt
DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt
DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt
DCD ADC0_IRQHandler ;Analog-to-digital converter 0
DCD CMP0_IRQHandler ;Comparator 0
DCD CMP1_IRQHandler ;Comparator 1
DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ;Carrier modulator transmitter
DCD RTC_IRQHandler ;Real time clock
DCD RTC_Seconds_IRQHandler ;Real time clock seconds
DCD PIT0CH0_IRQHandler ;Periodic interrupt timer 0 channel 0
DCD PIT0CH1_IRQHandler ;Periodic interrupt timer 0 channel 1
DCD PIT0CH2_IRQHandler ;Periodic interrupt timer 0 channel 2
DCD PIT0CH3_IRQHandler ;Periodic interrupt timer 0 channel 3
DCD PDB0_IRQHandler ;Programmable delay block
DCD USB0_IRQHandler ;USB OTG interrupt
DCD USBDCD_IRQHandler ;USB charger detect
DCD Reserved71_IRQHandler ;Reserved interrupt
DCD DAC0_IRQHandler ;Digital-to-analog converter 0
DCD MCG_IRQHandler ;Multipurpose clock generator
DCD LPTMR0_LPTMR1_IRQHandler ;Single interrupt vector for Low Power Timer 0 and 1
DCD PORTA_IRQHandler ;Port A pin detect interrupt
DCD PORTB_IRQHandler ;Port B pin detect interrupt
DCD PORTC_IRQHandler ;Port C pin detect interrupt
DCD PORTD_IRQHandler ;Port D pin detect interrupt
DCD PORTE_IRQHandler ;Port E pin detect interrupt
DCD SWI_IRQHandler ;Software interrupt
DCD SPI2_IRQHandler ;Serial peripheral Interface 2
DCD Reserved82_IRQHandler ;Reserved interrupt
DCD Reserved83_IRQHandler ;Reserved interrupt
DCD Reserved84_IRQHandler ;Reserved interrupt
DCD Reserved85_IRQHandler ;Reserved interrupt
DCD FLEXIO0_IRQHandler ;FLEXIO0
DCD FTM3_IRQHandler ;FlexTimer module 3 fault, overflow and channels interrupt
DCD Reserved88_IRQHandler ;Reserved interrupt
DCD Reserved89_IRQHandler ;Reserved interrupt
DCD I2C2_IRQHandler ;Inter-integrated circuit 2
DCD Reserved91_IRQHandler ;Reserved interrupt
DCD Reserved92_IRQHandler ;Reserved interrupt
DCD Reserved93_IRQHandler ;Reserved interrupt
DCD Reserved94_IRQHandler ;Reserved interrupt
DCD Reserved95_IRQHandler ;Reserved interrupt
DCD Reserved96_IRQHandler ;Reserved interrupt
DCD SDHC_IRQHandler ;Secured digital host controller
DCD Reserved98_IRQHandler ;Reserved interrupt
DCD Reserved99_IRQHandler ;Reserved interrupt
DCD Reserved100_IRQHandler ;Reserved interrupt
DCD Reserved101_IRQHandler ;Reserved interrupt
DCD Reserved102_IRQHandler ;Reserved interrupt
DCD TSI0_IRQHandler ;Touch Sensing Input
DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
DCD Reserved106_IRQHandler ;Reserved interrupt
DCD I2C3_IRQHandler ;Inter-integrated circuit 3
DCD Reserved108_IRQHandler ;Reserved interrupt
DCD Reserved109_IRQHandler ;Reserved interrupt
DCD Reserved110_IRQHandler ;Reserved interrupt
DCD Reserved111_IRQHandler ;Reserved interrupt
DCD Reserved112_IRQHandler ;Reserved interrupt
DCD Reserved113_IRQHandler ;Reserved interrupt
DCD Reserved114_IRQHandler ;Reserved interrupt
DCD Reserved115_IRQHandler ;Reserved interrupt
DCD QuadSPI0_IRQHandler ;qspi
DCD Reserved117_IRQHandler ;Reserved interrupt
DCD Reserved118_IRQHandler ;Reserved interrupt
DCD Reserved119_IRQHandler ;Reserved interrupt
DCD LTC0_IRQHandler ;LP Trusted Cryptography
DCD Reserved121_IRQHandler ;Reserved interrupt
DCD Reserved122_IRQHandler ;Reserved interrupt
DCD DefaultISR ;123
DCD DefaultISR ;124
DCD DefaultISR ;125
DCD DefaultISR ;126
DCD DefaultISR ;127
DCD DefaultISR ;128
DCD DefaultISR ;129
DCD DefaultISR ;130
DCD DefaultISR ;131
DCD DefaultISR ;132
DCD DefaultISR ;133
DCD DefaultISR ;134
DCD DefaultISR ;135
DCD DefaultISR ;136
DCD DefaultISR ;137
DCD DefaultISR ;138
DCD DefaultISR ;139
DCD DefaultISR ;140
DCD DefaultISR ;141
DCD DefaultISR ;142
DCD DefaultISR ;143
DCD DefaultISR ;144
DCD DefaultISR ;145
DCD DefaultISR ;146
DCD DefaultISR ;147
DCD DefaultISR ;148
DCD DefaultISR ;149
DCD DefaultISR ;150
DCD DefaultISR ;151
DCD DefaultISR ;152
DCD DefaultISR ;153
DCD DefaultISR ;154
DCD DefaultISR ;155
DCD DefaultISR ;156
DCD DefaultISR ;157
DCD DefaultISR ;158
DCD DefaultISR ;159
DCD DefaultISR ;160
DCD DefaultISR ;161
DCD DefaultISR ;162
DCD DefaultISR ;163
DCD DefaultISR ;164
DCD DefaultISR ;165
DCD DefaultISR ;166
DCD DefaultISR ;167
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict access to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program Flash Region Protect Register 0
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> Normal boot
; <o.1> BOOTPIN_OPT
; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI_b pin/interrupts reset default to enabled
; <o.5> FAST_INIT
; <0=> Slower initialization
; <1=> Fast Initialization
; <o.6..7> BOOTSRC_SEL
; <0=> Boot from Flash
; <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
; <3=> Boot from ROM and enter boot loader mode.
; <i> Boot source selection
FOPT EQU 0x3D
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor Key Security Enable
FSEC EQU 0xFE
; </h>
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA FlashConfig, DATA, READONLY
__FlashConfig
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
DCB FSEC , FOPT , 0xFF , 0xFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
IF :LNOT::DEF:RAM_TARGET
REQUIRE FlashConfig
ENDIF
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__Vectors
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
CPSIE i ; Unmask interrupts
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
DMA0_DMA16_IRQHandler\
PROC
EXPORT DMA0_DMA16_IRQHandler [WEAK]
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
ENDP
DMA1_DMA17_IRQHandler\
PROC
EXPORT DMA1_DMA17_IRQHandler [WEAK]
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
ENDP
DMA2_DMA18_IRQHandler\
PROC
EXPORT DMA2_DMA18_IRQHandler [WEAK]
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
ENDP
DMA3_DMA19_IRQHandler\
PROC
EXPORT DMA3_DMA19_IRQHandler [WEAK]
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
ENDP
DMA4_DMA20_IRQHandler\
PROC
EXPORT DMA4_DMA20_IRQHandler [WEAK]
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
ENDP
DMA5_DMA21_IRQHandler\
PROC
EXPORT DMA5_DMA21_IRQHandler [WEAK]
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
ENDP
DMA6_DMA22_IRQHandler\
PROC
EXPORT DMA6_DMA22_IRQHandler [WEAK]
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
ENDP
DMA7_DMA23_IRQHandler\
PROC
EXPORT DMA7_DMA23_IRQHandler [WEAK]
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
ENDP
DMA8_DMA24_IRQHandler\
PROC
EXPORT DMA8_DMA24_IRQHandler [WEAK]
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
ENDP
DMA9_DMA25_IRQHandler\
PROC
EXPORT DMA9_DMA25_IRQHandler [WEAK]
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
ENDP
DMA10_DMA26_IRQHandler\
PROC
EXPORT DMA10_DMA26_IRQHandler [WEAK]
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
ENDP
DMA11_DMA27_IRQHandler\
PROC
EXPORT DMA11_DMA27_IRQHandler [WEAK]
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
ENDP
DMA12_DMA28_IRQHandler\
PROC
EXPORT DMA12_DMA28_IRQHandler [WEAK]
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
ENDP
DMA13_DMA29_IRQHandler\
PROC
EXPORT DMA13_DMA29_IRQHandler [WEAK]
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
ENDP
DMA14_DMA30_IRQHandler\
PROC
EXPORT DMA14_DMA30_IRQHandler [WEAK]
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
ENDP
DMA15_DMA31_IRQHandler\
PROC
EXPORT DMA15_DMA31_IRQHandler [WEAK]
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
ENDP
DMA_Error_IRQHandler\
PROC
EXPORT DMA_Error_IRQHandler [WEAK]
LDR R0, =DMA_Error_DriverIRQHandler
BX R0
ENDP
I2C0_IRQHandler\
PROC
EXPORT I2C0_IRQHandler [WEAK]
LDR R0, =I2C0_DriverIRQHandler
BX R0
ENDP
I2C1_IRQHandler\
PROC
EXPORT I2C1_IRQHandler [WEAK]
LDR R0, =I2C1_DriverIRQHandler
BX R0
ENDP
SPI0_IRQHandler\
PROC
EXPORT SPI0_IRQHandler [WEAK]
LDR R0, =SPI0_DriverIRQHandler
BX R0
ENDP
SPI1_IRQHandler\
PROC
EXPORT SPI1_IRQHandler [WEAK]
LDR R0, =SPI1_DriverIRQHandler
BX R0
ENDP
I2S0_Tx_IRQHandler\
PROC
EXPORT I2S0_Tx_IRQHandler [WEAK]
LDR R0, =I2S0_Tx_DriverIRQHandler
BX R0
ENDP
I2S0_Rx_IRQHandler\
PROC
EXPORT I2S0_Rx_IRQHandler [WEAK]
LDR R0, =I2S0_Rx_DriverIRQHandler
BX R0
ENDP
LPUART0_IRQHandler\
PROC
EXPORT LPUART0_IRQHandler [WEAK]
LDR R0, =LPUART0_DriverIRQHandler
BX R0
ENDP
LPUART1_IRQHandler\
PROC
EXPORT LPUART1_IRQHandler [WEAK]
LDR R0, =LPUART1_DriverIRQHandler
BX R0
ENDP
LPUART2_IRQHandler\
PROC
EXPORT LPUART2_IRQHandler [WEAK]
LDR R0, =LPUART2_DriverIRQHandler
BX R0
ENDP
LPUART3_IRQHandler\
PROC
EXPORT LPUART3_IRQHandler [WEAK]
LDR R0, =LPUART3_DriverIRQHandler
BX R0
ENDP
LPUART4_IRQHandler\
PROC
EXPORT LPUART4_IRQHandler [WEAK]
LDR R0, =LPUART4_DriverIRQHandler
BX R0
ENDP
SPI2_IRQHandler\
PROC
EXPORT SPI2_IRQHandler [WEAK]
LDR R0, =SPI2_DriverIRQHandler
BX R0
ENDP
FLEXIO0_IRQHandler\
PROC
EXPORT FLEXIO0_IRQHandler [WEAK]
LDR R0, =FLEXIO0_DriverIRQHandler
BX R0
ENDP
I2C2_IRQHandler\
PROC
EXPORT I2C2_IRQHandler [WEAK]
LDR R0, =I2C2_DriverIRQHandler
BX R0
ENDP
SDHC_IRQHandler\
PROC
EXPORT SDHC_IRQHandler [WEAK]
LDR R0, =SDHC_DriverIRQHandler
BX R0
ENDP
I2C3_IRQHandler\
PROC
EXPORT I2C3_IRQHandler [WEAK]
LDR R0, =I2C3_DriverIRQHandler
BX R0
ENDP
QuadSPI0_IRQHandler\
PROC
EXPORT QuadSPI0_IRQHandler [WEAK]
LDR R0, =QuadSPI0_DriverIRQHandler
BX R0
ENDP
Default_Handler\
PROC
EXPORT DMA0_DMA16_DriverIRQHandler [WEAK]
EXPORT DMA1_DMA17_DriverIRQHandler [WEAK]
EXPORT DMA2_DMA18_DriverIRQHandler [WEAK]
EXPORT DMA3_DMA19_DriverIRQHandler [WEAK]
EXPORT DMA4_DMA20_DriverIRQHandler [WEAK]
EXPORT DMA5_DMA21_DriverIRQHandler [WEAK]
EXPORT DMA6_DMA22_DriverIRQHandler [WEAK]
EXPORT DMA7_DMA23_DriverIRQHandler [WEAK]
EXPORT DMA8_DMA24_DriverIRQHandler [WEAK]
EXPORT DMA9_DMA25_DriverIRQHandler [WEAK]
EXPORT DMA10_DMA26_DriverIRQHandler [WEAK]
EXPORT DMA11_DMA27_DriverIRQHandler [WEAK]
EXPORT DMA12_DMA28_DriverIRQHandler [WEAK]
EXPORT DMA13_DMA29_DriverIRQHandler [WEAK]
EXPORT DMA14_DMA30_DriverIRQHandler [WEAK]
EXPORT DMA15_DMA31_DriverIRQHandler [WEAK]
EXPORT DMA_Error_DriverIRQHandler [WEAK]
EXPORT MCM_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLWU_IRQHandler [WEAK]
EXPORT WDOG_EWM_IRQHandler [WEAK]
EXPORT TRNG0_IRQHandler [WEAK]
EXPORT I2C0_DriverIRQHandler [WEAK]
EXPORT I2C1_DriverIRQHandler [WEAK]
EXPORT SPI0_DriverIRQHandler [WEAK]
EXPORT SPI1_DriverIRQHandler [WEAK]
EXPORT I2S0_Tx_DriverIRQHandler [WEAK]
EXPORT I2S0_Rx_DriverIRQHandler [WEAK]
EXPORT LPUART0_DriverIRQHandler [WEAK]
EXPORT LPUART1_DriverIRQHandler [WEAK]
EXPORT LPUART2_DriverIRQHandler [WEAK]
EXPORT LPUART3_DriverIRQHandler [WEAK]
EXPORT LPUART4_DriverIRQHandler [WEAK]
EXPORT Reserved51_IRQHandler [WEAK]
EXPORT Reserved52_IRQHandler [WEAK]
EXPORT EMVSIM0_IRQHandler [WEAK]
EXPORT EMVSIM1_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT FTM2_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0CH0_IRQHandler [WEAK]
EXPORT PIT0CH1_IRQHandler [WEAK]
EXPORT PIT0CH2_IRQHandler [WEAK]
EXPORT PIT0CH3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT Reserved71_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTMR0_LPTMR1_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT SPI2_DriverIRQHandler [WEAK]
EXPORT Reserved82_IRQHandler [WEAK]
EXPORT Reserved83_IRQHandler [WEAK]
EXPORT Reserved84_IRQHandler [WEAK]
EXPORT Reserved85_IRQHandler [WEAK]
EXPORT FLEXIO0_DriverIRQHandler [WEAK]
EXPORT FTM3_IRQHandler [WEAK]
EXPORT Reserved88_IRQHandler [WEAK]
EXPORT Reserved89_IRQHandler [WEAK]
EXPORT I2C2_DriverIRQHandler [WEAK]
EXPORT Reserved91_IRQHandler [WEAK]
EXPORT Reserved92_IRQHandler [WEAK]
EXPORT Reserved93_IRQHandler [WEAK]
EXPORT Reserved94_IRQHandler [WEAK]
EXPORT Reserved95_IRQHandler [WEAK]
EXPORT Reserved96_IRQHandler [WEAK]
EXPORT SDHC_DriverIRQHandler [WEAK]
EXPORT Reserved98_IRQHandler [WEAK]
EXPORT Reserved99_IRQHandler [WEAK]
EXPORT Reserved100_IRQHandler [WEAK]
EXPORT Reserved101_IRQHandler [WEAK]
EXPORT Reserved102_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT Reserved106_IRQHandler [WEAK]
EXPORT I2C3_DriverIRQHandler [WEAK]
EXPORT Reserved108_IRQHandler [WEAK]
EXPORT Reserved109_IRQHandler [WEAK]
EXPORT Reserved110_IRQHandler [WEAK]
EXPORT Reserved111_IRQHandler [WEAK]
EXPORT Reserved112_IRQHandler [WEAK]
EXPORT Reserved113_IRQHandler [WEAK]
EXPORT Reserved114_IRQHandler [WEAK]
EXPORT Reserved115_IRQHandler [WEAK]
EXPORT QuadSPI0_DriverIRQHandler [WEAK]
EXPORT Reserved117_IRQHandler [WEAK]
EXPORT Reserved118_IRQHandler [WEAK]
EXPORT Reserved119_IRQHandler [WEAK]
EXPORT LTC0_IRQHandler [WEAK]
EXPORT Reserved121_IRQHandler [WEAK]
EXPORT Reserved122_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_Error_DriverIRQHandler
MCM_IRQHandler
FTFA_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLWU_IRQHandler
WDOG_EWM_IRQHandler
TRNG0_IRQHandler
I2C0_DriverIRQHandler
I2C1_DriverIRQHandler
SPI0_DriverIRQHandler
SPI1_DriverIRQHandler
I2S0_Tx_DriverIRQHandler
I2S0_Rx_DriverIRQHandler
LPUART0_DriverIRQHandler
LPUART1_DriverIRQHandler
LPUART2_DriverIRQHandler
LPUART3_DriverIRQHandler
LPUART4_DriverIRQHandler
Reserved51_IRQHandler
Reserved52_IRQHandler
EMVSIM0_IRQHandler
EMVSIM1_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
FTM2_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0CH0_IRQHandler
PIT0CH1_IRQHandler
PIT0CH2_IRQHandler
PIT0CH3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
Reserved71_IRQHandler
DAC0_IRQHandler
MCG_IRQHandler
LPTMR0_LPTMR1_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
SPI2_DriverIRQHandler
Reserved82_IRQHandler
Reserved83_IRQHandler
Reserved84_IRQHandler
Reserved85_IRQHandler
FLEXIO0_DriverIRQHandler
FTM3_IRQHandler
Reserved88_IRQHandler
Reserved89_IRQHandler
I2C2_DriverIRQHandler
Reserved91_IRQHandler
Reserved92_IRQHandler
Reserved93_IRQHandler
Reserved94_IRQHandler
Reserved95_IRQHandler
Reserved96_IRQHandler
SDHC_DriverIRQHandler
Reserved98_IRQHandler
Reserved99_IRQHandler
Reserved100_IRQHandler
Reserved101_IRQHandler
Reserved102_IRQHandler
TSI0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
Reserved106_IRQHandler
I2C3_DriverIRQHandler
Reserved108_IRQHandler
Reserved109_IRQHandler
Reserved110_IRQHandler
Reserved111_IRQHandler
Reserved112_IRQHandler
Reserved113_IRQHandler
Reserved114_IRQHandler
Reserved115_IRQHandler
QuadSPI0_DriverIRQHandler
Reserved117_IRQHandler
Reserved118_IRQHandler
Reserved119_IRQHandler
LTC0_IRQHandler
Reserved121_IRQHandler
Reserved122_IRQHandler
DefaultISR
B DefaultISR
ENDP
ALIGN
END

0
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/device/TOOLCHAIN_ARM_STD/sys.cpp → targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/sys.cpp
View File

275
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_GCC_ARM/MK82FN256xxx15.ld Normal file
View File

@ -0,0 +1,275 @@
/*
** ###################################################################
** Processors: MK82FN256CAx15
** MK82FN256VDC15
** MK82FN256VLL15
** MK82FN256VLQ15
**
** Compiler: GNU C Compiler
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
** Version: rev. 1.2, 2015-07-29
** Build: b160613
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
__ram_vector_table__ = 1;
/* Heap 1/4 of ram and stack 1/8 */
__stack_size__ = 0x8000;
__heap_size__ = 0x10000;
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x03C0 : 0x0;
/* Specify the memory areas */
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000003C0
m_bootloader_config (RX) : ORIGIN = 0x000003C0, LENGTH = 0x00000040
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0003FBF0
m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
.bootloader_config :
{
. = ALIGN(4);
KEEP(*(.BootloaderConfig)) /* Bootloader Configuration Area (BCA) */
. = ALIGN(4);
} > m_bootloader_config
.flash_config :
{
. = ALIGN(4);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(4);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x00;
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
. = ALIGN(512);
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data_2
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data_2
m_usb_bdt USB_RAM_START (NOLOAD) :
{
*(m_usb_bdt)
USB_RAM_BDT_END = .;
}
m_usb_global USB_RAM_BDT_END (NOLOAD) :
{
*(m_usb_global)
}
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

868
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_GCC_ARM/startup_MK82F25615.S Normal file
View File

@ -0,0 +1,868 @@
/* ---------------------------------------------------------------------------------------*/
/* @file: startup_MK82F25615.s */
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
/* MK82F25615 */
/* @version: 1.0 */
/* @date: 2015-4-9 */
/* @build: b151210 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without modification, */
/* are permitted provided that the following conditions are met: */
/* */
/* o Redistributions of source code must retain the above copyright notice, this list */
/* of conditions and the following disclaimer. */
/* */
/* o Redistributions in binary form must reproduce the above copyright notice, this */
/* list of conditions and the following disclaimer in the documentation and/or */
/* other materials provided with the distribution. */
/* */
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
/* contributors may be used to endorse or promote products derived from this */
/* software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_DMA16_IRQHandler /* DMA channel 0,16 transfer complete*/
.long DMA1_DMA17_IRQHandler /* DMA channel 1,17 transfer complete*/
.long DMA2_DMA18_IRQHandler /* DMA channel 2,18 transfer complete*/
.long DMA3_DMA19_IRQHandler /* DMA channel 3,19 transfer complete*/
.long DMA4_DMA20_IRQHandler /* DMA channel 4,20 transfer complete*/
.long DMA5_DMA21_IRQHandler /* DMA channel 5,21 transfer complete*/
.long DMA6_DMA22_IRQHandler /* DMA channel 6,22 transfer complete*/
.long DMA7_DMA23_IRQHandler /* DMA channel 7,23 transfer complete*/
.long DMA8_DMA24_IRQHandler /* DMA channel 8,24 transfer complete*/
.long DMA9_DMA25_IRQHandler /* DMA channel 9,25 transfer complete*/
.long DMA10_DMA26_IRQHandler /* DMA channel 10,26 transfer complete*/
.long DMA11_DMA27_IRQHandler /* DMA channel 11,27 transfer complete*/
.long DMA12_DMA28_IRQHandler /* DMA channel 12,28 transfer complete*/
.long DMA13_DMA29_IRQHandler /* DMA channel 13,29 transfer complete*/
.long DMA14_DMA30_IRQHandler /* DMA channel 14,30 transfer complete*/
.long DMA15_DMA31_IRQHandler /* DMA channel 15,31 transfer complete*/
.long DMA_Error_IRQHandler /* DMA channel 0 - 31 error*/
.long MCM_IRQHandler /* MCM normal interrupt*/
.long FTFA_IRQHandler /* FTFA command complete*/
.long Read_Collision_IRQHandler /* FTFA read collision*/
.long LVD_LVW_IRQHandler /* PMC controller low-voltage detect, low-voltage warning*/
.long LLWU_IRQHandler /* Low leakage wakeup unit*/
.long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/
.long TRNG0_IRQHandler /* True randon number generator*/
.long I2C0_IRQHandler /* Inter-integrated circuit 0*/
.long I2C1_IRQHandler /* Inter-integrated circuit 1*/
.long SPI0_IRQHandler /* Serial peripheral Interface 0*/
.long SPI1_IRQHandler /* Serial peripheral Interface 1*/
.long I2S0_Tx_IRQHandler /* Integrated interchip sound 0 transmit interrupt*/
.long I2S0_Rx_IRQHandler /* Integrated interchip sound 0 receive interrupt*/
.long LPUART0_IRQHandler /* LPUART0 receive/transmit/error interrupt*/
.long LPUART1_IRQHandler /* LPUART1 receive/transmit/error interrupt*/
.long LPUART2_IRQHandler /* LPUART2 receive/transmit/error interrupt*/
.long LPUART3_IRQHandler /* LPUART3 receive/transmit/error interrupt*/
.long LPUART4_IRQHandler /* LPUART4 receive/transmit/error interrupt*/
.long Reserved51_IRQHandler /* Reserved interrupt*/
.long Reserved52_IRQHandler /* Reserved interrupt*/
.long EMVSIM0_IRQHandler /* EMVSIM0 common interrupt*/
.long EMVSIM1_IRQHandler /* EMVSIM1 common interrupt*/
.long ADC0_IRQHandler /* Analog-to-digital converter 0*/
.long CMP0_IRQHandler /* Comparator 0*/
.long CMP1_IRQHandler /* Comparator 1*/
.long FTM0_IRQHandler /* FlexTimer module 0 fault, overflow and channels interrupt*/
.long FTM1_IRQHandler /* FlexTimer module 1 fault, overflow and channels interrupt*/
.long FTM2_IRQHandler /* FlexTimer module 2 fault, overflow and channels interrupt*/
.long CMT_IRQHandler /* Carrier modulator transmitter*/
.long RTC_IRQHandler /* Real time clock*/
.long RTC_Seconds_IRQHandler /* Real time clock seconds*/
.long PIT0CH0_IRQHandler /* Periodic interrupt timer 0 channel 0*/
.long PIT0CH1_IRQHandler /* Periodic interrupt timer 0 channel 1*/
.long PIT0CH2_IRQHandler /* Periodic interrupt timer 0 channel 2*/
.long PIT0CH3_IRQHandler /* Periodic interrupt timer 0 channel 3*/
.long PDB0_IRQHandler /* Programmable delay block*/
.long USB0_IRQHandler /* USB OTG interrupt*/
.long USBDCD_IRQHandler /* USB charger detect*/
.long Reserved71_IRQHandler /* Reserved interrupt*/
.long DAC0_IRQHandler /* Digital-to-analog converter 0*/
.long MCG_IRQHandler /* Multipurpose clock generator*/
.long LPTMR0_LPTMR1_IRQHandler /* Single interrupt vector for Low Power Timer 0 and 1*/
.long PORTA_IRQHandler /* Port A pin detect interrupt*/
.long PORTB_IRQHandler /* Port B pin detect interrupt*/
.long PORTC_IRQHandler /* Port C pin detect interrupt*/
.long PORTD_IRQHandler /* Port D pin detect interrupt*/
.long PORTE_IRQHandler /* Port E pin detect interrupt*/
.long SWI_IRQHandler /* Software interrupt*/
.long SPI2_IRQHandler /* Serial peripheral Interface 2*/
.long Reserved82_IRQHandler /* Reserved interrupt*/
.long Reserved83_IRQHandler /* Reserved interrupt*/
.long Reserved84_IRQHandler /* Reserved interrupt*/
.long Reserved85_IRQHandler /* Reserved interrupt*/
.long FLEXIO0_IRQHandler /* FLEXIO0*/
.long FTM3_IRQHandler /* FlexTimer module 3 fault, overflow and channels interrupt*/
.long Reserved88_IRQHandler /* Reserved interrupt*/
.long Reserved89_IRQHandler /* Reserved interrupt*/
.long I2C2_IRQHandler /* Inter-integrated circuit 2*/
.long Reserved91_IRQHandler /* Reserved interrupt*/
.long Reserved92_IRQHandler /* Reserved interrupt*/
.long Reserved93_IRQHandler /* Reserved interrupt*/
.long Reserved94_IRQHandler /* Reserved interrupt*/
.long Reserved95_IRQHandler /* Reserved interrupt*/
.long Reserved96_IRQHandler /* Reserved interrupt*/
.long SDHC_IRQHandler /* Secured digital host controller*/
.long Reserved98_IRQHandler /* Reserved interrupt*/
.long Reserved99_IRQHandler /* Reserved interrupt*/
.long Reserved100_IRQHandler /* Reserved interrupt*/
.long Reserved101_IRQHandler /* Reserved interrupt*/
.long Reserved102_IRQHandler /* Reserved interrupt*/
.long TSI0_IRQHandler /* Touch Sensing Input*/
.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
.long Reserved106_IRQHandler /* Reserved interrupt*/
.long I2C3_IRQHandler /* Inter-integrated circuit 3*/
.long Reserved108_IRQHandler /* Reserved interrupt*/
.long Reserved109_IRQHandler /* Reserved interrupt*/
.long Reserved110_IRQHandler /* Reserved interrupt*/
.long Reserved111_IRQHandler /* Reserved interrupt*/
.long Reserved112_IRQHandler /* Reserved interrupt*/
.long Reserved113_IRQHandler /* Reserved interrupt*/
.long Reserved114_IRQHandler /* Reserved interrupt*/
.long Reserved115_IRQHandler /* Reserved interrupt*/
.long QuadSPI0_IRQHandler /* qspi*/
.long Reserved117_IRQHandler /* Reserved interrupt*/
.long Reserved118_IRQHandler /* Reserved interrupt*/
.long Reserved119_IRQHandler /* Reserved interrupt*/
.long LTC0_IRQHandler /* LP Trusted Cryptography*/
.long Reserved121_IRQHandler /* Reserved interrupt*/
.long Reserved122_IRQHandler /* Reserved interrupt*/
.long DefaultISR /* 123*/
.long DefaultISR /* 124*/
.long DefaultISR /* 125*/
.long DefaultISR /* 126*/
.long DefaultISR /* 127*/
.long DefaultISR /* 128*/
.long DefaultISR /* 129*/
.long DefaultISR /* 130*/
.long DefaultISR /* 131*/
.long DefaultISR /* 132*/
.long DefaultISR /* 133*/
.long DefaultISR /* 134*/
.long DefaultISR /* 135*/
.long DefaultISR /* 136*/
.long DefaultISR /* 137*/
.long DefaultISR /* 138*/
.long DefaultISR /* 139*/
.long DefaultISR /* 140*/
.long DefaultISR /* 141*/
.long DefaultISR /* 142*/
.long DefaultISR /* 143*/
.long DefaultISR /* 144*/
.long DefaultISR /* 145*/
.long DefaultISR /* 146*/
.long DefaultISR /* 147*/
.long DefaultISR /* 148*/
.long DefaultISR /* 149*/
.long DefaultISR /* 150*/
.long DefaultISR /* 151*/
.long DefaultISR /* 152*/
.long DefaultISR /* 153*/
.long DefaultISR /* 154*/
.long DefaultISR /* 155*/
.long DefaultISR /* 156*/
.long DefaultISR /* 157*/
.long DefaultISR /* 158*/
.long DefaultISR /* 159*/
.long DefaultISR /* 160*/
.long DefaultISR /* 161*/
.long DefaultISR /* 162*/
.long DefaultISR /* 163*/
.long DefaultISR /* 164*/
.long DefaultISR /* 165*/
.long DefaultISR /* 166*/
.long DefaultISR /* 167*/
.long DefaultISR /* 168*/
.long DefaultISR /* 169*/
.long DefaultISR /* 170*/
.long DefaultISR /* 171*/
.long DefaultISR /* 172*/
.long DefaultISR /* 173*/
.long DefaultISR /* 174*/
.long DefaultISR /* 175*/
.long DefaultISR /* 176*/
.long DefaultISR /* 177*/
.long DefaultISR /* 178*/
.long DefaultISR /* 179*/
.long DefaultISR /* 180*/
.long DefaultISR /* 181*/
.long DefaultISR /* 182*/
.long DefaultISR /* 183*/
.long DefaultISR /* 184*/
.long DefaultISR /* 185*/
.long DefaultISR /* 186*/
.long DefaultISR /* 187*/
.long DefaultISR /* 188*/
.long DefaultISR /* 189*/
.long DefaultISR /* 190*/
.long DefaultISR /* 191*/
.long DefaultISR /* 192*/
.long DefaultISR /* 193*/
.long DefaultISR /* 194*/
.long DefaultISR /* 195*/
.long DefaultISR /* 196*/
.long DefaultISR /* 197*/
.long DefaultISR /* 198*/
.long DefaultISR /* 199*/
.long DefaultISR /* 200*/
.long DefaultISR /* 201*/
.long DefaultISR /* 202*/
.long DefaultISR /* 203*/
.long DefaultISR /* 204*/
.long DefaultISR /* 205*/
.long DefaultISR /* 206*/
.long DefaultISR /* 207*/
.long DefaultISR /* 208*/
.long DefaultISR /* 209*/
.long DefaultISR /* 210*/
.long DefaultISR /* 211*/
.long DefaultISR /* 212*/
.long DefaultISR /* 213*/
.long DefaultISR /* 214*/
.long DefaultISR /* 215*/
.long DefaultISR /* 216*/
.long DefaultISR /* 217*/
.long DefaultISR /* 218*/
.long DefaultISR /* 219*/
.long DefaultISR /* 220*/
.long DefaultISR /* 221*/
.long DefaultISR /* 222*/
.long DefaultISR /* 223*/
.long DefaultISR /* 224*/
.long DefaultISR /* 225*/
.long DefaultISR /* 226*/
.long DefaultISR /* 227*/
.long DefaultISR /* 228*/
.long DefaultISR /* 229*/
.long DefaultISR /* 230*/
.long DefaultISR /* 231*/
.long DefaultISR /* 232*/
.long DefaultISR /* 233*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFF3DFE
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak DMA0_DMA16_IRQHandler
.type DMA0_DMA16_IRQHandler, %function
DMA0_DMA16_IRQHandler:
ldr r0,=DMA0_DMA16_DriverIRQHandler
bx r0
.size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler
.align 1
.thumb_func
.weak DMA1_DMA17_IRQHandler
.type DMA1_DMA17_IRQHandler, %function
DMA1_DMA17_IRQHandler:
ldr r0,=DMA1_DMA17_DriverIRQHandler
bx r0
.size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler
.align 1
.thumb_func
.weak DMA2_DMA18_IRQHandler
.type DMA2_DMA18_IRQHandler, %function
DMA2_DMA18_IRQHandler:
ldr r0,=DMA2_DMA18_DriverIRQHandler
bx r0
.size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler
.align 1
.thumb_func
.weak DMA3_DMA19_IRQHandler
.type DMA3_DMA19_IRQHandler, %function
DMA3_DMA19_IRQHandler:
ldr r0,=DMA3_DMA19_DriverIRQHandler
bx r0
.size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler
.align 1
.thumb_func
.weak DMA4_DMA20_IRQHandler
.type DMA4_DMA20_IRQHandler, %function
DMA4_DMA20_IRQHandler:
ldr r0,=DMA4_DMA20_DriverIRQHandler
bx r0
.size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler
.align 1
.thumb_func
.weak DMA5_DMA21_IRQHandler
.type DMA5_DMA21_IRQHandler, %function
DMA5_DMA21_IRQHandler:
ldr r0,=DMA5_DMA21_DriverIRQHandler
bx r0
.size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler
.align 1
.thumb_func
.weak DMA6_DMA22_IRQHandler
.type DMA6_DMA22_IRQHandler, %function
DMA6_DMA22_IRQHandler:
ldr r0,=DMA6_DMA22_DriverIRQHandler
bx r0
.size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler
.align 1
.thumb_func
.weak DMA7_DMA23_IRQHandler
.type DMA7_DMA23_IRQHandler, %function
DMA7_DMA23_IRQHandler:
ldr r0,=DMA7_DMA23_DriverIRQHandler
bx r0
.size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler
.align 1
.thumb_func
.weak DMA8_DMA24_IRQHandler
.type DMA8_DMA24_IRQHandler, %function
DMA8_DMA24_IRQHandler:
ldr r0,=DMA8_DMA24_DriverIRQHandler
bx r0
.size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler
.align 1
.thumb_func
.weak DMA9_DMA25_IRQHandler
.type DMA9_DMA25_IRQHandler, %function
DMA9_DMA25_IRQHandler:
ldr r0,=DMA9_DMA25_DriverIRQHandler
bx r0
.size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler
.align 1
.thumb_func
.weak DMA10_DMA26_IRQHandler
.type DMA10_DMA26_IRQHandler, %function
DMA10_DMA26_IRQHandler:
ldr r0,=DMA10_DMA26_DriverIRQHandler
bx r0
.size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler
.align 1
.thumb_func
.weak DMA11_DMA27_IRQHandler
.type DMA11_DMA27_IRQHandler, %function
DMA11_DMA27_IRQHandler:
ldr r0,=DMA11_DMA27_DriverIRQHandler
bx r0
.size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler
.align 1
.thumb_func
.weak DMA12_DMA28_IRQHandler
.type DMA12_DMA28_IRQHandler, %function
DMA12_DMA28_IRQHandler:
ldr r0,=DMA12_DMA28_DriverIRQHandler
bx r0
.size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler
.align 1
.thumb_func
.weak DMA13_DMA29_IRQHandler
.type DMA13_DMA29_IRQHandler, %function
DMA13_DMA29_IRQHandler:
ldr r0,=DMA13_DMA29_DriverIRQHandler
bx r0
.size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler
.align 1
.thumb_func
.weak DMA14_DMA30_IRQHandler
.type DMA14_DMA30_IRQHandler, %function
DMA14_DMA30_IRQHandler:
ldr r0,=DMA14_DMA30_DriverIRQHandler
bx r0
.size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler
.align 1
.thumb_func
.weak DMA15_DMA31_IRQHandler
.type DMA15_DMA31_IRQHandler, %function
DMA15_DMA31_IRQHandler:
ldr r0,=DMA15_DMA31_DriverIRQHandler
bx r0
.size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler
.align 1
.thumb_func
.weak DMA_Error_IRQHandler
.type DMA_Error_IRQHandler, %function
DMA_Error_IRQHandler:
ldr r0,=DMA_Error_DriverIRQHandler
bx r0
.size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler
.align 1
.thumb_func
.weak I2C0_IRQHandler
.type I2C0_IRQHandler, %function
I2C0_IRQHandler:
ldr r0,=I2C0_DriverIRQHandler
bx r0
.size I2C0_IRQHandler, . - I2C0_IRQHandler
.align 1
.thumb_func
.weak I2C1_IRQHandler
.type I2C1_IRQHandler, %function
I2C1_IRQHandler:
ldr r0,=I2C1_DriverIRQHandler
bx r0
.size I2C1_IRQHandler, . - I2C1_IRQHandler
.align 1
.thumb_func
.weak SPI0_IRQHandler
.type SPI0_IRQHandler, %function
SPI0_IRQHandler:
ldr r0,=SPI0_DriverIRQHandler
bx r0
.size SPI0_IRQHandler, . - SPI0_IRQHandler
.align 1
.thumb_func
.weak SPI1_IRQHandler
.type SPI1_IRQHandler, %function
SPI1_IRQHandler:
ldr r0,=SPI1_DriverIRQHandler
bx r0
.size SPI1_IRQHandler, . - SPI1_IRQHandler
.align 1
.thumb_func
.weak I2S0_Tx_IRQHandler
.type I2S0_Tx_IRQHandler, %function
I2S0_Tx_IRQHandler:
ldr r0,=I2S0_Tx_DriverIRQHandler
bx r0
.size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler
.align 1
.thumb_func
.weak I2S0_Rx_IRQHandler
.type I2S0_Rx_IRQHandler, %function
I2S0_Rx_IRQHandler:
ldr r0,=I2S0_Rx_DriverIRQHandler
bx r0
.size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler
.align 1
.thumb_func
.weak LPUART0_IRQHandler
.type LPUART0_IRQHandler, %function
LPUART0_IRQHandler:
ldr r0,=LPUART0_DriverIRQHandler
bx r0
.size LPUART0_IRQHandler, . - LPUART0_IRQHandler
.align 1
.thumb_func
.weak LPUART1_IRQHandler
.type LPUART1_IRQHandler, %function
LPUART1_IRQHandler:
ldr r0,=LPUART1_DriverIRQHandler
bx r0
.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
.align 1
.thumb_func
.weak LPUART2_IRQHandler
.type LPUART2_IRQHandler, %function
LPUART2_IRQHandler:
ldr r0,=LPUART2_DriverIRQHandler
bx r0
.size LPUART2_IRQHandler, . - LPUART2_IRQHandler
.align 1
.thumb_func
.weak LPUART3_IRQHandler
.type LPUART3_IRQHandler, %function
LPUART3_IRQHandler:
ldr r0,=LPUART3_DriverIRQHandler
bx r0
.size LPUART3_IRQHandler, . - LPUART3_IRQHandler
.align 1
.thumb_func
.weak LPUART4_IRQHandler
.type LPUART4_IRQHandler, %function
LPUART4_IRQHandler:
ldr r0,=LPUART4_DriverIRQHandler
bx r0
.size LPUART4_IRQHandler, . - LPUART4_IRQHandler
.align 1
.thumb_func
.weak SPI2_IRQHandler
.type SPI2_IRQHandler, %function
SPI2_IRQHandler:
ldr r0,=SPI2_DriverIRQHandler
bx r0
.size SPI2_IRQHandler, . - SPI2_IRQHandler
.align 1
.thumb_func
.weak FLEXIO0_IRQHandler
.type FLEXIO0_IRQHandler, %function
FLEXIO0_IRQHandler:
ldr r0,=FLEXIO0_DriverIRQHandler
bx r0
.size FLEXIO0_IRQHandler, . - FLEXIO0_IRQHandler
.align 1
.thumb_func
.weak I2C2_IRQHandler
.type I2C2_IRQHandler, %function
I2C2_IRQHandler:
ldr r0,=I2C2_DriverIRQHandler
bx r0
.size I2C2_IRQHandler, . - I2C2_IRQHandler
.align 1
.thumb_func
.weak SDHC_IRQHandler
.type SDHC_IRQHandler, %function
SDHC_IRQHandler:
ldr r0,=SDHC_DriverIRQHandler
bx r0
.size SDHC_IRQHandler, . - SDHC_IRQHandler
.align 1
.thumb_func
.weak I2C3_IRQHandler
.type I2C3_IRQHandler, %function
I2C3_IRQHandler:
ldr r0,=I2C3_DriverIRQHandler
bx r0
.size I2C3_IRQHandler, . - I2C3_IRQHandler
.align 1
.thumb_func
.weak QuadSPI0_IRQHandler
.type QuadSPI0_IRQHandler, %function
QuadSPI0_IRQHandler:
ldr r0,=QuadSPI0_DriverIRQHandler
bx r0
.size QuadSPI0_IRQHandler, . - QuadSPI0_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler DMA0_DMA16_DriverIRQHandler
def_irq_handler DMA1_DMA17_DriverIRQHandler
def_irq_handler DMA2_DMA18_DriverIRQHandler
def_irq_handler DMA3_DMA19_DriverIRQHandler
def_irq_handler DMA4_DMA20_DriverIRQHandler
def_irq_handler DMA5_DMA21_DriverIRQHandler
def_irq_handler DMA6_DMA22_DriverIRQHandler
def_irq_handler DMA7_DMA23_DriverIRQHandler
def_irq_handler DMA8_DMA24_DriverIRQHandler
def_irq_handler DMA9_DMA25_DriverIRQHandler
def_irq_handler DMA10_DMA26_DriverIRQHandler
def_irq_handler DMA11_DMA27_DriverIRQHandler
def_irq_handler DMA12_DMA28_DriverIRQHandler
def_irq_handler DMA13_DMA29_DriverIRQHandler
def_irq_handler DMA14_DMA30_DriverIRQHandler
def_irq_handler DMA15_DMA31_DriverIRQHandler
def_irq_handler DMA_Error_DriverIRQHandler
def_irq_handler MCM_IRQHandler
def_irq_handler FTFA_IRQHandler
def_irq_handler Read_Collision_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler LLWU_IRQHandler
def_irq_handler WDOG_EWM_IRQHandler
def_irq_handler TRNG0_IRQHandler
def_irq_handler I2C0_DriverIRQHandler
def_irq_handler I2C1_DriverIRQHandler
def_irq_handler SPI0_DriverIRQHandler
def_irq_handler SPI1_DriverIRQHandler
def_irq_handler I2S0_Tx_DriverIRQHandler
def_irq_handler I2S0_Rx_DriverIRQHandler
def_irq_handler LPUART0_DriverIRQHandler
def_irq_handler LPUART1_DriverIRQHandler
def_irq_handler LPUART2_DriverIRQHandler
def_irq_handler LPUART3_DriverIRQHandler
def_irq_handler LPUART4_DriverIRQHandler
def_irq_handler Reserved51_IRQHandler
def_irq_handler Reserved52_IRQHandler
def_irq_handler EMVSIM0_IRQHandler
def_irq_handler EMVSIM1_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler CMP1_IRQHandler
def_irq_handler FTM0_IRQHandler
def_irq_handler FTM1_IRQHandler
def_irq_handler FTM2_IRQHandler
def_irq_handler CMT_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler PIT0CH0_IRQHandler
def_irq_handler PIT0CH1_IRQHandler
def_irq_handler PIT0CH2_IRQHandler
def_irq_handler PIT0CH3_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler USBDCD_IRQHandler
def_irq_handler Reserved71_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler MCG_IRQHandler
def_irq_handler LPTMR0_LPTMR1_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler SWI_IRQHandler
def_irq_handler SPI2_DriverIRQHandler
def_irq_handler Reserved82_IRQHandler
def_irq_handler Reserved83_IRQHandler
def_irq_handler Reserved84_IRQHandler
def_irq_handler Reserved85_IRQHandler
def_irq_handler FLEXIO0_DriverIRQHandler
def_irq_handler FTM3_IRQHandler
def_irq_handler Reserved88_IRQHandler
def_irq_handler Reserved89_IRQHandler
def_irq_handler I2C2_DriverIRQHandler
def_irq_handler Reserved91_IRQHandler
def_irq_handler Reserved92_IRQHandler
def_irq_handler Reserved93_IRQHandler
def_irq_handler Reserved94_IRQHandler
def_irq_handler Reserved95_IRQHandler
def_irq_handler Reserved96_IRQHandler
def_irq_handler SDHC_DriverIRQHandler
def_irq_handler Reserved98_IRQHandler
def_irq_handler Reserved99_IRQHandler
def_irq_handler Reserved100_IRQHandler
def_irq_handler Reserved101_IRQHandler
def_irq_handler Reserved102_IRQHandler
def_irq_handler TSI0_IRQHandler
def_irq_handler TPM1_IRQHandler
def_irq_handler TPM2_IRQHandler
def_irq_handler Reserved106_IRQHandler
def_irq_handler I2C3_DriverIRQHandler
def_irq_handler Reserved108_IRQHandler
def_irq_handler Reserved109_IRQHandler
def_irq_handler Reserved110_IRQHandler
def_irq_handler Reserved111_IRQHandler
def_irq_handler Reserved112_IRQHandler
def_irq_handler Reserved113_IRQHandler
def_irq_handler Reserved114_IRQHandler
def_irq_handler Reserved115_IRQHandler
def_irq_handler QuadSPI0_DriverIRQHandler
def_irq_handler Reserved117_IRQHandler
def_irq_handler Reserved118_IRQHandler
def_irq_handler Reserved119_IRQHandler
def_irq_handler LTC0_IRQHandler
def_irq_handler Reserved121_IRQHandler
def_irq_handler Reserved122_IRQHandler
.end

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/*
** ###################################################################
** Processors: MK82FN256CAx15
** MK82FN256VDC15
** MK82FN256VLL15
** MK82FN256VLQ15
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
** Version: rev. 1.2, 2015-07-29
** Build: b160406
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
define symbol __ram_vector_table__ = 1;
/* Heap 1/4 of ram and stack 1/8 */
define symbol __stack_size__=0x8000;
define symbol __heap_size__=0x10000;
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003C0 : 0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003BF : 0;
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003BF;
define symbol m_bootloader_config_start = 0x000003C0;
define symbol m_bootloader_config_end = 0x000003FF;
define symbol m_flash_config_start = 0x00000400;
define symbol m_flash_config_end = 0x0000040F;
define symbol m_text_start = 0x00000410;
define symbol m_text_end = 0x0003FFFF;
define symbol m_interrupts_ram_start = 0x1FFF0000;
define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__;
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end = 0x1FFFFFFF;
define symbol m_data_2_start = 0x20000000;
define symbol m_data_2_end = 0x2002FFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define memory mem with size = 4G;
define region m_bootloader_config_region = mem:[from m_bootloader_config_start to m_bootloader_config_end];
define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end]
| mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in m_bootloader_config_region { section BootloaderConfig };
place in m_flash_config_region { section FlashConfig };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };
place in m_interrupts_ram_region { section m_interrupts_ram };

816
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; ---------------------------------------------------------------------------------------
; @file: startup_MK82F25615.s
; @purpose: CMSIS Cortex-M4 Core Device Startup File
; MK82F25615
; @version: 1.0
; @date: 2015-4-9
; @build: b151210
; ---------------------------------------------------------------------------------------
;
; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification,
; are permitted provided that the following conditions are met:
;
; o Redistributions of source code must retain the above copyright notice, this list
; of conditions and the following disclaimer.
;
; o Redistributions in binary form must reproduce the above copyright notice, this
; list of conditions and the following disclaimer in the documentation and/or
; other materials provided with the distribution.
;
; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
__vector_table_0x1c
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA channel 0,16 transfer complete
DCD DMA1_DMA17_IRQHandler ;DMA channel 1,17 transfer complete
DCD DMA2_DMA18_IRQHandler ;DMA channel 2,18 transfer complete
DCD DMA3_DMA19_IRQHandler ;DMA channel 3,19 transfer complete
DCD DMA4_DMA20_IRQHandler ;DMA channel 4,20 transfer complete
DCD DMA5_DMA21_IRQHandler ;DMA channel 5,21 transfer complete
DCD DMA6_DMA22_IRQHandler ;DMA channel 6,22 transfer complete
DCD DMA7_DMA23_IRQHandler ;DMA channel 7,23 transfer complete
DCD DMA8_DMA24_IRQHandler ;DMA channel 8,24 transfer complete
DCD DMA9_DMA25_IRQHandler ;DMA channel 9,25 transfer complete
DCD DMA10_DMA26_IRQHandler ;DMA channel 10,26 transfer complete
DCD DMA11_DMA27_IRQHandler ;DMA channel 11,27 transfer complete
DCD DMA12_DMA28_IRQHandler ;DMA channel 12,28 transfer complete
DCD DMA13_DMA29_IRQHandler ;DMA channel 13,29 transfer complete
DCD DMA14_DMA30_IRQHandler ;DMA channel 14,30 transfer complete
DCD DMA15_DMA31_IRQHandler ;DMA channel 15,31 transfer complete
DCD DMA_Error_IRQHandler ;DMA channel 0 - 31 error
DCD MCM_IRQHandler ;MCM normal interrupt
DCD FTFA_IRQHandler ;FTFA command complete
DCD Read_Collision_IRQHandler ;FTFA read collision
DCD LVD_LVW_IRQHandler ;PMC controller low-voltage detect, low-voltage warning
DCD LLWU_IRQHandler ;Low leakage wakeup unit
DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM
DCD TRNG0_IRQHandler ;True randon number generator
DCD I2C0_IRQHandler ;Inter-integrated circuit 0
DCD I2C1_IRQHandler ;Inter-integrated circuit 1
DCD SPI0_IRQHandler ;Serial peripheral Interface 0
DCD SPI1_IRQHandler ;Serial peripheral Interface 1
DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt
DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt
DCD LPUART0_IRQHandler ;LPUART0 receive/transmit/error interrupt
DCD LPUART1_IRQHandler ;LPUART1 receive/transmit/error interrupt
DCD LPUART2_IRQHandler ;LPUART2 receive/transmit/error interrupt
DCD LPUART3_IRQHandler ;LPUART3 receive/transmit/error interrupt
DCD LPUART4_IRQHandler ;LPUART4 receive/transmit/error interrupt
DCD Reserved51_IRQHandler ;Reserved interrupt
DCD Reserved52_IRQHandler ;Reserved interrupt
DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt
DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt
DCD ADC0_IRQHandler ;Analog-to-digital converter 0
DCD CMP0_IRQHandler ;Comparator 0
DCD CMP1_IRQHandler ;Comparator 1
DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ;Carrier modulator transmitter
DCD RTC_IRQHandler ;Real time clock
DCD RTC_Seconds_IRQHandler ;Real time clock seconds
DCD PIT0CH0_IRQHandler ;Periodic interrupt timer 0 channel 0
DCD PIT0CH1_IRQHandler ;Periodic interrupt timer 0 channel 1
DCD PIT0CH2_IRQHandler ;Periodic interrupt timer 0 channel 2
DCD PIT0CH3_IRQHandler ;Periodic interrupt timer 0 channel 3
DCD PDB0_IRQHandler ;Programmable delay block
DCD USB0_IRQHandler ;USB OTG interrupt
DCD USBDCD_IRQHandler ;USB charger detect
DCD Reserved71_IRQHandler ;Reserved interrupt
DCD DAC0_IRQHandler ;Digital-to-analog converter 0
DCD MCG_IRQHandler ;Multipurpose clock generator
DCD LPTMR0_LPTMR1_IRQHandler ;Single interrupt vector for Low Power Timer 0 and 1
DCD PORTA_IRQHandler ;Port A pin detect interrupt
DCD PORTB_IRQHandler ;Port B pin detect interrupt
DCD PORTC_IRQHandler ;Port C pin detect interrupt
DCD PORTD_IRQHandler ;Port D pin detect interrupt
DCD PORTE_IRQHandler ;Port E pin detect interrupt
DCD SWI_IRQHandler ;Software interrupt
DCD SPI2_IRQHandler ;Serial peripheral Interface 2
DCD Reserved82_IRQHandler ;Reserved interrupt
DCD Reserved83_IRQHandler ;Reserved interrupt
DCD Reserved84_IRQHandler ;Reserved interrupt
DCD Reserved85_IRQHandler ;Reserved interrupt
DCD FLEXIO0_IRQHandler ;FLEXIO0
DCD FTM3_IRQHandler ;FlexTimer module 3 fault, overflow and channels interrupt
DCD Reserved88_IRQHandler ;Reserved interrupt
DCD Reserved89_IRQHandler ;Reserved interrupt
DCD I2C2_IRQHandler ;Inter-integrated circuit 2
DCD Reserved91_IRQHandler ;Reserved interrupt
DCD Reserved92_IRQHandler ;Reserved interrupt
DCD Reserved93_IRQHandler ;Reserved interrupt
DCD Reserved94_IRQHandler ;Reserved interrupt
DCD Reserved95_IRQHandler ;Reserved interrupt
DCD Reserved96_IRQHandler ;Reserved interrupt
DCD SDHC_IRQHandler ;Secured digital host controller
DCD Reserved98_IRQHandler ;Reserved interrupt
DCD Reserved99_IRQHandler ;Reserved interrupt
DCD Reserved100_IRQHandler ;Reserved interrupt
DCD Reserved101_IRQHandler ;Reserved interrupt
DCD Reserved102_IRQHandler ;Reserved interrupt
DCD TSI0_IRQHandler ;Touch Sensing Input
DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
DCD Reserved106_IRQHandler ;Reserved interrupt
DCD I2C3_IRQHandler ;Inter-integrated circuit 3
DCD Reserved108_IRQHandler ;Reserved interrupt
DCD Reserved109_IRQHandler ;Reserved interrupt
DCD Reserved110_IRQHandler ;Reserved interrupt
DCD Reserved111_IRQHandler ;Reserved interrupt
DCD Reserved112_IRQHandler ;Reserved interrupt
DCD Reserved113_IRQHandler ;Reserved interrupt
DCD Reserved114_IRQHandler ;Reserved interrupt
DCD Reserved115_IRQHandler ;Reserved interrupt
DCD QuadSPI0_IRQHandler ;qspi
DCD Reserved117_IRQHandler ;Reserved interrupt
DCD Reserved118_IRQHandler ;Reserved interrupt
DCD Reserved119_IRQHandler ;Reserved interrupt
DCD LTC0_IRQHandler ;LP Trusted Cryptography
DCD Reserved121_IRQHandler ;Reserved interrupt
DCD Reserved122_IRQHandler ;Reserved interrupt
DCD DefaultISR ;123
DCD DefaultISR ;124
DCD DefaultISR ;125
DCD DefaultISR ;126
DCD DefaultISR ;127
DCD DefaultISR ;128
DCD DefaultISR ;129
DCD DefaultISR ;130
DCD DefaultISR ;131
DCD DefaultISR ;132
DCD DefaultISR ;133
DCD DefaultISR ;134
DCD DefaultISR ;135
DCD DefaultISR ;136
DCD DefaultISR ;137
DCD DefaultISR ;138
DCD DefaultISR ;139
DCD DefaultISR ;140
DCD DefaultISR ;141
DCD DefaultISR ;142
DCD DefaultISR ;143
DCD DefaultISR ;144
DCD DefaultISR ;145
DCD DefaultISR ;146
DCD DefaultISR ;147
DCD DefaultISR ;148
DCD DefaultISR ;149
DCD DefaultISR ;150
DCD DefaultISR ;151
DCD DefaultISR ;152
DCD DefaultISR ;153
DCD DefaultISR ;154
DCD DefaultISR ;155
DCD DefaultISR ;156
DCD DefaultISR ;157
DCD DefaultISR ;158
DCD DefaultISR ;159
DCD DefaultISR ;160
DCD DefaultISR ;161
DCD DefaultISR ;162
DCD DefaultISR ;163
DCD DefaultISR ;164
DCD DefaultISR ;165
DCD DefaultISR ;166
DCD DefaultISR ;167
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
__Vectors_End
SECTION FlashConfig:CODE
__FlashConfig
DCD 0xFFFFFFFF
DCD 0xFFFFFFFF
DCD 0xFFFFFFFF
DCD 0xFFFF3DFE
__FlashConfig_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__vector_table
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
CPSIE I ; Unmask interrupts
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B .
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B .
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
PUBWEAK DMA0_DMA16_IRQHandler
PUBWEAK DMA0_DMA16_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA0_DMA16_IRQHandler
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
PUBWEAK DMA1_DMA17_IRQHandler
PUBWEAK DMA1_DMA17_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA1_DMA17_IRQHandler
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
PUBWEAK DMA2_DMA18_IRQHandler
PUBWEAK DMA2_DMA18_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA2_DMA18_IRQHandler
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
PUBWEAK DMA3_DMA19_IRQHandler
PUBWEAK DMA3_DMA19_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA3_DMA19_IRQHandler
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
PUBWEAK DMA4_DMA20_IRQHandler
PUBWEAK DMA4_DMA20_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA4_DMA20_IRQHandler
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
PUBWEAK DMA5_DMA21_IRQHandler
PUBWEAK DMA5_DMA21_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA5_DMA21_IRQHandler
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
PUBWEAK DMA6_DMA22_IRQHandler
PUBWEAK DMA6_DMA22_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA6_DMA22_IRQHandler
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
PUBWEAK DMA7_DMA23_IRQHandler
PUBWEAK DMA7_DMA23_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA7_DMA23_IRQHandler
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
PUBWEAK DMA8_DMA24_IRQHandler
PUBWEAK DMA8_DMA24_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA8_DMA24_IRQHandler
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
PUBWEAK DMA9_DMA25_IRQHandler
PUBWEAK DMA9_DMA25_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA9_DMA25_IRQHandler
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
PUBWEAK DMA10_DMA26_IRQHandler
PUBWEAK DMA10_DMA26_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA10_DMA26_IRQHandler
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
PUBWEAK DMA11_DMA27_IRQHandler
PUBWEAK DMA11_DMA27_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA11_DMA27_IRQHandler
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
PUBWEAK DMA12_DMA28_IRQHandler
PUBWEAK DMA12_DMA28_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA12_DMA28_IRQHandler
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
PUBWEAK DMA13_DMA29_IRQHandler
PUBWEAK DMA13_DMA29_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA13_DMA29_IRQHandler
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
PUBWEAK DMA14_DMA30_IRQHandler
PUBWEAK DMA14_DMA30_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA14_DMA30_IRQHandler
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
PUBWEAK DMA15_DMA31_IRQHandler
PUBWEAK DMA15_DMA31_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA15_DMA31_IRQHandler
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
PUBWEAK DMA_Error_IRQHandler
PUBWEAK DMA_Error_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA_Error_IRQHandler
LDR R0, =DMA_Error_DriverIRQHandler
BX R0
PUBWEAK MCM_IRQHandler
PUBWEAK FTFA_IRQHandler
PUBWEAK Read_Collision_IRQHandler
PUBWEAK LVD_LVW_IRQHandler
PUBWEAK LLWU_IRQHandler
PUBWEAK WDOG_EWM_IRQHandler
PUBWEAK TRNG0_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C0_IRQHandler
LDR R0, =I2C0_DriverIRQHandler
BX R0
PUBWEAK I2C1_IRQHandler
PUBWEAK I2C1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C1_IRQHandler
LDR R0, =I2C1_DriverIRQHandler
BX R0
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPI0_IRQHandler
LDR R0, =SPI0_DriverIRQHandler
BX R0
PUBWEAK SPI1_IRQHandler
PUBWEAK SPI1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPI1_IRQHandler
LDR R0, =SPI1_DriverIRQHandler
BX R0
PUBWEAK I2S0_Tx_IRQHandler
PUBWEAK I2S0_Tx_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2S0_Tx_IRQHandler
LDR R0, =I2S0_Tx_DriverIRQHandler
BX R0
PUBWEAK I2S0_Rx_IRQHandler
PUBWEAK I2S0_Rx_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2S0_Rx_IRQHandler
LDR R0, =I2S0_Rx_DriverIRQHandler
BX R0
PUBWEAK LPUART0_IRQHandler
PUBWEAK LPUART0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART0_IRQHandler
LDR R0, =LPUART0_DriverIRQHandler
BX R0
PUBWEAK LPUART1_IRQHandler
PUBWEAK LPUART1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART1_IRQHandler
LDR R0, =LPUART1_DriverIRQHandler
BX R0
PUBWEAK LPUART2_IRQHandler
PUBWEAK LPUART2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART2_IRQHandler
LDR R0, =LPUART2_DriverIRQHandler
BX R0
PUBWEAK LPUART3_IRQHandler
PUBWEAK LPUART3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART3_IRQHandler
LDR R0, =LPUART3_DriverIRQHandler
BX R0
PUBWEAK LPUART4_IRQHandler
PUBWEAK LPUART4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART4_IRQHandler
LDR R0, =LPUART4_DriverIRQHandler
BX R0
PUBWEAK Reserved51_IRQHandler
PUBWEAK Reserved52_IRQHandler
PUBWEAK EMVSIM0_IRQHandler
PUBWEAK EMVSIM1_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK CMP0_IRQHandler
PUBWEAK CMP1_IRQHandler
PUBWEAK FTM0_IRQHandler
PUBWEAK FTM1_IRQHandler
PUBWEAK FTM2_IRQHandler
PUBWEAK CMT_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK RTC_Seconds_IRQHandler
PUBWEAK PIT0CH0_IRQHandler
PUBWEAK PIT0CH1_IRQHandler
PUBWEAK PIT0CH2_IRQHandler
PUBWEAK PIT0CH3_IRQHandler
PUBWEAK PDB0_IRQHandler
PUBWEAK USB0_IRQHandler
PUBWEAK USBDCD_IRQHandler
PUBWEAK Reserved71_IRQHandler
PUBWEAK DAC0_IRQHandler
PUBWEAK MCG_IRQHandler
PUBWEAK LPTMR0_LPTMR1_IRQHandler
PUBWEAK PORTA_IRQHandler
PUBWEAK PORTB_IRQHandler
PUBWEAK PORTC_IRQHandler
PUBWEAK PORTD_IRQHandler
PUBWEAK PORTE_IRQHandler
PUBWEAK SWI_IRQHandler
PUBWEAK SPI2_IRQHandler
PUBWEAK SPI2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPI2_IRQHandler
LDR R0, =SPI2_DriverIRQHandler
BX R0
PUBWEAK Reserved82_IRQHandler
PUBWEAK Reserved83_IRQHandler
PUBWEAK Reserved84_IRQHandler
PUBWEAK Reserved85_IRQHandler
PUBWEAK FLEXIO0_IRQHandler
PUBWEAK FLEXIO0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXIO0_IRQHandler
LDR R0, =FLEXIO0_DriverIRQHandler
BX R0
PUBWEAK FTM3_IRQHandler
PUBWEAK Reserved88_IRQHandler
PUBWEAK Reserved89_IRQHandler
PUBWEAK I2C2_IRQHandler
PUBWEAK I2C2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C2_IRQHandler
LDR R0, =I2C2_DriverIRQHandler
BX R0
PUBWEAK Reserved91_IRQHandler
PUBWEAK Reserved92_IRQHandler
PUBWEAK Reserved93_IRQHandler
PUBWEAK Reserved94_IRQHandler
PUBWEAK Reserved95_IRQHandler
PUBWEAK Reserved96_IRQHandler
PUBWEAK SDHC_IRQHandler
PUBWEAK SDHC_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SDHC_IRQHandler
LDR R0, =SDHC_DriverIRQHandler
BX R0
PUBWEAK Reserved98_IRQHandler
PUBWEAK Reserved99_IRQHandler
PUBWEAK Reserved100_IRQHandler
PUBWEAK Reserved101_IRQHandler
PUBWEAK Reserved102_IRQHandler
PUBWEAK TSI0_IRQHandler
PUBWEAK TPM1_IRQHandler
PUBWEAK TPM2_IRQHandler
PUBWEAK Reserved106_IRQHandler
PUBWEAK I2C3_IRQHandler
PUBWEAK I2C3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C3_IRQHandler
LDR R0, =I2C3_DriverIRQHandler
BX R0
PUBWEAK Reserved108_IRQHandler
PUBWEAK Reserved109_IRQHandler
PUBWEAK Reserved110_IRQHandler
PUBWEAK Reserved111_IRQHandler
PUBWEAK Reserved112_IRQHandler
PUBWEAK Reserved113_IRQHandler
PUBWEAK Reserved114_IRQHandler
PUBWEAK Reserved115_IRQHandler
PUBWEAK QuadSPI0_IRQHandler
PUBWEAK QuadSPI0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
QuadSPI0_IRQHandler
LDR R0, =QuadSPI0_DriverIRQHandler
BX R0
PUBWEAK Reserved117_IRQHandler
PUBWEAK Reserved118_IRQHandler
PUBWEAK Reserved119_IRQHandler
PUBWEAK LTC0_IRQHandler
PUBWEAK Reserved121_IRQHandler
PUBWEAK Reserved122_IRQHandler
PUBWEAK DefaultISR
SECTION .text:CODE:REORDER:NOROOT(1)
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_Error_DriverIRQHandler
MCM_IRQHandler
FTFA_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLWU_IRQHandler
WDOG_EWM_IRQHandler
TRNG0_IRQHandler
I2C0_DriverIRQHandler
I2C1_DriverIRQHandler
SPI0_DriverIRQHandler
SPI1_DriverIRQHandler
I2S0_Tx_DriverIRQHandler
I2S0_Rx_DriverIRQHandler
LPUART0_DriverIRQHandler
LPUART1_DriverIRQHandler
LPUART2_DriverIRQHandler
LPUART3_DriverIRQHandler
LPUART4_DriverIRQHandler
Reserved51_IRQHandler
Reserved52_IRQHandler
EMVSIM0_IRQHandler
EMVSIM1_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
FTM2_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0CH0_IRQHandler
PIT0CH1_IRQHandler
PIT0CH2_IRQHandler
PIT0CH3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
Reserved71_IRQHandler
DAC0_IRQHandler
MCG_IRQHandler
LPTMR0_LPTMR1_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
SPI2_DriverIRQHandler
Reserved82_IRQHandler
Reserved83_IRQHandler
Reserved84_IRQHandler
Reserved85_IRQHandler
FLEXIO0_DriverIRQHandler
FTM3_IRQHandler
Reserved88_IRQHandler
Reserved89_IRQHandler
I2C2_DriverIRQHandler
Reserved91_IRQHandler
Reserved92_IRQHandler
Reserved93_IRQHandler
Reserved94_IRQHandler
Reserved95_IRQHandler
Reserved96_IRQHandler
SDHC_DriverIRQHandler
Reserved98_IRQHandler
Reserved99_IRQHandler
Reserved100_IRQHandler
Reserved101_IRQHandler
Reserved102_IRQHandler
TSI0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
Reserved106_IRQHandler
I2C3_DriverIRQHandler
Reserved108_IRQHandler
Reserved109_IRQHandler
Reserved110_IRQHandler
Reserved111_IRQHandler
Reserved112_IRQHandler
Reserved113_IRQHandler
Reserved114_IRQHandler
Reserved115_IRQHandler
QuadSPI0_DriverIRQHandler
Reserved117_IRQHandler
Reserved118_IRQHandler
Reserved119_IRQHandler
LTC0_IRQHandler
Reserved121_IRQHandler
Reserved122_IRQHandler
DefaultISR
B DefaultISR
END

0
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/device/cmsis.h → targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/cmsis.h
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42
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/cmsis_nvic.c Normal file
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@ -0,0 +1,42 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis_nvic.h"
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
InstallIRQHandler(IRQn, vector);
}
uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

51
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/cmsis_nvic.h Normal file
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@ -0,0 +1,51 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 107) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t __NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

57
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/fsl_device_registers.h Normal file
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@ -0,0 +1,57 @@
/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_DEVICE_REGISTERS_H__
#define __FSL_DEVICE_REGISTERS_H__
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
defined(CPU_MK82FN256VLQ15))
#define K82F25615_SERIES
/* CMSIS-style register definitions */
#include "MK82F25615.h"
/* CPU specific feature definitions */
#include "MK82F25615_features.h"
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DEVICE_REGISTERS_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

221
targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/system_MK82F25615.c Normal file
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@ -0,0 +1,221 @@
/*
** ###################################################################
** Processors: MK82FN256CAx15
** MK82FN256VDC15
** MK82FN256VLL15
** MK82FN256VLQ15
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
** Version: rev. 1.2, 2015-07-29
** Build: b151216
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2015-04-09)
** Initial version
** - rev. 1.1 (2015-05-28)
** Update according to the reference manual Rev. 0.
** - rev. 1.2 (2015-07-29)
** Correction of backward compatibility.
**
** ###################################################################
*/
/*!
* @file MK82F25615
* @version 1.2
* @date 2015-07-29
* @brief Device specific configuration file for MK82F25615 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "fsl_device_registers.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#endif /* (DISABLE_WDOG) */
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint16_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
case 0x38U:
Divider = 1536U;
break;
case 0x30U:
Divider = 1280U;
break;
default:
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
break;
}
} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
}
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x00U:
MCGOUTClock *= 640U;
break;
case 0x20U:
MCGOUTClock *= 1280U;
break;
case 0x40U:
MCGOUTClock *= 1920U;
break;
case 0x60U:
MCGOUTClock *= 2560U;
break;
case 0x80U:
MCGOUTClock *= 732U;
break;
case 0xA0U:
MCGOUTClock *= 1464U;
break;
case 0xC0U:
MCGOUTClock *= 2197U;
break;
case 0xE0U:
MCGOUTClock *= 2929U;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
/* PLL is selected */
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
MCGOUTClock *= Divider; /* Calculate the VCO output clock */
MCGOUTClock /= 2; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

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/*
** ###################################################################
** Processors: MK82FN256CAx15
** MK82FN256VDC15
** MK82FN256VLL15
** MK82FN256VLQ15
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
** Version: rev. 1.2, 2015-07-29
** Build: b151216
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2015-04-09)
** Initial version
** - rev. 1.1 (2015-05-28)
** Update according to the reference manual Rev. 0.
** - rev. 1.2 (2015-07-29)
** Correction of backward compatibility.
**
** ###################################################################
*/
/*!
* @file MK82F25615
* @version 1.2
* @date 2015-07-29
* @brief Device specific configuration file for MK82F25615 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_MK82F25615_H_
#define _SYSTEM_MK82F25615_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
#define CPU_XTAL32k_CLK_HZ 32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
/* RTC oscillator setting */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
#define DEFAULT_SYSTEM_CLOCK 20971520u
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MK82F25615_H_ */

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_adc16.h"
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for ADC16 module.
*
* @param base ADC16 peripheral base address
*/
static uint32_t ADC16_GetInstance(ADC_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to ADC16 bases for each instance. */
static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to ADC16 clocks for each instance. */
static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t ADC16_GetInstance(ADC_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++)
{
if (s_adc16Bases[instance] == base)
{
break;
}
}
assert(instance < FSL_FEATURE_SOC_ADC16_COUNT);
return instance;
}
void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
{
assert(NULL != config);
uint32_t tmp32;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* ADCx_CFG1. */
tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
if (kADC16_LongSampleDisabled != config->longSampleMode)
{
tmp32 |= ADC_CFG1_ADLSMP_MASK;
}
tmp32 |= ADC_CFG1_ADIV(config->clockDivider);
if (config->enableLowPower)
{
tmp32 |= ADC_CFG1_ADLPC_MASK;
}
base->CFG1 = tmp32;
/* ADCx_CFG2. */
tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK);
if (kADC16_LongSampleDisabled != config->longSampleMode)
{
tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode);
}
if (config->enableHighSpeed)
{
tmp32 |= ADC_CFG2_ADHSC_MASK;
}
if (config->enableAsynchronousClock)
{
tmp32 |= ADC_CFG2_ADACKEN_MASK;
}
base->CFG2 = tmp32;
/* ADCx_SC2. */
tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK);
tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource);
base->SC2 = tmp32;
/* ADCx_SC3. */
if (config->enableContinuousConversion)
{
base->SC3 |= ADC_SC3_ADCO_MASK;
}
else
{
base->SC3 &= ~ADC_SC3_ADCO_MASK;
}
}
void ADC16_Deinit(ADC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void ADC16_GetDefaultConfig(adc16_config_t *config)
{
assert(NULL != config);
config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
config->clockSource = kADC16_ClockSourceAsynchronousClock;
config->enableAsynchronousClock = true;
config->clockDivider = kADC16_ClockDivider8;
config->resolution = kADC16_ResolutionSE12Bit;
config->longSampleMode = kADC16_LongSampleDisabled;
config->enableHighSpeed = false;
config->enableLowPower = false;
config->enableContinuousConversion = false;
}
#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
status_t ADC16_DoAutoCalibration(ADC_Type *base)
{
bool bHWTrigger = false;
volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */
status_t status = kStatus_Success;
/* The calibration would be failed when in hardwar mode.
* Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
if (0U != (ADC_SC2_ADTRG_MASK & base->SC2))
{
bHWTrigger = true;
base->SC2 &= ~ADC_SC2_ADTRG_MASK;
}
/* Clear the CALF and launch the calibration. */
base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK;
while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U)))
{
/* Check the CALF when the calibration is active. */
if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
{
status = kStatus_Fail;
break;
}
}
tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */
/* Restore the hardware trigger setting if it was enabled before. */
if (bHWTrigger)
{
base->SC2 |= ADC_SC2_ADTRG_MASK;
}
/* Check the CALF at the end of calibration. */
if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
{
status = kStatus_Fail;
}
if (kStatus_Success != status) /* Check if the calibration process is succeed. */
{
return status;
}
/* Calculate the calibration values. */
tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS;
tmp32 = 0x8000U | (tmp32 >> 1U);
base->PG = tmp32;
#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS;
tmp32 = 0x8000U | (tmp32 >> 1U);
base->MG = tmp32;
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
return kStatus_Success;
}
#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode)
{
if (kADC16_ChannelMuxA == mode)
{
base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK;
}
else /* kADC16_ChannelMuxB. */
{
base->CFG2 |= ADC_CFG2_MUXSEL_MASK;
}
}
#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config)
{
uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK);
if (!config) /* Pass "NULL" to disable the feature. */
{
base->SC2 = tmp32;
return;
}
/* Enable the feature. */
tmp32 |= ADC_SC2_ACFE_MASK;
/* Select the hardware compare working mode. */
switch (config->hardwareCompareMode)
{
case kADC16_HardwareCompareMode0:
break;
case kADC16_HardwareCompareMode1:
tmp32 |= ADC_SC2_ACFGT_MASK;
break;
case kADC16_HardwareCompareMode2:
tmp32 |= ADC_SC2_ACREN_MASK;
break;
case kADC16_HardwareCompareMode3:
tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK;
break;
default:
break;
}
base->SC2 = tmp32;
/* Load the compare values. */
base->CV1 = ADC_CV1_CV(config->value1);
base->CV2 = ADC_CV2_CV(config->value2);
}
#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode)
{
uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
if (kADC16_HardwareAverageDisabled != mode)
{
tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode);
}
base->SC3 = tmp32;
}
#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config)
{
uint32_t tmp32;
if (!config) /* Passing "NULL" is to disable the feature. */
{
base->PGA = 0U;
return;
}
/* Enable the PGA and set the gain value. */
tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain);
/* Configure the misc features for PGA. */
if (config->enableRunInNormalMode)
{
tmp32 |= ADC_PGA_PGALPb_MASK;
}
#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
if (config->disablePgaChopping)
{
tmp32 |= ADC_PGA_PGACHPb_MASK;
}
#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
if (config->enableRunInOffsetMeasurement)
{
tmp32 |= ADC_PGA_PGAOFSM_MASK;
}
#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
base->PGA = tmp32;
}
#endif /* FSL_FEATURE_ADC16_HAS_PGA */
uint32_t ADC16_GetStatusFlags(ADC_Type *base)
{
uint32_t ret = 0;
if (0U != (base->SC2 & ADC_SC2_ADACT_MASK))
{
ret |= kADC16_ActiveFlag;
}
#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
if (0U != (base->SC3 & ADC_SC3_CALF_MASK))
{
ret |= kADC16_CalibrationFailedFlag;
}
#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
return ret;
}
void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask)
{
#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
if (0U != (mask & kADC16_CalibrationFailedFlag))
{
base->SC3 |= ADC_SC3_CALF_MASK;
}
#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
}
void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config)
{
assert(channelGroup < ADC_SC1_COUNT);
assert(NULL != config);
uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */
#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
/* Enable the differential conversion. */
if (config->enableDifferentialConversion)
{
sc1 |= ADC_SC1_DIFF_MASK;
}
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
/* Enable the interrupt when the conversion is done. */
if (config->enableInterruptOnConversionCompleted)
{
sc1 |= ADC_SC1_AIEN_MASK;
}
base->SC1[channelGroup] = sc1;
}
uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
{
assert(channelGroup < ADC_SC1_COUNT);
uint32_t ret = 0U;
if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK))
{
ret |= kADC16_ChannelConversionDoneFlag;
}
return ret;
}

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_ADC16_H_
#define _FSL_ADC16_H_
#include "fsl_common.h"
/*!
* @addtogroup adc16
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief ADC16 driver version 2.0.0. */
#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*!
* @brief Channel status flags.
*/
enum _adc16_channel_status_flags
{
kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */
};
/*!
* @brief Converter status flags.
*/
enum _adc16_status_flags
{
kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */
#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */
#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
};
#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
/*!
* @brief Channel multiplexer mode for each channel.
*
* For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
* are the different channels that share the same channel number.
*/
typedef enum _adc_channel_mux_mode
{
kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */
kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */
} adc16_channel_mux_mode_t;
#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
/*!
* @brief Clock divider for the converter.
*/
typedef enum _adc16_clock_divider
{
kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */
kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */
kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */
kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */
} adc16_clock_divider_t;
/*!
*@brief Converter's resolution.
*/
typedef enum _adc16_resolution
{
/* This group of enumeration is for internal use which is related to register setting. */
kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */
kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
/* This group of enumeration is for a public user. */
kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */
kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */
kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */
kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
/* 16-bit is supported by default. */
kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */
kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */
#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */
} adc16_resolution_t;
/*!
* @brief Clock source.
*/
typedef enum _adc16_clock_source
{
kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */
kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */
kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */
kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */
/* Chip defined clock source */
kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */
} adc16_clock_source_t;
/*!
* @brief Long sample mode.
*/
typedef enum _adc16_long_sample_mode
{
kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */
} adc16_long_sample_mode_t;
/*!
* @brief Reference voltage source.
*/
typedef enum _adc16_reference_voltage_source
{
kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */
} adc16_reference_voltage_source_t;
#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
/*!
* @brief Hardware average mode.
*/
typedef enum _adc16_hardware_average_mode
{
kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/
} adc16_hardware_average_mode_t;
#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
/*!
* @brief Hardware compare mode.
*/
typedef enum _adc16_hardware_compare_mode
{
kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */
kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */
kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2;
else, value1 > x > value2. */
kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2;
else x >= value1 || x <= value2. */
} adc16_hardware_compare_mode_t;
#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
/*!
* @brief PGA's Gain mode.
*/
typedef enum _adc16_pga_gain
{
kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */
kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */
kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */
kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */
kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */
kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */
kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */
} adc16_pga_gain_t;
#endif /* FSL_FEATURE_ADC16_HAS_PGA */
/*!
* @brief ADC16 converter configuration.
*/
typedef struct _adc16_config
{
adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */
bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */
adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */
adc16_resolution_t resolution; /*!< Select the sample resolution mode. */
adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */
bool enableHighSpeed; /*!< Enable the high-speed mode. */
bool enableLowPower; /*!< Enable low power. */
bool enableContinuousConversion; /*!< Enable continuous conversion mode. */
} adc16_config_t;
/*!
* @brief ADC16 Hardware comparison configuration.
*/
typedef struct _adc16_hardware_compare_config
{
adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
See "adc16_hardware_compare_mode_t". */
int16_t value1; /*!< Setting value1 for hardware compare mode. */
int16_t value2; /*!< Setting value2 for hardware compare mode. */
} adc16_hardware_compare_config_t;
/*!
* @brief ADC16 channel conversion configuration.
*/
typedef struct _adc16_channel_config
{
uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
See channel connection information for each chip in Reference
Manual document. */
bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
bool enableDifferentialConversion; /*!< Using Differential sample mode. */
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
} adc16_channel_config_t;
#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
/*!
* @brief ADC16 programmable gain amplifier configuration.
*/
typedef struct _adc16_pga_config
{
adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */
bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */
#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
bool disablePgaChopping; /*!< Disable the PGA chopping function.
The PGA employs chopping to remove/reduce offset and 1/f noise and offers
an offset measurement configuration that aids the offset calibration. */
#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode.
When this feature is enabled, the PGA disconnects itself from the external
inputs and auto-configures into offset measurement mode. With this field
set, run the ADC in the recommended settings and enable the maximum hardware
averaging to get the PGA offset number. The output is the
(PGA offset * (64+1)) for the given PGA setting. */
#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
} adc16_pga_config_t;
#endif /* FSL_FEATURE_ADC16_HAS_PGA */
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* API
******************************************************************************/
/*!
* @name Initialization
* @{
*/
/*!
* @brief Initializes the ADC16 module.
*
* @param base ADC16 peripheral base address.
* @param config Pointer to configuration structure. See "adc16_config_t".
*/
void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
/*!
* @brief De-initializes the ADC16 module.
*
* @param base ADC16 peripheral base address.
*/
void ADC16_Deinit(ADC_Type *base);
/*!
* @brief Gets an available pre-defined settings for the converter's configuration.
*
* This function initializes the converter configuration structure with available settings. The default values are as follows.
* @code
* config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
* config->clockSource = kADC16_ClockSourceAsynchronousClock;
* config->enableAsynchronousClock = true;
* config->clockDivider = kADC16_ClockDivider8;
* config->resolution = kADC16_ResolutionSE12Bit;
* config->longSampleMode = kADC16_LongSampleDisabled;
* config->enableHighSpeed = false;
* config->enableLowPower = false;
* config->enableContinuousConversion = false;
* @endcode
* @param config Pointer to the configuration structure.
*/
void ADC16_GetDefaultConfig(adc16_config_t *config);
#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
/*!
* @brief Automates the hardware calibration.
*
* This auto calibration helps to adjust the plus/minus side gain automatically.
* Execute the calibration before using the converter. Note that the hardware trigger should be used
* during the calibration.
*
* @param base ADC16 peripheral base address.
*
* @return Execution status.
* @retval kStatus_Success Calibration is done successfully.
* @retval kStatus_Fail Calibration has failed.
*/
status_t ADC16_DoAutoCalibration(ADC_Type *base);
#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
/*!
* @brief Sets the offset value for the conversion result.
*
* This offset value takes effect on the conversion result. If the offset value is not zero, the reading result
* is subtracted by it. Note, the hardware calibration fills the offset value automatically.
*
* @param base ADC16 peripheral base address.
* @param value Setting offset value.
*/
static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
{
base->OFS = (uint32_t)(value);
}
#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
/* @} */
/*!
* @name Advanced Features
* @{
*/
#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
/*!
* @brief Enables generating the DMA trigger when the conversion is complete.
*
* @param base ADC16 peripheral base address.
* @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
*/
static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
{
if (enable)
{
base->SC2 |= ADC_SC2_DMAEN_MASK;
}
else
{
base->SC2 &= ~ADC_SC2_DMAEN_MASK;
}
}
#endif /* FSL_FEATURE_ADC16_HAS_DMA */
/*!
* @brief Enables the hardware trigger mode.
*
* @param base ADC16 peripheral base address.
* @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled.
*/
static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
{
if (enable)
{
base->SC2 |= ADC_SC2_ADTRG_MASK;
}
else
{
base->SC2 &= ~ADC_SC2_ADTRG_MASK;
}
}
#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
/*!
* @brief Sets the channel mux mode.
*
* Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
* indicated channel.
*
* @param base ADC16 peripheral base address.
* @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
*/
void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
/*!
* @brief Configures the hardware compare mode.
*
* The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the result
* in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate reference
* manual for more information.
*
* @param base ADC16 peripheral base address.
* @param config Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature.
*/
void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
/*!
* @brief Sets the hardware average mode.
*
* The hardware average mode provides a way to process the conversion result automatically by using hardware. The multiple
* conversion results are accumulated and averaged internally making them easier to read.
*
* @param base ADC16 peripheral base address.
* @param mode Setting the hardware average mode. See "adc16_hardware_average_mode_t".
*/
void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
/*!
* @brief Configures the PGA for the converter's front end.
*
* @param base ADC16 peripheral base address.
* @param config Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature.
*/
void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
#endif /* FSL_FEATURE_ADC16_HAS_PGA */
/*!
* @brief Gets the status flags of the converter.
*
* @param base ADC16 peripheral base address.
*
* @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
*/
uint32_t ADC16_GetStatusFlags(ADC_Type *base);
/*!
* @brief Clears the status flags of the converter.
*
* @param base ADC16 peripheral base address.
* @param mask Mask value for the cleared flags. See "_adc16_status_flags".
*/
void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
/* @} */
/*!
* @name Conversion Channel
* @{
*/
/*!
* @brief Configures the conversion channel.
*
* This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
* configures the channel while the external trigger source helps to trigger the conversion.
*
* Note that the "Channel Group" has a detailed description.
* To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
* group of status and control registers, one for each conversion. The channel group parameter indicates which group of
* registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B registers. The
* channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
* the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and hardware
* trigger modes. Channel group 1 and greater indicates multiple channel group registers for
* use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for the
* number of SC1n registers (channel groups) specific to this device. Channel group 1 or greater are not used
* for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
* Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
* vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
* conversion aborts the current conversion.
*
* @param base ADC16 peripheral base address.
* @param channelGroup Channel group index.
* @param config Pointer to the "adc16_channel_config_t" structure for the conversion channel.
*/
void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
/*!
* @brief Gets the conversion value.
*
* @param base ADC16 peripheral base address.
* @param channelGroup Channel group index.
*
* @return Conversion value.
*/
static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
{
assert(channelGroup < ADC_R_COUNT);
return base->R[channelGroup];
}
/*!
* @brief Gets the status flags of channel.
*
* @param base ADC16 peripheral base address.
* @param channelGroup Channel group index.
*
* @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
*/
uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup);
/* @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_ADC16_H_ */

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_cmp.h"
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for CMP module.
*
* @param base CMP peripheral base address
*/
static uint32_t CMP_GetInstance(CMP_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to CMP bases for each instance. */
static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to CMP clocks for each instance. */
static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Codes
******************************************************************************/
static uint32_t CMP_GetInstance(CMP_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++)
{
if (s_cmpBases[instance] == base)
{
break;
}
}
assert(instance < FSL_FEATURE_SOC_CMP_COUNT);
return instance;
}
void CMP_Init(CMP_Type *base, const cmp_config_t *config)
{
assert(NULL != config);
uint8_t tmp8;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Configure. */
CMP_Enable(base, false); /* Disable the CMP module during configuring. */
/* CMPx_CR1. */
tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK);
if (config->enableHighSpeed)
{
tmp8 |= CMP_CR1_PMODE_MASK;
}
if (config->enableInvertOutput)
{
tmp8 |= CMP_CR1_INV_MASK;
}
if (config->useUnfilteredOutput)
{
tmp8 |= CMP_CR1_COS_MASK;
}
if (config->enablePinOut)
{
tmp8 |= CMP_CR1_OPE_MASK;
}
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
if (config->enableTriggerMode)
{
tmp8 |= CMP_CR1_TRIGM_MASK;
}
else
{
tmp8 &= ~CMP_CR1_TRIGM_MASK;
}
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
base->CR1 = tmp8;
/* CMPx_CR0. */
tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK;
tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
base->CR0 = tmp8;
CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
}
void CMP_Deinit(CMP_Type *base)
{
/* Disable the CMP module. */
CMP_Enable(base, false);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void CMP_GetDefaultConfig(cmp_config_t *config)
{
assert(NULL != config);
config->enableCmp = true; /* Enable the CMP module after initialization. */
config->hysteresisMode = kCMP_HysteresisLevel0;
config->enableHighSpeed = false;
config->enableInvertOutput = false;
config->useUnfilteredOutput = false;
config->enablePinOut = false;
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
config->enableTriggerMode = false;
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
}
void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
{
uint8_t tmp8 = base->MUXCR;
tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
base->MUXCR = tmp8;
}
#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
void CMP_EnableDMA(CMP_Type *base, bool enable)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
if (enable)
{
tmp8 |= CMP_SCR_DMAEN_MASK;
}
else
{
tmp8 &= ~CMP_SCR_DMAEN_MASK;
}
base->SCR = tmp8;
}
#endif /* FSL_FEATURE_CMP_HAS_DMA */
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
{
assert(NULL != config);
uint8_t tmp8;
#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
/* Choose the clock source for sampling. */
if (config->enableSample)
{
base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
}
else
{
base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */
}
#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
/* Set the filter count. */
tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
base->CR0 = tmp8;
/* Set the filter period. It is used as the divider to bus clock. */
base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
}
void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
{
uint8_t tmp8 = 0U;
if (NULL == config)
{
/* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/
base->DACCR = 0U;
return;
}
/* CMPx_DACCR. */
tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */
if (kCMP_VrefSourceVin2 == config->referenceVoltageSource)
{
tmp8 |= CMP_DACCR_VRSEL_MASK;
}
tmp8 |= CMP_DACCR_VOSEL(config->DACValue);
base->DACCR = tmp8;
}
void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
if (0U != (kCMP_OutputRisingInterruptEnable & mask))
{
tmp8 |= CMP_SCR_IER_MASK;
}
if (0U != (kCMP_OutputFallingInterruptEnable & mask))
{
tmp8 |= CMP_SCR_IEF_MASK;
}
base->SCR = tmp8;
}
void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
if (0U != (kCMP_OutputRisingInterruptEnable & mask))
{
tmp8 &= ~CMP_SCR_IER_MASK;
}
if (0U != (kCMP_OutputFallingInterruptEnable & mask))
{
tmp8 &= ~CMP_SCR_IEF_MASK;
}
base->SCR = tmp8;
}
uint32_t CMP_GetStatusFlags(CMP_Type *base)
{
uint32_t ret32 = 0U;
if (0U != (CMP_SCR_CFR_MASK & base->SCR))
{
ret32 |= kCMP_OutputRisingEventFlag;
}
if (0U != (CMP_SCR_CFF_MASK & base->SCR))
{
ret32 |= kCMP_OutputFallingEventFlag;
}
if (0U != (CMP_SCR_COUT_MASK & base->SCR))
{
ret32 |= kCMP_OutputAssertEventFlag;
}
return ret32;
}
void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
if (0U != (kCMP_OutputRisingEventFlag & mask))
{
tmp8 |= CMP_SCR_CFR_MASK;
}
if (0U != (kCMP_OutputFallingEventFlag & mask))
{
tmp8 |= CMP_SCR_CFF_MASK;
}
base->SCR = tmp8;
}

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_CMP_H_
#define _FSL_CMP_H_
#include "fsl_common.h"
/*!
* @addtogroup cmp
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CMP driver version 2.0.0. */
#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*!
* @brief Interrupt enable/disable mask.
*/
enum _cmp_interrupt_enable
{
kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */
kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */
};
/*!
* @brief Status flags' mask.
*/
enum _cmp_status_flags
{
kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */
kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */
kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
};
/*!
* @brief CMP Hysteresis mode.
*/
typedef enum _cmp_hysteresis_mode
{
kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */
kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */
kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */
kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */
} cmp_hysteresis_mode_t;
/*!
* @brief CMP Voltage Reference source.
*/
typedef enum _cmp_reference_voltage_source
{
kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */
kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */
} cmp_reference_voltage_source_t;
/*!
* @brief Configures the comparator.
*/
typedef struct _cmp_config
{
bool enableCmp; /*!< Enable the CMP module. */
cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */
bool enableHighSpeed; /*!< Enable High-speed (HS) comparison mode. */
bool enableInvertOutput; /*!< Enable the inverted comparator output. */
bool useUnfilteredOutput; /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */
bool enablePinOut; /*!< The comparator output is available on the associated pin. */
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
bool enableTriggerMode; /*!< Enable the trigger mode. */
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
} cmp_config_t;
/*!
* @brief Configures the filter.
*/
typedef struct _cmp_filter_config
{
#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
bool enableSample; /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */
#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/
uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */
} cmp_filter_config_t;
/*!
* @brief Configures the internal DAC.
*/
typedef struct _cmp_dac_config
{
cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
} cmp_dac_config_t;
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* API
******************************************************************************/
/*!
* @name Initialization
* @{
*/
/*!
* @brief Initializes the CMP.
*
* This function initializes the CMP module. The operations included are as follows.
* - Enabling the clock for CMP module.
* - Configuring the comparator.
* - Enabling the CMP module.
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
* any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
*
* @param base CMP peripheral base address.
* @param config Pointer to the configuration structure.
*/
void CMP_Init(CMP_Type *base, const cmp_config_t *config);
/*!
* @brief De-initializes the CMP module.
*
* This function de-initializes the CMP module. The operations included are as follows.
* - Disabling the CMP module.
* - Disabling the clock for CMP module.
*
* This function disables the clock for the CMP.
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
* clock for the CMP, ensure that all the CMP instances are not used.
*
* @param base CMP peripheral base address.
*/
void CMP_Deinit(CMP_Type *base);
/*!
* @brief Enables/disables the CMP module.
*
* @param base CMP peripheral base address.
* @param enable Enables or disables the module.
*/
static inline void CMP_Enable(CMP_Type *base, bool enable)
{
if (enable)
{
base->CR1 |= CMP_CR1_EN_MASK;
}
else
{
base->CR1 &= ~CMP_CR1_EN_MASK;
}
}
/*!
* @brief Initializes the CMP user configuration structure.
*
* This function initializes the user configuration structure to these default values.
* @code
* config->enableCmp = true;
* config->hysteresisMode = kCMP_HysteresisLevel0;
* config->enableHighSpeed = false;
* config->enableInvertOutput = false;
* config->useUnfilteredOutput = false;
* config->enablePinOut = false;
* config->enableTriggerMode = false;
* @endcode
* @param config Pointer to the configuration structure.
*/
void CMP_GetDefaultConfig(cmp_config_t *config);
/*!
* @brief Sets the input channels for the comparator.
*
* This function sets the input channels for the comparator.
* Note that two input channels cannot be set the same way in the application. When the user selects the same input
* from the analog mux to the positive and negative port, the comparator is disabled automatically.
*
* @param base CMP peripheral base address.
* @param positiveChannel Positive side input channel number. Available range is 0-7.
* @param negativeChannel Negative side input channel number. Available range is 0-7.
*/
void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel);
/* @} */
/*!
* @name Advanced Features
* @{
*/
#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
/*!
* @brief Enables/disables the DMA request for rising/falling events.
*
* This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
* the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
* if the DMA is disabled.
*
* @param base CMP peripheral base address.
* @param enable Enables or disables the feature.
*/
void CMP_EnableDMA(CMP_Type *base, bool enable);
#endif /* FSL_FEATURE_CMP_HAS_DMA */
#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE
/*!
* @brief Enables/disables the window mode.
*
* @param base CMP peripheral base address.
* @param enable Enables or disables the feature.
*/
static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable)
{
if (enable)
{
base->CR1 |= CMP_CR1_WE_MASK;
}
else
{
base->CR1 &= ~CMP_CR1_WE_MASK;
}
}
#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */
#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE
/*!
* @brief Enables/disables the pass through mode.
*
* @param base CMP peripheral base address.
* @param enable Enables or disables the feature.
*/
static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable)
{
if (enable)
{
base->MUXCR |= CMP_MUXCR_PSTM_MASK;
}
else
{
base->MUXCR &= ~CMP_MUXCR_PSTM_MASK;
}
}
#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */
/*!
* @brief Configures the filter.
*
* @param base CMP peripheral base address.
* @param config Pointer to the configuration structure.
*/
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config);
/*!
* @brief Configures the internal DAC.
*
* @param base CMP peripheral base address.
* @param config Pointer to the configuration structure. "NULL" disables the feature.
*/
void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config);
/*!
* @brief Enables the interrupts.
*
* @param base CMP peripheral base address.
* @param mask Mask value for interrupts. See "_cmp_interrupt_enable".
*/
void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask);
/*!
* @brief Disables the interrupts.
*
* @param base CMP peripheral base address.
* @param mask Mask value for interrupts. See "_cmp_interrupt_enable".
*/
void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask);
/* @} */
/*!
* @name Results
* @{
*/
/*!
* @brief Gets the status flags.
*
* @param base CMP peripheral base address.
*
* @return Mask value for the asserted flags. See "_cmp_status_flags".
*/
uint32_t CMP_GetStatusFlags(CMP_Type *base);
/*!
* @brief Clears the status flags.
*
* @param base CMP peripheral base address.
* @param mask Mask value for the flags. See "_cmp_status_flags".
*/
void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask);
/* @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_CMP_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_cmt.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* The standard intermediate frequency (IF). */
#define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U)
/* CMT data modulate mask. */
#define CMT_MODULATE_COUNT_WIDTH (8U)
/* CMT diver 1. */
#define CMT_CMTDIV_ONE (1)
/* CMT diver 2. */
#define CMT_CMTDIV_TWO (2)
/* CMT diver 4. */
#define CMT_CMTDIV_FOUR (4)
/* CMT diver 8. */
#define CMT_CMTDIV_EIGHT (8)
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for CMT module.
*
* @param base CMT peripheral base address.
*/
static uint32_t CMT_GetInstance(CMT_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to cmt clocks for each instance. */
static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief Pointers to cmt bases for each instance. */
static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS;
/*! @brief Pointers to cmt IRQ number for each instance. */
static const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
/*******************************************************************************
* Codes
******************************************************************************/
static uint32_t CMT_GetInstance(CMT_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_CMT_COUNT; instance++)
{
if (s_cmtBases[instance] == base)
{
break;
}
}
assert(instance < FSL_FEATURE_SOC_CMT_COUNT);
return instance;
}
void CMT_GetDefaultConfig(cmt_config_t *config)
{
assert(config);
/* Default infrared output is enabled and set with high active, the divider is set to 1. */
config->isInterruptEnabled = false;
config->isIroEnabled = true;
config->iroPolarity = kCMT_IROActiveHigh;
config->divider = kCMT_SecondClkDiv1;
}
void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz)
{
assert(config);
assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ);
uint8_t divider;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate clock. */
CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Sets clock divider. The divider set in pps should be set
to make sycClock_Hz/divder = 8MHz */
base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1);
divider = base->MSC;
divider &= ~CMT_MSC_CMTDIV_MASK;
divider |= CMT_MSC_CMTDIV(config->divider);
base->MSC = divider;
/* Set the IRO signal. */
base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled);
/* Set interrupt. */
if (config->isInterruptEnabled)
{
CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
}
}
void CMT_Deinit(CMT_Type *base)
{
/*Disable the CMT modulator. */
base->MSC = 0;
/* Disable the interrupt. */
CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Gate the clock. */
CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig)
{
uint8_t mscReg = base->MSC;
/* Judge the mode. */
if (mode != kCMT_DirectIROCtl)
{
assert(modulateConfig);
/* Set carrier generator. */
CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1);
if (mode == kCMT_FSKMode)
{
CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2);
}
/* Set carrier modulator. */
CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount);
mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK);
mscReg |= mode;
}
else
{
mscReg &= ~CMT_MSC_MCGEN_MASK;
}
/* Set the CMT mode. */
base->MSC = mscReg;
}
cmt_mode_t CMT_GetMode(CMT_Type *base)
{
uint8_t mode = base->MSC;
if (!(mode & CMT_MSC_MCGEN_MASK))
{ /* Carrier modulator disabled and the IRO signal is in direct software control. */
return kCMT_DirectIROCtl;
}
else
{
/* Carrier modulator is enabled. */
if (mode & CMT_MSC_BASE_MASK)
{
/* Base band mode. */
return kCMT_BasebandMode;
}
else if (mode & CMT_MSC_FSK_MASK)
{
/* FSK mode. */
return kCMT_FSKMode;
}
else
{
/* Time mode. */
return kCMT_TimeMode;
}
}
}
uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz)
{
uint32_t frequency;
uint32_t divider;
/* Get intermediate frequency. */
frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1);
/* Get the second divider. */
divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT);
/* Get CMT frequency. */
switch ((cmt_second_clkdiv_t)divider)
{
case kCMT_SecondClkDiv1:
frequency = frequency / CMT_CMTDIV_ONE;
break;
case kCMT_SecondClkDiv2:
frequency = frequency / CMT_CMTDIV_TWO;
break;
case kCMT_SecondClkDiv4:
frequency = frequency / CMT_CMTDIV_FOUR;
break;
case kCMT_SecondClkDiv8:
frequency = frequency / CMT_CMTDIV_EIGHT;
break;
default:
frequency = frequency / CMT_CMTDIV_ONE;
break;
}
return frequency;
}
void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount)
{
/* Set modulate mark. */
base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK;
base->CMD2 = (markCount & CMT_CMD2_MB_MASK);
/* Set modulate space. */
base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK;
base->CMD4 = spaceCount & CMT_CMD4_SB_MASK;
}
void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state)
{
uint8_t ocReg = base->OC;
ocReg &= ~CMT_OC_IROL_MASK;
ocReg |= CMT_OC_IROL(state);
/* Set the infrared output signal control. */
base->OC = ocReg;
}

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_CMT_H_
#define _FSL_CMT_H_
#include "fsl_common.h"
/*!
* @addtogroup cmt
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CMT driver version 2.0.1. */
#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*!
* @brief The modes of CMT.
*/
typedef enum _cmt_mode
{
kCMT_DirectIROCtl = 0x00U, /*!< Carrier modulator is disabled and the IRO signal is directly in software control */
kCMT_TimeMode = 0x01U, /*!< Carrier modulator is enabled in time mode. */
kCMT_FSKMode = 0x05U, /*!< Carrier modulator is enabled in FSK mode. */
kCMT_BasebandMode = 0x09U /*!< Carrier modulator is enabled in baseband mode. */
} cmt_mode_t;
/*!
* @brief The CMT clock divide primary prescaler.
* The primary clock divider is used to divider the bus clock to
* get the intermediate frequency to approximately equal to 8 MHZ.
* When the bus clock is 8 MHZ, set primary prescaler to "kCMT_PrimaryClkDiv1".
*/
typedef enum _cmt_primary_clkdiv
{
kCMT_PrimaryClkDiv1 = 0U, /*!< The intermediate frequency is the bus clock divided by 1. */
kCMT_PrimaryClkDiv2 = 1U, /*!< The intermediate frequency is the bus clock divided by 2. */
kCMT_PrimaryClkDiv3 = 2U, /*!< The intermediate frequency is the bus clock divided by 3. */
kCMT_PrimaryClkDiv4 = 3U, /*!< The intermediate frequency is the bus clock divided by 4. */
kCMT_PrimaryClkDiv5 = 4U, /*!< The intermediate frequency is the bus clock divided by 5. */
kCMT_PrimaryClkDiv6 = 5U, /*!< The intermediate frequency is the bus clock divided by 6. */
kCMT_PrimaryClkDiv7 = 6U, /*!< The intermediate frequency is the bus clock divided by 7. */
kCMT_PrimaryClkDiv8 = 7U, /*!< The intermediate frequency is the bus clock divided by 8. */
kCMT_PrimaryClkDiv9 = 8U, /*!< The intermediate frequency is the bus clock divided by 9. */
kCMT_PrimaryClkDiv10 = 9U, /*!< The intermediate frequency is the bus clock divided by 10. */
kCMT_PrimaryClkDiv11 = 10U, /*!< The intermediate frequency is the bus clock divided by 11. */
kCMT_PrimaryClkDiv12 = 11U, /*!< The intermediate frequency is the bus clock divided by 12. */
kCMT_PrimaryClkDiv13 = 12U, /*!< The intermediate frequency is the bus clock divided by 13. */
kCMT_PrimaryClkDiv14 = 13U, /*!< The intermediate frequency is the bus clock divided by 14. */
kCMT_PrimaryClkDiv15 = 14U, /*!< The intermediate frequency is the bus clock divided by 15. */
kCMT_PrimaryClkDiv16 = 15U /*!< The intermediate frequency is the bus clock divided by 16. */
} cmt_primary_clkdiv_t;
/*!
* @brief The CMT clock divide secondary prescaler.
* The second prescaler can be used to divide the 8 MHZ CMT clock
* by 1, 2, 4, or 8 according to the specification.
*/
typedef enum _cmt_second_clkdiv
{
kCMT_SecondClkDiv1 = 0U, /*!< The CMT clock is the intermediate frequency frequency divided by 1. */
kCMT_SecondClkDiv2 = 1U, /*!< The CMT clock is the intermediate frequency frequency divided by 2. */
kCMT_SecondClkDiv4 = 2U, /*!< The CMT clock is the intermediate frequency frequency divided by 4. */
kCMT_SecondClkDiv8 = 3U /*!< The CMT clock is the intermediate frequency frequency divided by 8. */
} cmt_second_clkdiv_t;
/*!
* @brief The CMT infrared output polarity.
*/
typedef enum _cmt_infrared_output_polarity
{
kCMT_IROActiveLow = 0U, /*!< The CMT infrared output signal polarity is active-low. */
kCMT_IROActiveHigh = 1U /*!< The CMT infrared output signal polarity is active-high. */
} cmt_infrared_output_polarity_t;
/*!
* @brief The CMT infrared output signal state control.
*/
typedef enum _cmt_infrared_output_state
{
kCMT_IROCtlLow = 0U, /*!< The CMT Infrared output signal state is controlled to low. */
kCMT_IROCtlHigh = 1U /*!< The CMT Infrared output signal state is controlled to high. */
} cmt_infrared_output_state_t;
/*!
* @brief CMT interrupt configuration structure, default settings all disabled.
*
* This structure contains the settings for all of the CMT interrupt configurations.
*/
enum _cmt_interrupt_enable
{
kCMT_EndOfCycleInterruptEnable = CMT_MSC_EOCIE_MASK, /*!< CMT end of cycle interrupt. */
};
/*!
* @brief CMT carrier generator and modulator configuration structure
*
*/
typedef struct _cmt_modulate_config
{
uint8_t highCount1; /*!< The high-time for carrier generator first register. */
uint8_t lowCount1; /*!< The low-time for carrier generator first register. */
uint8_t highCount2; /*!< The high-time for carrier generator second register for FSK mode. */
uint8_t lowCount2; /*!< The low-time for carrier generator second register for FSK mode. */
uint16_t markCount; /*!< The mark time for the modulator gate. */
uint16_t spaceCount; /*!< The space time for the modulator gate. */
} cmt_modulate_config_t;
/*! @brief CMT basic configuration structure. */
typedef struct _cmt_config
{
bool isInterruptEnabled; /*!< Timer interrupt 0-disable, 1-enable. */
bool isIroEnabled; /*!< The IRO output 0-disabled, 1-enabled. */
cmt_infrared_output_polarity_t iroPolarity; /*!< The IRO polarity. */
cmt_second_clkdiv_t divider; /*!< The CMT clock divide prescaler. */
} cmt_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Gets the CMT default configuration structure. This API
* gets the default configuration structure for the CMT_Init().
* Use the initialized structure unchanged in CMT_Init() or modify
* fields of the structure before calling the CMT_Init().
*
* @param config The CMT configuration structure pointer.
*/
void CMT_GetDefaultConfig(cmt_config_t *config);
/*!
* @brief Initializes the CMT module.
*
* This function ungates the module clock and sets the CMT internal clock,
* interrupt, and infrared output signal for the CMT module.
*
* @param base CMT peripheral base address.
* @param config The CMT basic configuration structure.
* @param busClock_Hz The CMT module input clock - bus clock frequency.
*/
void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz);
/*!
* @brief Disables the CMT module and gate control.
*
* This function disables CMT modulator, interrupts, and gates the
* CMT clock control. CMT_Init must be called to use the CMT again.
*
* @param base CMT peripheral base address.
*/
void CMT_Deinit(CMT_Type *base);
/*! @}*/
/*!
* @name Basic Control Operations
* @{
*/
/*!
* @brief Selects the mode for CMT.
*
* @param base CMT peripheral base address.
* @param mode The CMT feature mode enumeration. See "cmt_mode_t".
* @param modulateConfig The carrier generation and modulator configuration.
*/
void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig);
/*!
* @brief Gets the mode of the CMT module.
*
* @param base CMT peripheral base address.
* @return The CMT mode.
* kCMT_DirectIROCtl Carrier modulator is disabled; the IRO signal is directly in software control.
* kCMT_TimeMode Carrier modulator is enabled in time mode.
* kCMT_FSKMode Carrier modulator is enabled in FSK mode.
* kCMT_BasebandMode Carrier modulator is enabled in baseband mode.
*/
cmt_mode_t CMT_GetMode(CMT_Type *base);
/*!
* @brief Gets the actual CMT clock frequency.
*
* @param base CMT peripheral base address.
* @param busClock_Hz CMT module input clock - bus clock frequency.
* @return The CMT clock frequency.
*/
uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz);
/*!
* @brief Sets the primary data set for the CMT carrier generator counter.
*
* This function sets the high-time and low-time of the primary data set for the
* CMT carrier generator counter to control the period and the duty cycle of the
* output carrier signal.
* If the CMT clock period is Tcmt, the period of the carrier generator signal equals
* (highCount + lowCount) * Tcmt. The duty cycle equals to highCount / (highCount + lowCount).
*
* @param base CMT peripheral base address.
* @param highCount The number of CMT clocks for carrier generator signal high time,
* integer in the range of 1 ~ 0xFF.
* @param lowCount The number of CMT clocks for carrier generator signal low time,
* integer in the range of 1 ~ 0xFF.
*/
static inline void CMT_SetCarrirGenerateCountOne(CMT_Type *base, uint32_t highCount, uint32_t lowCount)
{
assert(highCount <= CMT_CGH1_PH_MASK);
assert(highCount);
assert(lowCount <= CMT_CGL1_PL_MASK);
assert(lowCount);
base->CGH1 = highCount;
base->CGL1 = lowCount;
}
/*!
* @brief Sets the secondary data set for the CMT carrier generator counter.
*
* This function is used for FSK mode setting the high-time and low-time of the secondary
* data set CMT carrier generator counter to control the period and the duty cycle
* of the output carrier signal.
* If the CMT clock period is Tcmt, the period of the carrier generator signal equals
* (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount).
*
* @param base CMT peripheral base address.
* @param highCount The number of CMT clocks for carrier generator signal high time,
* integer in the range of 1 ~ 0xFF.
* @param lowCount The number of CMT clocks for carrier generator signal low time,
* integer in the range of 1 ~ 0xFF.
*/
static inline void CMT_SetCarrirGenerateCountTwo(CMT_Type *base, uint32_t highCount, uint32_t lowCount)
{
assert(highCount <= CMT_CGH2_SH_MASK);
assert(highCount);
assert(lowCount <= CMT_CGL2_SL_MASK);
assert(lowCount);
base->CGH2 = highCount;
base->CGL2 = lowCount;
}
/*!
* @brief Sets the modulation mark and space time period for the CMT modulator.
*
* This function sets the mark time period of the CMT modulator counter
* to control the mark time of the output modulated signal from the carrier generator output signal.
* If the CMT clock frequency is Fcmt and the carrier out signal frequency is fcg:
* - In Time and Baseband mode: The mark period of the generated signal equals (markCount + 1) / (Fcmt/8).
* The space period of the generated signal equals spaceCount / (Fcmt/8).
* - In FSK mode: The mark period of the generated signal equals (markCount + 1)/fcg.
* The space period of the generated signal equals spaceCount / fcg.
*
* @param base Base address for current CMT instance.
* @param markCount The number of clock period for CMT modulator signal mark period,
* in the range of 0 ~ 0xFFFF.
* @param spaceCount The number of clock period for CMT modulator signal space period,
* in the range of the 0 ~ 0xFFFF.
*/
void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount);
/*!
* @brief Enables or disables the extended space operation.
*
* This function is used to make the space period longer
* for time, baseband, and FSK modes.
*
* @param base CMT peripheral base address.
* @param enable True enable the extended space, false disable the extended space.
*/
static inline void CMT_EnableExtendedSpace(CMT_Type *base, bool enable)
{
if (enable)
{
base->MSC |= CMT_MSC_EXSPC_MASK;
}
else
{
base->MSC &= ~CMT_MSC_EXSPC_MASK;
}
}
/*!
* @brief Sets the IRO (infrared output) signal state.
*
* Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set
* and the IRO signal is enabled.
*
* @param base CMT peripheral base address.
* @param state The control of the IRO signal. See "cmt_infrared_output_state_t"
*/
void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state);
/*!
* @brief Enables the CMT interrupt.
*
* This function enables the CMT interrupts according to the provided mask if enabled.
* The CMT only has the end of the cycle interrupt - an interrupt occurs at the end
* of the modulator cycle. This interrupt provides a means for the user
* to reload the new mark/space values into the CMT modulator data registers
* and verify the modulator mark and space.
* For example, to enable the end of cycle, do the following.
* @code
* CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
* @endcode
* @param base CMT peripheral base address.
* @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable.
*/
static inline void CMT_EnableInterrupts(CMT_Type *base, uint32_t mask)
{
base->MSC |= mask;
}
/*!
* @brief Disables the CMT interrupt.
*
* This function disables the CMT interrupts according to the provided maskIf enabled.
* The CMT only has the end of the cycle interrupt.
* For example, to disable the end of cycle, do the following.
* @code
* CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
* @endcode
*
* @param base CMT peripheral base address.
* @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable.
*/
static inline void CMT_DisableInterrupts(CMT_Type *base, uint32_t mask)
{
base->MSC &= ~mask;
}
/*!
* @brief Gets the end of the cycle status flag.
*
* The flag is set:
* - When the modulator is not currently active and carrier and modulator
* are set to start the initial CMT transmission.
* - At the end of each modulation cycle when the counter is reloaded and
* the carrier and modulator are enabled.
* @param base CMT peripheral base address.
* @return Current status of the end of cycle status flag
* @arg non-zero: End-of-cycle has occurred.
* @arg zero: End-of-cycle has not yet occurred since the flag last cleared.
*/
static inline uint32_t CMT_GetStatusFlags(CMT_Type *base)
{
return base->MSC & CMT_MSC_EOCF_MASK;
}
/*! @}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_CMT_H_*/

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_common.h"
/* This is not needed for mbed */
#if 0
#include "fsl_debug_console.h"
#ifndef NDEBUG
#if (defined(__CC_ARM)) || (defined(__ICCARM__))
void __aeabi_assert(const char *failedExpr, const char *file, int line)
{
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
for (;;)
{
__asm("bkpt #0");
}
}
#elif(defined(__GNUC__))
void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
{
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
for (;;)
{
__asm("bkpt #0");
}
}
#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
#endif /* NDEBUG */
#endif
void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) */
uint32_t n;
uint32_t interrupts_disabled;
interrupts_disabled = __get_PRIMASK();
__disable_irq();
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[irq + 16] = irqHandler;
if (!interrupts_disabled) {
__enable_irq();
}
}
#ifndef CPU_QN908X
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#else
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
/* SYSCON->STARTERSET[index] = 1u << intNumber; */
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
/* SYSCON->STARTERCLR[index] = 1u << intNumber; */
}
#endif /*CPU_QN908X */

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_COMMON_H_
#define _FSL_COMMON_H_
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "fsl_device_registers.h"
/*!
* @addtogroup ksdk_common
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Construct a status code value from a group and code number. */
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
/*! @brief Construct the version number for drivers. */
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
/*! @brief Status group numbers. */
enum _status_groups
{
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
};
/*! @brief Generic status return codes. */
enum _generic_status
{
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
/*
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
* defined in previous of this file.
*/
#include "fsl_clock.h"
/*
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
*/
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
#include "fsl_reset.h"
#endif
/*! @name Min/max macros */
/* @{ */
#if !defined(MIN)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#if !defined(MAX)
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
/* @} */
/*! @brief Computes the number of elements in an array. */
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
#if !defined(UINT16_MAX)
#define UINT16_MAX ((uint16_t)-1)
#endif
#if !defined(UINT32_MAX)
#define UINT32_MAX ((uint32_t)-1)
#endif
/* @} */
/*! @name Timer utilities */
/* @{ */
/*! Macro to convert a microsecond period to raw count value */
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
/*! Macro to convert a raw count value to microsecond */
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
/*! Macro to convert a millisecond period to raw count value */
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
/*! Macro to convert a raw count value to millisecond */
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
/* @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enable specific interrupt.
*
* Enable the interrupt not routed from intmux.
*
* @param interrupt The IRQ number.
*/
static inline void EnableIRQ(IRQn_Type interrupt)
{
if (NotAvail_IRQn == interrupt)
{
return;
}
#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
#endif
{
NVIC_EnableIRQ(interrupt);
}
}
/*!
* @brief Disable specific interrupt.
*
* Disable the interrupt not routed from intmux.
*
* @param interrupt The IRQ number.
*/
static inline void DisableIRQ(IRQn_Type interrupt)
{
if (NotAvail_IRQn == interrupt)
{
return;
}
#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
#endif
{
NVIC_DisableIRQ(interrupt);
}
}
/*!
* @brief Disable the global IRQ
*
* Disable the global interrupt and return the current primask register. User is required to provided the primask
* register for the EnableGlobalIRQ().
*
* @return Current primask value.
*/
static inline uint32_t DisableGlobalIRQ(void)
{
uint32_t regPrimask = __get_PRIMASK();
__disable_irq();
return regPrimask;
}
/*!
* @brief Enaable the global IRQ
*
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
* convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
*
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
* DisableGlobalIRQ().
*/
static inline void EnableGlobalIRQ(uint32_t primask)
{
__set_PRIMASK(primask);
}
/*!
* @brief install IRQ handler
*
* @param irq IRQ number
* @param irqHandler IRQ handler address
*/
void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*!
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
*
* Enable the interrupt for wake-up from deep sleep mode.
* Some interrupts are typically used in sleep mode only and will not occur during
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
*
* @param interrupt The IRQ number.
*/
void EnableDeepSleepIRQ(IRQn_Type interrupt);
/*!
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
*
* Disable the interrupt for wake-up from deep sleep mode.
* Some interrupts are typically used in sleep mode only and will not occur during
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
*
* @param interrupt The IRQ number.
*/
void DisableDeepSleepIRQ(IRQn_Type interrupt);
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* _FSL_COMMON_H_ */

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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_crc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @internal @brief Has data register with name CRC. */
#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
#define DATA CRC
#define DATALL CRCLL
#endif
#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT
/* @brief Default user configuration structure for CRC-16-CCITT */
#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U
/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */
#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
/*< Default initial checksum */
#define CRC_DRIVER_DEFAULT_REFLECT_IN false
/*< Default is no transpose */
#define CRC_DRIVER_DEFAULT_REFLECT_OUT false
/*< Default is transpose bytes */
#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false
/*< Default is without complement of CRC data register read data */
#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16
/*< Default is 16-bit CRC protocol */
#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum
/*< Default is resutl type is final checksum */
#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
/*! @brief CRC type of transpose of read write data */
typedef enum _crc_transpose_type
{
kCrcTransposeNone = 0U, /*! No transpose */
kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */
kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */
kCrcTransposeBytes = 3U, /*! Transpose bytes */
} crc_transpose_type_t;
/*!
* @brief CRC module configuration.
*
* This structure holds the configuration for the CRC module.
*/
typedef struct _crc_module_config
{
uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n
Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
uint32_t seed; /*!< Starting checksum value */
crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */
crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */
bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */
} crc_module_config_t;
/*******************************************************************************
* Code
******************************************************************************/
/*!
* @brief Returns transpose type for CRC protocol reflect in parameter.
*
* This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter.
*
* @param enable True or false for the selected CRC protocol Reflect In (refin) parameter.
*/
static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable)
{
return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes);
}
/*!
* @brief Returns transpose type for CRC protocol reflect out parameter.
*
* This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter.
*
* @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter.
*/
static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable)
{
return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone);
}
/*!
* @brief Starts checksum computation.
*
* Configures the CRC module for the specified CRC protocol. @n
* Starts the checksum computation by writing the seed value
*
* @param base CRC peripheral address.
* @param config Pointer to protocol configuration structure.
*/
static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
{
uint32_t crcControl;
/* pre-compute value for CRC control registger based on user configuraton without WAS field */
crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) |
CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits);
/* make sure the control register is clear - WAS is deasserted, and protocol is set */
base->CTRL = crcControl;
/* write polynomial register */
base->GPOLY = config->polynomial;
/* write pre-computed control register value along with WAS to start checksum computation */
base->CTRL = crcControl | CRC_CTRL_WAS(true);
/* write seed (initial checksum) */
base->DATA = config->seed;
/* deassert WAS by writing pre-computed CRC control register value */
base->CTRL = crcControl;
}
/*!
* @brief Starts final checksum computation.
*
* Configures the CRC module for the specified CRC protocol. @n
* Starts final checksum computation by writing the seed value.
* @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum
* (output reflection and xor functions are applied).
*
* @param base CRC peripheral address.
* @param protocolConfig Pointer to protocol configuration structure.
*/
static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
{
crc_module_config_t moduleConfig;
/* convert protocol to CRC peripheral module configuration, prepare for final checksum */
moduleConfig.polynomial = protocolConfig->polynomial;
moduleConfig.seed = protocolConfig->seed;
moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
moduleConfig.complementChecksum = protocolConfig->complementChecksum;
moduleConfig.crcBits = protocolConfig->crcBits;
CRC_ConfigureAndStart(base, &moduleConfig);
}
/*!
* @brief Starts intermediate checksum computation.
*
* Configures the CRC module for the specified CRC protocol. @n
* Starts intermediate checksum computation by writing the seed value.
* @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value).
*
* @param base CRC peripheral address.
* @param protocolConfig Pointer to protocol configuration structure.
*/
static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
{
crc_module_config_t moduleConfig;
/* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */
moduleConfig.polynomial = protocolConfig->polynomial;
moduleConfig.seed = protocolConfig->seed;
moduleConfig.readTranspose =
kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */
moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */
moduleConfig.crcBits = protocolConfig->crcBits;
CRC_ConfigureAndStart(base, &moduleConfig);
}
void CRC_Init(CRC_Type *base, const crc_config_t *config)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* ungate clock */
CLOCK_EnableClock(kCLOCK_Crc0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* configure CRC module and write the seed */
if (config->crcResult == kCrcFinalChecksum)
{
CRC_SetProtocolConfig(base, config);
}
else
{
CRC_SetRawProtocolConfig(base, config);
}
}
void CRC_GetDefaultConfig(crc_config_t *config)
{
static const crc_config_t crc16ccit = {
CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED,
CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT,
CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS,
CRC_DRIVER_DEFAULT_CRC_RESULT,
};
*config = crc16ccit;
}
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
{
const uint32_t *data32;
/* 8-bit reads and writes till source address is aligned 4 bytes */
while ((dataSize) && ((uint32_t)data & 3U))
{
base->ACCESS8BIT.DATALL = *data;
data++;
dataSize--;
}
/* use 32-bit reads and writes as long as possible */
data32 = (const uint32_t *)data;
while (dataSize >= sizeof(uint32_t))
{
base->DATA = *data32;
data32++;
dataSize -= sizeof(uint32_t);
}
data = (const uint8_t *)data32;
/* 8-bit reads and writes till end of data buffer */
while (dataSize)
{
base->ACCESS8BIT.DATALL = *data;
data++;
dataSize--;
}
}
uint32_t CRC_Get32bitResult(CRC_Type *base)
{
return base->DATA;
}
uint16_t CRC_Get16bitResult(CRC_Type *base)
{
uint32_t retval;
uint32_t totr; /* type of transpose read bitfield */
retval = base->DATA;
totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT;
/* check transpose type to get 16-bit out of 32-bit register */
if (totr >= 2U)
{
/* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */
retval &= 0xFFFF0000U;
retval = retval >> 16U;
}
else
{
/* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */
retval &= 0x0000FFFFU;
}
return (uint16_t)retval;
}

194
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_CRC_H_
#define _FSL_CRC_H_
#include "fsl_common.h"
/*!
* @addtogroup crc
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CRC driver version. Version 2.0.1.
*
* Current version: 2.0.1
*
* Change log:
* - Version 2.0.1
* - move DATA and DATALL macro definition from header file to source file
*/
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
#endif
/*! @brief CRC bit width */
typedef enum _crc_bits
{
kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */
kCrcBits32 = 1U /*!< Generate 32-bit CRC code */
} crc_bits_t;
/*! @brief CRC result type */
typedef enum _crc_result
{
kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum.
Reflect out and final xor protocol features are applied. */
kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value).
Reflect out and final xor protocol feature are not applied.
Intermediate checksum can be used as a seed for CRC_Init()
to continue adding data to this checksum. */
} crc_result_t;
/*!
* @brief CRC protocol configuration.
*
* This structure holds the configuration for the CRC protocol.
*
*/
typedef struct _crc_config
{
uint32_t polynomial; /*!< CRC Polynomial, MSBit first.
Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
uint32_t seed; /*!< Starting checksum value */
bool reflectIn; /*!< Reflect bits on input. */
bool reflectOut; /*!< Reflect bits on output. */
bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */
crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or
CRC_Get32bitResult() */
} crc_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enables and configures the CRC peripheral module.
*
* This function enables the clock gate in the Kinetis SIM module for the CRC peripheral.
* It also configures the CRC module and starts a checksum computation by writing the seed.
*
* @param base CRC peripheral address.
* @param config CRC module configuration structure.
*/
void CRC_Init(CRC_Type *base, const crc_config_t *config);
/*!
* @brief Disables the CRC peripheral module.
*
* This function disables the clock gate in the Kinetis SIM module for the CRC peripheral.
*
* @param base CRC peripheral address.
*/
static inline void CRC_Deinit(CRC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* gate clock */
CLOCK_DisableClock(kCLOCK_Crc0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief Loads default values to the CRC protocol configuration structure.
*
* Loads default values to the CRC protocol configuration structure. The default values are as follows.
* @code
* config->polynomial = 0x1021;
* config->seed = 0xFFFF;
* config->reflectIn = false;
* config->reflectOut = false;
* config->complementChecksum = false;
* config->crcBits = kCrcBits16;
* config->crcResult = kCrcFinalChecksum;
* @endcode
*
* @param config CRC protocol configuration structure.
*/
void CRC_GetDefaultConfig(crc_config_t *config);
/*!
* @brief Writes data to the CRC module.
*
* Writes input data buffer bytes to the CRC data register.
* The configured type of transpose is applied.
*
* @param base CRC peripheral address.
* @param data Input data stream, MSByte in data[0].
* @param dataSize Size in bytes of the input data buffer.
*/
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
/*!
* @brief Reads the 32-bit checksum from the CRC module.
*
* Reads the CRC data register (either an intermediate or the final checksum).
* The configured type of transpose and complement is applied.
*
* @param base CRC peripheral address.
* @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
*/
uint32_t CRC_Get32bitResult(CRC_Type *base);
/*!
* @brief Reads a 16-bit checksum from the CRC module.
*
* Reads the CRC data register (either an intermediate or the final checksum).
* The configured type of transpose and complement is applied.
*
* @param base CRC peripheral address.
* @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
*/
uint16_t CRC_Get16bitResult(CRC_Type *base);
#if defined(__cplusplus)
}
#endif
/*!
*@}
*/
#endif /* _FSL_CRC_H_ */

220
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_dac.h"
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for DAC module.
*
* @param base DAC peripheral base address
*/
static uint32_t DAC_GetInstance(DAC_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to DAC bases for each instance. */
static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to DAC clocks for each instance. */
static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Codes
******************************************************************************/
static uint32_t DAC_GetInstance(DAC_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_DAC_COUNT; instance++)
{
if (s_dacBases[instance] == base)
{
break;
}
}
assert(instance < FSL_FEATURE_SOC_DAC_COUNT);
return instance;
}
void DAC_Init(DAC_Type *base, const dac_config_t *config)
{
assert(NULL != config);
uint8_t tmp8;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Configure. */
/* DACx_C0. */
tmp8 = base->C0 & ~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK);
if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource)
{
tmp8 |= DAC_C0_DACRFS_MASK;
}
if (config->enableLowPowerMode)
{
tmp8 |= DAC_C0_LPEN_MASK;
}
base->C0 = tmp8;
/* DAC_Enable(base, true); */
/* Tip: The DAC output can be enabled till then after user sets their own available data in application. */
}
void DAC_Deinit(DAC_Type *base)
{
DAC_Enable(base, false);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void DAC_GetDefaultConfig(dac_config_t *config)
{
assert(NULL != config);
config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
config->enableLowPowerMode = false;
}
void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config)
{
assert(NULL != config);
uint8_t tmp8;
/* DACx_C0. */
tmp8 = base->C0 & ~(DAC_C0_DACTRGSEL_MASK);
if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode)
{
tmp8 |= DAC_C0_DACTRGSEL_MASK;
}
base->C0 = tmp8;
/* DACx_C1. */
tmp8 = base->C1 &
~(
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
DAC_C1_DACBFWM_MASK |
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
DAC_C1_DACBFMD_MASK);
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
tmp8 |= DAC_C1_DACBFWM(config->watermark);
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
tmp8 |= DAC_C1_DACBFMD(config->workMode);
base->C1 = tmp8;
/* DACx_C2. */
tmp8 = base->C2 & ~DAC_C2_DACBFUP_MASK;
tmp8 |= DAC_C2_DACBFUP(config->upperLimit);
base->C2 = tmp8;
}
void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config)
{
assert(NULL != config);
config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
config->watermark = kDAC_BufferWatermark1Word;
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
config->workMode = kDAC_BufferWorkAsNormalMode;
config->upperLimit = DAC_DATL_COUNT - 1U;
}
void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value)
{
assert(index < DAC_DATL_COUNT);
base->DAT[index].DATL = (uint8_t)(0xFFU & value); /* Low 8-bit. */
base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */
}
void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index)
{
assert(index < DAC_DATL_COUNT);
uint8_t tmp8 = base->C2 & ~DAC_C2_DACBFRP_MASK;
tmp8 |= DAC_C2_DACBFRP(index);
base->C2 = tmp8;
}
void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask)
{
mask &= (
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
DAC_C0_DACBWIEN_MASK |
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */
}
void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask)
{
mask &= (
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
DAC_C0_DACBWIEN_MASK |
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */
}
uint32_t DAC_GetBufferStatusFlags(DAC_Type *base)
{
return (uint32_t)(base->SR & (
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
DAC_SR_DACBFWMF_MASK |
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK));
}
void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask)
{
mask &= (
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
DAC_SR_DACBFWMF_MASK |
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK);
base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */
}

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_DAC_H_
#define _FSL_DAC_H_
#include "fsl_common.h"
/*!
* @addtogroup dac
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief DAC driver version 2.0.1. */
#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*!
* @brief DAC buffer flags.
*/
enum _dac_buffer_status_flags
{
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
kDAC_BufferWatermarkFlag = DAC_SR_DACBFWMF_MASK, /*!< DAC Buffer Watermark Flag. */
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
kDAC_BufferReadPointerTopPositionFlag = DAC_SR_DACBFRPTF_MASK, /*!< DAC Buffer Read Pointer Top Position Flag. */
kDAC_BufferReadPointerBottomPositionFlag = DAC_SR_DACBFRPBF_MASK, /*!< DAC Buffer Read Pointer Bottom Position
Flag. */
};
/*!
* @brief DAC buffer interrupts.
*/
enum _dac_buffer_interrupt_enable
{
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
kDAC_BufferWatermarkInterruptEnable = DAC_C0_DACBWIEN_MASK, /*!< DAC Buffer Watermark Interrupt Enable. */
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
kDAC_BufferReadPointerTopInterruptEnable = DAC_C0_DACBTIEN_MASK, /*!< DAC Buffer Read Pointer Top Flag Interrupt
Enable. */
kDAC_BufferReadPointerBottomInterruptEnable = DAC_C0_DACBBIEN_MASK, /*!< DAC Buffer Read Pointer Bottom Flag
Interrupt Enable */
};
/*!
* @brief DAC reference voltage source.
*/
typedef enum _dac_reference_voltage_source
{
kDAC_ReferenceVoltageSourceVref1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */
kDAC_ReferenceVoltageSourceVref2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */
} dac_reference_voltage_source_t;
/*!
* @brief DAC buffer trigger mode.
*/
typedef enum _dac_buffer_trigger_mode
{
kDAC_BufferTriggerByHardwareMode = 0U, /*!< The DAC hardware trigger is selected. */
kDAC_BufferTriggerBySoftwareMode = 1U, /*!< The DAC software trigger is selected. */
} dac_buffer_trigger_mode_t;
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
/*!
* @brief DAC buffer watermark.
*/
typedef enum _dac_buffer_watermark
{
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD
kDAC_BufferWatermark1Word = 0U, /*!< 1 word away from the upper limit. */
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS
kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS */
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS
kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS */
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS
kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS */
} dac_buffer_watermark_t;
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
/*!
* @brief DAC buffer work mode.
*/
typedef enum _dac_buffer_work_mode
{
kDAC_BufferWorkAsNormalMode = 0U, /*!< Normal mode. */
#if defined(FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE
kDAC_BufferWorkAsSwingMode, /*!< Swing mode. */
#endif /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */
kDAC_BufferWorkAsOneTimeScanMode, /*!< One-Time Scan mode. */
#if defined(FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE
kDAC_BufferWorkAsFIFOMode, /*!< FIFO mode. */
#endif /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */
} dac_buffer_work_mode_t;
/*!
* @brief DAC module configuration.
*/
typedef struct _dac_config
{
dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */
bool enableLowPowerMode; /*!< Enable the low-power mode. */
} dac_config_t;
/*!
* @brief DAC buffer configuration.
*/
typedef struct _dac_buffer_config
{
dac_buffer_trigger_mode_t triggerMode; /*!< Select the buffer's trigger mode. */
#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */
#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
dac_buffer_work_mode_t workMode; /*!< Select the buffer's work mode. */
uint8_t upperLimit; /*!< Set the upper limit for the buffer index.
Normally, 0-15 is available for a buffer with 16 items. */
} dac_buffer_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization
* @{
*/
/*!
* @brief Initializes the DAC module.
*
* This function initializes the DAC module including the following operations.
* - Enabling the clock for DAC module.
* - Configuring the DAC converter with a user configuration.
* - Enabling the DAC module.
*
* @param base DAC peripheral base address.
* @param config Pointer to the configuration structure. See "dac_config_t".
*/
void DAC_Init(DAC_Type *base, const dac_config_t *config);
/*!
* @brief De-initializes the DAC module.
*
* This function de-initializes the DAC module including the following operations.
* - Disabling the DAC module.
* - Disabling the clock for the DAC module.
*
* @param base DAC peripheral base address.
*/
void DAC_Deinit(DAC_Type *base);
/*!
* @brief Initializes the DAC user configuration structure.
*
* This function initializes the user configuration structure to a default value. The default values are as follows.
* @code
* config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
* config->enableLowPowerMode = false;
* @endcode
* @param config Pointer to the configuration structure. See "dac_config_t".
*/
void DAC_GetDefaultConfig(dac_config_t *config);
/*!
* @brief Enables the DAC module.
*
* @param base DAC peripheral base address.
* @param enable Enables or disables the feature.
*/
static inline void DAC_Enable(DAC_Type *base, bool enable)
{
if (enable)
{
base->C0 |= DAC_C0_DACEN_MASK;
}
else
{
base->C0 &= ~DAC_C0_DACEN_MASK;
}
}
/* @} */
/*!
* @name Buffer
* @{
*/
/*!
* @brief Enables the DAC buffer.
*
* @param base DAC peripheral base address.
* @param enable Enables or disables the feature.
*/
static inline void DAC_EnableBuffer(DAC_Type *base, bool enable)
{
if (enable)
{
base->C1 |= DAC_C1_DACBFEN_MASK;
}
else
{
base->C1 &= ~DAC_C1_DACBFEN_MASK;
}
}
/*!
* @brief Configures the CMP buffer.
*
* @param base DAC peripheral base address.
* @param config Pointer to the configuration structure. See "dac_buffer_config_t".
*/
void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config);
/*!
* @brief Initializes the DAC buffer configuration structure.
*
* This function initializes the DAC buffer configuration structure to default values. The default values are as follows.
* @code
* config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
* config->watermark = kDAC_BufferWatermark1Word;
* config->workMode = kDAC_BufferWorkAsNormalMode;
* config->upperLimit = DAC_DATL_COUNT - 1U;
* @endcode
* @param config Pointer to the configuration structure. See "dac_buffer_config_t".
*/
void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config);
/*!
* @brief Enables the DMA for DAC buffer.
*
* @param base DAC peripheral base address.
* @param enable Enables or disables the feature.
*/
static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable)
{
if (enable)
{
base->C1 |= DAC_C1_DMAEN_MASK;
}
else
{
base->C1 &= ~DAC_C1_DMAEN_MASK;
}
}
/*!
* @brief Sets the value for items in the buffer.
*
* @param base DAC peripheral base address.
* @param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC buffer.
* @param value Setting the value for items in the buffer. 12-bits are available.
*/
void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value);
/*!
* @brief Triggers the buffer using software and updates the read pointer of the DAC buffer.
*
* This function triggers the function using software. The read pointer of the DAC buffer is updated with one step
* after this function is called. Changing the read pointer depends on the buffer's work mode.
*
* @param base DAC peripheral base address.
*/
static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base)
{
base->C0 |= DAC_C0_DACSWTRG_MASK;
}
/*!
* @brief Gets the current read pointer of the DAC buffer.
*
* This function gets the current read pointer of the DAC buffer.
* The current output value depends on the item indexed by the read pointer. It is updated either
* by a software trigger or a hardware trigger.
*
* @param base DAC peripheral base address.
*
* @return The current read pointer of the DAC buffer.
*/
static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base)
{
return ((base->C2 & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT);
}
/*!
* @brief Sets the current read pointer of the DAC buffer.
*
* This function sets the current read pointer of the DAC buffer.
* The current output value depends on the item indexed by the read pointer. It is updated either by a
* software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes.
*
* @param base DAC peripheral base address.
* @param index Setting an index value for the pointer.
*/
void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index);
/*!
* @brief Enables interrupts for the DAC buffer.
*
* @param base DAC peripheral base address.
* @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable".
*/
void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask);
/*!
* @brief Disables interrupts for the DAC buffer.
*
* @param base DAC peripheral base address.
* @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable".
*/
void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask);
/*!
* @brief Gets the flags of events for the DAC buffer.
*
* @param base DAC peripheral base address.
*
* @return Mask value for the asserted flags. See "_dac_buffer_status_flags".
*/
uint32_t DAC_GetBufferStatusFlags(DAC_Type *base);
/*!
* @brief Clears the flags of events for the DAC buffer.
*
* @param base DAC peripheral base address.
* @param mask Mask value for flags. See "_dac_buffer_status_flags_t".
*/
void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask);
/* @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_DAC_H_ */

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_dmamux.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for DMAMUX.
*
* @param base DMAMUX peripheral base address.
*/
static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Array to map DMAMUX instance number to base pointer. */
static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Array to map DMAMUX instance number to clock name. */
static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++)
{
if (s_dmamuxBases[instance] == base)
{
break;
}
}
assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT);
return instance;
}
void DMAMUX_Init(DMAMUX_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void DMAMUX_Deinit(DMAMUX_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_DMAMUX_H_
#define _FSL_DMAMUX_H_
#include "fsl_common.h"
/*!
* @addtogroup dmamux
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief DMAMUX driver version 2.0.2. */
#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @name DMAMUX Initialization and de-initialization
* @{
*/
/*!
* @brief Initializes the DMAMUX peripheral.
*
* This function ungates the DMAMUX clock.
*
* @param base DMAMUX peripheral base address.
*
*/
void DMAMUX_Init(DMAMUX_Type *base);
/*!
* @brief Deinitializes the DMAMUX peripheral.
*
* This function gates the DMAMUX clock.
*
* @param base DMAMUX peripheral base address.
*/
void DMAMUX_Deinit(DMAMUX_Type *base);
/* @} */
/*!
* @name DMAMUX Channel Operation
* @{
*/
/*!
* @brief Enables the DMAMUX channel.
*
* This function enables the DMAMUX channel.
*
* @param base DMAMUX peripheral base address.
* @param channel DMAMUX channel number.
*/
static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
}
/*!
* @brief Disables the DMAMUX channel.
*
* This function disables the DMAMUX channel.
*
* @note The user must disable the DMAMUX channel before configuring it.
* @param base DMAMUX peripheral base address.
* @param channel DMAMUX channel number.
*/
static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
}
/*!
* @brief Configures the DMAMUX channel source.
*
* @param base DMAMUX peripheral base address.
* @param channel DMAMUX channel number.
* @param source Channel source, which is used to trigger the DMA transfer.
*/
static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
}
#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
/*!
* @brief Enables the DMAMUX period trigger.
*
* This function enables the DMAMUX period trigger feature.
*
* @param base DMAMUX peripheral base address.
* @param channel DMAMUX channel number.
*/
static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
}
/*!
* @brief Disables the DMAMUX period trigger.
*
* This function disables the DMAMUX period trigger.
*
* @param base DMAMUX peripheral base address.
* @param channel DMAMUX channel number.
*/
static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
}
#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
/*!
* @brief Enables the DMA channel to be always ON.
*
* This function enables the DMAMUX channel always ON feature.
*
* @param base DMAMUX peripheral base address.
* @param channel DMAMUX channel number.
* @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
*/
static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
if (enable)
{
base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
}
else
{
base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
}
}
#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
/* @} */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/* @} */
#endif /* _FSL_DMAMUX_H_ */

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targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/drivers/fsl_dspi.c Normal file
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