diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h index 2c662d8d40..3f0c4e35f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h @@ -47,6 +47,7 @@ #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h index 2c662d8d40..3f0c4e35f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h @@ -47,6 +47,7 @@ #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h index 760f6b9c74..e8d7455047 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h @@ -46,6 +46,7 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h index 34e8fead9a..0caa0508c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h @@ -46,6 +46,7 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h index 2c662d8d40..3f0c4e35f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h @@ -47,6 +47,7 @@ #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h index 082b22cebb..42c96c85c6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h index 082b22cebb..42c96c85c6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h index 91fd0c3789..ac30939625 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn #define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() #define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h index 91fd0c3789..ac30939625 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn #define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() #define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h index 91fd0c3789..ac30939625 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn #define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() #define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h index cc5b124ad1..94a71d0eef 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h @@ -46,6 +46,7 @@ extern "C" { #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h index 8ff2fb0ace..8bd5f6b136 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h index 8ff2fb0ace..8bd5f6b136 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h index 8ff2fb0ace..8bd5f6b136 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h index 8ff2fb0ace..8bd5f6b136 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h index 8ff2fb0ace..8bd5f6b136 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h index e428968d4a..5627990658 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h index d5ede91000..02aa6028c2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h index d5ede91000..02aa6028c2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h index 19d9584eee..cedecee545 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h index 3515470935..dede60361a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h index 90f6a00776..7f7c8cb4f7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h index fa8cc97963..e67b911185 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h index fa8cc97963..e67b911185 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h index fa8cc97963..e67b911185 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h index fa8cc97963..e67b911185 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h index 966ce876ae..80a92081d3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h index 7724b546fb..4f43c6e22e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h index 7724b546fb..4f43c6e22e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h index 7724b546fb..4f43c6e22e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h index 7724b546fb..4f43c6e22e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h index 408bc75d4f..f38bbe0fca 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h index 408bc75d4f..f38bbe0fca 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h index dc2245e8f8..15cb9f2c4e 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h index dc2245e8f8..15cb9f2c4e 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h index bdcb1570c3..934e8ed9d2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h index 315a9bf43f..11cd6c10df 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h index 173f8e7cb9..6c533d1997 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h index 173f8e7cb9..6c533d1997 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()