ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[LPC15XX] Fixed µs_ticker implementation 

Re-wrote µs_ticker implementation to use SCT3 instead of RIT in order to
fix a serious rollover bug at 1:11:34.
pull/2193/head
neilt6 2016-07-19 10:24:02 -06:00
parent fd757d3b84
commit 9f6b2c47ca
2 changed files with 41 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hal/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
View File

@ -27,7 +27,7 @@ static LPC_SCT0_Type *SCTs[4] = {
}; };
// bit flags for used SCTs // bit flags for used SCTs
static unsigned char sct_used = 0; static unsigned char sct_used = (1 << 3);
static int get_available_sct(void) { static int get_available_sct(void) {
int i; int i;
for (i=0; i<4; i++) { for (i=0; i<4; i++) {

60
hal/targets/hal/TARGET_NXP/TARGET_LPC15XX/us_ticker.c
View File

@ -17,33 +17,36 @@
#include "us_ticker_api.h" #include "us_ticker_api.h"
#include "PeripheralNames.h" #include "PeripheralNames.h"
#define US_TICKER_TIMER_IRQn RIT_IRQn #define US_TICKER_TIMER_IRQn SCT3_IRQn
int us_ticker_inited = 0; int us_ticker_inited = 0;
void us_ticker_init(void) { void us_ticker_init(void) {
if (us_ticker_inited) return; if (us_ticker_inited)
return;
us_ticker_inited = 1; us_ticker_inited = 1;
// Enable the RIT clock // Enable the SCT3 clock
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 1); LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 5);
// Clear peripheral reset the RIT // Clear peripheral reset the SCT3
LPC_SYSCON->PRESETCTRL1 |= (1 << 1); LPC_SYSCON->PRESETCTRL1 |= (1 << 5);
LPC_SYSCON->PRESETCTRL1 &= ~(1 << 1); LPC_SYSCON->PRESETCTRL1 &= ~(1 << 5);
LPC_RIT->MASK = 0; // Configure SCT3 as a 1MHz 32-bit counter with no auto limiting or match reload
LPC_RIT->MASK_H = 0; char sctClkDiv = ((SystemCoreClock + 1000000 - 1) / 1000000) - 1;
LPC_SCT3->CONFIG = (1 << 7) | (1 << 0);
LPC_SCT3->CTRL = (sctClkDiv << 5) | (1 << 3) | (1 << 2);
LPC_RIT->COUNTER = 0; // Configure SCT3 event 0 to fire on match register 0
LPC_RIT->COUNTER_H = 0; LPC_SCT3->EV0_STATE = (1 << 0);
LPC_SCT3->EV0_CTRL = (0x1 << 12);
LPC_RIT->COMPVAL = 0xffffffff; // Start SCT3
LPC_RIT->COMPVAL_H = 0x0000ffff; LPC_SCT3->CTRL &= ~(1 << 2);
// Timer enable, enable for debug
LPC_RIT->CTRL = 0xC;
// Set SCT3 interrupt vector
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
} }
@ -52,22 +55,29 @@ uint32_t us_ticker_read() {
if (!us_ticker_inited) if (!us_ticker_inited)
us_ticker_init(); us_ticker_init();
uint64_t temp; // Return SCT3 count value
temp = LPC_RIT->COUNTER | ((uint64_t)LPC_RIT->COUNTER_H << 32); return LPC_SCT3->COUNT;
temp /= (SystemCoreClock/1000000);
return (uint32_t)temp;
} }
void us_ticker_set_interrupt(timestamp_t timestamp) { void us_ticker_set_interrupt(timestamp_t timestamp) {
uint64_t temp = ((uint64_t)timestamp * (SystemCoreClock/1000000)); // Set SCT3 match register 0 (critical section)
LPC_RIT->COMPVAL = (temp & 0xFFFFFFFFL); int wasMasked = __disable_irq();
LPC_RIT->COMPVAL_H = ((temp >> 32)& 0x0000FFFFL); LPC_SCT3->CTRL |= (1 << 2);
LPC_SCT3->MATCH0 = (uint32_t)timestamp;
LPC_SCT3->CTRL &= ~(1 << 2);
if (!wasMasked)
__enable_irq();
// Enable interrupt on SCT3 event 0
LPC_SCT3->EVEN = (1 << 0);
} }
void us_ticker_disable_interrupt(void) { void us_ticker_disable_interrupt(void) {
LPC_RIT->CTRL |= (1 << 3); // Disable interrupt on SCT3 event 0
LPC_SCT3->EVEN = 0;
} }
void us_ticker_clear_interrupt(void) { void us_ticker_clear_interrupt(void) {
LPC_RIT->CTRL |= (1 << 0); // Clear SCT3 event 0 interrupt flag
LPC_SCT3->EVFLAG = (1 << 0);
} }