mirror of https://github.com/ARMmbed/mbed-os.git
Refactor flash setup for MIMXRT105x devices, add flash API support for MIMXRT1062 EVK (#187)
* Refactor flash setup for MIMXRT105x devices, adds flash support for MIMXRT1062 EVK * Remove commented code * Use BOARD_FLASH_SIZE in boot headers * Fix setting which should be disabled in run modepull/15494/head
Jamie Smith
GitHub
parent
05a57dc62c
commit
9f4987d1cb
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@ -187,11 +187,8 @@ if(NOT MBED_IS_NATIVE_BUILD)
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# We must set this global property before the targets subdirectory is added to the project. This is
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# required because the MBED_TARGET depends on the response file. If the path to the response file
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# is not defined when the target requests it the config definitions will not be passed to CPP.
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#
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# TODO: Remove this and find a more idiomatic way of passing compile definitions to CPP without
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# using response files or global properties.
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mbed_generate_options_for_linker(mbed-core-flags RESPONSE_FILE_PATH)
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set_property(GLOBAL PROPERTY COMPILE_DEFS_RESPONSE_FILE ${RESPONSE_FILE_PATH})
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set_property(GLOBAL PROPERTY LINKER_SCRIPT_PREPROCESS_FLAGS_RESPONSE_FILE ${RESPONSE_FILE_PATH})
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# Add compile definitions for backward compatibility with the toolchain
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# supported. New source files should instead check for __GNUC__ and __clang__
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@ -32,7 +32,8 @@
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#include "platform/NonCopyable.h"
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#include <algorithm>
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// Export ROM end address
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// Export ROM end address, if not defined by HAL layer
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#ifndef FLASHIAP_APP_ROM_END_ADDR
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#if defined(TOOLCHAIN_GCC_ARM)
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extern uint32_t __etext;
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extern uint32_t __data_start__;
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@ -48,6 +49,7 @@ extern uint32_t Load$$LR$$LR_IROM1$$Limit[];
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#define FLASHIAP_APP_ROM_END_ADDR std::max(std::max((uint32_t) __section_end(".rodata"), (uint32_t) __section_end(".text")), \
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(uint32_t) __section_end(".init_array"))
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#endif
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#endif
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namespace mbed {
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@ -111,7 +111,10 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
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*/
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uint32_t flash_get_page_size(const flash_t *obj);
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/** Get start address for the flash region
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/** Get start address for the flash region (as in, where the flash is mapped in main memory).
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*
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* \note This should return the start address of the entire flash region, not
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* the first address after the end of the program in flash.
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*
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* @param obj The flash object
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* @return The start address for the flash region
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@ -12,8 +12,7 @@ target_include_directories(mbed-mimxrt1050-evk
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target_sources(mbed-mimxrt1050-evk
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INTERFACE
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fsl_flexspi_nor_boot.c
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TARGET_1050_EVK/flash_api.c
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flash_api.c
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TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.c
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TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c
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@ -35,6 +34,7 @@ target_include_directories(mbed-mimxrt1060-evk
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target_sources(mbed-mimxrt1060-evk
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INTERFACE
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fsl_flexspi_nor_boot.c
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flash_api.c
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TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.c
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TARGET_1060_EVK/xip/dcd.c
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@ -12,6 +12,8 @@
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#define FSL_COMPONENT_ID "platform.drivers.xip_board"
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#endif
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#include "mimxrt_memory_info.h"
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/*******************************************************************************
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* Code
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******************************************************************************/
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@ -37,7 +39,7 @@ const flexspi_nor_config_t hyperflash_config = {
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(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
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.sflashPadType = kSerialFlash_8Pads,
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.serialClkFreq = kFlexSpiSerialClk_133MHz,
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.sflashA1Size = 64u * 1024u * 1024u,
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.sflashA1Size = BOARD_FLASH_SIZE,
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.dataValidTime = {16u, 16u},
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.lookupTable = {
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// Read LUTs
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@ -66,7 +68,7 @@ const flexspi_nor_config_t qspiflash_config = {
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_133MHz,
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.lutCustomSeqEnable = 0u,
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.sflashA1Size = 0x00800000u, /* 8MB/64Mbit */
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.sflashA1Size = BOARD_FLASH_SIZE,
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.lookupTable = {
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// Fast read sequence
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[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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@ -6,6 +6,7 @@
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*/
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#include "evkbmimxrt1060_flexspi_nor_config.h"
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#include "mimxrt_memory_info.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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@ -34,7 +35,7 @@ const flexspi_nor_config_t qspiflash_config = {
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_120MHz,
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.sflashA1Size = 8u * 1024u * 1024u,
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.sflashA1Size = BOARD_FLASH_SIZE,
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.lookupTable =
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{
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// Read LUTs
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@ -19,25 +19,9 @@
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#ifndef MBED_DEVICE_H
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#define MBED_DEVICE_H
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#define DEVICE_ID_LENGTH 24
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#include <stdint.h>
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#ifdef HYPERFLASH_BOOT
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/* 64MB HyperFlash, 4MB reserved for mbed-os */
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#define BOARD_FLASH_SIZE (0x4000000U)
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#define BOARD_FLASH_START_ADDR (0x60000000U)
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#define BOARD_FLASHIAP_SIZE (0x3C00000U)
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#define BOARD_FLASHIAP_START_ADDR (0x60400000U)
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#define BOARD_FLASH_PAGE_SIZE (512)
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#define BOARD_FLASH_SECTOR_SIZE (262144)
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#else
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/* 8MB QSPI Flash, 64KB reserved for mbed_bootloader */
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#define BOARD_FLASH_SIZE (0x800000U)
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#define BOARD_FLASH_START_ADDR (0x60000000U)
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#define BOARD_FLASHIAP_SIZE (0x7F0000U)
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#define BOARD_FLASHIAP_START_ADDR (0x60010000U)
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#define BOARD_FLASH_PAGE_SIZE (256)
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#define BOARD_FLASH_SECTOR_SIZE (4096)
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#endif
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#define DEVICE_ID_LENGTH 24
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#define BOARD_ENET_PHY_ADDR (2)
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@ -45,6 +29,12 @@
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to be as vector table */
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#undef __VECTOR_TABLE
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// The MIMXRT linker script provides the __USED_FLASH_END symbol to
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// indicate where application data ends in flash
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extern uint8_t __USED_FLASH_END[0];
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#define FLASHIAP_APP_ROM_END_ADDR ((uint32_t)__USED_FLASH_END)
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#include "mimxrt_memory_info.h"
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#include "objects.h"
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#endif
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@ -24,6 +24,10 @@
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#include "fsl_flexspi.h"
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#include "fsl_cache.h"
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#include "flash_defines.h"
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#include "mimxrt_flash_api.h"
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#include <inttypes.h>
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#include <stdio.h>
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AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void));
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr));
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@ -103,6 +107,13 @@ void flexspi_update_lut_ram(void)
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config.enableSckBDiffOpt = true;
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config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
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config.enableCombination = true;
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/* Wait for bus idle. It seems to be important to hold off on calling
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* FLEXSPI_Init() until after the bus is idle; I was getting random crashes
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* until I added this. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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FLEXSPI_Init(FLEXSPI, &config);
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/* Configure flash settings according to serial flash feature. */
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@ -116,6 +127,10 @@ void flexspi_update_lut_ram(void)
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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// Just in case any bad data got into the I-cache while we were reconfiguring
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// the flash, wipe it.
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SCB_InvalidateICache();
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}
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status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
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@ -319,13 +334,31 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr
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#else
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void));
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_read_status_register_ram(uint32_t * result));
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/*
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* Check if quad SPI mode is enabled and, if not, enable it.
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*
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* Note that I'm not totally sure if this function is needed because I don't think
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* that the application could boot without quad mode enabled, but this might be
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* useful for programming non-boot-device flashes at a later date.
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* Or, if you must run the application on a flash which does not have quad mode enabled,
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* you could temporarily change the boot header read command to use 1-pad read,
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* then rely on this function to update the setting.
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*/
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status_t flexspi_nor_enable_quad_mode_ram(void)
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{
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flexspi_transfer_t flashXfer;
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uint32_t writeValue = FLASH_QUAD_ENABLE;
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status_t status = kStatus_Success;
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uint32_t readResult = 0;
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status_t status = flexspi_nor_read_status_register_ram(&readResult);
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if (status != kStatus_Success) {
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return status;
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}
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if(readResult & (1 << FLASH_QE_STATUS_OFFSET)) {
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// QSPI mode already enabled, don't need to do anything
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return kStatus_Success;
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}
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flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
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/* Write enable */
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status = flexspi_nor_write_enable_ram(0);
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@ -334,6 +367,8 @@ status_t flexspi_nor_enable_quad_mode_ram(void)
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}
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/* Enable quad mode. */
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flexspi_transfer_t flashXfer = {};
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uint32_t writeValue = (1 << FLASH_QE_STATUS_OFFSET);
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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@ -349,17 +384,12 @@ status_t flexspi_nor_enable_quad_mode_ram(void)
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status = flexspi_nor_wait_bus_busy_ram();
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/* Do software reset. */
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FLEXSPI_SoftwareReset(FLEXSPI);
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return status;
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}
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void flexspi_update_lut_ram(void)
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{
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flexspi_config_t config;
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flexspi_memset(&config, 0, sizeof(config));
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flexspi_config_t config = {};
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/*Get FLEXSPI default settings and configure the flexspi. */
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FLEXSPI_GetDefaultConfig(&config);
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@ -370,6 +400,15 @@ void flexspi_update_lut_ram(void)
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config.ahbConfig.enableReadAddressOpt = true;
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config.ahbConfig.enableAHBCachable = true;
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config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
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config.enableDoze = false; // matches boot rom setting
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config.seqTimeoutCycle = 0xee6c; // matches boot rom setting
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/* Wait for bus idle. It seems to be important to hold off on calling
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* FLEXSPI_Init() until after the bus is idle; I was getting random crashes
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* until I added this. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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FLEXSPI_Init(FLEXSPI, &config);
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/* Configure flash settings according to serial flash feature. */
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@ -383,7 +422,12 @@ void flexspi_update_lut_ram(void)
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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flexspi_nor_enable_quad_mode_ram();
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// Just in case any bad data got into the I-cache while we were reconfiguring
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// the flash, wipe it.
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SCB_InvalidateICache();
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}
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status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
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@ -404,47 +448,46 @@ status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
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return status;
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}
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status_t flexspi_nor_wait_bus_busy_ram(void)
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// Read the status register and save the result into the given pointer
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status_t flexspi_nor_read_status_register_ram(uint32_t * result)
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{
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/* Wait status ready. */
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bool isBusy;
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uint32_t readValue;
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status_t status = kStatus_Success;
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flexspi_transfer_t flashXfer;
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flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
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flexspi_transfer_t flashXfer = {};
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
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flashXfer.data = &readValue;
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flashXfer.data = result;
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flashXfer.dataSize = 1;
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return FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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}
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status_t flexspi_nor_wait_bus_busy_ram(void)
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{
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/* Wait status ready. */
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bool isBusy;
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do {
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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uint32_t readResult;
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status_t status = flexspi_nor_read_status_register_ram(&readResult);
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if (status != kStatus_Success) {
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return status;
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}
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if (FLASH_BUSY_STATUS_POL) {
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if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
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isBusy = true;
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} else {
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isBusy = false;
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}
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} else {
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if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
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isBusy = false;
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} else {
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isBusy = true;
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if(readResult & (1U << FLASH_BUSY_STATUS_OFFSET)) {
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isBusy = FLASH_BUSY_STATUS_POL;
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}
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else
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{
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isBusy = !FLASH_BUSY_STATUS_POL;
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}
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} while (isBusy);
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return status;
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return kStatus_Success;
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}
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@ -540,12 +583,18 @@ void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t s
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memcpy(buffer, (void *)addr, size);
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}
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int32_t flash_init(flash_t *obj)
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void mimxrt_flash_setup(void)
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{
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core_util_critical_section_enter();
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flexspi_update_lut_ram();
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core_util_critical_section_exit();
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}
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int32_t flash_init(flash_t *obj)
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{
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// Setup is already done when the application boots by flash_setup().
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// Nothing left to do.
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(void)obj;
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return 0;
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}
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@ -581,6 +630,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
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if (status != kStatus_Success) {
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ret = -1;
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} else {
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SCB_InvalidateICache_by_Addr((void*)address, (int32_t)size);
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SCB_InvalidateDCache_by_Addr((void*)address, (int32_t)size);
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DCACHE_InvalidateByRange(address, size);
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}
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@ -604,8 +655,8 @@ int32_t flash_free(flash_t *obj)
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uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
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{
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uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
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uint32_t devicesize = BOARD_FLASHIAP_SIZE;
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uint32_t startaddr = BOARD_FLASHIAP_START_ADDR;
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uint32_t devicesize = BOARD_FLASH_SIZE;
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uint32_t startaddr = BOARD_FLASH_START_ADDR;
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if ((address >= startaddr) && (address < (startaddr + devicesize))) {
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sectorsize = BOARD_FLASH_SECTOR_SIZE;
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@ -621,12 +672,12 @@ uint32_t flash_get_page_size(const flash_t *obj)
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uint32_t flash_get_start_address(const flash_t *obj)
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{
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return BOARD_FLASHIAP_START_ADDR;
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return BOARD_FLASH_START_ADDR;
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}
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uint32_t flash_get_size(const flash_t *obj)
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{
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return BOARD_FLASHIAP_SIZE;
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return BOARD_FLASH_SIZE;
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}
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uint8_t flash_get_erase_value(const flash_t *obj)
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@ -19,7 +19,7 @@
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#include "fsl_common.h"
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#ifdef HYPERFLASH_BOOT /* 64MB Hyperflash */
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#ifdef HYPERFLASH_BOOT /* 64MB Hyperflash S26KS512SDPBHI02 */
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
|
||||
|
|
@ -177,7 +177,7 @@ flexspi_device_config_t deviceconfig = {
|
|||
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
|
||||
.AHBWriteWaitInterval = 20,
|
||||
};
|
||||
#else /* 8MB QSPI flash */
|
||||
#else /* 8MB QSPI flash IS25WP064AJBLE */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13
|
||||
|
|
@ -194,10 +194,16 @@ flexspi_device_config_t deviceconfig = {
|
|||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5
|
||||
#define CUSTOM_LUT_LENGTH 60
|
||||
#define FLASH_QUAD_ENABLE 0x40
|
||||
|
||||
// Polarity of the BUSY bit in the status register -- 1 here means the flash is BUSY wheb
|
||||
#define FLASH_BUSY_STATUS_POL 1
|
||||
|
||||
// Shift of the BUSY bit in the status register
|
||||
#define FLASH_BUSY_STATUS_OFFSET 0
|
||||
|
||||
// Shift of the Quad Enable bit in the status register
|
||||
#define FLASH_QE_STATUS_OFFSET 6
|
||||
|
||||
static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
|
||||
/* Normal read mode -SDR */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
|
||||
|
|
@ -245,7 +251,7 @@ static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
|
|||
[4 * NOR_CMD_LUT_SEQ_IDX_READID] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
|
||||
|
||||
/* Enable Quad mode */
|
||||
/* Write Status Register (used to enable quad mode) */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
|
||||
|
||||
|
|
@ -270,14 +276,14 @@ flexspi_device_config_t deviceconfig = {
|
|||
.flexspiRootClk = 120000000,
|
||||
.flashSize = (BOARD_FLASH_SIZE/1024),
|
||||
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
|
||||
.CSInterval = 2,
|
||||
.CSInterval = 0,
|
||||
.CSHoldTime = 3,
|
||||
.CSSetupTime = 3,
|
||||
.dataValidTime = 0,
|
||||
.columnspace = 0,
|
||||
.enableWordAddress = 0,
|
||||
.AWRSeqIndex = 0,
|
||||
.AWRSeqNumber = 0,
|
||||
.AWRSeqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE,
|
||||
.AWRSeqNumber = 1,
|
||||
.ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
|
||||
.ARDSeqNumber = 1,
|
||||
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2023 ARM Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MBED_OS_MIMXRT_FLASH_API_H
|
||||
#define MBED_OS_MIMXRT_FLASH_API_H
|
||||
|
||||
#include <fsl_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* When the MIMXRT initially boots, the flash peripheral (FlexSPI) has been configured
|
||||
* by the ROM bootloader based on the boot header attached to the program image.
|
||||
*
|
||||
* This function "takes over" control of the peripheral from the bootloader, and
|
||||
* uses the app-level FLEXSPI HAL driver to reconfigure it with settings from flash_defines.h.
|
||||
* Note that we need to be careful that this is done correctly because these settings are
|
||||
* used for the instruction read pipeline as well as for writing the flash, so if we mess up,
|
||||
* the code will crash in an ugly way. When debugging this code, I recommend using a register
|
||||
* viewer to view the state of FLEXSPI before and after this function runs and verify that
|
||||
* there are no significant differences.
|
||||
*
|
||||
* The main "reason" this exists is that the boot rom apparently doesn't insert the
|
||||
* sequences for erasing & programming pages into the FlexSPI sequence LUT when it
|
||||
* jumps to the application, *even if* those sequences exist in the boot header (????).
|
||||
* So, we need to build our own sequences in the application and use them instead of
|
||||
* what we booted up with.
|
||||
*/
|
||||
void mimxrt_flash_setup(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //MBED_OS_MIMXRT_FLASH_API_H
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2023 ARM Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
#define MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
|
||||
#ifdef HYPERFLASH_BOOT
|
||||
/* 64MB HyperFlash */
|
||||
#define BOARD_FLASH_SIZE (0x4000000)
|
||||
#define BOARD_FLASH_START_ADDR (0x60000000)
|
||||
#define BOARD_FLASH_PAGE_SIZE (512)
|
||||
#define BOARD_FLASH_SECTOR_SIZE (262144)
|
||||
#else
|
||||
/* 8MB QSPI Flash */
|
||||
#define BOARD_FLASH_SIZE (0x800000)
|
||||
#define BOARD_FLASH_START_ADDR (0x60000000)
|
||||
#define BOARD_FLASH_PAGE_SIZE (256)
|
||||
#define BOARD_FLASH_SECTOR_SIZE (4096)
|
||||
#endif
|
||||
|
||||
// Unless the user overrides it, define the app to use the entire flash space.
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START BOARD_FLASH_START_ADDR
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE BOARD_FLASH_SIZE
|
||||
#endif
|
||||
|
||||
#define MIMXRT105X_BOARD_HAS_EXTERNAL_RAM 1
|
||||
#define MIMXRT105X_EXTERNAL_RAM_SIZE 0x02000000
|
||||
|
||||
#endif //MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2023 ARM Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
#define MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
|
||||
/* 2MB QSPI Flash */
|
||||
#define BOARD_FLASH_SIZE (0x1F0000) // 1984k
|
||||
#define BOARD_FLASH_START_ADDR (0x60000000)
|
||||
#define BOARD_FLASH_PAGE_SIZE (256)
|
||||
#define BOARD_FLASH_SECTOR_SIZE (4096)
|
||||
|
||||
// Unless the user overrides it, define the app to use the entire flash space.
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START BOARD_FLASH_START_ADDR
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE BOARD_FLASH_SIZE
|
||||
#endif
|
||||
|
||||
#define MIMXRT105X_BOARD_HAS_EXTERNAL_RAM 0
|
||||
|
||||
#endif //MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2023 ARM Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
#define MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
|
||||
/* 8MB QSPI Flash */
|
||||
#define BOARD_FLASH_SIZE (0x7C0000) // 7936k
|
||||
#define BOARD_FLASH_START_ADDR (0x60000000)
|
||||
#define BOARD_FLASH_PAGE_SIZE (256)
|
||||
#define BOARD_FLASH_SECTOR_SIZE (4096)
|
||||
|
||||
// Unless the user overrides it, define the app to use the entire flash space.
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START BOARD_FLASH_START_ADDR
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE BOARD_FLASH_SIZE
|
||||
#endif
|
||||
|
||||
#define MIMXRT105X_BOARD_HAS_EXTERNAL_RAM 0
|
||||
|
||||
#endif //MBED_OS_MIMXRT_MEMORY_INFO_H
|
||||
|
|
@ -40,6 +40,7 @@
|
|||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <mimxrt_flash_info.h>
|
||||
|
||||
extern void Reset_Handler(void);
|
||||
extern unsigned long _estack;
|
||||
|
|
@ -105,7 +106,7 @@ uint32_t FlexSPI_NOR_Config[128] = {
|
|||
#elif defined(TARGET_TEENSY_41)
|
||||
0x00800000, // sflashA1Size 0x50
|
||||
#else
|
||||
#error "Unknow flash chip size";
|
||||
#error "Unknown flash chip size";
|
||||
#endif
|
||||
0, // sflashA2Size
|
||||
0, // sflashB1Size
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@
|
|||
// Set to 1 by MIMXRT pullups/pulldowns on CRS_DV and RXD0
|
||||
#define BOARD_ENET_PHY_ADDR 1
|
||||
|
||||
#include "mimxrt_memory_info.h"
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,19 +25,14 @@
|
|||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Pick up memory info for this specific device */
|
||||
#include <mimxrt_memory_info.h>
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
__ram_vector_table__ = 1;
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x60000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
||||
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
|
@ -50,31 +45,21 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
|
|||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
#if !defined(MBED_APP_COMPILE)
|
||||
m_flash_config (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00001000
|
||||
m_ivt (RX) : ORIGIN = MBED_APP_START + 0x1000, LENGTH = 0x00001000
|
||||
m_interrupts (RX) : ORIGIN = MBED_APP_START + 0x2000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = MBED_APP_START + 0x2400, LENGTH = MBED_APP_SIZE - 0x2400
|
||||
#else
|
||||
m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
|
||||
#endif
|
||||
|
||||
#if MIMXRT105X_BOARD_HAS_EXTERNAL_RAM
|
||||
/* Use the external RAM as main memory */
|
||||
m_data (RW) : ORIGIN = 0x80000000, LENGTH = MIMXRT105X_EXTERNAL_RAM_SIZE
|
||||
|
||||
/* DTCM memory.
|
||||
Startup code configures size to 256k (stealing space from OCRAM). */
|
||||
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
|
||||
#if MIMXRT105X_BOARD_HAS_EXTERNAL_RAM
|
||||
/* Use the external RAM as main memory */
|
||||
m_data (RW) : ORIGIN = 0x80000000, LENGTH = MIMXRT105X_EXTERNAL_RAM_SIZE
|
||||
#else
|
||||
/* Use DTCM as main memory (significantly faster than OCRAM).
|
||||
Startup code configures size to 256k (stealing space from OCRAM). */
|
||||
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
|
||||
/* No external data memory, store data in DTCM */
|
||||
/* No external data memory, store data in DTCM (significantly faster than OCRAM)*/
|
||||
#define m_data m_dtcm
|
||||
|
||||
#endif
|
||||
|
||||
/* ITCM bank -- used for functions that need to execute from RAM
|
||||
|
|
|
|||
|
|
@ -268,6 +268,10 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
|
|||
FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) |
|
||||
#endif
|
||||
FLEXSPI_MCR0_MDIS_MASK;
|
||||
|
||||
/* Bit 15 is reserved and must be set to 1 */
|
||||
configValue |= (1 << 15);
|
||||
|
||||
base->MCR0 = configValue;
|
||||
|
||||
/* Configure MCR1 configurations. */
|
||||
|
|
|
|||
|
|
@ -195,15 +195,8 @@ void LPM_Init(void)
|
|||
|
||||
/* DCM Mode */
|
||||
DCDC_BootIntoDCM(DCDC);
|
||||
/* Adjust SOC voltage to 1.275V */
|
||||
DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1);
|
||||
/* Disconnect internal the load resistor */
|
||||
DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK;
|
||||
|
||||
/* Enable FET ODRIVE */
|
||||
PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK;
|
||||
/* Connect vdd_high_in and connect vdd_snvs_in */
|
||||
PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
|
||||
}
|
||||
|
||||
void LPM_EnableWakeupSource(uint32_t irq)
|
||||
|
|
@ -308,6 +301,10 @@ void LPM_AdjustSystemSettings(lpm_power_mode_t curRunMode, lpm_power_mode_t targ
|
|||
ClockSelectRcOsc();
|
||||
/* Adjust SOC voltage to 0.95V */
|
||||
DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1);
|
||||
|
||||
/* Enable FET ODRIVE */
|
||||
PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK;
|
||||
|
||||
EnableWeakLDO();
|
||||
DisableRegularLDO();
|
||||
BandgapOff();
|
||||
|
|
@ -329,12 +326,18 @@ void LPM_AdjustSystemSettings(lpm_power_mode_t curRunMode, lpm_power_mode_t targ
|
|||
ClockSelectRcOsc();
|
||||
/* Adjust SOC voltage to 0.95V */
|
||||
DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1);
|
||||
|
||||
/* Enable FET ODRIVE */
|
||||
PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK;
|
||||
|
||||
EnableWeakLDO();
|
||||
DisableRegularLDO();
|
||||
BandgapOff();
|
||||
}
|
||||
break;
|
||||
case LPM_PowerModeLowPowerRun:
|
||||
/* Disable FET ODRIVE */
|
||||
PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK;
|
||||
if (targetMode == LPM_PowerModeOverRun)
|
||||
{
|
||||
/* Adjust SOC voltage to 1.275V */
|
||||
|
|
|
|||
|
|
@ -16,9 +16,6 @@
|
|||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define LPM_EnterCritical()
|
||||
#define LPM_ExitCritical()
|
||||
|
||||
/*
|
||||
* Power mode definition of low power management.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -26,6 +26,11 @@
|
|||
#include "usb_device_config.h"
|
||||
#include "us_ticker_defines.h"
|
||||
#include "us_ticker_api.h"
|
||||
#include "flash_api.h"
|
||||
|
||||
#if DEVICE_FLASH
|
||||
#include "mimxrt_flash_api.h"
|
||||
#endif
|
||||
|
||||
#define LPSPI_CLOCK_SOURCE_DIVIDER (7U)
|
||||
#define LPI2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
|
|
@ -183,10 +188,14 @@ void mbed_sdk_init()
|
|||
BOARD_ClockFullSpeed();
|
||||
#endif
|
||||
|
||||
// Switch to using an application-owned flexspi config instead of what the bootloader sets up
|
||||
#if DEVICE_FLASH
|
||||
mimxrt_flash_setup();
|
||||
#endif
|
||||
|
||||
// Initialize us ticker before LPM, because LPM uses it for timing
|
||||
us_ticker_init();
|
||||
|
||||
|
||||
#if TARGET_EVK
|
||||
/* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is
|
||||
* connected to LCD power switch circuit. So it needs to be configured as a low-level output GPIO to reduce the
|
||||
|
|
@ -283,7 +292,7 @@ void mbed_mac_address(char *mac) {
|
|||
|
||||
uint8_t mbed_otp_mac_address(char *mac) {
|
||||
|
||||
#if TARGET_MIMXRT1050_EVK
|
||||
#if TARGET_EVK
|
||||
/* Check if a valid MAC address is programmed to the fuse bank */
|
||||
if ((OCOTP->MAC0 != 0) &&
|
||||
(OCOTP->MAC1 != 0) &&
|
||||
|
|
|
|||
|
|
@ -27,7 +27,9 @@
|
|||
#include "fsl_clock.h"
|
||||
#include "lpm.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_flexspi.h"
|
||||
#include "clock_config.h"
|
||||
#include "mbed_critical.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <inttypes.h>
|
||||
|
|
@ -40,11 +42,15 @@ AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode)
|
|||
|
||||
void SwitchSystemClocks(lpm_power_mode_t power_mode)
|
||||
{
|
||||
// Make sure no one interrupts us while we're messing with clocks
|
||||
core_util_critical_section_enter();
|
||||
|
||||
#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
LPM_EnterCritical();
|
||||
while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
|
||||
{
|
||||
|
||||
/* Wait for bus idle. */
|
||||
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
|
||||
}
|
||||
|
||||
FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
|
||||
|
||||
/* Disable clock gate of flexspi. */
|
||||
|
|
@ -100,15 +106,21 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode)
|
|||
CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);
|
||||
|
||||
FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
|
||||
FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
|
||||
while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
|
||||
{
|
||||
|
||||
FLEXSPI_SoftwareReset(FLEXSPI);
|
||||
|
||||
/* Wait for bus idle. */
|
||||
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
|
||||
}
|
||||
while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
|
||||
{
|
||||
}
|
||||
LPM_ExitCritical();
|
||||
|
||||
// TODO it seems like the process of changing the FlexSPI clock introduces corrupt
|
||||
// data into the instruction cache of the processor. Without this line,
|
||||
// pretty much anything that uses deep sleep will hardfault.
|
||||
// It hurts performance but I wasn't able to figure out a way around it.
|
||||
SCB_InvalidateICache();
|
||||
#endif
|
||||
|
||||
core_util_critical_section_exit();
|
||||
}
|
||||
|
||||
void ClockSetToOverDriveRun(void)
|
||||
|
|
@ -162,18 +174,6 @@ void ClockSetToLowPowerRun(void)
|
|||
CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK;
|
||||
CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK;
|
||||
CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK;
|
||||
|
||||
/* Deinit USB2 PLL */
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
|
||||
/* Deinit AUDIO PLL */
|
||||
CLOCK_DeinitAudioPll();
|
||||
|
||||
/* Deinit VIDEO PLL */
|
||||
CLOCK_DeinitVideoPll();
|
||||
|
||||
/* Deinit ENET PLL */
|
||||
CLOCK_DeinitEnetPll();
|
||||
}
|
||||
|
||||
#define GPR4_STOP_REQ_BITS \
|
||||
|
|
|
|||
|
|
@ -5149,7 +5149,6 @@
|
|||
"FSL_RTOS_MBED",
|
||||
"XIP_BOOT_HEADER_ENABLE=1",
|
||||
"XIP_EXTERNAL_FLASH=1",
|
||||
"HYPERFLASH_BOOT",
|
||||
"FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1",
|
||||
"SKIP_SYSCLK_INIT",
|
||||
"__STARTUP_INITIALIZE_RAMFUNCTION",
|
||||
|
|
@ -5214,10 +5213,9 @@
|
|||
"ARDUINO_UNO"
|
||||
],
|
||||
"macros_add": [
|
||||
"HYPERFLASH_BOOT",
|
||||
"XIP_BOOT_HEADER_DCD_ENABLE=1",
|
||||
"FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE",
|
||||
"MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=1",
|
||||
"MIMXRT105X_EXTERNAL_RAM_SIZE=0x02000000"
|
||||
"FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE"
|
||||
],
|
||||
"device_has_add": [
|
||||
"FLASH"
|
||||
|
|
@ -5244,10 +5242,10 @@
|
|||
],
|
||||
"macros_add": [
|
||||
"XIP_BOOT_HEADER_DCD_ENABLE=1",
|
||||
"FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE",
|
||||
"MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=1",
|
||||
"MIMXRT105X_EXTERNAL_RAM_SIZE=0x01E00000",
|
||||
"MBED_APP_SIZE=0x800000"
|
||||
"FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE"
|
||||
],
|
||||
"device_has_add": [
|
||||
"FLASH"
|
||||
],
|
||||
"overrides": {
|
||||
"network-default-interface-type": "ETHERNET"
|
||||
|
|
@ -5262,10 +5260,6 @@
|
|||
"TEENSY_40",
|
||||
"MIMXRT1060"
|
||||
],
|
||||
"macros_add": [
|
||||
"MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=0",
|
||||
"MBED_APP_SIZE=0x1f0000"
|
||||
],
|
||||
"overrides": {
|
||||
"console-usb": true,
|
||||
"console-uart": false
|
||||
|
|
@ -5283,10 +5277,6 @@
|
|||
"TEENSY_41",
|
||||
"MIMXRT1060"
|
||||
],
|
||||
"macros_add": [
|
||||
"MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=0",
|
||||
"MBED_APP_SIZE=0x7C0000"
|
||||
],
|
||||
"overrides": {
|
||||
"console-usb": true,
|
||||
"console-uart": false,
|
||||
|
|
|
|||
|
|
@ -46,9 +46,9 @@ function(mbed_setup_linker_script mbed_os_target mbed_baremetal_target target_de
|
|||
set(LINKER_SCRIPT_PATH ${CMAKE_BINARY_DIR}/${MBED_TARGET_CMAKE_NAME}.link_script.ld)
|
||||
|
||||
# To avoid path limits on Windows, we create a "response file" and set the path to it as a
|
||||
# global property. We need this solely to pass the compile definitions to GCC's preprocessor,
|
||||
# so it can expand any macro definitions in the linker script.
|
||||
get_property(linker_defs_response_file GLOBAL PROPERTY COMPILE_DEFS_RESPONSE_FILE)
|
||||
# global property. We need this solely to pass the compile definitions and include paths
|
||||
# to GCC's preprocessor, so it can expand any macro definitions in the linker script.
|
||||
get_property(linker_defs_response_file GLOBAL PROPERTY LINKER_SCRIPT_PREPROCESS_FLAGS_RESPONSE_FILE)
|
||||
|
||||
get_filename_component(RAW_LINKER_SCRIPT_NAME ${RAW_LINKER_SCRIPT_PATHS} NAME)
|
||||
get_filename_component(LINKER_SCRIPT_NAME ${LINKER_SCRIPT_PATH} NAME)
|
||||
|
|
@ -114,7 +114,7 @@ function(mbed_set_custom_linker_script target new_linker_script_path)
|
|||
# To avoid path limits on Windows, we create a "response file" and set the path to it as a
|
||||
# global property. We need this solely to pass the compile definitions to GCC's preprocessor,
|
||||
# so it can expand any macro definitions in the linker script.
|
||||
get_property(linker_defs_response_file GLOBAL PROPERTY COMPILE_DEFS_RESPONSE_FILE)
|
||||
get_property(linker_defs_response_file GLOBAL PROPERTY LINKER_SCRIPT_PREPROCESS_FLAGS_RESPONSE_FILE)
|
||||
|
||||
get_filename_component(RAW_LINKER_SCRIPT_NAME ${RAW_LINKER_SCRIPT_PATHS} NAME)
|
||||
get_filename_component(LINKER_SCRIPT_NAME ${CUSTOM_LINKER_SCRIPT_PATH} NAME)
|
||||
|
|
|
|||
|
|
@ -1,18 +1,28 @@
|
|||
# Copyright (c) 2020 ARM Limited. All rights reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Generate a file containing compile definitions
|
||||
# Generate a file containing compile definitions and include paths
|
||||
function(mbed_generate_options_for_linker target output_response_file_path)
|
||||
set(_compile_definitions
|
||||
"$<TARGET_PROPERTY:${target},INTERFACE_COMPILE_DEFINITIONS>"
|
||||
)
|
||||
set(_include_directories
|
||||
"$<TARGET_PROPERTY:${target},INTERFACE_INCLUDE_DIRECTORIES>"
|
||||
)
|
||||
|
||||
# Append -D to all macros and quote them as we pass these as response file to cxx compiler
|
||||
set(_compile_definitions
|
||||
"$<$<BOOL:${_compile_definitions}>:'-D$<JOIN:${_compile_definitions},' '-D>'>"
|
||||
)
|
||||
file(GENERATE OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/compile_time_defs.txt" CONTENT "${_compile_definitions}\n")
|
||||
set(${output_response_file_path} ${CMAKE_CURRENT_BINARY_DIR}/compile_time_defs.txt PARENT_SCOPE)
|
||||
# Prepend -I to all macros and quote them as we pass these as response file to cxx compiler
|
||||
set(_include_directories
|
||||
"$<$<BOOL:${_compile_definitions}>:'-I$<JOIN:${_include_directories},' '-I>'>"
|
||||
)
|
||||
file(GENERATE OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/linker_script_preprocess_flags.txt" CONTENT
|
||||
"${_compile_definitions}
|
||||
${_include_directories}
|
||||
")
|
||||
set(${output_response_file_path} ${CMAKE_CURRENT_BINARY_DIR}/linker_script_preprocess_flags.txt PARENT_SCOPE)
|
||||
endfunction()
|
||||
|
||||
# Compiler setup
|
||||
|
|
|
|||
|
|
@ -60,6 +60,12 @@ set(UPLOAD_LAUNCH_COMMANDS
|
|||
"load"
|
||||
"break main"
|
||||
"monitor reset"
|
||||
|
||||
# Workaround for LinkServer supplying incomplete memory information to GDB
|
||||
# (in particular, seems to be missing the peripheral memory space and external RAM).
|
||||
# Without this command, GDB will block the user from accessing values in any of these
|
||||
# memory spaces.
|
||||
"set mem inaccessible-by-default off"
|
||||
)
|
||||
set(UPLOAD_RESTART_COMMANDS
|
||||
"monitor reset"
|
||||
|
|
|
|||
Loading…
Reference in New Issue