mirror of https://github.com/ARMmbed/mbed-os.git
Add EMAC support for NUCLEO_H743ZI
This port is based on :
* CurryGuy ethernet branch :
https://github.com/CurryGuy/mbed-os/tree/feature-stm32h7-emac
* STM32 Cube example :
Applications/LwIP/LwIP_HTTP_Server_Netconn_RTOS example
Signed-off-by: Vincent Veron <vincent.veron@st.com>
pull/11274/head
Vincent Veron
parent
181f4f7e93
commit
9f2e9aa576
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@ -0,0 +1,681 @@
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/**
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******************************************************************************
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* @file lan8742.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 08-March-2017
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* @brief This file provides a set of functions needed to manage the LAN742
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* PHY devices.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "lan8742.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Component
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* @{
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*/
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/** @defgroup LAN8742 LAN8742
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup LAN8742_Private_Defines LAN8742 Private Defines
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* @{
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*/
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#define LAN8742_SW_RESET_TO ((uint32_t)500U)
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#define LAN8742_INIT_TO ((uint32_t)2000U)
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#define LAN8742_MAX_DEV_ADDR ((uint32_t)31U)
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup LAN8742_Private_Functions LAN8742 Private Functions
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* @{
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*/
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/**
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* @brief Register IO functions to component object
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* @param pObj: device object of LAN8742_Object_t.
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* @param ioctx: holds device IO functions.
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* @retval LAN8742_STATUS_OK if OK
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* LAN8742_STATUS_ERROR if missing mandatory function
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*/
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int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx)
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{
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if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick)
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{
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return LAN8742_STATUS_ERROR;
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}
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pObj->IO.Init = ioctx->Init;
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pObj->IO.DeInit = ioctx->DeInit;
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pObj->IO.ReadReg = ioctx->ReadReg;
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pObj->IO.WriteReg = ioctx->WriteReg;
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pObj->IO.GetTick = ioctx->GetTick;
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return LAN8742_STATUS_OK;
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}
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/**
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* @brief Initialize the lan8742 and configure the needed hardware resources
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* @param pObj: device object LAN8742_Object_t.
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* @retval LAN8742_STATUS_OK if OK
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* LAN8742_STATUS_ADDRESS_ERROR if cannot find device address
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* LAN8742_STATUS_READ_ERROR if connot read register
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* LAN8742_STATUS_WRITE_ERROR if connot write to register
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* LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset
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*/
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int32_t LAN8742_Init(lan8742_Object_t *pObj)
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{
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uint32_t tickstart = 0, regvalue = 0, addr = 0;
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int32_t status = LAN8742_STATUS_OK;
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if(pObj->Is_Initialized == 0)
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{
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if(pObj->IO.Init != 0)
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{
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/* GPIO and Clocks initialization */
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pObj->IO.Init();
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}
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/* for later check */
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pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1;
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/* Get the device address from special mode register */
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for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++)
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{
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if(pObj->IO.ReadReg(addr, LAN8742_SMR, ®value) < 0)
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{
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status = LAN8742_STATUS_READ_ERROR;
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/* Can't read from this device address
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continue with next address */
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continue;
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}
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if((regvalue & LAN8742_SMR_PHY_ADDR) == addr)
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{
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pObj->DevAddr = addr;
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status = LAN8742_STATUS_OK;
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break;
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}
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}
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if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR)
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{
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status = LAN8742_STATUS_ADDRESS_ERROR;
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}
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/* if device address is matched */
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if(status == LAN8742_STATUS_OK)
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{
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/* set a software reset */
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if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0)
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{
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/* get software reset status */
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) >= 0)
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{
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tickstart = pObj->IO.GetTick();
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/* wait until software reset is done or timeout occured */
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while(regvalue & LAN8742_BCR_SOFT_RESET)
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{
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if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO)
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{
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) < 0)
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{
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status = LAN8742_STATUS_READ_ERROR;
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break;
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}
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}
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else
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{
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status = LAN8742_STATUS_RESET_TIMEOUT;
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}
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}
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}
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else
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{
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status = LAN8742_STATUS_READ_ERROR;
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}
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}
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else
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{
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status = LAN8742_STATUS_WRITE_ERROR;
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}
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}
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}
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if(status == LAN8742_STATUS_OK)
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{
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tickstart = pObj->IO.GetTick();
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/* Wait for 2s to perform initialization */
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while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO)
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{
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}
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pObj->Is_Initialized = 1;
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}
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return status;
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}
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/**
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* @brief De-Initialize the lan8742 and it's hardware resources
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* @param pObj: device object LAN8742_Object_t.
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* @retval None
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*/
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int32_t LAN8742_DeInit(lan8742_Object_t *pObj)
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{
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if(pObj->Is_Initialized)
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{
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if(pObj->IO.DeInit != 0)
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{
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if(pObj->IO.DeInit() < 0)
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{
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return LAN8742_STATUS_ERROR;
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}
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}
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pObj->Is_Initialized = 0;
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}
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return LAN8742_STATUS_OK;
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}
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/**
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* @brief Disable the LAN8742 power down mode.
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* @param pObj: device object LAN8742_Object_t.
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* @retval LAN8742_STATUS_OK if OK
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* LAN8742_STATUS_READ_ERROR if connot read register
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* LAN8742_STATUS_WRITE_ERROR if connot write to register
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*/
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int32_t LAN8742_DisablePowerDownMode(lan8742_Object_t *pObj)
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{
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uint32_t readval = 0;
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int32_t status = LAN8742_STATUS_OK;
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
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{
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readval &= ~LAN8742_BCR_POWER_DOWN;
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/* Apply configuration */
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if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
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{
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status = LAN8742_STATUS_WRITE_ERROR;
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}
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}
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else
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{
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status = LAN8742_STATUS_READ_ERROR;
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}
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return status;
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}
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/**
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* @brief Enable the LAN8742 power down mode.
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* @param pObj: device object LAN8742_Object_t.
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* @retval LAN8742_STATUS_OK if OK
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* LAN8742_STATUS_READ_ERROR if connot read register
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* LAN8742_STATUS_WRITE_ERROR if connot write to register
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*/
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int32_t LAN8742_EnablePowerDownMode(lan8742_Object_t *pObj)
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{
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uint32_t readval = 0;
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int32_t status = LAN8742_STATUS_OK;
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
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{
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readval |= LAN8742_BCR_POWER_DOWN;
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/* Apply configuration */
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if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
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{
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status = LAN8742_STATUS_WRITE_ERROR;
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}
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}
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else
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{
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status = LAN8742_STATUS_READ_ERROR;
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}
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return status;
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}
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/**
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* @brief Start the auto negotiation process.
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* @param pObj: device object LAN8742_Object_t.
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* @retval LAN8742_STATUS_OK if OK
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* LAN8742_STATUS_READ_ERROR if connot read register
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* LAN8742_STATUS_WRITE_ERROR if connot write to register
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*/
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int32_t LAN8742_StartAutoNego(lan8742_Object_t *pObj)
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{
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uint32_t readval = 0;
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int32_t status = LAN8742_STATUS_OK;
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
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{
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readval |= LAN8742_BCR_AUTONEGO_EN;
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/* Apply configuration */
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if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
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{
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status = LAN8742_STATUS_WRITE_ERROR;
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}
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}
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else
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{
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status = LAN8742_STATUS_READ_ERROR;
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}
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return status;
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}
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/**
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* @brief Get the link state of LAN8742 device.
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* @param pObj: Pointer to device object.
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* @param pLinkState: Pointer to link state
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* @retval LAN8742_STATUS_LINK_DOWN if link is down
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* LAN8742_STATUS_AUTONEGO_NOTDONE if Auto nego not completed
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* LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD
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* LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD
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* LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD
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* LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD
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* LAN8742_STATUS_READ_ERROR if connot read register
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* LAN8742_STATUS_WRITE_ERROR if connot write to register
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*/
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int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj)
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{
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uint32_t readval = 0;
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/* Read Status register */
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
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{
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return LAN8742_STATUS_READ_ERROR;
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}
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/* Read Status register again */
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
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{
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return LAN8742_STATUS_READ_ERROR;
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}
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if((readval & LAN8742_BSR_LINK_STATUS) == 0)
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{
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/* Return Link Down status */
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return LAN8742_STATUS_LINK_DOWN;
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}
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/* Check Auto negotiaition */
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0)
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{
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return LAN8742_STATUS_READ_ERROR;
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}
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if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN)
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{
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if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE))
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{
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return LAN8742_STATUS_100MBITS_FULLDUPLEX;
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}
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else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT)
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{
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return LAN8742_STATUS_100MBITS_HALFDUPLEX;
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}
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else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)
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{
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return LAN8742_STATUS_10MBITS_FULLDUPLEX;
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}
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else
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{
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return LAN8742_STATUS_10MBITS_HALFDUPLEX;
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}
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}
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else /* Auto Nego enabled */
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{
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0)
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{
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return LAN8742_STATUS_READ_ERROR;
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}
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/* Check if auto nego not done */
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if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0)
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{
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return LAN8742_STATUS_AUTONEGO_NOTDONE;
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}
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if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD)
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{
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return LAN8742_STATUS_100MBITS_FULLDUPLEX;
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}
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else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD)
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{
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return LAN8742_STATUS_100MBITS_HALFDUPLEX;
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}
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else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD)
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{
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return LAN8742_STATUS_10MBITS_FULLDUPLEX;
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}
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else
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{
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return LAN8742_STATUS_10MBITS_HALFDUPLEX;
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}
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}
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}
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/**
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* @brief Set the link state of LAN8742 device.
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* @param pObj: Pointer to device object.
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* @param pLinkState: link state can be one of the following
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* LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD
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* LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD
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* LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD
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* LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD
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* @retval LAN8742_STATUS_OK if OK
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* LAN8742_STATUS_ERROR if parameter error
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* LAN8742_STATUS_READ_ERROR if connot read register
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* LAN8742_STATUS_WRITE_ERROR if connot write to register
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*/
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int32_t LAN8742_SetLinkState(lan8742_Object_t *pObj, uint32_t LinkState)
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{
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uint32_t bcrvalue = 0;
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int32_t status = LAN8742_STATUS_OK;
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if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &bcrvalue) >= 0)
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{
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/* Disable link config (Auto nego, speed and duplex) */
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bcrvalue &= ~(LAN8742_BCR_AUTONEGO_EN | LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE);
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if(LinkState == LAN8742_STATUS_100MBITS_FULLDUPLEX)
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{
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bcrvalue |= (LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE);
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}
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else if (LinkState == LAN8742_STATUS_100MBITS_HALFDUPLEX)
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{
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bcrvalue |= LAN8742_BCR_SPEED_SELECT;
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}
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else if (LinkState == LAN8742_STATUS_10MBITS_FULLDUPLEX)
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{
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bcrvalue |= LAN8742_BCR_DUPLEX_MODE;
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}
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else
|
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{
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/* Wrong link status parameter */
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status = LAN8742_STATUS_ERROR;
|
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}
|
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}
|
||||
else
|
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{
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status = LAN8742_STATUS_READ_ERROR;
|
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}
|
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|
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if(status == LAN8742_STATUS_OK)
|
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{
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/* Apply configuration */
|
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if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, bcrvalue) < 0)
|
||||
{
|
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status = LAN8742_STATUS_WRITE_ERROR;
|
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}
|
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}
|
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return status;
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}
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|
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/**
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* @brief Enable loopback mode.
|
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* @param pObj: Pointer to device object.
|
||||
* @retval LAN8742_STATUS_OK if OK
|
||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||
*/
|
||||
int32_t LAN8742_EnableLoopbackMode(lan8742_Object_t *pObj)
|
||||
{
|
||||
uint32_t readval = 0;
|
||||
int32_t status = LAN8742_STATUS_OK;
|
||||
|
||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
|
||||
{
|
||||
readval |= LAN8742_BCR_LOOPBACK;
|
||||
|
||||
/* Apply configuration */
|
||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
|
||||
{
|
||||
status = LAN8742_STATUS_WRITE_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = LAN8742_STATUS_READ_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable loopback mode.
|
||||
* @param pObj: Pointer to device object.
|
||||
* @retval LAN8742_STATUS_OK if OK
|
||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||
*/
|
||||
int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj)
|
||||
{
|
||||
uint32_t readval = 0;
|
||||
int32_t status = LAN8742_STATUS_OK;
|
||||
|
||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
|
||||
{
|
||||
readval &= ~LAN8742_BCR_LOOPBACK;
|
||||
|
||||
/* Apply configuration */
|
||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
|
||||
{
|
||||
status = LAN8742_STATUS_WRITE_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = LAN8742_STATUS_READ_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable IT source.
|
||||
* @param pObj: Pointer to device object.
|
||||
* @param Interrupt: IT source to be enabled
|
||||
* should be a value or a combination of the following:
|
||||
* LAN8742_WOL_IT
|
||||
* LAN8742_ENERGYON_IT
|
||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||
* LAN8742_REMOTE_FAULT_IT
|
||||
* LAN8742_LINK_DOWN_IT
|
||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||
* @retval LAN8742_STATUS_OK if OK
|
||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||
*/
|
||||
int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||
{
|
||||
uint32_t readval = 0;
|
||||
int32_t status = LAN8742_STATUS_OK;
|
||||
|
||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0)
|
||||
{
|
||||
readval |= Interrupt;
|
||||
|
||||
/* Apply configuration */
|
||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0)
|
||||
{
|
||||
status = LAN8742_STATUS_WRITE_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = LAN8742_STATUS_READ_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable IT source.
|
||||
* @param pObj: Pointer to device object.
|
||||
* @param Interrupt: IT source to be disabled
|
||||
* should be a value or a combination of the following:
|
||||
* LAN8742_WOL_IT
|
||||
* LAN8742_ENERGYON_IT
|
||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||
* LAN8742_REMOTE_FAULT_IT
|
||||
* LAN8742_LINK_DOWN_IT
|
||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||
* @retval LAN8742_STATUS_OK if OK
|
||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||
*/
|
||||
int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||
{
|
||||
uint32_t readval = 0;
|
||||
int32_t status = LAN8742_STATUS_OK;
|
||||
|
||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0)
|
||||
{
|
||||
readval &= ~Interrupt;
|
||||
|
||||
/* Apply configuration */
|
||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0)
|
||||
{
|
||||
status = LAN8742_STATUS_WRITE_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = LAN8742_STATUS_READ_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear IT flag.
|
||||
* @param pObj: Pointer to device object.
|
||||
* @param Interrupt: IT flag to be cleared
|
||||
* should be a value or a combination of the following:
|
||||
* LAN8742_WOL_IT
|
||||
* LAN8742_ENERGYON_IT
|
||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||
* LAN8742_REMOTE_FAULT_IT
|
||||
* LAN8742_LINK_DOWN_IT
|
||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||
* @retval LAN8742_STATUS_OK if OK
|
||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||
*/
|
||||
int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||
{
|
||||
uint32_t readval = 0;
|
||||
int32_t status = LAN8742_STATUS_OK;
|
||||
|
||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) < 0)
|
||||
{
|
||||
status = LAN8742_STATUS_READ_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get IT Flag status.
|
||||
* @param pObj: Pointer to device object.
|
||||
* @param Interrupt: IT Flag to be checked,
|
||||
* should be a value or a combination of the following:
|
||||
* LAN8742_WOL_IT
|
||||
* LAN8742_ENERGYON_IT
|
||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||
* LAN8742_REMOTE_FAULT_IT
|
||||
* LAN8742_LINK_DOWN_IT
|
||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||
* @retval 1 IT flag is SET
|
||||
* 0 IT flag is RESET
|
||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||
*/
|
||||
int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||
{
|
||||
uint32_t readval = 0;
|
||||
int32_t status = 0;
|
||||
|
||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) >= 0)
|
||||
{
|
||||
status = ((readval & Interrupt) == Interrupt);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = LAN8742_STATUS_READ_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,466 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file lan8742.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 08-March-2017
|
||||
* @brief This file contains all the functions prototypes for the
|
||||
* lan8742.c PHY driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __LAN8742_H
|
||||
#define __LAN8742_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Component
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742
|
||||
* @{
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LAN8742_Exported_Constants LAN8742 Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_Registers_Mapping LAN8742 Registers Mapping
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_BCR ((uint16_t)0x0000U)
|
||||
#define LAN8742_BSR ((uint16_t)0x0001U)
|
||||
#define LAN8742_PHYI1R ((uint16_t)0x0002U)
|
||||
#define LAN8742_PHYI2R ((uint16_t)0x0003U)
|
||||
#define LAN8742_ANAR ((uint16_t)0x0004U)
|
||||
#define LAN8742_ANLPAR ((uint16_t)0x0005U)
|
||||
#define LAN8742_ANER ((uint16_t)0x0006U)
|
||||
#define LAN8742_ANNPTR ((uint16_t)0x0007U)
|
||||
#define LAN8742_ANNPRR ((uint16_t)0x0008U)
|
||||
#define LAN8742_MMDACR ((uint16_t)0x000DU)
|
||||
#define LAN8742_MMDAADR ((uint16_t)0x000EU)
|
||||
#define LAN8742_ENCTR ((uint16_t)0x0010U)
|
||||
#define LAN8742_MCSR ((uint16_t)0x0011U)
|
||||
#define LAN8742_SMR ((uint16_t)0x0012U)
|
||||
#define LAN8742_TPDCR ((uint16_t)0x0018U)
|
||||
#define LAN8742_TCSR ((uint16_t)0x0019U)
|
||||
#define LAN8742_SECR ((uint16_t)0x001AU)
|
||||
#define LAN8742_SCSIR ((uint16_t)0x001BU)
|
||||
#define LAN8742_CLR ((uint16_t)0x001CU)
|
||||
#define LAN8742_ISFR ((uint16_t)0x001DU)
|
||||
#define LAN8742_IMR ((uint16_t)0x001EU)
|
||||
#define LAN8742_PHYSCSR ((uint16_t)0x001FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_BCR_Bit_Definition LAN8742 BCR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_BCR_SOFT_RESET ((uint16_t)0x8000U)
|
||||
#define LAN8742_BCR_LOOPBACK ((uint16_t)0x4000U)
|
||||
#define LAN8742_BCR_SPEED_SELECT ((uint16_t)0x2000U)
|
||||
#define LAN8742_BCR_AUTONEGO_EN ((uint16_t)0x1000U)
|
||||
#define LAN8742_BCR_POWER_DOWN ((uint16_t)0x0800U)
|
||||
#define LAN8742_BCR_ISOLATE ((uint16_t)0x0400U)
|
||||
#define LAN8742_BCR_RESTART_AUTONEGO ((uint16_t)0x0200U)
|
||||
#define LAN8742_BCR_DUPLEX_MODE ((uint16_t)0x0100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_BSR_Bit_Definition LAN8742 BSR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_BSR_100BASE_T4 ((uint16_t)0x8000U)
|
||||
#define LAN8742_BSR_100BASE_TX_FD ((uint16_t)0x4000U)
|
||||
#define LAN8742_BSR_100BASE_TX_HD ((uint16_t)0x2000U)
|
||||
#define LAN8742_BSR_10BASE_T_FD ((uint16_t)0x1000U)
|
||||
#define LAN8742_BSR_10BASE_T_HD ((uint16_t)0x0800U)
|
||||
#define LAN8742_BSR_100BASE_T2_FD ((uint16_t)0x0400U)
|
||||
#define LAN8742_BSR_100BASE_T2_HD ((uint16_t)0x0200U)
|
||||
#define LAN8742_BSR_EXTENDED_STATUS ((uint16_t)0x0100U)
|
||||
#define LAN8742_BSR_AUTONEGO_CPLT ((uint16_t)0x0020U)
|
||||
#define LAN8742_BSR_REMOTE_FAULT ((uint16_t)0x0010U)
|
||||
#define LAN8742_BSR_AUTONEGO_ABILITY ((uint16_t)0x0008U)
|
||||
#define LAN8742_BSR_LINK_STATUS ((uint16_t)0x0004U)
|
||||
#define LAN8742_BSR_JABBER_DETECT ((uint16_t)0x0002U)
|
||||
#define LAN8742_BSR_EXTENDED_CAP ((uint16_t)0x0001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_PHYI1R_Bit_Definition LAN8742 PHYI1R Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_PHYI1R_OUI_3_18 ((uint16_t)0xFFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_PHYI2R_Bit_Definition LAN8742 PHYI2R Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_PHYI2R_OUI_19_24 ((uint16_t)0xFC00U)
|
||||
#define LAN8742_PHYI2R_MODEL_NBR ((uint16_t)0x03F0U)
|
||||
#define LAN8742_PHYI2R_REVISION_NBR ((uint16_t)0x000FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_ANAR_Bit_Definition LAN8742 ANAR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_ANAR_NEXT_PAGE ((uint16_t)0x8000U)
|
||||
#define LAN8742_ANAR_REMOTE_FAULT ((uint16_t)0x2000U)
|
||||
#define LAN8742_ANAR_PAUSE_OPERATION ((uint16_t)0x0C00U)
|
||||
#define LAN8742_ANAR_PO_NOPAUSE ((uint16_t)0x0000U)
|
||||
#define LAN8742_ANAR_PO_SYMMETRIC_PAUSE ((uint16_t)0x0400U)
|
||||
#define LAN8742_ANAR_PO_ASYMMETRIC_PAUSE ((uint16_t)0x0800U)
|
||||
#define LAN8742_ANAR_PO_ADVERTISE_SUPPORT ((uint16_t)0x0C00U)
|
||||
#define LAN8742_ANAR_100BASE_TX_FD ((uint16_t)0x0100U)
|
||||
#define LAN8742_ANAR_100BASE_TX ((uint16_t)0x0080U)
|
||||
#define LAN8742_ANAR_10BASE_T_FD ((uint16_t)0x0040U)
|
||||
#define LAN8742_ANAR_10BASE_T ((uint16_t)0x0020U)
|
||||
#define LAN8742_ANAR_SELECTOR_FIELD ((uint16_t)0x000FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_ANLPAR_Bit_Definition LAN8742 ANLPAR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_ANLPAR_NEXT_PAGE ((uint16_t)0x8000U)
|
||||
#define LAN8742_ANLPAR_REMOTE_FAULT ((uint16_t)0x2000U)
|
||||
#define LAN8742_ANLPAR_PAUSE_OPERATION ((uint16_t)0x0C00U)
|
||||
#define LAN8742_ANLPAR_PO_NOPAUSE ((uint16_t)0x0000U)
|
||||
#define LAN8742_ANLPAR_PO_SYMMETRIC_PAUSE ((uint16_t)0x0400U)
|
||||
#define LAN8742_ANLPAR_PO_ASYMMETRIC_PAUSE ((uint16_t)0x0800U)
|
||||
#define LAN8742_ANLPAR_PO_ADVERTISE_SUPPORT ((uint16_t)0x0C00U)
|
||||
#define LAN8742_ANLPAR_100BASE_TX_FD ((uint16_t)0x0100U)
|
||||
#define LAN8742_ANLPAR_100BASE_TX ((uint16_t)0x0080U)
|
||||
#define LAN8742_ANLPAR_10BASE_T_FD ((uint16_t)0x0040U)
|
||||
#define LAN8742_ANLPAR_10BASE_T ((uint16_t)0x0020U)
|
||||
#define LAN8742_ANLPAR_SELECTOR_FIELD ((uint16_t)0x000FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_ANER_Bit_Definition LAN8742 ANER Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_ANER_RX_NP_LOCATION_ABLE ((uint16_t)0x0040U)
|
||||
#define LAN8742_ANER_RX_NP_STORAGE_LOCATION ((uint16_t)0x0020U)
|
||||
#define LAN8742_ANER_PARALLEL_DETECT_FAULT ((uint16_t)0x0010U)
|
||||
#define LAN8742_ANER_LP_NP_ABLE ((uint16_t)0x0008U)
|
||||
#define LAN8742_ANER_NP_ABLE ((uint16_t)0x0004U)
|
||||
#define LAN8742_ANER_PAGE_RECEIVED ((uint16_t)0x0002U)
|
||||
#define LAN8742_ANER_LP_AUTONEG_ABLE ((uint16_t)0x0001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_ANNPTR_Bit_Definition LAN8742 ANNPTR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_ANNPTR_NEXT_PAGE ((uint16_t)0x8000U)
|
||||
#define LAN8742_ANNPTR_MESSAGE_PAGE ((uint16_t)0x2000U)
|
||||
#define LAN8742_ANNPTR_ACK2 ((uint16_t)0x1000U)
|
||||
#define LAN8742_ANNPTR_TOGGLE ((uint16_t)0x0800U)
|
||||
#define LAN8742_ANNPTR_MESSAGGE_CODE ((uint16_t)0x07FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_ANNPRR_Bit_Definition LAN8742 ANNPRR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_ANNPTR_NEXT_PAGE ((uint16_t)0x8000U)
|
||||
#define LAN8742_ANNPRR_ACK ((uint16_t)0x4000U)
|
||||
#define LAN8742_ANNPRR_MESSAGE_PAGE ((uint16_t)0x2000U)
|
||||
#define LAN8742_ANNPRR_ACK2 ((uint16_t)0x1000U)
|
||||
#define LAN8742_ANNPRR_TOGGLE ((uint16_t)0x0800U)
|
||||
#define LAN8742_ANNPRR_MESSAGGE_CODE ((uint16_t)0x07FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_MMDACR_Bit_Definition LAN8742 MMDACR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_MMDACR_MMD_FUNCTION ((uint16_t)0xC000U)
|
||||
#define LAN8742_MMDACR_MMD_FUNCTION_ADDR ((uint16_t)0x0000U)
|
||||
#define LAN8742_MMDACR_MMD_FUNCTION_DATA ((uint16_t)0x4000U)
|
||||
#define LAN8742_MMDACR_MMD_DEV_ADDR ((uint16_t)0x001FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_ENCTR_Bit_Definition LAN8742 ENCTR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_ENCTR_TX_ENABLE ((uint16_t)0x8000U)
|
||||
#define LAN8742_ENCTR_TX_TIMER ((uint16_t)0x6000U)
|
||||
#define LAN8742_ENCTR_TX_TIMER_1S ((uint16_t)0x0000U)
|
||||
#define LAN8742_ENCTR_TX_TIMER_768MS ((uint16_t)0x2000U)
|
||||
#define LAN8742_ENCTR_TX_TIMER_512MS ((uint16_t)0x4000U)
|
||||
#define LAN8742_ENCTR_TX_TIMER_265MS ((uint16_t)0x6000U)
|
||||
#define LAN8742_ENCTR_RX_ENABLE ((uint16_t)0x1000U)
|
||||
#define LAN8742_ENCTR_RX_MAX_INTERVAL ((uint16_t)0x0C00U)
|
||||
#define LAN8742_ENCTR_RX_MAX_INTERVAL_64MS ((uint16_t)0x0000U)
|
||||
#define LAN8742_ENCTR_RX_MAX_INTERVAL_256MS ((uint16_t)0x0400U)
|
||||
#define LAN8742_ENCTR_RX_MAX_INTERVAL_512MS ((uint16_t)0x0800U)
|
||||
#define LAN8742_ENCTR_RX_MAX_INTERVAL_1S ((uint16_t)0x0C00U)
|
||||
#define LAN8742_ENCTR_EX_CROSS_OVER ((uint16_t)0x0002U)
|
||||
#define LAN8742_ENCTR_EX_MANUAL_CROSS_OVER ((uint16_t)0x0001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_MCSR_Bit_Definition LAN8742 MCSR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_MCSR_EDPWRDOWN ((uint16_t)0x2000U)
|
||||
#define LAN8742_MCSR_FARLOOPBACK ((uint16_t)0x0200U)
|
||||
#define LAN8742_MCSR_ALTINT ((uint16_t)0x0040U)
|
||||
#define LAN8742_MCSR_ENERGYON ((uint16_t)0x0002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_SMR_Bit_Definition LAN8742 SMR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_SMR_MODE ((uint16_t)0x00E0U)
|
||||
#define LAN8742_SMR_PHY_ADDR ((uint16_t)0x001FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_TPDCR_Bit_Definition LAN8742 TPDCR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_TPDCR_DELAY_IN ((uint16_t)0x8000U)
|
||||
#define LAN8742_TPDCR_LINE_BREAK_COUNTER ((uint16_t)0x7000U)
|
||||
#define LAN8742_TPDCR_PATTERN_HIGH ((uint16_t)0x0FC0U)
|
||||
#define LAN8742_TPDCR_PATTERN_LOW ((uint16_t)0x003FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_TCSR_Bit_Definition LAN8742 TCSR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_TCSR_TDR_ENABLE ((uint16_t)0x8000U)
|
||||
#define LAN8742_TCSR_TDR_AD_FILTER_ENABLE ((uint16_t)0x4000U)
|
||||
#define LAN8742_TCSR_TDR_CH_CABLE_TYPE ((uint16_t)0x0600U)
|
||||
#define LAN8742_TCSR_TDR_CH_CABLE_DEFAULT ((uint16_t)0x0000U)
|
||||
#define LAN8742_TCSR_TDR_CH_CABLE_SHORTED ((uint16_t)0x0200U)
|
||||
#define LAN8742_TCSR_TDR_CH_CABLE_OPEN ((uint16_t)0x0400U)
|
||||
#define LAN8742_TCSR_TDR_CH_CABLE_MATCH ((uint16_t)0x0600U)
|
||||
#define LAN8742_TCSR_TDR_CH_STATUS ((uint16_t)0x0100U)
|
||||
#define LAN8742_TCSR_TDR_CH_LENGTH ((uint16_t)0x00FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_SCSIR_Bit_Definition LAN8742 SCSIR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_SCSIR_AUTO_MDIX_ENABLE ((uint16_t)0x8000U)
|
||||
#define LAN8742_SCSIR_CHANNEL_SELECT ((uint16_t)0x2000U)
|
||||
#define LAN8742_SCSIR_SQE_DISABLE ((uint16_t)0x0800U)
|
||||
#define LAN8742_SCSIR_XPOLALITY ((uint16_t)0x0010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_CLR_Bit_Definition LAN8742 CLR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_CLR_CABLE_LENGTH ((uint16_t)0xF000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_IMR_ISFR_Bit_Definition LAN8742 IMR ISFR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_INT_8 ((uint16_t)0x0100U)
|
||||
#define LAN8742_INT_7 ((uint16_t)0x0080U)
|
||||
#define LAN8742_INT_6 ((uint16_t)0x0040U)
|
||||
#define LAN8742_INT_5 ((uint16_t)0x0020U)
|
||||
#define LAN8742_INT_4 ((uint16_t)0x0010U)
|
||||
#define LAN8742_INT_3 ((uint16_t)0x0008U)
|
||||
#define LAN8742_INT_2 ((uint16_t)0x0004U)
|
||||
#define LAN8742_INT_1 ((uint16_t)0x0002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_PHYSCSR_Bit_Definition LAN8742 PHYSCSR Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_PHYSCSR_AUTONEGO_DONE ((uint16_t)0x1000U)
|
||||
#define LAN8742_PHYSCSR_HCDSPEEDMASK ((uint16_t)0x001CU)
|
||||
#define LAN8742_PHYSCSR_10BT_HD ((uint16_t)0x0004U)
|
||||
#define LAN8742_PHYSCSR_10BT_FD ((uint16_t)0x0014U)
|
||||
#define LAN8742_PHYSCSR_100BTX_HD ((uint16_t)0x0008U)
|
||||
#define LAN8742_PHYSCSR_100BTX_FD ((uint16_t)0x0018U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_Status LAN8742 Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LAN8742_STATUS_READ_ERROR ((int32_t)-5)
|
||||
#define LAN8742_STATUS_WRITE_ERROR ((int32_t)-4)
|
||||
#define LAN8742_STATUS_ADDRESS_ERROR ((int32_t)-3)
|
||||
#define LAN8742_STATUS_RESET_TIMEOUT ((int32_t)-2)
|
||||
#define LAN8742_STATUS_ERROR ((int32_t)-1)
|
||||
#define LAN8742_STATUS_OK ((int32_t) 0)
|
||||
#define LAN8742_STATUS_LINK_DOWN ((int32_t) 1)
|
||||
#define LAN8742_STATUS_100MBITS_FULLDUPLEX ((int32_t) 2)
|
||||
#define LAN8742_STATUS_100MBITS_HALFDUPLEX ((int32_t) 3)
|
||||
#define LAN8742_STATUS_10MBITS_FULLDUPLEX ((int32_t) 4)
|
||||
#define LAN8742_STATUS_10MBITS_HALFDUPLEX ((int32_t) 5)
|
||||
#define LAN8742_STATUS_AUTONEGO_NOTDONE ((int32_t) 6)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LAN8742_IT_Flags LAN8742 IT Flags
|
||||
* @{
|
||||
*/
|
||||
#define LAN8742_WOL_IT LAN8742_INT_8
|
||||
#define LAN8742_ENERGYON_IT LAN8742_INT_7
|
||||
#define LAN8742_AUTONEGO_COMPLETE_IT LAN8742_INT_6
|
||||
#define LAN8742_REMOTE_FAULT_IT LAN8742_INT_5
|
||||
#define LAN8742_LINK_DOWN_IT LAN8742_INT_4
|
||||
#define LAN8742_AUTONEGO_LP_ACK_IT LAN8742_INT_3
|
||||
#define LAN8742_PARALLEL_DETECTION_FAULT_IT LAN8742_INT_2
|
||||
#define LAN8742_AUTONEGO_PAGE_RECEIVED_IT LAN8742_INT_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LAN8742_Exported_Types LAN8742 Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef int32_t (*lan8742_Init_Func) (void);
|
||||
typedef int32_t (*lan8742_DeInit_Func) (void);
|
||||
typedef int32_t (*lan8742_ReadReg_Func) (uint32_t, uint32_t, uint32_t *);
|
||||
typedef int32_t (*lan8742_WriteReg_Func) (uint32_t, uint32_t, uint32_t);
|
||||
typedef int32_t (*lan8742_GetTick_Func) (void);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
lan8742_Init_Func Init;
|
||||
lan8742_DeInit_Func DeInit;
|
||||
lan8742_WriteReg_Func WriteReg;
|
||||
lan8742_ReadReg_Func ReadReg;
|
||||
lan8742_GetTick_Func GetTick;
|
||||
} lan8742_IOCtx_t;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DevAddr;
|
||||
uint32_t Is_Initialized;
|
||||
lan8742_IOCtx_t IO;
|
||||
void *pData;
|
||||
}lan8742_Object_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup LAN8742_Exported_Functions LAN8742 Exported Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx);
|
||||
int32_t LAN8742_Init(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_DeInit(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_DisablePowerDownMode(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_EnablePowerDownMode(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_StartAutoNego(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_SetLinkState(lan8742_Object_t *pObj, uint32_t LinkState);
|
||||
int32_t LAN8742_EnableLoopbackMode(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj);
|
||||
int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||
int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||
int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||
int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __LAN8742_H */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2018, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
|
||||
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
#define MCO_Pin GPIO_PIN_0
|
||||
#define MCO_GPIO_Port GPIOH
|
||||
#define RMII_MDC_Pin GPIO_PIN_1
|
||||
#define RMII_MDC_GPIO_Port GPIOC
|
||||
#define RMII_REF_CLK_Pin GPIO_PIN_1
|
||||
#define RMII_REF_CLK_GPIO_Port GPIOA
|
||||
#define RMII_MDIO_Pin GPIO_PIN_2
|
||||
#define RMII_MDIO_GPIO_Port GPIOA
|
||||
#define RMII_CRS_DV_Pin GPIO_PIN_7
|
||||
#define RMII_CRS_DV_GPIO_Port GPIOA
|
||||
#define RMII_RXD0_Pin GPIO_PIN_4
|
||||
#define RMII_RXD0_GPIO_Port GPIOC
|
||||
#define RMII_RXD1_Pin GPIO_PIN_5
|
||||
#define RMII_RXD1_GPIO_Port GPIOC
|
||||
#define RMII_TXD1_Pin GPIO_PIN_13
|
||||
#define RMII_TXD1_GPIO_Port GPIOB
|
||||
#define TMS_Pin GPIO_PIN_13
|
||||
#define TMS_GPIO_Port GPIOA
|
||||
#define TCK_Pin GPIO_PIN_14
|
||||
#define TCK_GPIO_Port GPIOA
|
||||
#define RMII_TX_EN_Pin GPIO_PIN_11
|
||||
#define RMII_TX_EN_GPIO_Port GPIOG
|
||||
#define RMII_TXD0_Pin GPIO_PIN_13
|
||||
#define RMII_TXD0_GPIO_Port GPIOG
|
||||
|
||||
/**
|
||||
* Override HAL Eth Init function
|
||||
*/
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
if(heth->Instance == ETH)
|
||||
{
|
||||
/* Disable DCache for STM32H7 family */
|
||||
SCB_DisableDCache();
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
|
||||
/* Enable Peripheral clock */
|
||||
__HAL_RCC_ETH1MAC_CLK_ENABLE();
|
||||
__HAL_RCC_ETH1TX_CLK_ENABLE();
|
||||
__HAL_RCC_ETH1RX_CLK_ENABLE();
|
||||
|
||||
/**ETH GPIO Configuration
|
||||
PC1 ------> ETH_MDC
|
||||
PA1 ------> ETH_REF_CLK
|
||||
PA2 ------> ETH_MDIO
|
||||
PA7 ------> ETH_CRS_DV
|
||||
PC4 ------> ETH_RXD0
|
||||
PC5 ------> ETH_RXD1
|
||||
PB13 ------> ETH_TXD1
|
||||
PG11 ------> ETH_TX_EN
|
||||
PG13 ------> ETH_TXD0
|
||||
*/
|
||||
GPIO_InitStruct.Pin = RMII_MDC_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = RMII_RXD0_Pin|RMII_RXD1_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = RMII_TXD1_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Override HAL Eth DeInit function
|
||||
*/
|
||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
if(heth->Instance == ETH)
|
||||
{
|
||||
/* Disable Peripheral clock */
|
||||
__HAL_RCC_ETH1MAC_CLK_DISABLE();
|
||||
__HAL_RCC_ETH1TX_CLK_DISABLE();
|
||||
__HAL_RCC_ETH1RX_CLK_DISABLE();
|
||||
|
||||
/**ETH GPIO Configuration
|
||||
PC1 ------> ETH_MDC
|
||||
PA1 ------> ETH_REF_CLK
|
||||
PA2 ------> ETH_MDIO
|
||||
PA7 ------> ETH_CRS_DV
|
||||
PC4 ------> ETH_RXD0
|
||||
PC5 ------> ETH_RXD1
|
||||
PB13 ------> ETH_TXD1
|
||||
PG11 ------> ETH_TX_EN
|
||||
PG13 ------> ETH_TXD0
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
|
||||
|
||||
HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */
|
||||
|
|
@ -27,6 +27,12 @@
|
|||
#include "stm32xx_emac_config.h"
|
||||
#include "stm32xx_emac.h"
|
||||
|
||||
#if defined(ETH_IP_VERSION_V2)
|
||||
#include "lan8742/lan8742.h"
|
||||
#include "lwip/memp.h"
|
||||
#include "lwip/api.h"
|
||||
#endif
|
||||
|
||||
/* \brief Flags for worker thread */
|
||||
#define FLAG_RX 1
|
||||
|
||||
|
|
@ -40,6 +46,8 @@
|
|||
#define STM_ETH_MTU_SIZE 1500
|
||||
#define STM_ETH_IF_NAME "st"
|
||||
|
||||
#ifndef ETH_IP_VERSION_V2
|
||||
|
||||
#if defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
|
|
@ -60,6 +68,52 @@ __ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethe
|
|||
#endif
|
||||
__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
|
||||
|
||||
#else // ETH_IP_VERSION_V2
|
||||
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
|
||||
#pragma location=0x30040000
|
||||
ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
|
||||
#pragma location=0x30040100
|
||||
ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
|
||||
#pragma location=0x30040400
|
||||
uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */
|
||||
|
||||
#elif defined ( __CC_ARM ) /* MDK ARM Compiler */
|
||||
|
||||
__attribute__((section(".RxDecripSection"))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
|
||||
__attribute__((section(".TxDecripSection"))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
|
||||
__attribute__((section(".RxArraySection"))) uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_RX_BUFFER_SIZE]; /* Ethernet Receive Buffer */
|
||||
|
||||
#elif defined ( __GNUC__ ) /* GNU Compiler */
|
||||
|
||||
ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
|
||||
ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */
|
||||
uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE] __attribute__((section(".RxArraySection"))); /* Ethernet Receive Buffers */
|
||||
|
||||
#endif
|
||||
|
||||
static lan8742_Object_t LAN8742;
|
||||
|
||||
static int32_t ETH_PHY_IO_Init(void);
|
||||
static int32_t ETH_PHY_IO_DeInit(void);
|
||||
static int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal);
|
||||
static int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal);
|
||||
static int32_t ETH_PHY_IO_GetTick(void);
|
||||
|
||||
static lan8742_IOCtx_t LAN8742_IOCtx =
|
||||
{
|
||||
ETH_PHY_IO_Init,
|
||||
ETH_PHY_IO_DeInit,
|
||||
ETH_PHY_IO_WriteReg,
|
||||
ETH_PHY_IO_ReadReg,
|
||||
ETH_PHY_IO_GetTick
|
||||
};
|
||||
|
||||
static ETH_TxPacketConfig TxConfig;
|
||||
|
||||
#endif // ETH_IP_VERSION_V2
|
||||
|
||||
__weak uint8_t mbed_otp_mac_address(char *mac);
|
||||
void mbed_default_mac_address(char *mac);
|
||||
|
||||
|
|
@ -75,6 +129,100 @@ void ETH_IRQHandler(void);
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef ETH_IP_VERSION_V2
|
||||
bool _phy_init()
|
||||
{
|
||||
/* Set PHY IO functions */
|
||||
LAN8742_RegisterBusIO(&LAN8742, &LAN8742_IOCtx);
|
||||
|
||||
/* Initialize the LAN8742 ETH PHY */
|
||||
return LAN8742_Init(&LAN8742) == LAN8742_STATUS_OK;
|
||||
}
|
||||
|
||||
int32_t _phy_get_state()
|
||||
{
|
||||
return LAN8742_GetLinkState(&LAN8742);
|
||||
}
|
||||
|
||||
bool _phy_get_duplex_and_speed(int32_t phy_state, uint32_t *duplex, uint32_t *speed)
|
||||
{
|
||||
switch (phy_state)
|
||||
{
|
||||
case LAN8742_STATUS_100MBITS_FULLDUPLEX:
|
||||
*duplex = ETH_FULLDUPLEX_MODE;
|
||||
*speed = ETH_SPEED_100M;
|
||||
break;
|
||||
case LAN8742_STATUS_100MBITS_HALFDUPLEX:
|
||||
*duplex = ETH_HALFDUPLEX_MODE;
|
||||
*speed = ETH_SPEED_100M;
|
||||
break;
|
||||
case LAN8742_STATUS_10MBITS_FULLDUPLEX:
|
||||
*duplex = ETH_FULLDUPLEX_MODE;
|
||||
*speed = ETH_SPEED_10M;
|
||||
break;
|
||||
case LAN8742_STATUS_10MBITS_HALFDUPLEX:
|
||||
*duplex = ETH_HALFDUPLEX_MODE;
|
||||
*speed = ETH_SPEED_10M;
|
||||
break;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool _phy_is_up(int32_t phy_state)
|
||||
{
|
||||
return phy_state > LAN8742_STATUS_LINK_DOWN;
|
||||
}
|
||||
|
||||
static void MPU_Config(void)
|
||||
{
|
||||
MPU_Region_InitTypeDef MPU_InitStruct;
|
||||
|
||||
/* Disable the MPU */
|
||||
HAL_MPU_Disable();
|
||||
|
||||
/* Configure the MPU attributes as Device not cacheable
|
||||
for ETH DMA descriptors */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.BaseAddress = 0x30040000;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_1KB;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
||||
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
||||
MPU_InitStruct.SubRegionDisable = 0x00;
|
||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
||||
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
/* Configure the MPU attributes as Cacheable write through
|
||||
for LwIP RAM heap which contains the Tx buffers */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.BaseAddress = 0x30044000;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
|
||||
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
||||
MPU_InitStruct.SubRegionDisable = 0x00;
|
||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
||||
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
/* Enable the MPU */
|
||||
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* Ethernet Rx Transfer completed callback
|
||||
*
|
||||
|
|
@ -103,6 +251,9 @@ void ETH_IRQHandler(void)
|
|||
|
||||
STM32_EMAC::STM32_EMAC()
|
||||
: thread(0)
|
||||
#ifdef ETH_IP_VERSION_V2
|
||||
, phy_status(0)
|
||||
#endif
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -122,6 +273,7 @@ static osThreadId_t create_new_thread(const char *threadName, void (*thread)(voi
|
|||
* In this function, the hardware should be initialized.
|
||||
*/
|
||||
bool STM32_EMAC::low_level_init_successful()
|
||||
#ifndef ETH_IP_VERSION_V2
|
||||
{
|
||||
/* Init ETH */
|
||||
uint8_t MACAddr[6];
|
||||
|
|
@ -160,6 +312,51 @@ bool STM32_EMAC::low_level_init_successful()
|
|||
|
||||
return true;
|
||||
}
|
||||
#else // ETH_IP_VERSION_V2
|
||||
{
|
||||
uint32_t idx, duplex, speed = 0;
|
||||
int32_t PHYLinkState;
|
||||
ETH_MACConfigTypeDef MACConf;
|
||||
|
||||
MPU_Config();
|
||||
|
||||
/* Init ETH */
|
||||
uint8_t MACAddr[6];
|
||||
EthHandle.Instance = ETH;
|
||||
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
|
||||
MACAddr[0] = MBED_MAC_ADDR_0;
|
||||
MACAddr[1] = MBED_MAC_ADDR_1;
|
||||
MACAddr[2] = MBED_MAC_ADDR_2;
|
||||
MACAddr[3] = MBED_MAC_ADDR_3;
|
||||
MACAddr[4] = MBED_MAC_ADDR_4;
|
||||
MACAddr[5] = MBED_MAC_ADDR_5;
|
||||
#else
|
||||
mbed_mac_address((char *)MACAddr);
|
||||
#endif
|
||||
EthHandle.Init.MACAddr = &MACAddr[0];
|
||||
EthHandle.Init.MediaInterface = HAL_ETH_RMII_MODE;
|
||||
EthHandle.Init.RxDesc = DMARxDscrTab;
|
||||
EthHandle.Init.TxDesc = DMATxDscrTab;
|
||||
EthHandle.Init.RxBuffLen = 1524;
|
||||
|
||||
if (HAL_ETH_Init(&EthHandle) != HAL_OK)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
memset(&TxConfig, 0, sizeof(ETH_TxPacketConfig));
|
||||
TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
|
||||
TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
|
||||
TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
|
||||
|
||||
for(idx = 0; idx < ETH_RX_DESC_CNT; idx++)
|
||||
{
|
||||
HAL_ETH_DescAssignMemory(&EthHandle, idx, Rx_Buff[idx], NULL);
|
||||
}
|
||||
|
||||
return _phy_init();
|
||||
}
|
||||
#endif // ETH_IP_VERSION_V2
|
||||
|
||||
/**
|
||||
* This function should do the actual transmission of the packet. The packet is
|
||||
|
|
@ -175,6 +372,7 @@ bool STM32_EMAC::low_level_init_successful()
|
|||
* dropped because of memory failure (except for the TCP timers).
|
||||
*/
|
||||
bool STM32_EMAC::link_out(emac_mem_buf_t *buf)
|
||||
#ifndef ETH_IP_VERSION_V2
|
||||
{
|
||||
bool success;
|
||||
emac_mem_buf_t *q;
|
||||
|
|
@ -252,6 +450,68 @@ error:
|
|||
|
||||
return success;
|
||||
}
|
||||
#else // ETH_IP_VERSION_V2
|
||||
{
|
||||
bool success = false;
|
||||
uint32_t i = 0;
|
||||
uint32_t frameLength = 0;
|
||||
struct pbuf *q;
|
||||
ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT];
|
||||
HAL_StatusTypeDef status;
|
||||
struct pbuf *p = NULL;
|
||||
p = (struct pbuf *)buf;
|
||||
/* Get exclusive access */
|
||||
TXLockMutex.lock();
|
||||
|
||||
memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef));
|
||||
|
||||
/* copy frame from pbufs to driver buffers */
|
||||
for (q = p; q != NULL; q = q->next) {
|
||||
if (i >= ETH_TX_DESC_CNT) {
|
||||
printf("Error : ETH_TX_DESC_CNT not sufficient\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
Txbuffer[i].buffer = (uint8_t *)q->payload;
|
||||
Txbuffer[i].len = q->len;
|
||||
frameLength += q->len;
|
||||
|
||||
if (i > 0)
|
||||
{
|
||||
Txbuffer[i - 1].next = &Txbuffer[i];
|
||||
}
|
||||
|
||||
if (q->next == NULL)
|
||||
{
|
||||
Txbuffer[i].next = NULL;
|
||||
}
|
||||
|
||||
i++;
|
||||
}
|
||||
|
||||
TxConfig.Length = frameLength;
|
||||
TxConfig.TxBuffer = Txbuffer;
|
||||
|
||||
status = HAL_ETH_Transmit(&EthHandle, &TxConfig, 50);
|
||||
if(status == HAL_OK){
|
||||
success = 1;
|
||||
} else {
|
||||
printf("Error returned by HAL_ETH_Transmit (%d)\n", status);
|
||||
success = 0;
|
||||
}
|
||||
|
||||
error:
|
||||
|
||||
if (p->ref > 1) {
|
||||
pbuf_free(p);
|
||||
}
|
||||
|
||||
/* Restore access */
|
||||
TXLockMutex.unlock();
|
||||
|
||||
return success;
|
||||
}
|
||||
#endif // ETH_IP_VERSION_V2
|
||||
|
||||
/**
|
||||
* Should allocate a contiguous memory buffer and transfer the bytes of the incoming
|
||||
|
|
@ -263,6 +523,7 @@ error:
|
|||
* zero when frame is received
|
||||
*/
|
||||
int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
|
||||
#ifndef ETH_IP_VERSION_V2
|
||||
{
|
||||
uint16_t len = 0;
|
||||
uint8_t *buffer;
|
||||
|
|
@ -336,7 +597,39 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
#else // ETH_IP_VERSION_V2
|
||||
{
|
||||
ETH_BufferTypeDef RxBuff;
|
||||
uint32_t frameLength = 0;
|
||||
|
||||
if (HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK)
|
||||
{
|
||||
if (HAL_ETH_GetRxDataLength(&EthHandle, &frameLength) != HAL_OK)
|
||||
{
|
||||
printf("Error: returned by HAL_ETH_GetRxDataLength\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Build Rx descriptor to be ready for next data reception */
|
||||
HAL_ETH_BuildRxDescriptors(&EthHandle);
|
||||
|
||||
/* Invalidate data cache for ETH Rx Buffers */
|
||||
SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, frameLength);
|
||||
|
||||
*buf = pbuf_alloc(PBUF_RAW, frameLength, PBUF_POOL);
|
||||
if (*buf)
|
||||
{
|
||||
pbuf_take((struct pbuf *)*buf, RxBuff.buffer, frameLength);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif // ETH_IP_VERSION_V2
|
||||
|
||||
/** \brief Attempt to read a packet from the EMAC interface.
|
||||
*
|
||||
|
|
@ -346,12 +639,15 @@ void STM32_EMAC::packet_rx()
|
|||
/* move received packet into a new buf */
|
||||
while (1) {
|
||||
emac_mem_buf_t *p = NULL;
|
||||
RXLockMutex.lock();
|
||||
if (low_level_input(&p) < 0) {
|
||||
RXLockMutex.unlock();
|
||||
break;
|
||||
}
|
||||
if (p) {
|
||||
emac_link_input_cb(p);
|
||||
}
|
||||
RXLockMutex.unlock();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -378,6 +674,7 @@ void STM32_EMAC::thread_function(void *pvParameters)
|
|||
* This task checks phy link status and updates net status
|
||||
*/
|
||||
void STM32_EMAC::phy_task()
|
||||
#ifndef ETH_IP_VERSION_V2
|
||||
{
|
||||
uint32_t status;
|
||||
|
||||
|
|
@ -393,6 +690,51 @@ void STM32_EMAC::phy_task()
|
|||
}
|
||||
|
||||
}
|
||||
#else // ETH_IP_VERSION_V2
|
||||
{
|
||||
const int32_t status = _phy_get_state();
|
||||
const int32_t old_status = (int32_t)phy_status;
|
||||
const bool is_up = _phy_is_up(status);
|
||||
const bool was_up = _phy_is_up(old_status);
|
||||
|
||||
if (is_up && !was_up)
|
||||
{
|
||||
uint32_t duplex, speed;
|
||||
ETH_MACConfigTypeDef MACConf;
|
||||
|
||||
if (!_phy_get_duplex_and_speed(status, &speed, &duplex))
|
||||
{
|
||||
// Default
|
||||
duplex = ETH_FULLDUPLEX_MODE;
|
||||
speed = ETH_SPEED_10M;
|
||||
}
|
||||
|
||||
/* Get MAC Config MAC */
|
||||
HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
|
||||
MACConf.DuplexMode = duplex;
|
||||
MACConf.Speed = speed;
|
||||
HAL_ETH_SetMACConfig(&EthHandle, &MACConf);
|
||||
HAL_ETH_Start_IT(&EthHandle);
|
||||
}
|
||||
else if (was_up && !is_up)
|
||||
{
|
||||
// Stop ETH
|
||||
disable_interrupts();
|
||||
HAL_ETH_Stop(&EthHandle);
|
||||
enable_interrupts();
|
||||
}
|
||||
|
||||
if (emac_link_state_cb) {
|
||||
if (is_up && !was_up) {
|
||||
emac_link_state_cb(true);
|
||||
} else if (!is_up && was_up) {
|
||||
emac_link_state_cb(false);
|
||||
}
|
||||
}
|
||||
|
||||
phy_status = (uint32_t)status;
|
||||
}
|
||||
#endif // ETH_IP_VERSION_V2
|
||||
|
||||
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\
|
||||
|| defined (STM32F779xx)
|
||||
|
|
@ -475,6 +817,8 @@ void mbed_default_mac_address(char *mac)
|
|||
uint32_t word0 = *(uint32_t *)0x1FFF7A10;
|
||||
#elif defined (TARGET_STM32F7)
|
||||
uint32_t word0 = *(uint32_t *)0x1FF0F420;
|
||||
#elif defined (TARGET_STM32H7)
|
||||
uint32_t word0 = *(uint32_t *)0x1FF1E800;
|
||||
#else
|
||||
#error MAC address can not be derived from target unique Id
|
||||
#endif
|
||||
|
|
@ -594,3 +938,100 @@ MBED_WEAK EMAC &EMAC::get_default_instance()
|
|||
{
|
||||
return STM32_EMAC::get_instance();
|
||||
}
|
||||
|
||||
#if defined(ETH_IP_VERSION_V2)
|
||||
/*******************************************************************************
|
||||
PHI IO Functions
|
||||
*******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Initializes the MDIO interface GPIO and clocks.
|
||||
* @param None
|
||||
* @retval 0 if OK, -1 if ERROR
|
||||
*/
|
||||
static int32_t ETH_PHY_IO_Init(void)
|
||||
{
|
||||
/* We assume that MDIO GPIO configuration is already done
|
||||
in the ETH_MspInit() else it should be done here
|
||||
*/
|
||||
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
||||
|
||||
/* Configure the MDIO Clock */
|
||||
HAL_ETH_SetMDIOClockRange(&emac.EthHandle);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-Initializes the MDIO interface .
|
||||
* @param None
|
||||
* @retval 0 if OK, -1 if ERROR
|
||||
*/
|
||||
static int32_t ETH_PHY_IO_DeInit (void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read a PHY register through the MDIO interface.
|
||||
* @param DevAddr: PHY port address
|
||||
* @param RegAddr: PHY register address
|
||||
* @param pRegVal: pointer to hold the register value
|
||||
* @retval 0 if OK -1 if Error
|
||||
*/
|
||||
static int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal)
|
||||
{
|
||||
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
||||
if(HAL_ETH_ReadPHYRegister(&emac.EthHandle, DevAddr, RegAddr, pRegVal) != HAL_OK)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write a value to a PHY register through the MDIO interface.
|
||||
* @param DevAddr: PHY port address
|
||||
* @param RegAddr: PHY register address
|
||||
* @param RegVal: Value to be written
|
||||
* @retval 0 if OK -1 if Error
|
||||
*/
|
||||
static int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal)
|
||||
{
|
||||
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
||||
if(HAL_ETH_WritePHYRegister(&emac.EthHandle, DevAddr, RegAddr, RegVal) != HAL_OK)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the time in millisecons used for internal PHY driver process.
|
||||
* @retval Time value
|
||||
*/
|
||||
static int32_t ETH_PHY_IO_GetTick(void)
|
||||
{
|
||||
return HAL_GetTick();
|
||||
}
|
||||
|
||||
/**
|
||||
* Ethernet DMA transfer error callbacks
|
||||
*/
|
||||
void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_ETHERNET, EIO), \
|
||||
"Error from ethernet HAL (HAL_ETH_DMAErrorCallback)\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* Ethernet MAC transfer error callbacks
|
||||
*/
|
||||
void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_ETHERNET, EIO), \
|
||||
"Error from ethernet HAL (HAL_ETH_MACErrorCallback)\n");
|
||||
}
|
||||
#endif // ETH_IP_VERSION_V2
|
||||
|
|
|
|||
|
|
@ -167,6 +167,7 @@ private:
|
|||
osThreadId_t rmii_watchdog_thread; /**< Watchdog processing thread */
|
||||
#endif
|
||||
rtos::Mutex TXLockMutex;/**< TX critical section mutex */
|
||||
rtos::Mutex RXLockMutex;/**< RX critical section mutex */
|
||||
emac_link_input_cb_t emac_link_input_cb; /**< Callback for incoming data */
|
||||
emac_link_state_change_cb_t emac_link_state_cb; /**< Link state change callback */
|
||||
EMACMemoryManager *memory_manager; /**< Memory manager */
|
||||
|
|
|
|||
|
|
@ -208,7 +208,7 @@
|
|||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
|
||||
/* ########################### Ethernet Configuration ######################### */
|
||||
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
|
||||
#define ETH_TX_DESC_CNT 10 /* number of Ethernet Tx DMA descriptors */
|
||||
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
|
||||
|
||||
#define ETH_MAC_ADDR0 ((uint8_t)0x02)
|
||||
|
|
|
|||
|
|
@ -3195,7 +3195,8 @@
|
|||
"core": "Cortex-M7FD",
|
||||
"extra_labels_add": [
|
||||
"STM32H7",
|
||||
"STM32H743xI"
|
||||
"STM32H743xI",
|
||||
"STM_EMAC"
|
||||
],
|
||||
"config": {
|
||||
"d11_configuration": {
|
||||
|
|
@ -3221,9 +3222,13 @@
|
|||
"macros_add": [
|
||||
"STM32H743xx",
|
||||
"EXTRA_IDLE_STACK_REQUIRED",
|
||||
"MBED_TICKLESS"
|
||||
"MBED_TICKLESS",
|
||||
"ETH_IP_VERSION_V2"
|
||||
],
|
||||
"overrides": { "lpticker_delay_ticks": 0 },
|
||||
"overrides": {
|
||||
"lpticker_delay_ticks": 0,
|
||||
"network-default-interface-type": "ETHERNET"
|
||||
},
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"detect_code": ["0813"],
|
||||
"device_has_add": [
|
||||
|
|
@ -3232,7 +3237,8 @@
|
|||
"CRC",
|
||||
"TRNG",
|
||||
"FLASH",
|
||||
"MPU"
|
||||
"MPU",
|
||||
"EMAC"
|
||||
],
|
||||
"release_versions": ["2", "5"],
|
||||
"device_name": "STM32H743ZI",
|
||||
|
|
@ -4029,7 +4035,7 @@
|
|||
"MBED_TICKLESS",
|
||||
"EXTRA_IDLE_STACK_REQUIRED"
|
||||
],
|
||||
"overrides": {
|
||||
"overrides": {
|
||||
"lse_available": 0,
|
||||
"lpticker_delay_ticks": 0
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue