ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

STM32U5: STM32Cube_FW_U5_V1.2.0

pull/15420/head
Jerome Coutant 2023-05-10 12:18:24 +02:00
parent cc39261968
commit 9f0ede486d
248 changed files with 203829 additions and 13624 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/LICENSE.txt Normal file
View File

@ -0,0 +1,6 @@
This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0

80
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/partition_stm32u5xx.h Normal file
View File

@ -0,0 +1,80 @@
/**
******************************************************************************
* @file partition_stm32u5xx.h
* @author MCD Application Team
* @brief CMSIS STM32U5xx Device Header File for Initial Setup for
* Secure / Non-Secure Zones based on CMSIS CORE V5.4.0
*
* The file is included in system_stm32u5xx_s.c in secure application.
* It includes the configuration section that allows to select the
* STM32U5xx device partitioning file for system core secure attributes
* and interrupt secure and non-secure assignment.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32u5xx
* @{
*/
#ifndef PARTITION_STM32U5XX_H
#define PARTITION_STM32U5XX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Secure_configuration_section
* @{
*/
#if defined(STM32U575xx)
#include "partition_stm32u575xx.h"
#elif defined(STM32U585xx)
#include "partition_stm32u585xx.h"
#elif defined(STM32U595xx)
#include "partition_stm32u595xx.h"
#elif defined(STM32U5A5xx)
#include "partition_stm32u5a5xx.h"
#elif defined(STM32U599xx)
#include "partition_stm32u599xx.h"
#elif defined(STM32U5A9xx)
#include "partition_stm32u5a9xx.h"
#elif defined(STM32U535xx)
#include "partition_stm32u535xx.h"
#elif defined(STM32U545xx)
#include "partition_stm32u545xx.h"
#else
#error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* PARTITION_STM32U5XX_H */
/**
* @}
*/
/**
* @}
*/

21195
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u535xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

22026
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u545xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

2835
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u575xx.h
View File

File diff suppressed because it is too large Load Diff

2846
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u585xx.h
View File

File diff suppressed because it is too large Load Diff

25581
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u595xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

29428
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u599xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

26462
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5a5xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

30309
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5a9xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

37
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5xx.h
View File

@ -56,9 +56,18 @@
application
*/
#if !defined (STM32U575xx) && !defined (STM32U585xx)
/* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */
/* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */
#if !defined (STM32U575xx) && !defined (STM32U585xx) \
&& !defined (STM32U595xx) && !defined (STM32U599xx) \
&& !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \
&& !defined (STM32U535xx) && !defined (STM32U545xx) \
/* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */
/* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */
/* #define STM32U595xx */ /*!< STM32U595ZJT6Q Device */
/* #define STM32U599xx */ /*!< STM32U599NJH6Q STM32U599BJY6Q STM32U599NIH6Q Devices */
/* #define STM32U5A5xx */ /*!< STM32U5A5ZJT6Q Device */
/* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6Q Devices */
/* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Device */
/* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Device */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -74,12 +83,12 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number 1.0.0
* @brief CMSIS Device version number 1.2.0
*/
#define __STM32U5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32U5_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32U5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32U5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32U5_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32U5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\
|(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\
|(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\
@ -97,6 +106,18 @@
#include "stm32u575xx.h"
#elif defined(STM32U585xx)
#include "stm32u585xx.h"
#elif defined(STM32U595xx)
#include "stm32u595xx.h"
#elif defined(STM32U599xx)
#include "stm32u599xx.h"
#elif defined(STM32U5A5xx)
#include "stm32u5a5xx.h"
#elif defined(STM32U5A9xx)
#include "stm32u5a9xx.h"
#elif defined(STM32U535xx)
#include "stm32u535xx.h"
#elif defined(STM32U545xx)
#include "stm32u545xx.h"
#else
#error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
#endif

6
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMakeLists.txt
View File

@ -22,12 +22,15 @@ target_sources(mbed-stm32u5cube-fw
STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_flash.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_flash_ex.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.c
@ -38,6 +41,8 @@ target_sources(mbed-stm32u5cube-fw
STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc_ex.c
@ -79,6 +84,7 @@ target_sources(mbed-stm32u5cube-fw
STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_wwdg.c
STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.c
STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.c
STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.c
STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.c

593
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/Legacy/stm32_hal_legacy.h
View File

@ -37,14 +37,16 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5)
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
#endif /* STM32U5 || STM32H7 || STM32MP1 */
/**
* @}
*/
@ -104,6 +106,16 @@ extern "C" {
#if defined(STM32H7)
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
#if defined(STM32U5)
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
#if defined(STM32H5)
#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
#endif /* STM32H5 */
/**
* @}
*/
@ -131,7 +143,8 @@ extern "C" {
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@ -205,6 +218,11 @@ extern "C" {
#endif
#endif
#if defined(STM32U5)
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
#endif
/**
* @}
*/
@ -213,6 +231,11 @@ extern "C" {
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
#if defined(STM32U5)
#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
#endif /* STM32U5 */
/**
* @}
*/
@ -220,10 +243,12 @@ extern "C" {
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
#if defined(STM32H5) || defined(STM32C0)
#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
inter STM32 series compatibility */
#endif
/**
* @}
@ -254,12 +279,25 @@ extern "C" {
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#if defined(STM32U5)
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
#if defined(STM32H5)
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@ -324,7 +362,8 @@ extern "C" {
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@ -401,6 +440,10 @@ extern "C" {
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
#if defined(STM32U5)
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
#endif /* STM32U5 */
/**
* @}
*/
@ -480,7 +523,7 @@ extern "C" {
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
#if defined(STM32G0)
#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@ -505,6 +548,9 @@ extern "C" {
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
/**
@ -549,6 +595,104 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
#if defined(STM32H5)
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
#define SYSCFG_ETH_MII SBS_ETH_MII
#define SYSCFG_ETH_RMII SBS_ETH_RMII
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SYSCFG_SAU SBS_SAU
#define SYSCFG_MPU_SEC SBS_MPU_SEC
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#else
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#endif /* __ARM_FEATURE_CMSE */
#define SYSCFG_CLK SBS_CLK
#define SYSCFG_CLASSB SBS_CLASSB
#define SYSCFG_FPU SBS_FPU
#define SYSCFG_ALL SBS_ALL
#define SYSCFG_SEC SBS_SEC
#define SYSCFG_NSEC SBS_NSEC
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
#define HAL_SYSCFG_Lock HAL_SBS_Lock
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
#endif /* __ARM_FEATURE_CMSE */
#endif /* STM32H5 */
/**
@ -618,14 +762,16 @@ extern "C" {
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@ -646,6 +792,42 @@ extern "C" {
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
#if defined(STM32U5) || defined(STM32H5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
#endif /* STM32U5 || STM32H5 */
#if defined(STM32U5)
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
* @{
*/
#if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */
#if defined(STM32H5)
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
#endif /* STM32H5 */
#if defined(STM32H5) || defined(STM32U5)
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@ -826,7 +1008,8 @@ extern "C" {
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -883,9 +1066,19 @@ extern "C" {
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
/**
* @}
*/
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
#define LPTIM_CHANNEL_ALL 0x00000000U
#endif /* STM32U5 */
/**
* @}
@ -954,7 +1147,7 @@ extern "C" {
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@ -1038,8 +1231,8 @@ extern "C" {
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@ -1050,15 +1243,42 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H5)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
#endif /* STM32H5 */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
#if defined(STM32H5) || defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
#endif /* STM32H5 || STM32WBA */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
#endif /* STM32F7 */
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#endif /* STM32H7 */
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
#endif /* STM32F7 || STM32H7 || STM32L0 */
/**
* @}
@ -1225,6 +1445,10 @@ extern "C" {
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
#if defined(STM32U5)
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
#endif
/**
* @}
*/
@ -1334,30 +1558,40 @@ extern "C" {
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
(or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@ -1528,7 +1762,8 @@ extern "C" {
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@ -1537,8 +1772,10 @@ extern "C" {
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@ -1572,16 +1809,21 @@ extern "C" {
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@ -1655,10 +1897,111 @@ extern "C" {
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
#if defined (STM32U5)
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
#endif
/**
* @}
*/
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32H5) || defined(STM32WBA)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
#endif /* STM32H5 || STM32WBA */
/**
* @}
*/
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@ -1684,7 +2027,8 @@ extern "C" {
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@ -1941,7 +2285,8 @@ extern "C" {
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@ -2113,8 +2458,10 @@ extern "C" {
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
/**
* @}
*/
@ -2273,7 +2620,9 @@ extern "C" {
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@ -2282,8 +2631,12 @@ extern "C" {
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
} while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
} while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@ -2319,8 +2672,8 @@ extern "C" {
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@ -2824,6 +3177,11 @@ extern "C" {
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@ -3288,7 +3646,8 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@ -3401,8 +3760,8 @@ extern "C" {
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@ -3413,7 +3772,112 @@ extern "C" {
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
#endif
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#endif /* STM32U5 */
#if defined(STM32H5)
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
#endif /* STM32H5 */
/**
* @}
*/
@ -3430,7 +3894,9 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3483,6 +3949,11 @@ extern "C" {
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
#if defined (STM32H5)
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
#endif /* STM32H5 */
/**
* @}
*/
@ -3494,12 +3965,14 @@ extern "C" {
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
#endif
#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
@ -3829,6 +4302,16 @@ extern "C" {
* @}
*/
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32F7)
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
#endif /* STM32F7 */
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/

219
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.c
View File

@ -52,10 +52,10 @@
* @{
*/
/**
* @brief STM32U5xx HAL Driver version number 1.0.0
* @brief STM32U5xx HAL Driver version number 1.2.0
*/
#define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32U5xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
#define __STM32U5xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\
@ -346,7 +346,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/**
* @brief Return tick frequency.
* @retval tick period in Hz
* @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
@ -439,6 +440,33 @@ uint32_t HAL_GetDEVID(void)
return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return (READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @}
*/
@ -620,6 +648,98 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
#if defined(SYSCFG_CFGR1_SRAMCACHED)
/**
* @brief Enable the Cacheability of internal SRAMx by DCACHE2
*
* @retval None
*/
void HAL_SYSCFG_EnableSRAMCached(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED);
}
/**
* @brief Disable the Cacheability of internal SRAMx by DCACHE2
*
* @retval None
*/
void HAL_SYSCFG_DisableSRAMCached(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED);
}
#endif /* SYSCFG_CFGR1_SRAMCACHED */
/**
* @brief Enable the Compensation Cell of GPIO supplied by VDD
* @rmtoll CCCSR EN1 HAL_SYSCFG_EnableVddCompensationCell
* @note The vdd compensation cell can be used only when the device supply
* voltage ranges from 1.71 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_EnableVddCompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
}
/**
* @brief Enable the Compensation Cell of GPIO supplied by VDDIO2
* @rmtoll CCCSR EN2 HAL_SYSCFG_EnableVddIO2CompensationCell
* @note The Vdd I/O compensation cell can be used only when the device supply
* voltage ranges from 1.08 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_EnableVddIO2CompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
}
#if defined(SYSCFG_CCCSR_EN3)
/**
* @brief Enable the Compensation Cell of HSPI IO supplied by VDD
* @rmtoll CCCSR EN3 HAL_SYSCFG_EnableVddHSPICompensationCell
* @retval None
*/
void HAL_SYSCFG_EnableVddHSPICompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
}
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @brief Disable the Compensation Cell of GPIO supplied by VDD
* @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell
* @note The Vdd compensation cell can be used only when the device supply
* voltage ranges from 1.71 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_DisableVddCompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
}
/**
* @brief Disable the Compensation Cell of GPIO supplied by VDDIO2
* @rmtoll CCCSR EN2 HAL_SYSCFG_DisableVddIO2CompensationCell
* @note The Vdd I/O compensation cell can be used only when the device supply
* voltage ranges from 1.08 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_DisableVddIO2CompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
}
#if defined(SYSCFG_CCCSR_EN3)
/**
* @brief Disable the Compensation Cell of HSPI IO supplied by VDD
* @rmtoll CCCSR EN3 HAL_SYSCFG_DisableVddHSPICompensationCell
* @retval None
*/
void HAL_SYSCFG_DisableVddHSPICompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
}
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @}
*/
@ -779,6 +899,99 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri
#endif /* __ARM_FEATURE_CMSE */
#ifdef SYSCFG_OTGHSPHYCR_EN
/**
* @brief Enable the OTG PHY .
* @param OTGPHYConfig Defines the OTG PHY configuration.
This parameter can be one of @ref SYSCFG_OTG_PHY_Enable
* @retval None
*/
void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig));
MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig);
}
/**
* @brief Set the OTG PHY Power Down config.
* @param PowerDownConfig Defines the OTG PHY Power down configuration.
This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown
* @retval None
*/
void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig));
MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig);
}
/**
* @brief Set the OTG PHY reference clock selection.
* @param RefClkSelection Defines the OTG PHY reference clock selection.
This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection
* @retval None
*/
void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection));
MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection);
}
/**
* @brief Set the OTG PHY Disconnect Threshold.
* @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event.
This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold
* @retval None
*/
void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold));
MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold);
}
/**
* @brief Adjust the voltage level for the threshold used to detect valid high speed data.
* @param SquelchThreshold Defines the voltage level.
This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold
* @retval None
*/
void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold));
MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold);
}
/**
* @brief Set the OTG PHY Current config.
* @param PreemphasisCurrent Defines the current configuration.
This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent
* @retval None
*/
void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent));
MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent);
}
#endif /* SYSCFG_OTGHSPHYCR_EN */
/**
* @}
*/

152
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.h
View File

@ -80,6 +80,8 @@ extern HAL_TickFreqTypeDef uwTickFreq;
* @}
*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
@ -191,6 +193,85 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#endif /* __ARM_FEATURE_CMSE */
#ifdef SYSCFG_OTGHSPHYCR_EN
/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection
* @{
*/
/** @brief OTG HS PHY reference clock frequency selection
*/
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */
/**
* @}
*/
/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down
* @{
*/
/** @brief OTG HS PHY Power Down config
*/
#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */
#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */
/**
* @}
*/
/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable
* @{
*/
#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */
#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */
/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current
* @{
*/
/** @brief High-speed (HS) transmitter preemphasis current control
*/
#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */
#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */
#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */
#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */
/**
* @}
*/
/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold
* @{
*/
/** @brief Squelch threshold adjustment
*/
#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */
#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */
/**
* @}
*/
/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold
* @{
*/
/** @brief Disconnect threshold adjustment
*/
#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */
#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */
/**
* @}
*/
#endif /* SYSCFG_OTGHSPHYCR_EN */
/**
* @}
*/
@ -258,16 +339,21 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP)
#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP)
#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_FDCAN_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
@ -555,6 +641,33 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#endif /* __ARM_FEATURE_CMSE */
#ifdef SYSCFG_OTGHSPHYCR_EN
#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6))
#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON))
#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE))
#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT))
#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT))
#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X))
#endif /* SYSCFG_OTGHSPHYCR_EN */
/**
* @}
*/
@ -605,6 +718,9 @@ void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
@ -636,10 +752,28 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
#ifdef SYSCFG_OTGHSPHYCR_EN
void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection);
void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig);
void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig);
void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold);
void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold);
void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent);
#endif /* SYSCFG_OTGHSPHYCR_EN */
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_EnableSRAMCached(void);
void HAL_SYSCFG_DisableSRAMCached(void);
void HAL_SYSCFG_EnableVddCompensationCell(void);
void HAL_SYSCFG_EnableVddIO2CompensationCell(void);
#if defined(SYSCFG_CCCSR_EN3)
void HAL_SYSCFG_EnableVddHSPICompensationCell(void);
#endif /* SYSCFG_CCCSR_EN3 */
void HAL_SYSCFG_DisableVddCompensationCell(void);
void HAL_SYSCFG_DisableVddIO2CompensationCell(void);
#if defined(SYSCFG_CCCSR_EN3)
void HAL_SYSCFG_DisableVddHSPICompensationCell(void);
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @}
*/
@ -684,6 +818,10 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

943
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.c
View File

File diff suppressed because it is too large Load Diff

136
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.h
View File

@ -49,7 +49,10 @@ extern "C" {
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
In case of ADC1 or ADC2 (if available), this parameter can be in the
range from 0 to 1023
In case of ADC4, this parameter can be a value of
@ref ADC_HAL_EC_OVS_RATIO */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
@ -393,9 +396,11 @@ typedef struct
Conversion time is the addition of sampling time and processing time
(14.5 ADC clock cycles at ADC resolution 14 bits, 12.5 cycles at 12 bits,
10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
For ADC1 and 2 (if available): This parameter can be a value of
@ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
Caution: This parameter applies to a channel that can be used into regular
and/or injected group. It overwrites the last setting.
For ADC4: This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON.
Note: On this STM32 family, two different sampling time settings are available
(refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"),
each channel can use one of these two settings.
@ -439,12 +444,16 @@ typedef struct
continuous mode or external trigger that could launch a conversion). */
FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter is applied only for 14-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE.*/
FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
This parameter is only applied when OffsetSaturation is ENABLE.
This parameter is applied only for 14-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE.
Note:
- If OffsetSignedSaturation is set to DISABLE the unsigned
saturation feature is used */
FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
This parameter value can be ENABLE or DISABLE.
@ -594,7 +603,6 @@ typedef struct
low power auto power-on (if feature available),
multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
@ -638,6 +646,9 @@ typedef struct
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
void (* CalibrationCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of calibration callback */
void (* VoltageRegulatorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC voltage regulator (LDO) Ready callback */
void (* ADCReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Ready callback */
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
@ -658,8 +669,11 @@ typedef enum
HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
HAL_ADC_END_OF_CALIBRATION_CB_ID = 0x09U, /*!< ADC end of calibration callback ID */
HAL_ADC_VOLTAGE_REGULATOR_CB_ID = 0x0AU, /*!< ADC voltage regulator (LDO) Ready callback ID */
HAL_ADC_ADC_READY_CB_ID = 0x0BU, /*!< ADC Ready callback ID */
HAL_ADC_MSPINIT_CB_ID = 0x0CU, /*!< ADC Msp Init callback ID */
HAL_ADC_MSPDEINIT_CB_ID = 0x0DU /*!< ADC Msp DeInit callback ID */
} HAL_ADC_CallbackIDTypeDef;
/**
@ -688,7 +702,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
@ -718,17 +731,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */
#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits (ADC1, ADC2 only) */
#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
#define ADC_RESOLUTION_6B (0xFFFFFFFFUL)
#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits (ADC4 only) */
#define ADC4_RESOLUTION_12B (LL_ADC_RESOLUTION_12B_ADC4) /*!< ADC resolution 12 bits */
#define ADC4_RESOLUTION_10B (LL_ADC_RESOLUTION_10B_ADC4) /*!< ADC resolution 10 bits */
#define ADC4_RESOLUTION_8B (LL_ADC_RESOLUTION_8B_ADC4) /*!< ADC resolution 8 bits */
#define ADC4_RESOLUTION_6B (LL_ADC_RESOLUTION_6B_ADC4) /*!< ADC resolution 6 bits */
/* Legacy literals */
#define ADC4_RESOLUTION_12B ADC_RESOLUTION_12B
#define ADC4_RESOLUTION_10B ADC_RESOLUTION_10B
#define ADC4_RESOLUTION_8B ADC_RESOLUTION_8B
#define ADC4_RESOLUTION_6B ADC_RESOLUTION_6B
/**
* @}
*/
@ -782,10 +795,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_LowPower_DPD ADC low power and deep power down selection
* @{
*/
#define ADC_LOW_POWER_NONE (0x00000000UL) /*!< Both Low Power Auto Off and Deep Power Down is Disabled*/
#define ADC_LOW_POWER_AUTOFF (ADC4_PW_AUTOFF) /*!< Low Power Auto Off Enabled and Deep Power Down is Disabled*/
#define ADC_LOW_POWER_DPD (ADC4_PW_DPD) /*!< Low Power Auto Off Disabled and Deep Power Down is Enabaled*/
#define ADC_LOW_POWER_AUTOFF_DPD (ADC4_PW_AUTOFF | ADC4_PW_DPD) /*!< Low Power Auto Off Disabled and Deep Power Down is Enabaled*/
#define ADC_LOW_POWER_NONE (0x00000000UL) /*!< Both Low Power Auto Off and Deep Power Down is disabled */
#define ADC_LOW_POWER_AUTOFF (ADC4_PWRR_AUTOFF) /*!< Low Power Auto Off enabled and Deep Power Down is disabled */
#define ADC_LOW_POWER_DPD (ADC4_PWRR_DPD) /*!< Low Power Auto Off disabled and Deep Power Down is enabled */
#define ADC_LOW_POWER_AUTOFF_DPD (ADC4_PWRR_AUTOFF | ADC4_PWRR_DPD) /*!< Low Power Auto Off and Deep Power Down are enabled */
/**
* @}
*/
@ -793,10 +806,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_VrefProt ADC VREF+ protection mode selection
* @{
*/
#define ADC_VREF_PPROT_NONE (0x00000000UL) /*!< No VREF protection is applied*/
#define ADC_VREF_PPROT_VREFPROT (ADC4_PW_VREFPROT) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider is used.*/
#define ADC_VREF_PPROT_VREFSECSMP (ADC4_PW_VREFSECSMP) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider of 1 is used.*/
#define ADC_VREF_PPROT_VREF_VREFSECSMP (ADC4_PW_VREFPROT | ADC4_PW_VREFSECSMP) /*!< Both VREF+ protection when multiple ADCs are working simultaneously and VREF+ second sample protection.*/
#define ADC_VREF_PPROT_NONE (0x00000000UL) /*!< No VREF protection is applied*/
#define ADC_VREF_PPROT_VREFPROT (ADC4_PWRR_VREFPROT) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider is used.*/
#define ADC_VREF_PPROT_VREFSECSMP (ADC4_PWRR_VREFSECSMP) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider of 1 is used.*/
#define ADC_VREF_PPROT_VREF_VREFSECSMP (ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP) /*!< Both VREF+ protection when multiple ADCs are working simultaneously and VREF+ second sample protection.*/
/**
* @}
*/
@ -822,11 +835,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 CH1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 CH1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 CH1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM4_OUT (LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 15 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 channel 1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM4_OUT (LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC4_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC4_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4)
@ -935,13 +948,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
#define ADC_SAMPLETIME_5CYCLE (LL_ADC_SAMPLINGTIME_5CYCLE) /*!< Sampling time 5 ADC clock cycles */
#define ADC_SAMPLETIME_5CYCLES (LL_ADC_SAMPLINGTIME_5CYCLES) /*!< Sampling time 5 ADC clock cycles */
#define ADC_SAMPLETIME_6CYCLES (LL_ADC_SAMPLINGTIME_6CYCLES) /*!< Sampling time 6 ADC clock cycles */
#define ADC_SAMPLETIME_12CYCLES (LL_ADC_SAMPLINGTIME_12CYCLES) /*!< Sampling time 12 ADC clock cycles */
#define ADC_SAMPLETIME_20CYCLES (LL_ADC_SAMPLINGTIME_20CYCLES) /*!< Sampling time 20 ADC clock cycles */
#define ADC_SAMPLETIME_36CYCLES (LL_ADC_SAMPLINGTIME_36CYCLES) /*!< Sampling time 36 ADC clock cycles */
#define ADC_SAMPLETIME_68CYCLES (LL_ADC_SAMPLINGTIME_68CYCLES) /*!< Sampling time 68 ADC clock cycles */
#define ADC_SAMPLETIME_391CYCLES_5 (LL_ADC_SAMPLINGTIME_391CYCLES_5)/*!< Sampling time 391.5 ADC clock cycles */
#define ADC_SAMPLETIME_391CYCLES (LL_ADC_SAMPLINGTIME_391CYCLES) /*!< Sampling time 391 ADC clock cycles */
#define ADC_SAMPLETIME_814CYCLES (LL_ADC_SAMPLINGTIME_814CYCLES) /*!< Sampling time 814 ADC clock cycles */
/**
* @}
@ -957,7 +970,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC4_SAMPLETIME_19CYCLES_5 (LL_ADC4_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
#define ADC4_SAMPLETIME_39CYCLES_5 (LL_ADC4_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
#define ADC4_SAMPLETIME_79CYCLES_5 (LL_ADC4_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
#define ADC4_SAMPLETIME_160CYCLES_5 (LL_ADC4_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
#define ADC4_SAMPLETIME_814CYCLES_5 (LL_ADC4_SAMPLINGTIME_814CYCLES_5) /*!< Sampling time 814.5 ADC clock cycles */
/**
* @}
*/
@ -1055,14 +1068,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
* @{
*/
#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_2SAMPLES ((ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_3SAMPLES ((ADC_HTR_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_4SAMPLES ((ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_5SAMPLES ((ADC_HTR_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_6SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_7SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_8SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_2SAMPLES ((ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_3SAMPLES ((ADC_HTR_AWDFILT_1)) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_4SAMPLES ((ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_5SAMPLES ((ADC_HTR_AWDFILT_2)) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_6SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_7SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1)) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_8SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
/**
* @}
*/
@ -1174,7 +1187,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
/**
* @}
*/
@ -1193,7 +1205,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */
#define ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC Voltage Regulator (LDO) Ready interrupt source */
#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
@ -1214,7 +1227,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC End of Calibration flag */
#define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC Voltage Regulator (LDO) Ready flag */
/**
* @}
@ -1485,13 +1499,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @param __TIME__ ADC conversions sampling time.
* @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
*/
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_5CYCLE) || \
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_5CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_6CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_12CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_12CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_20CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_36CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_68CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_391CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_391CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_814CYCLES) )
#define IS_ADC4_SAMPLE_TIME(TIME) (((TIME) == ADC4_SAMPLETIME_1CYCLE_5) || \
@ -1501,8 +1515,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
((TIME) == ADC4_SAMPLETIME_19CYCLES_5) || \
((TIME) == ADC4_SAMPLETIME_39CYCLES_5) || \
((TIME) == ADC4_SAMPLETIME_79CYCLES_5) || \
((TIME) == ADC4_SAMPLETIME_160CYCLES_5) )
((TIME) == ADC4_SAMPLETIME_814CYCLES_5) )
#define IS_ADC4_SAMPLE_TIME_COMMON(TIME) (((TIME) == ADC4_SAMPLINGTIME_COMMON_1) || \
((TIME) == ADC4_SAMPLINGTIME_COMMON_2) )
/**
* @brief Verify the ADC regular channel setting.
* @param __CHANNEL__ programmed ADC regular channel.
@ -1629,7 +1645,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source
* @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source
* @retval None
*/
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1650,7 +1667,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source
* @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source
* @retval None
*/
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1670,7 +1688,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source
* @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source
* @retval State of interruption (SET or RESET)
*/
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
@ -1691,7 +1710,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @arg @ref ADC_FLAG_EOCAL ADC End of Calibration flag
* @arg @ref ADC_FLAG_LDORDY ADC Voltage Regulator (LDO) Ready flag
* @retval State of flag (TRUE or FALSE).
*/
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
@ -1712,7 +1732,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @arg @ref ADC_FLAG_EOCAL ADC End of Calibration flag
* @arg @ref ADC_FLAG_LDORDY ADC Voltage Regulator (LDO) Ready flag
* @retval None
*/
/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
@ -2324,7 +2345,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
@ -2332,6 +2353,9 @@ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_VoltageRegulatorCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
@ -2352,8 +2376,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
/**
* @}

643
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.c
View File

@ -66,14 +66,13 @@
once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescalers. */
/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
/* according to Data sheet), calibration_time MAX = 16384 / f_ADC */
/* 16384 / 4577.63671875 = 3.58s */
/* At maximum CPU speed (400 MHz), this means */
/* 3.58 * 400 MHz = 1432000000 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (1432000000U) /*!< ADC calibration time-out value */
/* Values defined to be higher than worst cases: maximum ratio between ADC */
/* and CPU clock frequencies. */
/* Example of profile low frequency : ADC frequency minimum 140kHz (cf */
/* datasheet for ADC4), CPU frequency 160MHz. */
/* Calibration time max = 25502 / fADC (refer to datasheet) */
/* = 29M CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (29000000U) /*!< ADC calibration time-out value */
/**
* @}
@ -135,6 +134,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
{
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
uint32_t backup_setting_cfgr1;
uint32_t backup_setting_pwrr;
UNUSED(SingleDiff); /* STM32U5 calibration is not making difference between Single and Diff ended */
/* We keep this to be inligne with old products API and for any further use */
@ -156,28 +157,114 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration in mode single-ended or differential */
LL_ADC_StartCalibration(hadc->Instance, CalibrationMode);
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
if (hadc->Instance == ADC4)
{
wait_loop_index++;
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
/* Manage settings impacting calibration */
/* - Disable ADC mode auto power-off */
/* - Disable ADC DMA transfer request during calibration */
/* Note: Specificity of this STM32 series: Calibration factor is */
/* available in data register and also transferred by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
/* in array variable, DMA transfer must be disabled during */
/* calibration. */
backup_setting_pwrr = READ_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF);
backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG);
CLEAR_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG);
CLEAR_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF);
/* Start ADC calibration in mode single-ended */
LL_ADC_StartCalibration(hadc->Instance, LL_ADC_CALIB_OFFSET);
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
wait_loop_index++;
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
__HAL_UNLOCK(hadc);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
return HAL_ERROR;
}
}
/* Restore configuration after calibration */
SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
SET_BIT(hadc->Instance->PWRR, backup_setting_pwrr);
}
else /* ADC instance ADC1 or ADC2 */
{
/* Get device information */
uint32_t dev_id = READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID);
uint32_t rev_id = READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos;
/* Assess whether extended calibration is available on the selected device */
if ((dev_id == 0x455UL) || (dev_id == 0x476UL)
|| (((dev_id == 0x481UL) || (dev_id == 0x482UL)) && (rev_id >= 0x3000UL)))
{
/* Perform extended calibration */
/* Refer to ref manual for extended calibration procedure details */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos);
MODIFY_REG(hadc->Instance->CALFACT2, 0x00FF0000UL, 0x00020000UL);
SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
tmp_hal_status = ADC_Disable(hadc);
if (CalibrationMode == ADC_CALIB_OFFSET_LINEARITY)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALLIN | ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCALLIN);
}
MODIFY_REG(hadc->Instance->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL);
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
{
wait_loop_index++;
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
}
}
}
else
{
/* Start ADC calibration in mode single-ended or differential */
LL_ADC_StartCalibration(hadc->Instance, CalibrationMode);
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
{
wait_loop_index++;
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
}
}
}
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
}
else
else /* ADC not disabled */
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@ -200,18 +287,36 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
*/
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
uint32_t Calib_Val = 0UL;
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Return the selected ADC calibration value */
return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
if (hadc->Instance != ADC4)
{
tmp_hal_status = ADC_Enable(hadc); /* ADC need to be enabled to perform calibration for ADC1/2 and not for ADC4 */
}
if (tmp_hal_status == HAL_OK)
{
/* Return the selected ADC calibration value */
Calib_Val = LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
}
if (hadc->Instance != ADC4)
{
tmp_hal_status = ADC_Disable(hadc);
UNUSED(tmp_hal_status);
}
return Calib_Val;
}
/**
* @brief Get the calibration factor from automatic conversion result
* @param hadc ADC handle
* @param pLinearCalib_Buffer: Linear calibration factor
* @param hadc ADC handle
* @param pLinearCalib_Buffer Linear calibration factor (table of 9 elements)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
@ -222,23 +327,33 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc,
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
if (hadc->Instance != ADC4)
{
SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
for (cnt = 0UL; cnt <= 8UL; cnt++)
/* Enable the ADC to be able to read the linear calibration factor */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
MODIFY_REG(hadc->Instance->CR,
(ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
(cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
pLinearCalib_Buffer[cnt] = (uint32_t)(READ_BIT(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
/* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
therefore they are not cleared in this function. */
SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
for (cnt = 0UL; cnt <= 8UL; cnt++)
{
MODIFY_REG(hadc->Instance->CR,
(ADC_CR_CALINDEX),
(cnt << ADC_CR_CALINDEX_Pos));
pLinearCalib_Buffer[cnt] = (uint32_t)(READ_BIT(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
}
}
tmp_hal_status = ADC_Disable(hadc);
}
else
{
/* ADC linear calibration not available on ADC4 */
tmp_hal_status = HAL_ERROR;
}
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
tmp_hal_status = ADC_Disable(hadc);
return tmp_hal_status;
}
@ -250,13 +365,13 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc,
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @param CalibrationFactor Calibration factor (range 0xFFFF for ADC1 and ADC2, range 0x7F for ADC4)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
HAL_StatusTypeDef tmp_hal_status;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
@ -272,13 +387,20 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
/* Set the selected ADC calibration value */
LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
/* Enable the ADC to be able to set the calibration factor */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
/* Set the selected ADC calibration value */
LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
tmp_hal_status = ADC_Disable(hadc);
}
}
else
{
@ -298,80 +420,58 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
/**
* @brief Set the linear calibration factor
* @param hadc ADC handle
* @param pLinearCalib_Buffer: Linear calibration factor
* @param hadc ADC handle
* @param pLinearCalib_Buffer Linear calibration factor (table of 9 elements)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
{
uint32_t cnt;
__IO uint32_t wait_loop_index;
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
/* Exit deep power down mode if still in that state */
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
if (hadc->Instance != ADC4)
{
/* Exit deep power down mode */
CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
tmp_hal_status = ADC_Enable(hadc);
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
{
/* Enable ADC internal voltage regulator */
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
/* Delay for ADC stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
while (wait_loop_index != 0UL)
if (tmp_hal_status == HAL_OK)
{
wait_loop_index--;
/* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
therefore they are not cleared in this function. */
for (cnt = 0UL; cnt <= 7UL; cnt++)
{
MODIFY_REG(hadc->Instance->CR,
(ADC_CR_CALINDEX),
(cnt << ADC_CR_CALINDEX_Pos));
if (cnt == 7UL)
{
/* Specific case for linearity factor 7 and internal offset: must be concatenated */
MODIFY_REG(hadc->Instance->CALFACT2,
ADC_CALFACT2_CALFACT,
pLinearCalib_Buffer[cnt] | ((pLinearCalib_Buffer[cnt + 1UL] & 0xFF000000UL) >> 8UL));
}
else
{
MODIFY_REG(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT, pLinearCalib_Buffer[cnt]);
}
}
SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
CLEAR_BIT(hadc->Instance->CR, ADC_CR_CALINDEX);
tmp_hal_status = ADC_Disable(hadc);
}
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
/* ADC linear calibration not available on ADC4 */
tmp_hal_status = HAL_ERROR;
}
if (ADC_Enable(hadc) == HAL_OK)
{
/* We need to wait till ADC_ISR_ADRDY flag go up to set calibration values. */
/* However this is already done by ADC_Enable(). */
/* Therefore a simple check of the flag could help to ensure ADC is ready. */
if ((hadc->Instance->ISR & ADC_ISR_ADRDY) == 0UL)
{
return HAL_ERROR;
}
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
for (cnt = 0UL; cnt <= 8UL; cnt++)
{
MODIFY_REG(hadc->Instance->CR,
(ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
(cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
MODIFY_REG(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT, pLinearCalib_Buffer[cnt]);
}
}
SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
return HAL_OK;
return tmp_hal_status;
}
/**
@ -417,16 +517,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
{
/* Check if a regular conversion is ongoing */
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
{
/* Reset ADC error code field related to injected conversions only */
CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
}
else
{
ADC_CLEAR_ERRORCODE(hadc);
}
/* Clear ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
@ -734,16 +826,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
{
/* Check if a regular conversion is ongoing */
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
{
/* Reset ADC error code field related to injected conversions only */
CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
}
else
{
ADC_CLEAR_ERRORCODE(hadc);
}
/* Clear ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
@ -870,7 +954,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC end of conversion interrupt for injected channels */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS));
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
@ -920,6 +1004,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui
ADC_HandleTypeDef tmp_hadc_slave;
ADC_Common_TypeDef *tmp_adc_common;
uint32_t LengthInBytes;
DMA_NodeConfTypeDef node_conf;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
@ -954,6 +1039,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
/* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */
tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff;
tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
}
@ -994,19 +1081,39 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Length should be converted to number of bytes */
LengthInBytes = Length * 4U;
/* Start the DMA channel */
/* Check linkedlist mode */
if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
{
/* Length should be converted to number of bytes */
if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
{
return HAL_ERROR;
}
/* Length should be converted to number of bytes */
if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&tmp_adc_common->CDR;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
}
else
@ -1016,7 +1123,24 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui
}
else
{
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \
/* Length should be converted to number of bytes */
if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \
LengthInBytes);
}
@ -1167,7 +1291,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
* @retval The converted data values.
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
{
const ADC_Common_TypeDef *tmp_adc_common;
@ -1184,6 +1308,176 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
/* Return the multi mode conversion value */
return tmp_adc_common->CDR;
}
/**
* @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
* @note Multimode must have been previously configured using
* HAL_ADCEx_MultiModeConfigChannel() function.
* Interruptions enabled in this function:
* overrun, DMA half transfer, DMA transfer complete.
* Each of these interruptions has its dedicated callback function.
* @note State field of Slave ADC handle is not updated in this configuration:
* user should not rely on it for information related to Slave regular
* conversions.
* @param hadc ADC handle of ADC
* @note - Only ADC master could start the conversion.
* - Two ADC conversions (Master & Slave) per external trig and so two DMA requests.
* @param pData Destination Buffer address.
* @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
{
HAL_StatusTypeDef tmp_hal_status;
ADC_HandleTypeDef tmp_hadc_slave;
ADC_Common_TypeDef *tmp_adc_common;
uint32_t LengthInBytes;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
return HAL_BUSY;
}
else
{
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmp_hadc_slave.Instance == NULL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
/* Enable the ADC peripherals: master and slave (in case if not already */
/* enabled previously) */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
/* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */
tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff;
tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
}
/* Start multimode conversion of ADCs pair */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
(HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR \
| HAL_ADC_STATE_REG_EOSMP),
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
/* Pointer to the common control register */
tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Length should be converted to number of bytes */
LengthInBytes = (uint32_t)(Length * 4U);
/* Start the DMA channel */
if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
{
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (LengthInBytes * 2U);
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&tmp_adc_common->CDR2;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
}
else
{
tmp_hal_status = HAL_ERROR;
};
}
else
{
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR2, (uint32_t)pData, \
(LengthInBytes * 2U));
}
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
}
/* Return function status */
return tmp_hal_status;
}
}
/**
* @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
* @retval The converted data values.
*/
uint32_t HAL_ADCEx_MultiModeGetValue_Data32(const ADC_HandleTypeDef *hadc)
{
const ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
/* Prevent unused argument(s) compilation warning if no assert_param check */
/* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
UNUSED(hadc);
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Return the multi mode conversion value */
return tmpADC_Common->CDR2;
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
@ -1214,7 +1508,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
* @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
* @retval ADC group injected conversion data
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
{
uint32_t tmp_jdr;
@ -1748,7 +2042,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
#if defined (ADC2)
assert_param(IS_ADC12_DIFF_CHANNEL(pConfigInjected->InjectedChannel));
#else
assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel));
#endif /* ADC2 */
}
}
@ -1955,7 +2253,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
if (pConfigInjected->InjecOversamplingMode == ENABLE)
{
assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
assert_param(IS_ADC12_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
/* JOVSE must be reset in case of triggered regular mode */
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
@ -1968,9 +2266,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Enable OverSampling mode */
MODIFY_REG(hadc->Instance->CFGR2,
ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS,
ADC_CFGR2_JOVSE | pConfigInjected->InjecOversampling.Ratio |
pConfigInjected->InjecOversampling.RightBitShift
);
ADC_CFGR2_JOVSE | (pConfigInjected->InjecOversampling.Ratio << ADC_CFGR2_OVSR_Pos) |
pConfigInjected->InjecOversampling.RightBitShift);
}
else
{
@ -1995,39 +2292,53 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
tmp_offset_shifted);
/* Set ADC selected offset sign */
LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
/* Set ADC selected offset signed saturation */
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
(pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \
: LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
/* Configure offset saturation */
if (pConfigInjected->InjectedOffsetSaturation == ENABLE)
{
/* Set ADC selected offset unsigned/signed saturation */
LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
(pConfigInjected->InjectedOffsetSignedSaturation == DISABLE)
? LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE \
: LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE);
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
(pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \
: LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
else
{
/* Disable ADC offset signed saturation */
LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE);
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel, 0x0);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel, 0x0);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_3, pConfigInjected->InjectedChannel, 0x0);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel, 0x0);
}
}
}
@ -2149,9 +2460,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pMultimode)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
ADC_Common_TypeDef *tmp_adc_common;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
@ -2168,9 +2479,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmphadcSlave.Instance == NULL)
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@ -2185,19 +2496,19 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
&& (tmphadcSlave_conversion_on_going == 0UL))
&& (tmp_hadc_slave_conversion_on_going == 0UL))
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* If multimode is selected, configure all pMultimode parameters. */
/* Otherwise, reset pMultimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData);
MODIFY_REG(tmp_adc_common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData);
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
@ -2211,20 +2522,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
MODIFY_REG(tmpADC_Common->CCR, (ADC_CCR_DUAL | ADC_CCR_DELAY), \
MODIFY_REG(tmp_adc_common->CCR, (ADC_CCR_DUAL | ADC_CCR_DELAY), \
(pMultimode->Mode | pMultimode->TwoSamplingDelay));
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DAMDF);
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
}
}
}

166
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.h
View File

@ -46,7 +46,10 @@ extern "C" {
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
In case of ADC1 or ADC2 (if available), this parameter can be in the
range from 0 to 1023
In case of ADC4, this parameter can be a value of
@ref ADC_HAL_EC_OVS_RATIO */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
@ -58,13 +61,13 @@ typedef struct
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
* InjectedOffsetNumber, InjectedOffset
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
* InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv,
* InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConv,
* ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
* 'InjectedSingleDiff')
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling':
* - For parameters 'InjectedDiscontinuousConvMode', 'InjecOversampling':
* ADC enabled without conversion on going on injected group.
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv':
* ADC enabled without conversion on going on regular and injected groups.
@ -139,9 +142,14 @@ typedef struct
without continuous mode or external trigger that could launch a
conversion). */
FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
This parameter is applied only for 14-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState InjectedOffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
This parameter is only applied when InjectedOffsetSaturation is
ENABLE.
This parameter is applied only for 14-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE.
Note:
- If InjectedOffsetSignedSaturation is set to DISABLE the unsigned
saturation feature is used */
uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added
(positive sign) from or to the raw converted data.
@ -398,15 +406,22 @@ typedef struct
/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_13CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_14CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_15CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_16CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
/**
* @}
@ -544,7 +559,7 @@ typedef struct
* @retval SET (ADC is independent) or RESET (ADC is not).
*/
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC3) \
( ( ( ((__HANDLE__)->Instance) == ADC4) \
)? \
SET \
: \
@ -597,7 +612,7 @@ typedef struct
* @param _AUTOOFF_ Auto off bit enable or disable.
* @retval None
*/
#define ADC4_CFGR_AUTOOFF(_AUTOOFF_)((_AUTOOFF_) << ADC4_PW_AUTOOFF_Pos)
#define ADC4_CFGR_AUTOOFF(_AUTOOFF_)((_AUTOOFF_) << ADC4_PWRR_AUTOOFF_Pos)
/**
* @brief Configure the ADC auto delay mode.
@ -619,6 +634,15 @@ typedef struct
* @param __DMACONTREQ_MODE__: DMA continuous request mode.
* @retval None
*/
#if defined (ADC2)
#define ADC_CFGR_DMACONTREQ(__HANDLE__,__DMACONTREQ_MODE__) \
( (((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
)? \
((__DMACONTREQ_MODE__)) \
: \
((__DMACONTREQ_MODE__) << 1U) \
)
#else
#define ADC_CFGR_DMACONTREQ(__HANDLE__,__DMACONTREQ_MODE__) \
( (((__HANDLE__)->Instance == ADC1) \
)? \
@ -626,7 +650,7 @@ typedef struct
: \
((__DMACONTREQ_MODE__) << 1U) \
)
#endif /*ADC2 */
/**
* @brief Configure the channel number into offset OFRx register.
@ -666,6 +690,24 @@ typedef struct
#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with
* handle of ADC master.
* @param __HANDLE__ ADC handle.
* @note Return SET if multimode feature is not available.
* @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
*/
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC4) \
)? \
SET \
: \
(((__LL_ADC_COMMON_INSTANCE(__HANDLE__))->CCR & ADC_CCR_DUAL) == RESET) \
)
/**
* @brief Configure the ADC DMA continuous request for ADC multimode.
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
@ -906,11 +948,11 @@ typedef struct
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
/**
* @brief Calibration factor size verification (7 bits maximum).
* @brief Calibration factor size verification.
* @param __CALIBRATION_FACTOR__ Calibration factor value.
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
*/
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0xFFFFU))
/**
@ -950,7 +992,30 @@ typedef struct
((__CHANNEL__) == ADC4_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VCORE) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT) )
#if defined (ADC2)
/**
* @brief Verify the ADC channel setting in differential mode for ADC1 and ADC2.
* @param __CHANNEL__: programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC12_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) ||\
((__CHANNEL__) == ADC_CHANNEL_4) ||\
((__CHANNEL__) == ADC_CHANNEL_5) ||\
((__CHANNEL__) == ADC_CHANNEL_6) ||\
((__CHANNEL__) == ADC_CHANNEL_7) ||\
((__CHANNEL__) == ADC_CHANNEL_8) ||\
((__CHANNEL__) == ADC_CHANNEL_9) ||\
((__CHANNEL__) == ADC_CHANNEL_10) ||\
((__CHANNEL__) == ADC_CHANNEL_11) ||\
( (__CHANNEL__) == ADC_CHANNEL_12) ||\
((__CHANNEL__) == ADC_CHANNEL_13) ||\
((__CHANNEL__) == ADC_CHANNEL_14) ||\
((__CHANNEL__) == ADC_CHANNEL_15) ||\
((__CHANNEL__) == ADC_CHANNEL_16) ||\
((__CHANNEL__) == ADC_CHANNEL_17) )
#else
/**
* @brief Verify the ADC channel setting in differential mode for ADC1.
* @param __CHANNEL__: programmed ADC channel.
@ -973,6 +1038,7 @@ typedef struct
((__CHANNEL__) == ADC_CHANNEL_15) ||\
((__CHANNEL__) == ADC_CHANNEL_16) ||\
((__CHANNEL__) == ADC_CHANNEL_17) )
#endif /* ADC2 */
/**
@ -1084,7 +1150,16 @@ typedef struct
((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) )
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) )
#endif /* ADC_MULTIMODE_SUPPORT */
/**
@ -1144,16 +1219,30 @@ typedef struct
((__EVENT__) == ADC_AWD_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \
((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) || \
((__EVENT__) == ADC_JQOVF_EVENT) )
((__EVENT__) == ADC_OVR_EVENT) )
/**
* @brief Verify the ADC oversampling ratio.
* @param RATIO: programmed ADC oversampling ratio.
* @param __RATIO__: programmed ADC oversampling ratio.
* @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
*/
#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024UL)
#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) \
((((__RATIO__) & ADC4_OVERSAMPLING_RATIO_PARAMETER) != ADC4_OVERSAMPLING_RATIO_PARAMETER) && \
((__RATIO__) < 1024UL))
/**
* @brief Verify the ADC oversampling ratio.
* @param __RATIO__: programmed ADC oversampling ratio.
* @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
*/
#define IS_ADC4_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256))
/**
* @brief Verify the ADC oversampling shift.
* @param __SHIFT__ programmed ADC oversampling shift.
@ -1169,6 +1258,24 @@ typedef struct
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
/**
* @brief Verify the ADC oversampling shift.
* @param __SHIFT__ programmed ADC oversampling shift.
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
*/
#define IS_ADC12_RIGHT_BIT_SHIFT( __SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_11 ))
/**
* @brief Verify the ADC oversampling triggered mode.
* @param __MODE__ programmed ADC oversampling triggered mode.
@ -1221,12 +1328,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
#if defined(ADC_MULTIMODE_SUPPORT)
/* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef *hadc, const uint32_t *pData,
uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue_Data32(const ADC_HandleTypeDef *hadc);
#endif /* ADC_MULTIMODE_SUPPORT */
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);

47
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.c
View File

@ -29,7 +29,8 @@
[..]
The STM32U5xx device family integrates two analog comparators instances:
COMP1, COMP2.
COMP1, COMP2 except for the products featuring only
one instance: COMP1 (in this case, all comments related to pair of comparators are not applicable)
(#) Comparators input minus (inverting input) and input plus (non inverting input)
can be set to internal references or to GPIO pins
(refer to GPIO list in reference manual).
@ -40,7 +41,7 @@
(refer to GPIO list in reference manual).
(#) The comparators have interrupt capability through the EXTI controller
with wake-up from sleep and stop modes:
with wake-up from sleep and stop modes.
(++) COMP1 is internally connected to EXTI Line 20
(++) COMP2 is internally connected to EXTI Line 21
@ -257,11 +258,15 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
#if defined(COMP_WINDOW_MODE_SUPPORT)
#if defined(COMP2)
assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode));
#endif /* COMP2 */
if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
{
assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput));
}
#endif /* COMP_WINDOW_MODE_SUPPORT */
if (hcomp->State == HAL_COMP_STATE_RESET)
{
@ -271,7 +276,6 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Set COMP error code to none */
COMP_CLEAR_ERRORCODE(hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Init the COMP Callback settings */
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
@ -316,6 +320,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
tmp_csr
);
#if defined(COMP_WINDOW_MODE_SUPPORT)
/* Set window mode */
/* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
/* instances. Therefore, this function can update another COMP */
@ -363,6 +368,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
break;
}
#endif /* COMP_WINDOW_MODE_SUPPORT */
/* Delay for COMP scaler bridge voltage stabilization */
/* Apply the delay if voltage scaler bridge is required and not already enabled */
@ -410,7 +416,6 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
WRITE_REG(EXTI->RPR1, exti_line);
WRITE_REG(EXTI->FPR1, exti_line);
/* Configure EXTI event mode */
if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
{
@ -816,12 +821,16 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
/* Get the EXTI line corresponding to the selected COMP instance */
uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
#if defined(COMP_WINDOW_MODE_SUPPORT)
uint32_t comparator_window_mode = READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE);
#endif /* COMP_WINDOW_MODE_SUPPORT */
/* Check COMP EXTI flag */
if (READ_BIT(EXTI->RPR1, exti_line) != 0UL)
{
#if defined(COMP_WINDOW_MODE_SUPPORT)
/* Check whether comparator is in independent or window mode */
if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL)
if (comparator_window_mode != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
@ -833,6 +842,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
WRITE_REG(EXTI->RPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
#endif /* COMP_WINDOW_MODE_SUPPORT */
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI->RPR1, exti_line);
@ -845,10 +855,11 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
else
else if (READ_BIT(EXTI->FPR1, exti_line) != 0UL)
{
#if defined(COMP_WINDOW_MODE_SUPPORT)
/* Check whether comparator is in independent or window mode */
if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL)
if (comparator_window_mode != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
@ -860,6 +871,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
WRITE_REG(EXTI->FPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
#endif /* COMP_WINDOW_MODE_SUPPORT */
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI->FPR1, exti_line);
@ -872,16 +884,10 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
/* Change COMP state */
hcomp->State = HAL_COMP_STATE_READY;
/* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp);
#else
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
else
{
/* nothing to do */
}
}
/**
@ -968,7 +974,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
* @arg COMP_OUTPUT_LEVEL_HIGH
*
*/
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
@ -1016,7 +1022,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
* @param hcomp COMP handle
* @retval HAL state
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp)
{
/* Check the COMP handle allocation */
if (hcomp == NULL)
@ -1036,7 +1042,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
* @param hcomp COMP handle
* @retval COMP error code
*/
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
@ -1063,4 +1069,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
/**
* @}
*/

207
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.h
View File

@ -46,16 +46,18 @@ extern "C" {
*/
typedef struct
{
#if defined(COMP_WINDOW_MODE_SUPPORT)
#if defined(COMP2)
uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
Note: HAL COMP driver allows to set window mode from any COMP
instance of the pair of COMP instances composing window mode.
This parameter can be a value of @ref COMP_WindowMode */
#endif /* COMP2 */
uint32_t WindowOutput; /*!< Set window mode output.
This parameter can be a value of @ref COMP_WindowOutput */
#endif /* COMP_WINDOW_MODE_SUPPORT */
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
Note: For the characteristics of comparator power modes
(propagation delay and power consumption), refer to device datasheet.
@ -154,26 +156,74 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @}
*/
#if defined(COMP_WINDOW_MODE_SUPPORT)
#if defined(COMP2)
/** @defgroup COMP_WindowMode COMP Window Mode
* @{
*/
#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible) */
#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators
instances pair COMP1 and COMP2 are
independent */
#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances
pair COMP1 and COMP2 have their input
plus connected together.
The common input is COMP1 input plus
(COMP2 input plus is no more accessible).
*/
#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE \
| COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or
COMP2 instance, comparators instances
pair COMP1 and COMP2 have their input
plus connected together, the common input
is COMP2 input plus (COMP1 input plus is
no more accessible). */
/**
* @}
*/
#endif /* COMP2 */
/** @defgroup COMP_WindowOutput COMP Window output
* @{
*/
#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. */
#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are
indicating each their own state.
To know window mode state: each comparator output
must be read, if "((COMPx exclusive or COMPy) == 1)"
then monitored signal is within comparators window.*/
#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthesized on COMP1 output:
COMP1 output is no more indicating its own state, but
global window mode state (logical high means
monitored signal is within comparators window).
Note: impacts only comparator output signal level
(COMPx_OUT propagated to GPIO, EXTI lines,
timers, ...), does not impact output digital state
of comparator (COMPx_VALUE) always reflecting each
comparator output state.*/
#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT \
| COMP_WINDOWMODE_COMP2) /*!< Window output synthesized on COMP2 output:
COMP2 output is no more indicating its own state, but
global window mode state (logical high means
monitored signal is within comparators window).
Note: impacts only comparator output signal level
(COMPx_OUT propagated to GPIO, EXTI lines,
timers, ...), does not impact output digital state
of comparator (COMPx_VALUE) always reflecting each
comparator output state.*/
#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthesized on both comparators output
of pair of comparator selected (COMP1 and COMP2:
both comparators outputs are no more indicating their
own state, but global window mode state (logical high
means monitored signal is within comparators window).
This is a specific configuration (technically
possible but not relevant from application
point of view:
2 comparators output used for the same signal level),
standard configuration for window mode is one of the
settings above. */
/**
* @}
*/
#endif /* COMP_WINDOW_MODE_SUPPORT */
/** @defgroup COMP_PowerMode COMP power mode
* @{
@ -181,9 +231,9 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/* Note: For the characteristics of comparator power modes */
/* (propagation delay and power consumption), */
/* refer to device datasheet. */
#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */
#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< Ultra-low power */
#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */
#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< Ultra-low power */
/**
* @}
*/
@ -194,6 +244,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA2 for COMP1) */
#if defined(COMP_CSR_INPSEL_2)
#define COMP_INPUT_PLUS_IO4 (COMP_CSR_INPSEL_1 | COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO4 (pin PB3 for COMP1) */
#define COMP_INPUT_PLUS_IO5 (COMP_CSR_INPSEL_2) /*!< Comparator input plus connected to IO5 (pin PB4 for COMP1) */
#define COMP_INPUT_PLUS_IO6 (COMP_CSR_INPSEL_2 | COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO6 (pin PB6 for COMP1) */
#endif /* COMP_CSR_INPSEL_2 */
/**
* @}
*/
@ -201,14 +256,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
* @{
*/
#define COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000 ) /*!< Comparator input minus connected to 1/4 VrefInt */
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB7 for COMP2) */
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB3 for COMP2) */
#define COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL) /*!< Comparator input minus connected to 1/4 VrefInt */
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#define COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB7 for COMP2) */
#define COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB3 for COMP2) */
/**
* @}
*/
@ -216,34 +271,33 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_Hysteresis COMP hysteresis
* @{
*/
#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
#define COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0) /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1) /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST ) /*!< Hysteresis level high */
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
/**
* @}
*/
/** @defgroup COMP_OutputPolarity COMP Output Polarity
/** @defgroup COMP_OutputPolarity COMP output Polarity
* @{
*/
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
/**
* @}
*/
/** @defgroup COMP_BlankingSrce COMP Blanking Source
/** @defgroup COMP_BlankingSrce COMP blanking source
* @{
*/
#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKSEL_0) /*!< TIM1 OC5 selected as blanking source for COMP1 */
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKSEL_1) /*!< TIM2 OC3 selected as blanking source for COMP1 */
#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKSEL_2) /*!< TIM3 OC3 selected as blanking source for COMP1 */
#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CSR_BLANKSEL_0) /*!< TIM3 OC4 selected as blanking source for COMP2 */
#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CSR_BLANKSEL_1) /*!< TIM8 OC5 selected as blanking source for COMP2 */
#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKSEL_2) /*!< TIM15 OC1 selected as blanking source for COMP2 */
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKSEL_0) /*!< TIM1 OC5 selected as blanking source for COMP1 */
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKSEL_1) /*!< TIM2 OC3 selected as blanking source for COMP1 */
#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKSEL_2) /*!< TIM3 OC3 selected as blanking source for COMP1 */
#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CSR_BLANKSEL_0) /*!< TIM3 OC4 selected as blanking source for COMP2 */
#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CSR_BLANKSEL_1) /*!< TIM8 OC5 selected as blanking source for COMP2 */
#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKSEL_2) /*!< TIM15 OC1 selected as blanking source for COMP2 */
/**
* @}
*/
@ -318,14 +372,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Disable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Lock the specified comparator configuration.
@ -336,15 +390,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
/**
* @brief Check whether the specified comparator is locked.
* @param __HANDLE__ COMP handle
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
*/
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)\
== COMP_CSR_LOCK)
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
/**
* @}
@ -412,13 +465,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI Line in event mode.
* @brief Generate a software interrupt on the COMP1 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI Line in event mode.
* @brief Disable the COMP1 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
@ -436,10 +495,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() READ_BIT(EXTI->FPR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Clear the COMP1 EXTI rasing flag.
* @brief Clear the COMP1 EXTI raising flag.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP1)
#define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Clear the COMP1 EXTI falling flag.
@ -447,14 +506,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
*/
#define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Generate a software interrupt on the COMP1 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
#if defined(COMP2)
/**
* @brief Enable the COMP2 EXTI line rising edge trigger.
* @retval None
@ -521,7 +573,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Check whether the COMP2 EXTI line rasing flag is set or not.
* @brief Check whether the COMP2 EXTI line raising flag is set or not.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() READ_BIT(EXTI->RPR1, COMP_EXTI_LINE_COMP2)
@ -534,7 +586,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @brief Clear the the COMP2 EXTI rasing flag.
* @brief Clear the the COMP2 EXTI raising flag.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP2)
@ -550,6 +602,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
#endif /* COMP2 */
/**
* @}
@ -578,10 +631,13 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @{
*/
#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17) /*!< EXTI line 17 connected to COMP1 output */
#if defined(COMP2)
#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */
#endif /* COMP2 */
/**
* @}
*/
/** @defgroup COMP_ExtiLine COMP EXTI Lines
* @{
*/
@ -610,8 +666,12 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
COMP_EXTI_LINE_COMP2)
#if defined(COMP2)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
: COMP_EXTI_LINE_COMP2)
#else
#define COMP_GET_EXTI_LINE(__INSTANCE__) COMP_EXTI_LINE_COMP1
#endif /* COMP2 */
/**
* @}
*/
@ -619,23 +679,32 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
* @{
*/
#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINMODE__) (((__WINMODE__) == COMP_WINDOWMODE_DISABLE) ||\
((__WINMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)||\
((__WINMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON))
#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) )
#define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2) || \
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH))
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER))
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH) )
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
#if defined(COMP_CSR_INPSEL_2)
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO6))
#else
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
#endif /* COMP_CSR_INPSEL_2 */
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\
@ -663,7 +732,6 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
@ -725,7 +793,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp);
/* Callback in interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
@ -736,8 +804,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp);
/**
* @}
*/
@ -759,4 +827,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
#endif
#endif /* STM32U5xx_HAL_COMP_H */

120
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.c
View File

@ -10,6 +10,7 @@
* + Callback functions
* + IRQ handler management
* + Peripheral State functions
*
******************************************************************************
* @attention
*
@ -21,7 +22,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
* @verbatim
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
@ -89,9 +90,9 @@
The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback.
Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback.
Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks:
Function HAL_CORDIC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : Error Callback.
(+) CalculateCpltCallback : Calculate complete Callback.
(+) MspInitCallback : CORDIC MspInit.
@ -99,9 +100,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : Error Callback.
@ -111,11 +112,11 @@
By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
all callbacks are set to the corresponding weak functions:
examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback().
examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when
reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit()
if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
@ -123,7 +124,7 @@
in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit()
using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit()
or HAL_CORDIC_Init() function.
When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
@ -131,6 +132,7 @@
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -157,8 +159,8 @@
/** @defgroup CORDIC_Private_Functions CORDIC Private Functions
* @{
*/
static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff);
static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff);
static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
@ -553,7 +555,7 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H
* contains the CORDIC configuration information.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig)
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -600,12 +602,12 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
int32_t *p_tmp_in_buff = pInBuff;
const int32_t *p_tmp_in_buff = pInBuff;
int32_t *p_tmp_out_buff = pOutBuff;
/* Check parameters setting */
@ -694,12 +696,12 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
int32_t *p_tmp_in_buff = pInBuff;
const int32_t *p_tmp_in_buff = pInBuff;
int32_t *p_tmp_out_buff = pOutBuff;
/* Check parameters setting */
@ -787,10 +789,10 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t
* @param NbCalc Number of CORDIC calculation to process.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc)
{
int32_t *tmp_pInBuff = pInBuff;
const int32_t *tmp_pInBuff = pInBuff;
/* Check parameters setting */
if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
@ -879,14 +881,11 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t
* DMA transfer to and from the Peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t DMADirection)
{
HAL_StatusTypeDef status;
uint32_t sizeinbuff;
uint32_t sizeoutbuff;
uint32_t inputaddr;
uint32_t outputaddr;
/* Check the parameters */
assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
@ -963,42 +962,13 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_
This is necessary as the DMA handles the data at byte-level. */
sizeoutbuff = 4U * sizeoutbuff;
outputaddr = (uint32_t)pOutBuff;
/* Enable the DMA stream managing CORDIC output data read */
if ((hcordic->hdmaOut->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hcordic->hdmaOut->LinkedListQueue != NULL) && (hcordic->hdmaOut->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
sizeoutbuff; /* Set DMA data size */
hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)&hcordic->Instance->RDATA; /* Set DMA source address */
hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
outputaddr; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hcordic->hdmaOut);
}
else
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff);
}
if (status != HAL_OK)
if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff)
!= HAL_OK)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Return error status */
return HAL_ERROR;
}
@ -1030,38 +1000,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_
This is necessary as the DMA handles the data at byte-level. */
sizeinbuff = 4U * sizeinbuff;
inputaddr = (uint32_t)pInBuff;
/* Enable the DMA stream managing CORDIC input data write */
if ((hcordic->hdmaIn->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hcordic->hdmaIn->LinkedListQueue != NULL) && (hcordic->hdmaIn->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
sizeinbuff; /* Set DMA data size */
hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
inputaddr; /* Set DMA source address */
hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hcordic->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hcordic->hdmaIn);
}
else
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff);
}
if (status != HAL_OK)
if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff)
!= HAL_OK)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
@ -1069,6 +1010,7 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_
/* Return error status */
return HAL_ERROR;
}
/* Enable input data Write DMA request */
SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
}
@ -1231,7 +1173,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
* the configuration information for CORDIC module
* @retval HAL state
*/
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic)
{
/* Return CORDIC handle state */
return hcordic->State;
@ -1244,7 +1186,7 @@ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
* @note The returned error is a bit-map combination of possible errors
* @retval Error bit-map
*/
uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic)
{
/* Return CORDIC error code */
return hcordic->ErrorCode;
@ -1269,7 +1211,7 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
* @param ppInBuff Pointer to pointer to input buffer.
* @retval none
*/
static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff)
static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff)
{
/* First write of input data in the Write Data register */
WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
@ -1295,7 +1237,7 @@ static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_
* @param ppOutBuff Pointer to pointer to output buffer.
* @retval none
*/
static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
{
/* First read of output data from the Read Data register */
**ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);

16
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.h
View File

@ -64,7 +64,7 @@ typedef struct
{
CORDIC_TypeDef *Instance; /*!< Register base address */
int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
@ -546,14 +546,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H
*/
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig);
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout);
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout);
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc);
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t DMADirection);
/**
* @}
@ -582,8 +582,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
* @{
*/
/* Peripheral State functions *************************************************/
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic);
uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.c
View File

@ -627,8 +627,8 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const
}
else
{
MPUx->RBAR = 0U;
MPUx->RLAR = 0U;
MPUx->RBAR = 0U;
}
}

6
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.h
View File

@ -203,9 +203,9 @@ typedef struct
/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
* @{
*/
#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */

8
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc.h
View File

@ -119,15 +119,15 @@ typedef struct
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
(8-bit data)
(8-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
half-words (16-bit data)
half-words (16-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
(32-bit data)
(32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
error must occur if InputBufferFormat is not one of the three values listed
above */
above */
} CRC_HandleTypeDef;
/**
* @}

77
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc_ex.c
View File

@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
/* Ensure that the generating polynomial is odd */
if ((Pol & (uint32_t)(0x1U)) == 0U)
{
status = HAL_ERROR;
}
switch (PolyLength)
else
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
}
}
if (status == HAL_OK)
{

103
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp.c
View File

@ -81,7 +81,7 @@
the CRYP peripheral is configured and processes the buffer in input.
At second call, no need to Initialize the CRYP, user have to get current configuration via
HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
new parametres, finally user can start encryption/decryption.
new parameters, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@ -190,7 +190,7 @@
(##) To perform message payload encryption or decryption AES is configured in CTR mode.
(##) For authentication two phases are performed :
- Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
only cleartext payload (not the ciphertext payload) is used and no outpout.
only cleartext payload (not the ciphertext payload) is used and no output.
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
user should consider only part of this 4 words, if Tag length is less than 128 bits
@ -305,6 +305,7 @@
/** @addtogroup CRYP_Private_Defines
* @{
*/
#define CRYP_GENERAL_TIMEOUT 82U
#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey
is 299 clock cycles.*/
@ -435,6 +436,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
{
uint32_t cr_value;
uint32_t tickstart;
/* Check the CRYP handle allocation */
if (hcryp == NULL)
@ -486,6 +488,21 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
}
else
{
/* SAES is initializing, fetching random number from the RNG */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
{
__HAL_CRYP_DISABLE(hcryp);
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
cr_value = (uint32_t)(hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | \
hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection);
/* Set the key size, data type, algorithm, Key selection and key protection */
@ -2314,6 +2331,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
else /*SAES*/
{
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* we should re-write Key, in the case where we change key after first operation*/
@ -4195,6 +4213,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
uint32_t npblb;
uint32_t mode;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
uint32_t headersize_in_bytes;
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@ -4288,7 +4312,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
headersize_in_bytes = hcryp->Init.HeaderSize;
}
if (headersize_in_bytes == 0U) /* Header phase is skipped */
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@ -4370,26 +4403,66 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */
/* Enter header data */
/* Check first whether header length is small enough to enter the full header in one shot */
else if (headersize_in_bytes <= 16U)
{
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
while (loopcounter < 4U)
/* If the header size is a multiple of words */
if ((headersize_in_bytes % 4U) == 0U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
else
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
hcryp->CrypHeaderCount++;
loopcounter++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
{
/* Write the input block in the IN FIFO */
/* Write the first input header block in the Input FIFO,
the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@ -4398,7 +4471,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
}/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
} /* end of if (dokeyivconfig == 1U) */
else /* Key and IV have already been configured,
@ -4473,6 +4546,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}

29
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.c
View File

@ -382,6 +382,7 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput
HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t tickstart;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@ -399,7 +400,25 @@ HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInp
__HAL_CRYP_DISABLE(hcryp);
/* Set the operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KEYSEL, CRYP_KEYMODE_WRAPPED | CRYP_KEYSEL_HW);
/* Wait for Valid KEY flag to set */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_KEYVALID))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
status = CRYPEx_KeyDecrypt(hcryp, Timeout);
}
@ -417,14 +436,14 @@ HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInp
* @}
*/
/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions
* @brief Encrypt/Decrypt Shared key functions.
/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions
* @brief Encrypt and Decrypt Shared key functions.
*
@verbatim
==============================================================================
##### Encrypt/Decrypt Shared key functions #####
##### Encrypt and Decrypt Shared key functions #####
==============================================================================
[..] This section provides API allowing to Encrypt/Decrypt Shared key
[..] This section provides API allowing to Encrypt and Decrypt Shared key
@endverbatim
* @{

2
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.h
View File

@ -68,7 +68,7 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput
* @}
*/
/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions
/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions
* @{
*/
HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID,

131
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.c
View File

@ -11,6 +11,17 @@
* + Peripheral State and Errors functions
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### DAC Peripheral features #####
@ -229,7 +240,7 @@
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
Use Functions HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@ -244,8 +255,8 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
@ -259,12 +270,12 @@
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@ -272,12 +283,12 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
or @ref HAL_DAC_Init function.
using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
or HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@ -293,16 +304,6 @@
(@) You can refer to the DAC HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -532,6 +533,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
__IO uint32_t wait_loop_index;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@ -544,7 +546,14 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */
/* bits register capacity and handle low frequency. */
wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
if (Channel == DAC_CHANNEL_1)
{
@ -594,8 +603,6 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@ -621,13 +628,14 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg;
uint32_t LengthInBytes;
DMA_NodeConfTypeDef node_conf;
__IO uint32_t wait_loop_index;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@ -703,8 +711,6 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
}
}
/* Enable the DMA channel */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
@ -866,7 +872,15 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
else
{
@ -897,8 +911,6 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Disable the DMA channel */
@ -939,10 +951,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
uint32_t itsource = hdac->Instance->CR;
uint32_t itflag = hdac->Instance->SR;
if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
{
/* Check underrun flag of DAC channel 1 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@ -954,7 +969,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@ -966,10 +981,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
}
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
{
/* Check underrun flag of DAC channel 2 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@ -981,7 +996,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
/* Disable the selected DAC channel2 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@ -1135,22 +1150,25 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
uint32_t result;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Returns the DAC channel data output register value */
if (Channel == DAC_CHANNEL_1)
{
return hdac->Instance->DOR1;
result = hdac->Instance->DOR1;
}
else
{
return hdac->Instance->DOR2;
result = hdac->Instance->DOR2;
}
/* Returns the DAC channel data output register value */
return result;
}
/**
@ -1177,8 +1195,10 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpreg1;
uint32_t tmpreg2;
uint32_t tickstart;
@ -1240,7 +1260,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
}
}
}
HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
@ -1265,7 +1284,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
}
}
}
HAL_Delay(1U);
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
@ -1303,6 +1321,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
{
connectOnChip = 0x00000000UL;
@ -1383,7 +1403,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
return status;
}
/**
@ -1412,7 +1432,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
* the configuration information for the specified DAC.
* @retval HAL state
*/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
{
/* Return DAC handle state */
return hdac->State;
@ -1425,7 +1445,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
@ -1448,7 +1468,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used instead of the weak (overridden) predefined callback
* @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@ -1479,9 +1501,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
@ -1552,14 +1571,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (surcharged) predefined callback
* DAC Callback is redirected to the weak (overridden) predefined callback
* @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@ -1580,9 +1599,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdac);
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
@ -1667,8 +1683,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@ -1754,7 +1768,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
#endif /* DAC1 */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/

56
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.h
View File

@ -122,7 +122,9 @@ typedef struct
This parameter can be a value of @ref DAC_HighFrequency */
uint32_t DAC_AutonomousMode; /*!< Specifies whether the autonomous mode state
This parameter can be a value of @ref DACx_Autonomous_mode */
This parameter can be a value of @ref DAC_AutonomousMode
Note: HAL_DACEx_SetConfigAutonomousMode() API allows to select and update
the autonomous mode state afterwards */
FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
This parameter can be ENABLE or DISABLE */
@ -139,7 +141,7 @@ typedef struct
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
@ -218,8 +220,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 CH1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
/**
@ -315,6 +317,27 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @defgroup DAC_AutonomousMode DAC Autonomous Mode
* @brief DAC Autonomous mode
* @{
*/
#define DAC_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
#define DAC_AUTONOMOUS_MODE_ENABLE DAC_AUTOCR_AUTOMODE /*!< Autonomous mode enable */
/**
* @}
*/
/** @defgroup DAC_Trigger_Stop_mode DAC Trigger Stop Mode
* @brief DAC Trigger stop mode
* @{
*/
#define DAC_TRIGGER_STOP_LPTIM1_CH1 DAC_TRIGGER_LPTIM1_CH1 /*!< LPTIM1 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_LPTIM3_CH1 DAC_TRIGGER_LPTIM3_CH1 /*!< LPTIM3 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */
/**
* @}
*/
/** @defgroup DAC_HighFrequency DAC high frequency interface mode
* @{
*/
@ -331,6 +354,20 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @}
*/
/* Delay for DAC channel voltage settling time from DAC channel startup */
/* (transition from disable to enable). */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
@ -495,7 +532,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
@ -521,8 +558,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
@ -531,8 +569,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
/**
* @}

104
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.c
View File

@ -7,12 +7,22 @@
* functionalities of the DAC peripheral.
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Dual mode IO operation ***
==============================
[..]
@ -34,7 +44,6 @@
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
*** Signal generation operation ***
===================================
[..]
@ -55,16 +64,6 @@
(+) Use HAL_DACx_ClearConfigAutonomousMode() to clear the configuration of the autonomous mode
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -87,6 +86,16 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Delay for DAC minimum trimming time. */
/* Note: minimum time needed between two calibration steps */
/* The delay below is specified under conditions: */
/* - DAC channel output buffer enabled */
/* Literal set to maximum value (refer to device datasheet, */
/* electrical characteristics, parameter "tTRIM"). */
/* Unit: us */
#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -125,6 +134,7 @@
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
{
uint32_t tmp_swtrig = 0UL;
__IO uint32_t wait_loop_index;
/* Process locked */
@ -137,7 +147,15 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
@ -173,8 +191,6 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@ -200,11 +216,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment)
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
const uint32_t *pData, uint32_t Length, uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg;
uint32_t tmpreg = 0UL;
__IO uint32_t wait_loop_index;
uint32_t LengthInBytes;
/* Check the parameters */
@ -256,10 +273,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Chan
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
break;
default: /* case DAC_ALIGN_8B_R */
case DAC_ALIGN_8B_R:
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
break;
default:
break;
}
/* Enable the DMA channel */
@ -347,7 +366,15 @@ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Chan
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
else
{
@ -379,8 +406,6 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Disable the DMA channel */
@ -650,6 +675,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
__IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
__IO uint32_t wait_loop_index;
/* store/restore channel configuration structure purpose */
uint32_t oldmodeconfiguration;
@ -710,9 +736,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1);
/* Wait minimum time needed between two calibration steps (OTRIM) */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
/* 32 bits register capacity and handle low frequency. */
wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
{
@ -732,9 +764,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1U);
/* Wait minimum time needed between two calibration steps (OTRIM) */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
/* 32 bits register capacity and handle low frequency. */
wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
@ -815,7 +853,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel
* @retval Trimming value : range: 0->31
*
*/
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(Channel));
@ -849,7 +887,7 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0UL;
@ -873,7 +911,8 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
* @param sConfig pointer to Autonomous mode structure parameters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig)
HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac,
const DAC_AutonomousModeConfTypeDef *sConfig)
{
assert_param(IS_DAC_AUTONOMOUS(sConfig->AutonomousModeState));
@ -911,7 +950,8 @@ HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC
* @param sConfig pointer to Autonomous mode structure parameters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig)
HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(const DAC_HandleTypeDef *hdac,
DAC_AutonomousModeConfTypeDef *sConfig)
{
/* Fill Autonomous structure parameter */
sConfig->AutonomousModeState = READ_BIT(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE);

44
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.h
View File

@ -45,7 +45,7 @@ extern "C" {
typedef struct
{
uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.
This parameter can be a value of @ref DACx_Autonomous_mode */
This parameter can be a value of @ref DAC_AutonomousMode */
} DAC_AutonomousModeConfTypeDef;
@ -91,26 +91,6 @@ typedef struct
* @}
*/
/** @defgroup DACx_Autonomous_mode DACx Autonomous Mode
* @brief DAC Autonomous mode
* @{
*/
#define DAC_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
#define DAC_AUTONOMOUS_MODE_ENABLE DAC_AUTOCR_AUTOMODE /*!< Autonomous mode enable */
/**
* @}
*/
/** @defgroup DACx_Trigger_Stop_mode DACx Trigger Stop Mode
* @brief DAC Trigger stop mode
* @{
*/
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_LPTIM1_OUT /*!< LPTIM1 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_LPTIM3_OUT /*!< LPTIM3 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */
/**
* @}
*/
/**
* @}
@ -133,11 +113,11 @@ typedef struct
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \
((TRIGGER) == DAC_TRIGGER_LPTIM3_CH1) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_OUT) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_OUT) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_CH1) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_CH1) || \
((TRIGGER) == DAC_TRIGGER_STOP_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
@ -212,11 +192,11 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
const uint32_t *pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
@ -236,11 +216,13 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
/* Autonomous Mode Control functions **********************************************/
HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac,
const DAC_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(const DAC_HandleTypeDef *hdac,
DAC_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_DACEx_ClearConfigAutonomousMode(DAC_HandleTypeDef *hdac);
/**

1148
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.c
View File

File diff suppressed because it is too large Load Diff

74
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.h
View File

@ -31,6 +31,8 @@ extern "C" {
* @{
*/
#if defined (DCACHE1) || defined (DCACHE2)
/** @addtogroup DCACHE
* @{
*/
@ -45,7 +47,8 @@ extern "C" {
*/
typedef struct
{
uint32_t ReadBurstType; /*!< Burst type to be applied for Data Cache */
uint32_t ReadBurstType; /*!< Burst type to be applied for Data Cache
This parameter can be a value of @ref DCACHE_Read_Burst_Type*/
} DCACHE_InitTypeDef;
/**
@ -53,12 +56,11 @@ typedef struct
*/
typedef enum
{
HAL_DCACHE_STATE_RESET = 0x00U, /* !< DCACHE not yet initialized or disabled */
HAL_DCACHE_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */
HAL_DCACHE_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */
HAL_DCACHE_STATE_TIMEOUT = 0x05U, /* !< Timeout state */
HAL_DCACHE_STATE_ERROR = 0x06U, /* !< DCACHE state error */
HAL_DCACHE_STATE_RESET = 0x00U, /*!< DCACHE not yet initialized or disabled */
HAL_DCACHE_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
HAL_DCACHE_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_DCACHE_STATE_TIMEOUT = 0x05U, /*!< Timeout state */
HAL_DCACHE_STATE_ERROR = 0x06U, /*!< DCACHE state error */
} HAL_DCACHE_StateTypeDef;
/** @defgroup DCACHE_Configuration_Structure_definition DCACHE Configuration Structure definition
@ -81,7 +83,6 @@ typedef struct __DCACHE_HandleTypeDef
__IO HAL_DCACHE_StateTypeDef State;
__IO uint32_t ErrorCode;
} DCACHE_HandleTypeDef;
/**
@ -103,7 +104,6 @@ typedef enum
HAL_DCACHE_MSPINIT_CB_ID = 0x05U, /*!< DCACHE Msp Init callback ID */
HAL_DCACHE_MSPDEINIT_CB_ID = 0x06U /*!< DCACHE Msp DeInit callback ID */
} HAL_DCACHE_CallbackIDTypeDef;
/**
@ -122,9 +122,12 @@ typedef enum
/** @defgroup DCACHE_Error_Code DCACHE Error Code
* @{
*/
#define HAL_DCACHE_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DCACHE_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_DCACHE_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */
#define HAL_DCACHE_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DCACHE_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_DCACHE_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */
#define HAL_DCACHE_ERROR_EVICTION_CLEAN 0x00000040U /*!< Eviction or clean operation write-back error */
#define HAL_DCACHE_ERROR_INVALID_OPERATION 0x00000080U /*!< Invalid operation */
/**
* @}
*/
@ -246,18 +249,31 @@ typedef enum
/* Exported functions -------------------------------------------------------*/
/** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions
* @brief DCACHE Exported functions
* @{
*/
/** @defgroup DCACHE_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @brief Initialization and De-Initialization Functions
* @{
*/
/* Initialization and de-initialization functions ***/
HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache);
HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache);
void HAL_DCACHE_MspInit(DCACHE_HandleTypeDef *hdcache);
void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache);
/**
* @}
*/
/** @defgroup DCACHE_Exported_Functions_Group2 I/O Operation Functions
* @brief I/O Operation Functions
* @{
*/
/* Peripheral Control functions ***/
HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache);
HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache);
HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBrustType);
uint32_t HAL_DCACHE_IsEnabled(const DCACHE_HandleTypeDef *hdcache);
HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBurstType);
/*** Cache maintenance in blocking mode (Polling) ***/
HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache);
@ -290,30 +306,44 @@ HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL
HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID);
/*** Performance instruction cache monitoring functions ***/
uint32_t HAL_DCACHE_Monitor_GetReadHitValue(DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_Monitor_GetReadMissValue(DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_Monitor_GetReadHitValue(const DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_Monitor_GetReadMissValue(const DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_HandleTypeDef *hdcache);
HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
/* Peripheral State functions ***************************************************/
HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_GetError(DCACHE_HandleTypeDef *hdcache);
/**
* @}
*/
/** @defgroup DCACHE_Exported_Functions_Group3 State and Error Functions
* @brief State and Error Functions
* @{
*/
HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(const DCACHE_HandleTypeDef *hdcache);
uint32_t HAL_DCACHE_GetError(const DCACHE_HandleTypeDef *hdcache);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
#endif /* DCACHE1 || DCACHE2 */
/**
* @}
*/

38
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.c
View File

@ -73,9 +73,9 @@
The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback.
Use functions HAL_DCMI_RegisterCallback() to register a user callback.
Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks:
Function HAL_DCMI_RegisterCallback() allows to register following callbacks:
(+) FrameEventCallback : callback for DCMI Frame Event.
(+) VsyncEventCallback : callback for DCMI Vsync Event.
(+) LineEventCallback : callback for DCMI Line Event.
@ -85,9 +85,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default
Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
This function allows to reset following callbacks:
(+) FrameEventCallback : callback for DCMI Frame Event.
@ -97,13 +97,13 @@
(+) MspInitCallback : callback for DCMI MspInit.
(+) MspDeInitCallback : callback for DCMI MspDeInit.
By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback().
examples FrameEventCallback(), HAL_DCMI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init
and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit
reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init
and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
@ -111,8 +111,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit
or @ref HAL_DCMI_Init function.
using HAL_DCMI_RegisterCallback before calling HAL_DCMI_DeInit
or HAL_DCMI_Init function.
When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@ -1049,7 +1049,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn
* the configuration information for DCMI.
* @retval HAL state
*/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->State;
}
@ -1060,7 +1060,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
* the configuration information for DCMI.
* @retval DCMI Error Code
*/
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->ErrorCode;
}
@ -1163,7 +1163,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_
/**
* @brief Unregister a DCMI Callback
* DCMI callabck is redirected to the weak predefined callback
* DCMI callback is redirected to the weak predefined callback
* @param hdcmi DCMI handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@ -1250,6 +1250,11 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
@ -1355,10 +1360,6 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
}
/**
* @}
*/
/**
* @}
*/
@ -1371,4 +1372,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
/**
* @}
*/

5
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.h
View File

@ -584,8 +584,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_
* @{
*/
/* Peripheral State functions *************************************************/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi);
/**
* @}
*/
@ -696,4 +696,3 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
#endif
#endif /* STM32U5xx_HAL_DCMI_H */

4
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_def.h
View File

@ -70,7 +70,9 @@ typedef enum
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#define UNUSED(x) ((void)(x))
#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.

33
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c
View File

@ -884,9 +884,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
{
DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag);
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* Global Interrupt Flag management *********************************************************************************/
if (IS_DMA_GLOBAL_ACTIVE_FLAG(p_dma_instance, global_it_flag) == 0U)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U))
#else
if (global_active_flag_ns == 0U)
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
{
return; /* the global interrupt flag for the current channel is down , nothing to do */
}
@ -999,6 +1007,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
/* Clear remaining data size to ensure loading linked-list from memory next start */
hdma->Instance->CBR1 = 0U;
}
/* Process Unlocked */
@ -1113,6 +1124,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
/**
* @brief Register callback according to specified ID.
* @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
* to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration.
@ -1131,9 +1144,6 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
@ -1177,6 +1187,8 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
default:
{
/* Update error status */
status = HAL_ERROR;
break;
}
}
@ -1187,14 +1199,13 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @brief Unregister callback according to specified ID.
* @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
* to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum.
@ -1211,9 +1222,6 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
@ -1280,9 +1288,6 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
@ -1542,7 +1547,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
uint32_t channel_idx;
/* Check the DMA peripheral handle and lock state parameters */
if (hdma == NULL)
if ((hdma == NULL) || (pLockState == NULL))
{
return HAL_ERROR;
}

55
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.h
View File

@ -277,8 +277,10 @@ typedef struct __DMA_HandleTypeDef
#define GPDMA1_REQUEST_I2C4_EVC (23U) /*!< GPDMA1 HW request is I2C4_EVC */
#define GPDMA1_REQUEST_USART1_RX (24U) /*!< GPDMA1 HW request is USART1_RX */
#define GPDMA1_REQUEST_USART1_TX (25U) /*!< GPDMA1 HW request is USART1_TX */
#if defined (USART2)
#define GPDMA1_REQUEST_USART2_RX (26U) /*!< GPDMA1 HW request is USART2_RX */
#define GPDMA1_REQUEST_USART2_TX (27U) /*!< GPDMA1 HW request is USART2_TX */
#endif /* USART2 */
#define GPDMA1_REQUEST_USART3_RX (28U) /*!< GPDMA1 HW request is USART3_RX */
#define GPDMA1_REQUEST_USART3_TX (29U) /*!< GPDMA1 HW request is USART3_TX */
#define GPDMA1_REQUEST_UART4_RX (30U) /*!< GPDMA1 HW request is UART4_RX */
@ -289,10 +291,14 @@ typedef struct __DMA_HandleTypeDef
#define GPDMA1_REQUEST_LPUART1_TX (35U) /*!< GPDMA1 HW request is LPUART1_TX */
#define GPDMA1_REQUEST_SAI1_A (36U) /*!< GPDMA1 HW request is SAI1_A */
#define GPDMA1_REQUEST_SAI1_B (37U) /*!< GPDMA1 HW request is SAI1_B */
#if defined (SAI2)
#define GPDMA1_REQUEST_SAI2_A (38U) /*!< GPDMA1 HW request is SAI2_A */
#define GPDMA1_REQUEST_SAI2_B (39U) /*!< GPDMA1 HW request is SAI2_B */
#endif /* SAI2 */
#define GPDMA1_REQUEST_OCTOSPI1 (40U) /*!< GPDMA1 HW request is OCTOSPI1 */
#if defined (OCTOSPI2)
#define GPDMA1_REQUEST_OCTOSPI2 (41U) /*!< GPDMA1 HW request is OCTOSPI2 */
#endif /* OCTOSPI2 */
#define GPDMA1_REQUEST_TIM1_CH1 (42U) /*!< GPDMA1 HW request is TIM1_CH1 */
#define GPDMA1_REQUEST_TIM1_CH2 (43U) /*!< GPDMA1 HW request is TIM1_CH2 */
#define GPDMA1_REQUEST_TIM1_CH3 (44U) /*!< GPDMA1 HW request is TIM1_CH3 */
@ -337,12 +343,14 @@ typedef struct __DMA_HandleTypeDef
#define GPDMA1_REQUEST_TIM16_UP (83U) /*!< GPDMA1 HW request is TIM16_UP */
#define GPDMA1_REQUEST_TIM17_CH1 (84U) /*!< GPDMA1 HW request is TIM17_CH1 */
#define GPDMA1_REQUEST_TIM17_UP (85U) /*!< GPDMA1 HW request is TIM17_UP */
#define GPDMA1_REQUEST_DCMI (86U) /*!< GPDMA1 HW request is DCMI */
#define GPDMA1_REQUEST_DCMI_PSSI (86U) /*!< GPDMA1 HW request is DCMI_PSSI */
#define GPDMA1_REQUEST_AES_IN (87U) /*!< GPDMA1 HW request is AES_IN */
#define GPDMA1_REQUEST_AES_OUT (88U) /*!< GPDMA1 HW request is AES_OUT */
#define GPDMA1_REQUEST_HASH_IN (89U) /*!< GPDMA1 HW request is HASH_IN */
#if defined (UCPD1)
#define GPDMA1_REQUEST_UCPD1_TX (90U) /*!< GPDMA1 HW request is UCPD1_TX */
#define GPDMA1_REQUEST_UCPD1_RX (91U) /*!< GPDMA1 HW request is UCPD1_RX */
#endif /* UCPD1 */
#define GPDMA1_REQUEST_MDF1_FLT0 (92U) /*!< GPDMA1 HW request is MDF1_FLT0 */
#define GPDMA1_REQUEST_MDF1_FLT1 (93U) /*!< GPDMA1 HW request is MDF1_FLT1 */
#define GPDMA1_REQUEST_MDF1_FLT2 (94U) /*!< GPDMA1 HW request is MDF1_FLT2 */
@ -365,6 +373,26 @@ typedef struct __DMA_HandleTypeDef
#define GPDMA1_REQUEST_LPTIM3_IC1 (111U) /*!< GPDMA1 HW request is LPTIM3_IC1 */
#define GPDMA1_REQUEST_LPTIM3_IC2 (112U) /*!< GPDMA1 HW request is LPTIM3_IC2 */
#define GPDMA1_REQUEST_LPTIM3_UE (113U) /*!< GPDMA1 HW request is LPTIM3_UE */
#if defined (HSPI1_BASE)
#define GPDMA1_REQUEST_HSPI1 (114U) /*!< GPDMA1 HW request is HSPI1 */
#endif /* defined (HSPI1_BASE) */
#if defined (I2C5)
#define GPDMA1_REQUEST_I2C5_RX (115U) /*!< GPDMA1 HW request is I2C5_RX */
#define GPDMA1_REQUEST_I2C5_TX (116U) /*!< GPDMA1 HW request is I2C5_TX */
#define GPDMA1_REQUEST_I2C5_EVC (117U) /*!< GPDMA1 HW request is I2C5_EVC */
#endif /* defined (I2C5) */
#if defined (I2C6)
#define GPDMA1_REQUEST_I2C6_RX (118U) /*!< GPDMA1 HW request is I2C6_RX */
#define GPDMA1_REQUEST_I2C6_TX (119U) /*!< GPDMA1 HW request is I2C6_TX */
#define GPDMA1_REQUEST_I2C6_EVC (120U) /*!< GPDMA1 HW request is I2C6_EVC */
#endif /* defined (I2C6) */
#if defined (USART6)
#define GPDMA1_REQUEST_USART6_RX (121U) /*!< GPDMA1 HW request is USART6_RX */
#define GPDMA1_REQUEST_USART6_TX (122U) /*!< GPDMA1 HW request is USART6_TX */
#endif /* defined (USART6) */
#if defined (ADC2)
#define GPDMA1_REQUEST_ADC2 (123U) /*!< GPDMA1 HW request is ADC2 */
#endif /* defined (ADC2) */
/* LPDMA1 requests */
#define LPDMA1_REQUEST_LPUART1_RX (0U) /*!< LPDMA1 HW request is LPUART1_RX */
@ -759,7 +787,8 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */
#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */
#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */
#define DMA_CHANNEL_ATTR_MASK (0xFFFFFFF0U) /* DMA channel attributes mask */
#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */
#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */
#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
/**
@ -821,9 +850,11 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
(((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
#define IS_DMA_REQUEST(REQUEST) \
(((REQUEST) == DMA_REQUEST_SW) || \
((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE))
#if defined (GPDMA1_REQUEST_ADC2)
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_ADC2))
#else
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE))
#endif /* GPDMA1_REQUEST_ADC2 */
#define IS_DMA_BLOCK_HW_REQUEST(MODE) \
(((MODE) == DMA_BREQ_SINGLE_BURST) || \
@ -839,9 +870,10 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
(((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((((~((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) >> 4U) & ((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) == 0U) && \
((ATTRIBUTE) != 0U))
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \
(((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \
(((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U)))
#else
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
@ -849,12 +881,11 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \
(((INSTANCE)->SMISR & (GLOBAL_FLAG)))
#else
#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
(((INSTANCE)->MISR & (GLOBAL_FLAG)))
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \
(((INSTANCE)->MISR & (GLOBAL_FLAG)))
/**
* @}
*/

19
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.c
View File

@ -1788,6 +1788,13 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
#if defined(DMA2D_FGPFCCR_CSS)
if ((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR))
{
assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling));
}
#endif /* DMA2D_FGPFCCR_CSS */
/* Process locked */
__HAL_LOCK(hdma2d);
@ -1831,6 +1838,13 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
else
{
#if defined(DMA2D_FGPFCCR_CSS)
if (pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
{
regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos);
regMask |= DMA2D_FGPFCCR_CSS;
}
#endif /* DMA2D_FGPFCCR_CSS */
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
@ -2052,7 +2066,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
* the configuration information for the DMA2D.
* @retval HAL state
*/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->State;
}
@ -2063,7 +2077,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
* the configuration information for DMA2D.
* @retval DMA2D Error Code
*/
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->ErrorCode;
}
@ -2173,4 +2187,3 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
*/
#endif /* DMA2D */
#endif /* HAL_DMA2D_MODULE_ENABLED */

44
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.h
View File

@ -121,6 +121,10 @@ typedef struct
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
This parameter can be one value of @ref DMA2D_RB_Swap. */
#if defined(DMA2D_FGPFCCR_CSS)
uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
#endif /* DMA2D_FGPFCCR_CSS */
} DMA2D_LayerCfgTypeDef;
@ -240,6 +244,9 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe
#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
#if defined(DMA2D_FGPFCCR_CSS)
#define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */
#endif /* DMA2D_FGPFCCR_CSS */
/**
* @}
*/
@ -293,6 +300,17 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe
* @}
*/
#if defined(DMA2D_FGPFCCR_CSS)
/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
* @{
*/
#define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */
#define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */
#define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */
/**
* @}
*/
#endif /* DMA2D_FGPFCCR_CSS */
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{
@ -538,8 +556,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
*/
/* Peripheral State functions ***************************************************/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
/**
* @}
@ -640,6 +658,20 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#if defined(DMA2D_FGPFCCR_CSS)
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || \
((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || \
((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || \
((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4) || \
((INPUT_CM) == DMA2D_INPUT_YCBCR))
#else
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || \
@ -651,6 +683,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
((INPUT_CM) == DMA2D_INPUT_L4) || \
((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
#endif /* DMA2D_FGPFCCR_CSS */
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
@ -668,6 +701,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
((BYTES_SWAP) == DMA2D_BYTES_SWAP))
#if defined(DMA2D_FGPFCCR_CSS)
#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \
((CSS) == DMA2D_CSS_422) || \
((CSS) == DMA2D_CSS_420))
#endif /* DMA2D_FGPFCCR_CSS */
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
@ -697,5 +735,3 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#endif
#endif /* STM32U5xx_HAL_DMA2D_H */

107
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.c
View File

@ -162,6 +162,8 @@
in memory.
Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the
link access port can access to the specified SRAM.
(++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte
addressable space.
(+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node.
This API can be used when need to change few parameter to build new node.
@ -376,7 +378,7 @@
In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to
FIFO capabilities titled data handling.
(++) Padding pattern
Padding selected patter (zero padding or sign extension) when the source data width is smaller than
Padding selected pattern (zero padding or sign extension) when the source data width is smaller than
the destination data width at single level.
Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000)
Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA)
@ -536,12 +538,10 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode);
static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3,
DMA_NodeTypeDef const *const pNode4);
DMA_NodeTypeDef const *const pNode3);
static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3,
DMA_NodeTypeDef const *const pNode4);
DMA_NodeTypeDef const *const pNode3);
static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
uint32_t *const cllr_mask,
uint32_t *const cllr_offset);
@ -743,9 +743,10 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
hdma->XferAbortCallback = NULL;
hdma->XferSuspendCallback = NULL;
/* Update the queue state and error code */
if(hdma->LinkedListQueue != NULL)
/* Check the linked-list queue */
if (hdma->LinkedListQueue != NULL)
{
/* Update the queue state and error code */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
@ -781,7 +782,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
*
@verbatim
======================================================================================================================
############### Linked-List I/O Operation Functions ###############
############### Linked-List IO Operation Functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
@ -1031,6 +1032,8 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma)
* specified DMA linked-list Node.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte
* addressable space.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
@ -1155,7 +1158,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -1164,7 +1167,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -1283,7 +1286,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -1292,7 +1295,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -1363,7 +1366,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -1372,7 +1375,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -1793,7 +1796,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -1802,7 +1805,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -1955,7 +1958,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -1964,7 +1967,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -2235,7 +2238,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -2247,7 +2250,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -2433,7 +2436,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -2445,7 +2448,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -2570,7 +2573,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
@ -2582,7 +2585,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U)
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
@ -3495,7 +3498,7 @@ HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma)
hdma->Instance->CCR |= DMA_CCR_SUSP;
/* Check if the DMA channel is suspended */
while ((hdma->Instance->CSR & DMA_CSR_SUSPF) != 0U)
while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
{
/* Check for the timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
@ -3511,10 +3514,10 @@ HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma)
return HAL_ERROR;
}
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_SUSPEND;
}
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_SUSPEND;
}
return HAL_OK;
@ -3650,7 +3653,13 @@ static void DMA_List_Init(DMA_HandleTypeDef const *const hdma)
uint32_t tmpreg;
/* Prepare DMA Channel Control Register (CCR) value */
tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode | hdma->InitLinkedList.LinkAllocatedPort;
tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode;
/* Check DMA channel instance */
if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
{
tmpreg |= hdma->InitLinkedList.LinkAllocatedPort;
}
/* Write DMA Channel Control Register (CCR) */
MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
@ -4070,15 +4079,13 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
* @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
* @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
* @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
* @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations.
* @retval Return 0 when nodes addresses are compatible, 1 otherwise.
*/
static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3,
DMA_NodeTypeDef const *const pNode4)
DMA_NodeTypeDef const *const pNode3)
{
uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3 | (uint32_t)pNode4) & DMA_CLBAR_LBA);
uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA);
uint32_t ref = 0U;
/* Check node 1 address */
@ -4096,11 +4103,6 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN
{
ref = (uint32_t)pNode3;
}
/* Check node 4 address */
else if ((uint32_t)pNode4 != 0U)
{
ref = (uint32_t)pNode4;
}
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
@ -4120,13 +4122,11 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN
* @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
* @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
* @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
* @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations.
* @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible.
*/
static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3,
DMA_NodeTypeDef const *const pNode4)
DMA_NodeTypeDef const *const pNode3)
{
uint32_t ref = 0U;
@ -4145,26 +4145,11 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
{
ref = pNode3->NodeInfo & NODE_TYPE_MASK;
}
/* Check node 4 parameter */
else if (pNode4 != NULL)
{
ref = pNode4->NodeInfo & NODE_TYPE_MASK;
}
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
}
/* Check node 1 parameter */
if (pNode1 != NULL)
{
/* Check node type compatibility */
if (ref != (pNode1->NodeInfo & NODE_TYPE_MASK))
{
return 1U;
}
}
/* Check node 2 parameter */
if (pNode2 != NULL)
{
@ -4185,16 +4170,6 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
}
}
/* Check node 4 parameter */
if (pNode4 != NULL)
{
/* Check node type compatibility */
if (ref != (pNode4->NodeInfo & NODE_TYPE_MASK))
{
return 4U;
}
}
return 0U;
}

34
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.h
View File

@ -327,6 +327,33 @@ typedef struct __DMA_QListTypeDef
#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF (41U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */
#define GPDMA1_TRIGGER_TIM2_TRGO (42U) /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
#define GPDMA1_TRIGGER_TIM15_TRGO (43U) /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
#if defined (TIM3_TRGO_TRIGGER_SUPPORT)
#define GPDMA1_TRIGGER_TIM3_TRGO (44U) /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
#endif /* defined (TRIGGER_TIM3_TRGO_SUPPORT) */
#if defined (TIM4_TRGO_TRIGGER_SUPPORT)
#define GPDMA1_TRIGGER_TIM4_TRGO (45U) /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
#endif /* defined (TRIGGER_TIM4_TRGO_SUPPORT) */
#if defined (TIM5_TRGO_TRIGGER_SUPPORT)
#define GPDMA1_TRIGGER_TIM5_TRGO (46U) /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
#endif /* defined (TRIGGER_TIM5_TRGO_SUPPORT) */
#if defined (LTDC)
#define GPDMA1_TRIGGER_LTDC_LI (47U) /*!< GPDMA1 HW Trigger signal is LTDC_LI */
#endif /* defined (LTDC) */
#if defined (DSI)
#define GPDMA1_TRIGGER_DSI_TE (48U) /*!< GPDMA1 HW Trigger signal is DSI_TE */
#define GPDMA1_TRIGGER_DSI_ER (49U) /*!< GPDMA1 HW Trigger signal is DSI_ER */
#endif /* defined (DSI) */
#if defined (DMA2D_TRIGGER_SUPPORT)
#define GPDMA1_TRIGGER_DMA2D_TC (50U) /*!< GPDMA1 HW Trigger signal is DMA2D_TC */
#define GPDMA1_TRIGGER_DMA2D_CTC (51U) /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */
#define GPDMA1_TRIGGER_DMA2D_TW (52U) /*!< GPDMA1 HW Trigger signal is DMA2D_TW */
#endif /* defined (DMA2D_TRIGGER_SUPPORT) */
#if defined (GPU2D)
#define GPDMA1_TRIGGER_GPU2D_FLAG0 (53U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */
#define GPDMA1_TRIGGER_GPU2D_FLAG1 (54U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */
#define GPDMA1_TRIGGER_GPU2D_FLAG2 (55U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */
#define GPDMA1_TRIGGER_GPU2D_FLAG3 (56U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */
#endif /* defined (GPU2D) */
#define GPDMA1_TRIGGER_ADC4_AWD1 (57U) /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */
#define GPDMA1_TRIGGER_ADC1_AWD1 (58U) /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */
@ -418,8 +445,8 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List I/O Operation Functions
* @brief Linked-List I/O Operation Functions
/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
* @brief Linked-List IO Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
@ -645,8 +672,7 @@ typedef struct
((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
((POLARITY) == DMA_TRIG_POLARITY_FALLING))
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \
((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1)
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1)
#define IS_DMA_NODE_TYPE(TYPE) \
(((TYPE) == DMA_LPDMA_LINEAR_NODE) || \

2864
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c Normal file
View File

File diff suppressed because it is too large Load Diff

1445
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.h Normal file
View File

File diff suppressed because it is too large Load Diff

35
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c
View File

@ -259,7 +259,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
const __IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
@ -351,7 +351,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
@ -548,9 +548,9 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
* @arg @ref EXTI_TRIGGER_FALLING
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
const __IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
@ -592,7 +592,7 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
* @arg @ref EXTI_TRIGGER_FALLING
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
@ -628,7 +628,7 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
@ -754,7 +754,7 @@ void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes)
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes)
{
__IO uint32_t *regaddr;
const __IO uint32_t *regaddr;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
@ -807,6 +807,25 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *
return HAL_OK;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Lock the secure and privilege configuration registers.
* @retval None
*/
void HAL_EXTI_LockAttributes(void)
{
SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
}
/**
* @brief Return the secure and privilege configuration registers LOCK status
* @retval 1 if the secure and privilege configuration registers have been locked else 0.
*/
uint32_t HAL_EXTI_GetLockAttributes(void)
{
return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @}

66
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.h
View File

@ -104,12 +104,21 @@ typedef struct
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U)
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U)
#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U)
#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U)
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11U)
#if defined(EXTI_IMR1_IM18)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12U)
#endif /* EXTI_IMR1_IM18 */
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13U)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14U)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15U)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16U)
#define EXTI_LINE_23 (EXTI_CONFIG | EXTI_REG1 | 0x17U)
#if defined(EXTI_IMR1_IM24)
#define EXTI_LINE_24 (EXTI_CONFIG | EXTI_REG1 | 0x18U)
#endif /* EXTI_IMR1_IM24 */
#if defined(EXTI_IMR1_IM25)
#define EXTI_LINE_25 (EXTI_CONFIG | EXTI_REG1 | 0x19U)
#endif /* EXTI_IMR1_IM25 */
/**
* @}
*/
@ -144,10 +153,18 @@ typedef struct
#define EXTI_GPIOC 0x00000002U
#define EXTI_GPIOD 0x00000003U
#define EXTI_GPIOE 0x00000004U
#if defined(GPIOF)
#define EXTI_GPIOF 0x00000005U
#endif /* GPIOF */
#define EXTI_GPIOG 0x00000006U
#define EXTI_GPIOH 0x00000007U
#if defined(GPIOI)
#define EXTI_GPIOI 0x00000008U
#endif /* GPIOI */
#if defined(GPIOJ)
#define EXTI_GPIOJ 0x00000009U
#endif /* GPIOJ */
/**
* @}
*/
@ -213,7 +230,11 @@ typedef struct
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 23U
#if defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25)
#define EXTI_LINE_NB 26U
#else
#define EXTI_LINE_NB 24U
#endif /* defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) */
/**
* @brief EXTI Mask for secure & privilege attributes
@ -246,6 +267,18 @@ typedef struct
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#if defined(GPIOJ)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI) || \
((__PORT__) == EXTI_GPIOJ))
#elif defined(GPIOF) && defined (GPIOI)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
@ -255,6 +288,15 @@ typedef struct
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#endif /* GPIOJ */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
@ -294,7 +336,7 @@ typedef struct
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
@ -307,10 +349,10 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti);
/**
* @}
@ -323,6 +365,10 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/* EXTI line attributes management functions **********************************/
void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes);
HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
void HAL_EXTI_LockAttributes(void);
uint32_t HAL_EXTI_GetLockAttributes(void);
#endif /* __ARM_FEATURE_CMSE */
/**
* @}

220
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.c
View File

@ -10,7 +10,6 @@
* + IO operation functions
* + Peripheral Configuration and Control functions
* + Peripheral State and Error functions
*
******************************************************************************
* @attention
*
@ -97,12 +96,12 @@
*** Callback registration ***
=============================================
The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
to register an interrupt callback.
Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
(+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
(+) HighPriorityMessageCallback : High Priority Message Callback.
(+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
@ -115,14 +114,14 @@
For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
register callbacks : respectively @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
@ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
@ref HAL_FDCAN_RegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback()
and @ref HAL_FDCAN_RegisterErrorStatusCallback().
register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(),
HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback()
and HAL_FDCAN_RegisterErrorStatusCallback().
Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
@ -135,18 +134,18 @@
For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
unregister callbacks : respectively @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(),
@ref HAL_FDCAN_UnRegisterRxFifo0Callback(), @ref HAL_FDCAN_UnRegisterRxFifo1Callback(),
@ref HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback()
and @ref HAL_FDCAN_UnRegisterErrorStatusCallback().
unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback()
and HAL_FDCAN_UnRegisterErrorStatusCallback().
By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
all callbacks are set to the corresponding weak functions:
examples @ref HAL_FDCAN_ErrorCallback().
examples HAL_FDCAN_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
@ -154,8 +153,8 @@
in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
or @ref HAL_FDCAN_Init() function.
using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
or HAL_FDCAN_Init() function.
When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
@ -250,9 +249,15 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24,
*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup FDCAN_Private_Functions_Prototypes
* @{
*/
static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
uint32_t BufferIndex);
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
const uint8_t *pTxData, uint32_t BufferIndex);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
@ -325,22 +330,17 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
hfdcan->Lock = HAL_UNLOCKED;
/* Reset callbacks to legacy functions */
hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
TxBufferCompleteCallback */
hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak
TxBufferAbortCallback */
hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
HighPriorityMessageCallback */
hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
TimestampWraparoundCallback */
hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak
TimeoutOccurredCallback */
hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */
hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */
hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */
hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */
hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */
hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */
hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */
hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */
hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */
hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */
hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */
hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */
if (hfdcan->MspInitCallback == NULL)
{
@ -576,7 +576,7 @@ __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspInit could be implemented in the user file
*/
}
@ -591,7 +591,7 @@ __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspDeInit could be implemented in the user file
*/
}
@ -1286,7 +1286,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h
* contains the filter configuration information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
{
uint32_t FilterElementW1;
uint32_t FilterElementW2;
@ -1411,7 +1411,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param Mask Extended ID Mask.
This parameter must be a number between 0 and 0x1FFFFFFF
* This parameter must be a number between 0 and 0x1FFFFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
@ -1601,7 +1601,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
* the configuration information for the specified FDCAN.
* @retval Timestamp counter value
*/
uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan)
{
return (uint16_t)(hfdcan->Instance->TSCV);
}
@ -1724,7 +1724,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
* the configuration information for the specified FDCAN.
* @retval Timeout counter value
*/
uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan)
{
return (uint16_t)(hfdcan->Instance->TOCV);
}
@ -2097,8 +2097,8 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
* @param pTxData pointer to a buffer containing the payload of the Tx frame.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
uint8_t *pTxData)
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
const uint8_t *pTxData)
{
uint32_t PutIndex;
@ -2165,7 +2165,7 @@ HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDC
* - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
* - 0 if no Tx FIFO/Queue request have been submitted.
*/
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan)
{
/* Return Last Tx FIFO/Queue Request Buffer */
return hfdcan->LatestTxFifoQRequest;
@ -2217,7 +2217,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
uint32_t *RxAddress;
uint8_t *pData;
uint32_t ByteCounter;
uint32_t GetIndex;
uint32_t GetIndex = 0;
HAL_FDCAN_StateTypeDef state = hfdcan->State;
/* Check function parameters */
@ -2237,8 +2237,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
}
else
{
/* Check that the Rx FIFO 0 is full & overwrite mode is on */
if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
{
if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
{
/* When overwrite status is on discard first message in FIFO */
GetIndex = 1U;
}
}
/* Calculate Rx FIFO 0 element index */
GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
/* Calculate Rx FIFO 0 element address */
GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE));
}
}
@ -2254,8 +2266,19 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
}
else
{
/* Check that the Rx FIFO 1 is full & overwrite mode is on */
if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
{
if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
{
/* When overwrite status is on discard first message in FIFO */
GetIndex = 1U;
}
}
/* Calculate Rx FIFO 1 element index */
GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
/* Calculate Rx FIFO 1 element address */
GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE));
}
}
@ -2286,7 +2309,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
/* Retrieve BitRateSwitch */
pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
@ -2305,7 +2328,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
/* Retrieve Rx payload */
pData = (uint8_t *)RxAddress;
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++)
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
{
pRxData[ByteCounter] = pData[ByteCounter];
}
@ -2387,7 +2410,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven
pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
/* Retrieve BitRateSwitch */
pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
@ -2423,7 +2446,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven
* @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
{
HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
@ -2442,7 +2465,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hf
* @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
{
uint32_t StatusReg;
@ -2473,7 +2497,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN
* @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_ErrorCountersTypeDef *ErrorCounters)
{
uint32_t CountersReg;
@ -2497,10 +2522,10 @@ HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_
* @param TxBufferIndex Tx buffer index.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval Status
* - 0 : No pending transmission request on TxBufferIndex list
* - 0 : No pending transmission request on TxBufferIndex list.
* - 1 : Pending transmission request on TxBufferIndex.
*/
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
{
/* Check function parameters */
assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
@ -2523,7 +2548,7 @@ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_
* @arg FDCAN_RX_FIFO1: Rx FIFO 1
* @retval Rx FIFO fill level.
*/
uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
{
uint32_t FillLevel;
@ -2550,7 +2575,7 @@ uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
* the configuration information for the specified FDCAN.
* @retval Tx FIFO free level.
*/
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan)
{
uint32_t FreeLevel;
@ -2568,7 +2593,7 @@ uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
* - 0 : Normal FDCAN operation.
* - 1 : Restricted Operation Mode active.
*/
uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan)
{
uint32_t OperationMode;
@ -2879,6 +2904,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
uint32_t ErrorStatusITs;
uint32_t TransmittedBuffers;
uint32_t AbortedBuffers;
uint32_t itsource;
uint32_t itflag;
TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
TxEventFifoITs &= hfdcan->Instance->IE;
@ -2890,11 +2917,13 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
Errors &= hfdcan->Instance->IE;
ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
ErrorStatusITs &= hfdcan->Instance->IE;
itsource = hfdcan->Instance->IE;
itflag = hfdcan->Instance->IR;
/* High Priority Message interrupt management *******************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
{
/* Clear the High Priority Message flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
@ -2910,9 +2939,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Transmission Abort interrupt management **********************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
{
/* List of aborted monitored buffers */
AbortedBuffers = hfdcan->Instance->TXBCF;
@ -2977,9 +3006,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Tx FIFO empty interrupt management ***************************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
{
/* Clear the Tx FIFO empty flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
@ -2995,9 +3024,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Transmission Complete interrupt management *******************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET)
{
/* List of transmitted monitored buffers */
TransmittedBuffers = hfdcan->Instance->TXBTO;
@ -3017,9 +3046,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Timestamp Wraparound interrupt management ********************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
{
/* Clear the Timestamp Wraparound flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
@ -3035,9 +3064,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Timeout Occurred interrupt management ************************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
{
/* Clear the Timeout Occurred flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
@ -3053,9 +3082,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Message RAM access failure interrupt management **************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
{
/* Clear the Message RAM access failure flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
@ -3135,7 +3164,7 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
* @brief Tx Event callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled.
* @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
* @retval None
*/
@ -3145,7 +3174,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
UNUSED(hfdcan);
UNUSED(TxEventFifoITs);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
*/
}
@ -3154,7 +3183,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
* @brief Rx FIFO 0 callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled.
* @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
* @retval None
*/
@ -3164,7 +3193,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
UNUSED(hfdcan);
UNUSED(RxFifo0ITs);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
*/
}
@ -3173,7 +3202,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
* @brief Rx FIFO 1 callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled.
* @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
* @retval None
*/
@ -3183,7 +3212,7 @@ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
UNUSED(hfdcan);
UNUSED(RxFifo1ITs);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
*/
}
@ -3199,7 +3228,7 @@ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
*/
}
@ -3218,7 +3247,7 @@ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint
UNUSED(hfdcan);
UNUSED(BufferIndexes);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
*/
}
@ -3237,7 +3266,7 @@ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_
UNUSED(hfdcan);
UNUSED(BufferIndexes);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
*/
}
@ -3253,7 +3282,7 @@ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
*/
}
@ -3269,7 +3298,7 @@ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
*/
}
@ -3285,7 +3314,7 @@ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
*/
}
@ -3301,7 +3330,7 @@ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorCallback could be implemented in the user file
*/
}
@ -3320,7 +3349,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
UNUSED(hfdcan);
UNUSED(ErrorStatusITs);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
*/
}
@ -3350,7 +3379,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
* the configuration information for the specified FDCAN.
* @retval HAL state
*/
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan)
{
/* Return FDCAN state */
return hfdcan->State;
@ -3362,7 +3391,7 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
* the configuration information for the specified FDCAN.
* @retval FDCAN Error Code
*/
uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan)
{
/* Return FDCAN error code */
return hfdcan->ErrorCode;
@ -3431,8 +3460,8 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
* @param BufferIndex index of the buffer to be configured.
* @retval none
*/
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
uint32_t BufferIndex)
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
const uint8_t *pTxData, uint32_t BufferIndex)
{
uint32_t TxElementW1;
uint32_t TxElementW2;
@ -3460,7 +3489,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
pTxHeader->TxEventFifoControl |
pTxHeader->FDFormat |
pTxHeader->BitRateSwitch |
pTxHeader->DataLength);
(pTxHeader->DataLength << 16U));
/* Calculate Tx element address */
TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
@ -3472,7 +3501,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
TxAddress++;
/* Write Tx payload to the message RAM */
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U)
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
{
*TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
@ -3495,4 +3524,3 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
*/
#endif /* FDCAN1 */

129
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.h
View File

@ -230,12 +230,15 @@ typedef struct
uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
This parameter must be a number between:
- 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
- 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
- 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID
When the frame is a Non-Filter matching frame, this parameter
is unused. */
uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
Acceptance of non-matching frames may be enabled via
HAL_FDCAN_ConfigGlobalFilter().
This parameter can be 0 or 1 */
Acceptance of non-matching frames may be enabled via
HAL_FDCAN_ConfigGlobalFilter().
This parameter takes 0 if the frame matched an Rx filter or
1 if it did not match any Rx filter */
} FDCAN_RxHeaderTypeDef;
@ -315,53 +318,55 @@ typedef struct
typedef struct
{
uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
This parameter can be a value of @ref FDCAN_protocol_error_code */
This parameter can be a value of @ref FDCAN_protocol_error_code */
uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
of a CAN FD format frame with its BRS flag set.
This parameter can be a value of @ref FDCAN_protocol_error_code */
This parameter can be a value of @ref FDCAN_protocol_error_code */
uint32_t Activity; /*!< Specifies the FDCAN module communication state.
This parameter can be a value of @ref FDCAN_communication_state */
This parameter can be a value of @ref FDCAN_communication_state */
uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
This parameter can be:
- 0 : The FDCAN is in Error_Active state
- 1 : The FDCAN is in Error_Passive state */
- 1 : The FDCAN is in Error_Passive state */
uint32_t Warning; /*!< Specifies the FDCAN module warning status.
This parameter can be:
- 0 : error counters (RxErrorCnt and TxErrorCnt)
are below the Error_Warning limit of 96
- 1 : at least one of error counters has reached the Error_Warning limit of 96 */
- 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
Error_Warning limit of 96
- 1 : at least one of error counters has reached the Error_Warning
limit of 96 */
uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
This parameter can be:
- 0 : The FDCAN is not in Bus_Off state
- 1 : The FDCAN is in Bus_Off state */
- 1 : The FDCAN is in Bus_Off state */
uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
This parameter can be:
- 0 : Last received CAN FD message did not have its ESI flag set
- 1 : Last received CAN FD message had its ESI flag set */
- 1 : Last received CAN FD message had its ESI flag set */
uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
This parameter can be:
- 0 : Last received CAN FD message did not have its BRS flag set
- 1 : Last received CAN FD message had its BRS flag set */
- 1 : Last received CAN FD message had its BRS flag set */
uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
since last protocol status.This parameter can be:
since last protocol status.
This parameter can be:
- 0 : No CAN FD message received
- 1 : CAN FD message received */
- 1 : CAN FD message received */
uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
This parameter can be:
- 0 : No protocol exception event occurred since last read access
- 1 : Protocol exception event occurred */
- 1 : Protocol exception event occurred */
uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
This parameter can be a number between 0 and 127 */
This parameter can be a number between 0 and 127 */
} FDCAN_ProtocolStatusTypeDef;
@ -371,22 +376,24 @@ typedef struct
typedef struct
{
uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
This parameter can be a number between 0 and 255 */
This parameter can be a number between 0 and 255 */
uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
This parameter can be a number between 0 and 127 */
This parameter can be a number between 0 and 127 */
uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
This parameter can be:
- 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
- 1 : The Receive Error Counter (RxErrorCnt)
has reached the error passive level of 128 */
- 0 : The Receive Error Counter (RxErrorCnt) is below the error
passive level of 128
- 1 : The Receive Error Counter (RxErrorCnt) has reached the error
passive level of 128 */
uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
This parameter can be a number between 0 and 255.
This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
This counter is incremented each time when a FDCAN protocol error causes
the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
} FDCAN_ErrorCountersTypeDef;
@ -601,21 +608,21 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan,
* @{
*/
#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
/**
* @}
*/
@ -1037,7 +1044,7 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan,
* @retval None
*/
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
@ -1164,7 +1171,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
uint32_t RejectRemoteExt);
@ -1174,13 +1181,13 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3
HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
uint32_t TimeoutPeriod);
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
uint32_t TdcFilter);
@ -1200,21 +1207,23 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
/* Control functions **********************************************************/
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
uint8_t *pTxData);
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
const uint8_t *pTxData);
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_ErrorCountersTypeDef *ErrorCounters);
uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
/**
* @}
@ -1256,8 +1265,8 @@ void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorSt
* @{
*/
/* Peripheral State functions *************************************************/
uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
/**
* @}
*/
@ -1406,6 +1415,10 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \
((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 ))
#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/**
* @}
*/
@ -1427,5 +1440,3 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
#endif
#endif /* STM32U5xx_HAL_FDCAN_H */

18
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash.h
View File

@ -81,7 +81,7 @@ typedef struct
uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
@ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
@ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
@ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
@ -324,7 +324,7 @@ typedef struct
#define OB_USER_NRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */
#define OB_USER_NRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */
#define OB_USER_NRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */
#define OB_USER_SRAM134_RST 0x00000010U /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */
#define OB_USER_SRAM_RST 0x00000010U /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */
#define OB_USER_IWDG_SW 0x00000020U /*!< Independent watchdog selection */
#define OB_USER_IWDG_STOP 0x00000040U /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY 0x00000080U /*!< Independent watchdog counter freeze in standby mode */
@ -332,7 +332,9 @@ typedef struct
#define OB_USER_SWAP_BANK 0x00000200U /*!< Swap banks */
#define OB_USER_DUALBANK 0x00000400U /*!< Dual-Bank on 1MB/512kB Flash memory devices */
#define OB_USER_BKPRAM_ECC 0x00000800U /*!< Backup RAM ECC detection and correction enable */
#if defined(SRAM3_BASE)
#define OB_USER_SRAM3_ECC 0x00001000U /*!< SRAM3 ECC detection and correction enable */
#endif /* SRAM3_BASE */
#define OB_USER_SRAM2_ECC 0x00002000U /*!< SRAM2 ECC detection and correction enable */
#define OB_USER_SRAM2_RST 0x00004000U /*!< SRAM2 Erase when system reset */
#define OB_USER_NSWBOOT0 0x00008000U /*!< Software BOOT0 */
@ -389,13 +391,13 @@ typedef struct
* @}
*/
/** @defgroup FLASH_OB_USER_SRAM134_RST FLASH Option Bytes User SRAM134 Erase On Reset Type
/** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes User SRAM Erase On Reset Type
* @{
*/
#define OB_SRAM134_RST_ERASE 0x00000000U /*!< SRAM1, SRAM3 and SRAM4 erased
when a system reset occurs */
#define OB_SRAM134_RST_NOT_ERASE FLASH_OPTR_SRAM134_RST /*!< SRAM1, SRAM3 and SRAM4 are not erased
when a system reset occurs */
#define OB_SRAM_RST_ERASE 0x00000000U /*!< All SRAMs (except SRAM2 and BKPSRAM) erased
when a system reset occurs */
#define OB_SRAM_RST_NOT_ERASE FLASH_OPTR_SRAM_RST /*!< All SRAMs (except SRAM2 and BKPSRAM) not erased
when a system reset occurs */
/**
* @}
*/
@ -1020,7 +1022,7 @@ extern FLASH_ProcessTypeDef pFlash;
#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
#define IS_OB_USER_SRAM134_RST(VALUE) (((VALUE) == OB_SRAM134_RST_ERASE) || ((VALUE) == OB_SRAM134_RST_NOT_ERASE))
#define IS_OB_USER_SRAM_RST(VALUE) (((VALUE) == OB_SRAM_RST_ERASE) || ((VALUE) == OB_SRAM_RST_NOT_ERASE))
#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))

20
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash_ex.c
View File

@ -1081,7 +1081,7 @@ static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_
* @param UserConfig The selected User Option Bytes values.
* This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
* @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
* @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
* @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
* @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
* @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
* @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
@ -1140,14 +1140,14 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
}
if ((UserType & OB_USER_SRAM134_RST) != 0U)
if ((UserType & OB_USER_SRAM_RST) != 0U)
{
/* SRAM134_RST option byte should be modified */
assert_param(IS_OB_USER_SRAM134_RST(UserConfig & FLASH_OPTR_SRAM134_RST));
/* SRAM_RST option byte should be modified */
assert_param(IS_OB_USER_SRAM_RST(UserConfig & FLASH_OPTR_SRAM_RST));
/* Set value and mask for SRAM134_RST option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM134_RST);
optr_reg_mask |= FLASH_OPTR_SRAM134_RST;
/* Set value and mask for SRAM_RST option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_RST);
optr_reg_mask |= FLASH_OPTR_SRAM_RST;
}
if ((UserType & OB_USER_IWDG_SW) != 0U)
@ -1219,7 +1219,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC);
optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC;
}
#if defined(SRAM3_BASE)
if ((UserType & OB_USER_SRAM3_ECC) != 0U)
{
/* SRAM3_ECC option byte should be modified */
@ -1229,7 +1229,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC);
optr_reg_mask |= FLASH_OPTR_SRAM3_ECC;
}
#endif /* SRAM3_BASE */
if ((UserType & OB_USER_SRAM2_ECC) != 0U)
{
/* SRAM2_ECC option byte should be modified */
@ -1550,7 +1550,7 @@ static uint32_t FLASH_OB_GetRDP(void)
* @retval The FLASH User Option Bytes values.
* The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
* @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
* @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
* @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST,
* @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
* @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
* @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,

139
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c
View File

@ -30,17 +30,17 @@
[..]
The FMAC HAL driver can be used as follows:
(#) Initialize the FMAC low level resources by implementing the @ref HAL_FMAC_MspInit():
(++) Enable the FMAC interface clock using @ref __HAL_RCC_FMAC_CLK_ENABLE().
(#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit():
(++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE().
(++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT):
(+++) Configure the FMAC interrupt priority using @ref HAL_NVIC_SetPriority().
(+++) Enable the FMAC IRQ handler using @ref HAL_NVIC_EnableIRQ().
(+++) In FMAC IRQ handler, call @ref HAL_FMAC_IRQHandler().
(+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority().
(+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ().
(+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
(++) In case of using DMA to control data transfer (e.g. access configured
as FMAC_BUFFER_ACCESS_DMA):
(+++) Enable the DMA interface clock using @ref __HAL_RCC_DMA1_CLK_ENABLE()
or @ref __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
(+++) Enable the DMAMUX1 interface clock using @ref __HAL_RCC_DMAMUX1_CLK_ENABLE().
(+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE()
or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
(+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
(+++) If the initialization of the internal buffers (coefficients, input,
output) is done via DMA, configure and enable one DMA channel for
managing data transfer from memory to memory (preload channel).
@ -51,16 +51,16 @@
one DMA channel for managing data transfer from peripheral to
memory (output channel).
(+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s)
using @ref __HAL_LINKDMA().
using __HAL_LINKDMA().
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the enabled DMA channel(s) using @ref HAL_NVIC_SetPriority()
and @ref HAL_NVIC_EnableIRQ().
interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority()
and HAL_NVIC_EnableIRQ().
(#) Initialize the FMAC HAL using @ref HAL_FMAC_Init(). This function
resorts to @ref HAL_FMAC_MspInit() for low-level initialization.
(#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function
resorts to HAL_FMAC_MspInit() for low-level initialization.
(#) Configure the FMAC processing (filter) using @ref HAL_FMAC_FilterConfig()
or @ref HAL_FMAC_FilterConfig_DMA().
(#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig()
or HAL_FMAC_FilterConfig_DMA().
This function:
(++) Defines the memory area within the FMAC internal memory
(input, coefficients, output) and the associated threshold (input, output).
@ -73,61 +73,61 @@
(++) Enable the error interruptions in the input access and/or the output
access is done through IT/DMA. If an error occurs, the interruption
will be triggered in loop. In order to recover, the user will have
to reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init.
Optionally, he can also disable the interrupt using @ref __HAL_FMAC_DISABLE_IT;
to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
the error status will be kept, but no more interrupt will be triggered.
(++) Write the provided coefficients into the internal memory using polling
mode ( @ref HAL_FMAC_FilterConfig() ) or DMA ( @ref HAL_FMAC_FilterConfig_DMA() ).
In the DMA case, @ref HAL_FMAC_FilterConfigCallback() is called when
mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ).
In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
the handling is over.
(#) Optionally, the user can enable the error interruption related to
saturation by calling @ref __HAL_FMAC_ENABLE_IT. This helps in debugging the
saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the
filter. If a saturation occurs, the interruption will be triggered in loop.
In order to recover, the user will have to:
(++) Disable the interruption by calling @ref __HAL_FMAC_DISABLE_IT if
(++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
the user wishes to continue all the same.
(++) Reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init.
(++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
(#) Optionally, preload input (FIR, IIR) and output (IIR) data using
@ref HAL_FMAC_FilterPreload() or @ref HAL_FMAC_FilterPreload_DMA().
In the DMA case, @ref HAL_FMAC_FilterPreloadCallback() is called when
HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA().
In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when
the handling is over.
This step is optional as the filter can be started without preloaded
data.
(#) Start the FMAC processing (filter) using @ref HAL_FMAC_FilterStart().
(#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart().
This function also configures the output buffer that will be filled from
the circular internal output buffer. The function returns immediately
without updating the provided buffer. The IP processing will be active until
@ref HAL_FMAC_FilterStop() is called.
HAL_FMAC_FilterStop() is called.
(#) If the input internal buffer is accessed via DMA, @ref HAL_FMAC_HalfGetDataCallback()
(#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback()
will be called to indicate that half of the input buffer has been handled.
(#) If the input internal buffer is accessed via DMA or interrupt, @ref HAL_FMAC_GetDataCallback()
(#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback()
will be called to require new input data. It will be provided through
@ref HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
(#) If the output internal buffer is accessed via DMA, @ref HAL_FMAC_HalfOutputDataReadyCallback()
(#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback()
will be called to indicate that half of the output buffer has been handled.
(#) If the output internal buffer is accessed via DMA or interrupt,
@ref HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
buffer. It will be provided through @ref HAL_FMAC_ConfigFilterOutputBuffer()
HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer()
if the DMA isn't in circular mode.
(#) In all modes except none, provide new input data to be processed via @ref HAL_FMAC_AppendFilterData().
(#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData().
This function should only be called once the previous input data has been handled
(the preloaded input data isn't concerned).
(#) In all modes except none, provide a new output buffer to be filled via
@ref HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
user's output buffer has been filled.
(#) In polling mode, handle the input and output data using @ref HAL_FMAC_PollFilterData().
(#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData().
This function:
(++) Write the user's input data (provided via @ref HAL_FMAC_AppendFilterData())
(++) Write the user's input data (provided via HAL_FMAC_AppendFilterData())
into the FMAC input memory area.
(++) Read the FMAC output memory area and write it into the user's output buffer.
It will return either when:
@ -137,10 +137,10 @@
The user will have to use the updated input and output sizes to keep track
of them.
(#) Stop the FMAC processing (filter) using @ref HAL_FMAC_FilterStop().
(#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop().
(#) Call @ref HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
resorts to @ref HAL_FMAC_MspDeInit() for low-level de-initialization.
(#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
resorts to HAL_FMAC_MspDeInit() for low-level de-initialization.
##### Callback registration #####
==================================
@ -150,8 +150,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_FMAC_RegisterCallback() to register a user callback.
Function @ref HAL_FMAC_RegisterCallback() allows to register following callbacks:
Use Function HAL_FMAC_RegisterCallback() to register a user callback.
Function HAL_FMAC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : Error Callback.
(+) HalfGetDataCallback : Get Half Data Callback.
(+) GetDataCallback : Get Data Callback.
@ -165,9 +165,9 @@
and a pointer to the user callback function.
[..]
Use function @ref HAL_FMAC_UnRegisterCallback() to reset a callback to the default
Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : Error Callback.
@ -181,13 +181,13 @@
(+) MspDeInitCallback : FMAC MspDeInit.
[..]
By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples @ref GetDataCallback(), @ref OutputDataReadyCallback().
examples GetDataCallback(), OutputDataReadyCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init()
and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit()
reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init()
and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@ -196,8 +196,8 @@
in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_FMAC_RegisterCallback() before calling @ref HAL_FMAC_DeInit()
or @ref HAL_FMAC_Init() function.
using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit()
or HAL_FMAC_Init() function.
[..]
When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
@ -528,6 +528,8 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac)
/**
* @brief Register a User FMAC Callback.
* @note The User FMAC Callback is to be used instead of the weak predefined callback.
* @note The HAL_FMAC_RegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register
* callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param CallbackID ID of the callback to be registered.
@ -562,7 +564,6 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_
return HAL_ERROR;
}
__HAL_LOCK(hfmac);
if (hfmac->State == HAL_FMAC_STATE_READY)
{
@ -643,14 +644,14 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_
status = HAL_ERROR;
}
__HAL_UNLOCK(hfmac);
return status;
}
/**
* @brief Unregister a FMAC CallBack.
* @note The FMAC callback is redirected to the weak predefined callback.
* @note The HAL_FMAC_UnRegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register
* callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module
* @param CallbackID ID of the callback to be unregistered.
@ -676,8 +677,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
return HAL_ERROR;
}
__HAL_LOCK(hfmac);
if (hfmac->State == HAL_FMAC_STATE_READY)
{
switch (CallbackID)
@ -760,8 +759,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
status = HAL_ERROR;
}
__HAL_UNLOCK(hfmac);
return status;
}
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
@ -1530,7 +1527,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
* the configuration information for FMAC module.
* @retval HAL_FMAC_StateTypeDef FMAC state
*/
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac)
{
/* Return FMAC state */
return hfmac->State;
@ -1543,7 +1540,7 @@ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
* @note The returned error is a bit-map combination of possible errors.
* @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
*/
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac)
{
/* Return FMAC error code */
return hfmac->ErrorCode;
@ -1972,7 +1969,7 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
return (HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload));
}
else
{
@ -1982,14 +1979,8 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * InputSize));
}
if (status != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * InputSize)));
}
}
}
@ -2038,7 +2029,7 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
return (HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload));
}
else
{
@ -2048,14 +2039,8 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * OutputSize));
}
if (status != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * OutputSize)));
}
}
}

115
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.h
View File

@ -69,10 +69,12 @@ typedef struct
uint32_t FilterParam; /*!< Filter configuration (operation and parameters).
Set to 0 if no valid configuration was applied. */
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
int16_t *pInput; /*!< Pointer to FMAC input data buffer */
@ -95,7 +97,8 @@ typedef struct
DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */
DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */
DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle
parameters */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */
@ -164,37 +167,39 @@ typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer
*/
typedef struct
{
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
Ignored if InputBufferSize is set to 0
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory
(0x00 to 0xFF). Ignored if InputBufferSize is set to 0
(previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom").
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer
(including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
in the buffer is lower than this threshold.
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number
of free spaces in the buffer is lower than this threshold.
This parameter can be a value
of @ref FMAC_Data_Buffer_Threshold. */
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
Ignored if CoeffBufferSize is set to 0
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal
memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0
(previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
0 if a previous configuration should be kept. */
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
Ignored if OuputBufferSize is set to 0
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal
memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0
(previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom").
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer
(including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
in the buffer is lower than this threshold.
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number
of unread values in the buffer is lower than this threshold.
This parameter can be a value
of @ref FMAC_Data_Buffer_Threshold. */
@ -209,14 +214,16 @@ typedef struct
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping
is done when the clipping feature is disabled
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range
is exceeded, wrapping is done when the clipping feature is disabled
and saturation is done when the clipping feature is enabled.
This parameter can be a value of @ref FMAC_Clip_State. */
@ -266,11 +273,11 @@ typedef struct
/** @defgroup FMAC_Functions FMAC Functions
* @{
*/
#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
/**
* @}
*/
@ -279,18 +286,22 @@ typedef struct
* @{
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
*/
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 1. */
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 2. */
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 4. */
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 8. */
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces
in the buffer is less than 1.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 1. */
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces
in the buffer is less than 2.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 2. */
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces
in the buffer is less than 4.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 4. */
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces
in the buffer is less than 8.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 8. */
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
/**
* @}
@ -323,7 +334,8 @@ typedef struct
#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
#define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
#define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag
(this helps in debugging a filter) */
/**
* @}
*/
@ -335,7 +347,8 @@ typedef struct
#define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable
(this helps in debugging a filter) */
/**
* @}
*/
@ -345,8 +358,8 @@ typedef struct
*/
/* External variables --------------------------------------------------------*/
/** @defgroup FMAC_External_variables FMAC External variables
/* Exported variables --------------------------------------------------------*/
/** @defgroup FMAC_Exported_variables FMAC Exported variables
* @{
*/
/**
@ -358,7 +371,8 @@ typedef struct
* @{
*/
/** @brief Reset FMAC handle state.
/**
* @brief Reset FMAC handle state.
* @param __HANDLE__ FMAC handle.
* @retval None
*/
@ -402,7 +416,8 @@ typedef struct
#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified FMAC interrupt occurred or not.
/**
* @brief Check whether the specified FMAC interrupt occurred or not.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to check.
* This parameter can be any combination of the following values:
@ -416,7 +431,8 @@ typedef struct
#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
/** @brief Clear specified FMAC interrupt status. Dummy macro as the
/**
* @brief Clear specified FMAC interrupt status. Dummy macro as the
interrupt status flags are read-only.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to clear.
@ -424,7 +440,8 @@ typedef struct
*/
#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
/** @brief Check whether the specified FMAC status flag is set or not.
/**
* @brief Check whether the specified FMAC status flag is set or not.
* @param __HANDLE__ FMAC handle.
* @param __FLAG__ FMAC flag to check.
* This parameter can be any combination of the following values:
@ -438,7 +455,8 @@ typedef struct
#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear specified FMAC status flag. Dummy macro as no
/**
* @brief Clear specified FMAC status flag. Dummy macro as no
flag can be cleared.
* @param __HANDLE__ FMAC handle.
* @param __FLAG__ FMAC flag to clear.
@ -446,7 +464,8 @@ typedef struct
*/
#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
/** @brief Check whether the specified FMAC interrupt is enabled or not.
/**
* @brief Check whether the specified FMAC interrupt is enabled or not.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to check.
* This parameter can be one of the following values:
@ -663,8 +682,8 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
* @{
*/
/* Peripheral State functions *************************************************/
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
/**
* @}
*/

977
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.c Normal file
View File

@ -0,0 +1,977 @@
/**
******************************************************************************
* @file stm32u5xx_hal_gfxmmu.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Graphic MMU (GFXMMU) peripheral:
* + Initialization and De-initialization.
* + LUT configuration.
* + Force flush and/or invalidate of cache.
* + Modify physical buffer addresses.
* + Modify cache and pre-fetch parameters.
* + Error management.
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Initialization ***
======================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspInit() :
(++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts are used, enable and configure GFXMMU global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the number of blocks per line, default value, physical
buffer addresses, cache and pre-fetch parameters and interrupts
using the HAL_GFXMMU_Init() function.
*** LUT configuration ***
=========================
[..]
(#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a
range of lines).
(#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
(#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.
*** Force flush and/or invalidate of cache ***
==============================================
[..]
(#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache.
*** Modify physical buffer addresses ***
=======================================
[..]
(#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
*** Modify cache and pre-fetch parameters ***
=============================================
[..]
(#) Use HAL_GFXMMU_ModifyCachePrefetch() to modify cache and pre-fetch
parameters.
*** Modify address cache parameters ***
=========================================
[..]
NOTE : This feature is only available on STM32U5F9/STM32U5G9 devices.
(#) Use HAL_GFXMMU_ModifyAddressCache() to modify address cache parameters.
*** Error management ***
========================
[..]
(#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when
an error occurs. This function will call HAL_GFXMMU_ErrorCallback().
Use HAL_GFXMMU_GetError() to get the error code.
*** De-initialization ***
=========================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() :
(++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts has been used, disable GFXMMU global interrupt with
HAL_NVIC_DisableIRQ().
(#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function.
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions HAL_GFXMMU_RegisterCallback() to register a user callback.
[..]
Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
[..]
Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples HAL_GFXMMU_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init
and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit
or HAL_GFXMMU_Init function.
[..]
When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_GFXMMU_MODULE_ENABLED
#if defined(GFXMMU)
/** @defgroup GFXMMU GFXMMU
* @brief GFXMMU HAL driver module
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup GFXMMU_Private_Constants GFXMMU Private Constants
* @{
*/
#define GFXMMU_LUTXL_FVB_OFFSET 8U
#define GFXMMU_LUTXL_LVB_OFFSET 16U
#define GFXMMU_CR_ITS_MASK 0x1FU
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions
* @{
*/
/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the GFXMMU.
(+) De-initialize the GFXMMU.
@endverbatim
* @{
*/
/**
* @brief Initialize the GFXMMU according to the specified parameters in the
* GFXMMU_InitTypeDef structure and initialize the associated handle.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if (hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address));
#if defined(GFXMMU_CR_CE)
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.CachePrefetch.Activation));
#endif /* GFXMMU_CR_CE */
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation));
#if defined (GFXMMU_CR_ACE)
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.AddressCache.Activation));
#endif /* GFXMMU_CR_ACE */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
/* Call GFXMMU MSP init function */
if (hgfxmmu->MspInitCallback == NULL)
{
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
}
hgfxmmu->MspInitCallback(hgfxmmu);
#else
/* Call GFXMMU MSP init function */
HAL_GFXMMU_MspInit(hgfxmmu);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/* Configure blocks per line, cache and interrupts parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE | GFXMMU_CR_192BM);
#if defined(GFXMMU_CR_CE)
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC |
GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB);
#endif /* GFXMMU_CR_CE */
#if defined (GFXMMU_CR_ACE)
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_ACE | GFXMMU_CR_ACLB);
#endif /* GFXMMU_CR_ACE */
hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine);
#if defined(GFXMMU_CR_CE)
if (hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(hgfxmmu->Init.CachePrefetch.CacheLock));
assert_param(IS_GFXMMU_PREFETCH(hgfxmmu->Init.CachePrefetch.Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(hgfxmmu->Init.CachePrefetch.OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(hgfxmmu->Init.CachePrefetch.OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
hgfxmmu->Init.CachePrefetch.CacheLock |
hgfxmmu->Init.CachePrefetch.Prefetch |
hgfxmmu->Init.CachePrefetch.OutterBufferability |
hgfxmmu->Init.CachePrefetch.OutterCachability);
if (hgfxmmu->Init.CachePrefetch.CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(hgfxmmu->Init.CachePrefetch.CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(hgfxmmu->Init.CachePrefetch.CacheForce));
hgfxmmu->Instance->CR |= (hgfxmmu->Init.CachePrefetch.CacheLockBuffer |
hgfxmmu->Init.CachePrefetch.CacheForce);
}
}
#endif /* GFXMMU_CR_CE */
if (hgfxmmu->Init.Interrupts.Activation == ENABLE)
{
assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts));
hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts;
}
/* Configure default value on GFXMMU_DVR register */
hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
/* Configure physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address;
#if defined(GFXMMU_CR_CE)
/* Force invalidate cache if cache is enabled */
if (hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
hgfxmmu->Instance->CCR |= GFXMMU_CACHE_FORCE_INVALIDATE;
}
#endif /* GFXMMU_CR_CE */
#if defined (GFXMMU_CR_ACE)
if (hgfxmmu->Init.AddressCache.Activation == ENABLE)
{
assert_param(IS_GFXMMU_ADDRESSCACHE_LOCK_BUFFER(hgfxmmu->Init.AddressCache.AddressCacheLockBuffer));
hgfxmmu->Instance->CR |= GFXMMU_CR_ACE |
hgfxmmu->Init.AddressCache.AddressCacheLockBuffer;
}
#endif /* GFXMMU_CR_ACE */
/* Reset GFXMMU error code */
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Set GFXMMU to ready state */
hgfxmmu->State = HAL_GFXMMU_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief De-initialize the GFXMMU.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if (hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Disable all interrupts on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE);
/* Call GFXMMU MSP de-init function */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
if (hgfxmmu->MspDeInitCallback == NULL)
{
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
}
hgfxmmu->MspDeInitCallback(hgfxmmu);
#else
HAL_GFXMMU_MspDeInit(hgfxmmu);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/* Set GFXMMU to reset state */
hgfxmmu->State = HAL_GFXMMU_STATE_RESET;
}
/* Return function status */
return status;
}
/**
* @brief Initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspInit could be implemented in the user file.
*/
}
/**
* @brief De-initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspDeInit could be implemented in the user file.
*/
}
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/**
* @brief Register a user GFXMMU callback
* to be used instead of the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be registered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @param pCallback pointer to the callback function.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
pGFXMMU_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
if (HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = pCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Unregister a user GFXMMU callback.
* GFXMMU callback is redirected to the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be unregistered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions
* @brief GFXMMU operation functions
*
@verbatim
==============================================================================
##### Operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure LUT.
(+) Force flush and/or invalidate of cache.
(+) Modify physical buffer addresses.
(+) Modify cache and pre-fetch parameters.
(+) Manage error.
@endverbatim
* @{
*/
/**
* @brief This function allows to copy LUT from flash to look up RAM.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line enabled on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines enabled on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @param Address Start address of LUT in flash.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber,
uint32_t Address)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_address;
uint32_t current_line;
uint32_t lutxl_address;
uint32_t lutxh_address;
/* Initialize local variables */
current_address = Address;
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Copy LUT from flash to look up RAM */
while (current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = *((uint32_t *)current_address);
current_address += 4U;
*((uint32_t *)lutxh_address) = *((uint32_t *)current_address);
current_address += 4U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to disable a range of LUT lines.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line to disable on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines to disable on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_line;
uint32_t lutxl_address;
uint32_t lutxh_address;
/* Initialize local variables */
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Disable LUT lines */
while (current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to configure one line of LUT.
* @param hgfxmmu GFXMMU handle.
* @param lutLine LUT line parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber));
assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock));
assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset));
/* Check GFXMMU state */
if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
uint32_t lutxl_address;
uint32_t lutxh_address;
/* Initialize local variables */
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]);
/* Configure LUT line */
if (lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE)
{
/* Enable and configure LUT line */
*((uint32_t *)lutxl_address) = (lutLine->LineStatus |
(lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) |
(lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET));
*((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset;
}
else
{
/* Disable LUT line */
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
}
}
/* Return function status */
return status;
}
#if defined(GFXMMU_CR_CE)
/**
* @brief This function allows to force flush and/or invalidate of cache.
* @param hgfxmmu GFXMMU handle.
* @param ForceParam Force cache parameter.
* This parameter can be a values combination of @ref GFXMMU_CacheForceParam.
* @retval HAL status.
* @note This function is only available on STM32U599/STM32U5A9 devices.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_CACHE_FORCE_ACTION(ForceParam));
/* Check GFXMMU state and cache status */
if (((hgfxmmu->Instance->CR & GFXMMU_CR_CE) != GFXMMU_CR_CE) || (hgfxmmu->State != HAL_GFXMMU_STATE_READY))
{
status = HAL_ERROR;
}
else
{
/* Force flush and/or invalidate cache on GFXMMU_CCR register */
hgfxmmu->Instance->CCR |= ForceParam;
}
/* Return function status */
return status;
}
#endif /* GFXMMU_CR_CE */
/**
* @brief This function allows to modify physical buffer addresses.
* @param hgfxmmu GFXMMU handle.
* @param Buffers Buffers parameters.
* @retval HAL status.
* @note This function is only available on STM32U599/STM32U5A9 devices.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address));
/* Check GFXMMU state */
if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
hgfxmmu->Instance->B3CR = Buffers->Buf3Address;
}
/* Return function status */
return status;
}
#if defined(GFXMMU_CR_CE)
/**
* @brief This function allows to modify cache and pre-fetch parameters.
* @param hgfxmmu GFXMMU handle.
* @param CachePrefetch Cache and pre-fetch parameters.
* @retval HAL status.
* @note This function is only available on STM32U599/STM32U5A9 devices.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_CachePrefetchTypeDef *CachePrefetch)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation));
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Check GFXMMU state */
if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify cache and pre-fetch parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC |
GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB);
if (CachePrefetch->Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(CachePrefetch->CacheLock));
assert_param(IS_GFXMMU_PREFETCH(CachePrefetch->Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(CachePrefetch->OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(CachePrefetch->OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
CachePrefetch->CacheLock |
CachePrefetch->Prefetch |
CachePrefetch->OutterBufferability |
CachePrefetch->OutterCachability);
if (CachePrefetch->CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(CachePrefetch->CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(CachePrefetch->CacheForce));
hgfxmmu->Instance->CR |= (CachePrefetch->CacheLockBuffer |
CachePrefetch->CacheForce);
}
}
}
/* Return function status */
return status;
}
#endif /* GFXMMU_CR_CE */
#if defined (GFXMMU_CR_ACE)
/**
* @brief This function allows to modify address cache parameters.
* @param hgfxmmu GFXMMU handle.
* @param address cache parameters.
* @retval HAL status.
* @note This function is only available on STM32U5F9/STM32U5G9 devices.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_AddressCacheTypeDef *AddressCache)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_FUNCTIONAL_STATE(AddressCache->Activation));
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Check GFXMMU state */
if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify Address cache parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_ACE | GFXMMU_CR_ACLB);
if (AddressCache->Activation == ENABLE)
{
assert_param(IS_GFXMMU_ADDRESSCACHE_LOCK_BUFFER(AddressCache->AddressCacheLockBuffer));
hgfxmmu->Instance->CR |= (GFXMMU_CR_ACE |
AddressCache->AddressCacheLockBuffer);
}
}
/* Return function status */
return status;
}
#endif /* GFXMMU_CR_ACE */
/**
* @brief This function handles the GFXMMU interrupts.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t flags, interrupts, error;
/* Read current flags and interrupts and determine which error occurs */
flags = hgfxmmu->Instance->SR;
interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK);
error = (flags & interrupts);
if (error != 0U)
{
/* Clear flags on GFXMMU_FCR register */
hgfxmmu->Instance->FCR = error;
/* Update GFXMMU error code */
hgfxmmu->ErrorCode |= error;
/* Call GFXMMU error callback */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
hgfxmmu->ErrorCallback(hgfxmmu);
#else
HAL_GFXMMU_ErrorCallback(hgfxmmu);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
}
}
/**
* @brief Error callback.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_GFXMMU_ErrorCallback could be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
* @brief GFXMMU state functions
*
@verbatim
==============================================================================
##### State functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Get GFXMMU handle state.
(+) Get GFXMMU error code.
@endverbatim
* @{
*/
/**
* @brief This function allows to get the current GFXMMU handle state.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU state.
*/
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Return GFXMMU handle state */
return hgfxmmu->State;
}
/**
* @brief This function allows to get the current GFXMMU error code.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU error code.
*/
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t error_code;
/* Enter in critical section */
__disable_irq();
/* Store and reset GFXMMU error code */
error_code = hgfxmmu->ErrorCode;
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Exit from critical section */
__enable_irq();
/* Return GFXMMU error code */
return error_code;
}
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
#endif /* GFXMMU */
#endif /* HAL_GFXMMU_MODULE_ENABLED */
/**
* @}
*/

504
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.h Normal file
View File

@ -0,0 +1,504 @@
/**
******************************************************************************
* @file stm32u5xx_hal_gfxmmu.h
* @author MCD Application Team
* @brief Header file of GFXMMU HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_GFXMMU_H
#define STM32U5xx_HAL_GFXMMU_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
#if defined(GFXMMU)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup GFXMMU
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types
* @{
*/
/**
* @brief HAL GFXMMU states definition
*/
typedef enum
{
HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */
HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */
} HAL_GFXMMU_StateTypeDef;
/**
* @brief GFXMMU buffers structure definition
*/
typedef struct
{
uint32_t Buf0Address; /*!< Physical address of buffer 0. */
uint32_t Buf1Address; /*!< Physical address of buffer 1. */
uint32_t Buf2Address; /*!< Physical address of buffer 2. */
uint32_t Buf3Address; /*!< Physical address of buffer 3. */
} GFXMMU_BuffersTypeDef;
#if defined (GFXMMU_CR_CE)
/**
* @brief GFXMMU cache and pre-fetch structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Cache and pre-fetch enable/disable.
@note: All following parameters are useful only if cache
and pre-fetch are enabled. */
uint32_t CacheLock; /*!< Locking the cache to a buffer.
This parameter can be a value of @ref GFXMMU_CacheLock. */
uint32_t CacheLockBuffer; /*!< Buffer on which the cache is locked.
This parameter can be a value of @ref GFXMMU_CacheLockBuffer.
@note: Useful only when lock of the cache is enabled. */
uint32_t CacheForce; /*!< Forcing the cache regardless MPU attributes.
This parameter can be a value of @ref GFXMMU_CacheForce.
@note: Useful only when lock of the cache is enabled. */
uint32_t OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache.
This parameter can be a value of @ref GFXMMU_OutterBufferability. */
uint32_t OutterCachability; /*!< Cachability of an access generated by the GFXMMU cache.
This parameter can be a value of @ref GFXMMU_OutterCachability. */
uint32_t Prefetch; /*!< Pre-fetch enable/disable.
This parameter can be a value of @ref GFXMMU_Prefetch. */
} GFXMMU_CachePrefetchTypeDef;
#endif /* GFXMMU_CR_CE */
#if defined (GFXMMU_CR_ACE)
/**
* @brief GFXMMU address cache structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Address Cache and enable/disable.
@note: All following parameters are useful only if address
cache is enabled. */
uint32_t AddressCacheLockBuffer; /*!< Buffer on which the address cache is locked.
This parameter can be a value of @ref GFXMMU_AddressCacheLockBuffer.
@note: Useful only when lock of the address cache is enabled. */
} GFXMMU_AddressCacheTypeDef;
#endif /* GFXMMU_CR_ACE */
/**
* @brief GFXMMU interrupts structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Interrupts enable/disable */
uint32_t UsedInterrupts; /*!< Interrupts used.
This parameter can be a values combination of @ref GFXMMU_Interrupts.
@note: Useful only when interrupts are enabled. */
} GFXMMU_InterruptsTypeDef;
/**
* @brief GFXMMU init structure definition
*/
typedef struct
{
uint32_t BlocksPerLine; /*!< Number of blocks of 16 bytes per line.
This parameter can be a value of @ref GFXMMU_BlocksPerLine. */
uint32_t DefaultValue; /*!< Value returned when virtual memory location not physically mapped. */
GFXMMU_BuffersTypeDef Buffers; /*!< Physical buffers addresses. */
#if defined (GFXMMU_CR_CE)
GFXMMU_CachePrefetchTypeDef CachePrefetch; /*!< Cache and pre-fetch parameters. */
#endif /* GFXMMU_CR_CE */
#if defined (GFXMMU_CR_ACE)
GFXMMU_AddressCacheTypeDef AddressCache; /*!< Address Cache parameters. */
#endif /* GFXMMU_CR_ACE */
GFXMMU_InterruptsTypeDef Interrupts; /*!< Interrupts parameters. */
} GFXMMU_InitTypeDef;
/**
* @brief GFXMMU handle structure definition
*/
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
typedef struct __GFXMMU_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
{
GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */
GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */
HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */
__IO uint32_t ErrorCode; /*!< GFXMMU error code */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
void (*ErrorCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */
void (*MspInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */
void (*MspDeInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
} GFXMMU_HandleTypeDef;
/**
* @brief GFXMMU LUT line structure definition
*/
typedef struct
{
uint32_t LineNumber; /*!< LUT line number.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */
uint32_t LineStatus; /*!< LUT line enable/disable.
This parameter can be a value of @ref GFXMMU_LutLineStatus. */
uint32_t FirstVisibleBlock; /*!< First visible block on this line.
This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
uint32_t LastVisibleBlock; /*!< Last visible block on this line.
This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
int32_t LineOffset; /*!< Offset of block 0 of the current line in physical buffer.
This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208.
@note: Line offset has to be computed with the following formula:
LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */
} GFXMMU_LutLineTypeDef;
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/**
* @brief GFXMMU callback ID enumeration definition
*/
typedef enum
{
HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID */
HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID */
HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID */
} HAL_GFXMMU_CallbackIDTypeDef;
/**
* @brief GFXMMU callback pointer definition
*/
typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants
* @{
*/
/** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line
* @{
*/
#define GFXMMU_256BLOCKS 0x00000000U /*!< 256 blocks of 16 bytes per line */
#define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */
/**
* @}
*/
/** @defgroup GFXMMU_CacheLock GFXMMU cache lock
* @{
*/
#define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U /*!< Cache not locked to a buffer */
#define GFXMMU_CACHE_LOCK_ENABLE GFXMMU_CR_CL /*!< Cache locked to a buffer */
/**
* @}
*/
/** @defgroup GFXMMU_CacheLockBuffer GFXMMU cache lock buffer
* @{
*/
#define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U /*!< Cache locked to buffer 0 */
#define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0 /*!< Cache locked to buffer 1 */
#define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1 /*!< Cache locked to buffer 2 */
#define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB /*!< Cache locked to buffer 3 */
/**
* @}
*/
/** @defgroup GFXMMU_CacheForce GFXMMU cache force
* @{
*/
#define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U /*!< Caching not forced */
#define GFXMMU_CACHE_FORCE_ENABLE GFXMMU_CR_FC /*!< Caching forced */
/**
* @}
*/
/** @defgroup GFXMMU_OutterBufferability GFXMMU outer bufferability
* @{
*/
#define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U /*!< No bufferable */
#define GFXMMU_OUTTER_BUFFERABILITY_ENABLE GFXMMU_CR_OB /*!< Bufferable */
/**
* @}
*/
/** @defgroup GFXMMU_OutterCachability GFXMMU outer cachability
* @{
*/
#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U /*!< No cacheable */
#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC /*!< Cacheable */
/**
* @}
*/
/** @defgroup GFXMMU_Prefetch GFXMMU pre-fetch
* @{
*/
#define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD /*!< Pre-fetch disable */
#define GFXMMU_PREFETCH_ENABLE 0x00000000U /*!< Pre-fetch enable */
/**
* @}
*/
/** @defgroup GFXMMU_Interrupts GFXMMU interrupts
* @{
*/
#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */
#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */
#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */
#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */
#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */
/**
* @}
*/
/** @defgroup GFXMMU_Error_Code GFXMMU Error Code
* @{
*/
#define GFXMMU_ERROR_NONE 0x00000000U /*!< No error */
#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */
#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */
#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */
#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */
#define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/**
* @}
*/
/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status
* @{
*/
#define GFXMMU_LUT_LINE_DISABLE 0x00000000U /*!< LUT line disabled */
#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN /*!< LUT line enabled */
/**
* @}
*/
/** @defgroup GFXMMU_CacheForceParam GFXMMU cache force parameter
* @{
*/
#define GFXMMU_CACHE_FORCE_FLUSH GFXMMU_CCR_FF /*!< Force cache flush */
#define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI /*!< Force cache invalidate */
/**
* @}
*/
#if defined (GFXMMU_CR_ACE)
/** @defgroup GFXMMU_CacheLockBuffer GFXMMU address cache lock buffer
* @{
*/
#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER0 0x00000000U /*!< Address Cache locked to buffer 0 */
#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER1 GFXMMU_CR_ACLB_0 /*!< Address Cache locked to buffer 1 */
#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER2 GFXMMU_CR_ACLB_1 /*!< Address Cache locked to buffer 2 */
#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER3 GFXMMU_CR_ACLB /*!< Address Cache locked to buffer 3 */
/**
* @}
*/
#endif /* GFXMMU_CR_ACE */
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros
* @{
*/
/** @brief Reset GFXMMU handle state.
* @param __HANDLE__ GFXMMU handle.
* @retval None
*/
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/**
* @}
*/
/* End of exported macros ----------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions
* @{
*/
/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/* GFXMMU callbacks register/unregister functions *****************************/
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
pGFXMMU_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/**
* @}
*/
/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions
* @{
*/
/* Operation functions ********************************************************/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber,
uint32_t Address);
HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber);
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine);
#if defined (GFXMMU_CR_CE)
HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam);
#endif /* GFXMMU_CR_CE */
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers);
#if defined (GFXMMU_CR_CE)
HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_CachePrefetchTypeDef *CachePrefetch);
#endif /* GFXMMU_CR_CE */
#if defined (GFXMMU_CR_ACE)
HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_AddressCacheTypeDef *AddressCache);
#endif /* GFXMMU_CR_ACE */
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
* @{
*/
/* State function *************************************************************/
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu);
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros
* @{
*/
#define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \
((VALUE) == GFXMMU_192BLOCKS))
#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
#define IS_GFXMMU_CACHE_LOCK(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \
((VALUE) == GFXMMU_CACHE_LOCK_ENABLE))
#define IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \
((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \
((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \
((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3))
#define IS_GFXMMU_CACHE_FORCE(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \
((VALUE) == GFXMMU_CACHE_FORCE_ENABLE))
#define IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \
((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE))
#define IS_GFXMMU_OUTTER_CACHABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \
((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE))
#define IS_GFXMMU_PREFETCH(VALUE) (((VALUE) == GFXMMU_PREFETCH_DISABLE) || \
((VALUE) == GFXMMU_PREFETCH_ENABLE))
#if defined (GFXMMU_CR_ACE)
#define IS_GFXMMU_ADDRESSCACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER0) || \
((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER1) || \
((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER2) || \
((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER3))
#endif /* GFXMMU_CR_ACE */
#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
((VALUE) == GFXMMU_LUT_LINE_ENABLE))
#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))
#define IS_GFXMMU_CACHE_FORCE_ACTION(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \
((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \
((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE)))
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* GFXMMU */
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_GFXMMU_H */

76
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c
View File

@ -83,7 +83,10 @@
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) To set the level of several pins and reset level of several other pins in
same cycle, use HAL_GPIO_WriteMultipleStatePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
@ -238,7 +241,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
/* Configure Alternate function mapped with the current IO */
tmp = p_gpio->AFR[(pin_position) >> 3U];
tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U));
tmp |= ((GPIO_AF11_LPGPIO & 0x0FUL) << (((pin_position) & 0x07U) * 4U));
tmp |= ((GPIO_AF11_LPGPIO1 & 0x0FUL) << (((pin_position) & 0x07U) * 4U));
p_gpio->AFR[(pin_position) >> 3U] = tmp;
/* Configure IO Direction mode (Alternate) */
@ -319,23 +322,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)));
EXTI->EXTICR[position >> 2U] = tmp;
/* Clear EXTI line configuration */
tmp = EXTI->IMR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
tmp |= iocurrent;
}
EXTI->IMR1 = tmp;
tmp = EXTI->EMR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
tmp |= iocurrent;
}
EXTI->EMR1 = tmp;
/* Clear Rising Falling edge configuration */
tmp = EXTI->RTSR1;
tmp &= ~((uint32_t)iocurrent);
@ -352,6 +338,23 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
tmp |= iocurrent;
}
EXTI->FTSR1 = tmp;
/* Clear EXTI line configuration */
tmp = EXTI->EMR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
tmp |= iocurrent;
}
EXTI->EMR1 = tmp;
tmp = EXTI->IMR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
tmp |= iocurrent;
}
EXTI->IMR1 = tmp;
}
}
position++;
@ -468,7 +471,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
@ -518,6 +521,34 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
}
}
/**
* @brief Set and clear several pins of a dedicated port in same cycle.
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
* accesses.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param PinReset specifies the port bits to be reset
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
* @param PinSet specifies the port bits to be set
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
* @note Both PinReset and PinSet combinations shall not get any common bit, else
* assert would be triggered.
* @note At least one of the two parameters used to set or reset shall be different from zero.
* @retval None
*/
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet)
{
uint32_t tmp;
/* Check the parameters */
/* Make sure at least one parameter is different from zero and that there is no common pin */
assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet));
assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet));
tmp = (((uint32_t)PinReset << 16) | PinSet);
GPIOx->BSRR = tmp;
}
/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
@ -875,12 +906,13 @@ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32
* @param pPinAttributes: pointer to return the pin attributes.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes)
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
uint32_t *pPinAttributes)
{
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
const GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));

9
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.h
View File

@ -278,6 +278,9 @@ typedef enum
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
@ -339,8 +342,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
@ -361,7 +365,8 @@ void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
/* IO attributes management functions *****************************************/
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes);
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes);
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
uint32_t *pPinAttributes);
/**
* @}

260
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio_ex.h
View File

@ -50,7 +50,6 @@ typedef struct
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
@ -59,176 +58,236 @@ typedef struct
* @{
*/
#if (defined(STM32U575xx) || defined(STM32U585xx))
/*--------------STM32U575xx/STM32U585xx---------------------------*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */
#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */
#if defined(I2C5)
#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C5 Alternate Function mapping */
#endif /* I2C5 */
#if defined(I2C6)
#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */
#endif /* I2C6 */
#if defined(GFXTIM)
#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /* GFXTIM Alternate Function mapping */
#endif /* GFXTIM */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */
#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
#if defined(USART2)
#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
#endif /* USART2 */
#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */
#if defined(USB_OTG_HS)
#define GPIO_AF3_USB_HS ((uint8_t)0x03) /* USB_HS Alternate Function mapping */
#endif /* USB_OTG_HS */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */
#if defined (I2C5)
#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
#endif /* I2C5 */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */
#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */
#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */
#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */
#if defined(OCTOSPI2)
#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */
#endif /* OCTOSPI2 */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */
#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */
#if defined(GFXTIM)
#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */
#endif /* GFXTIM */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */
#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */
#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */
#if defined(OCTOSPI2)
#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */
#endif /* OCTOPSI2 */
#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#if defined(USART2)
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#endif /* USART2 */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#if defined(USART6)
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#endif /* USART6 */
#if defined(LTDC)
#define GPIO_AF7_LTDC ((uint8_t)0x07) /* LTDC Alternate Function mapping */
#endif /* LTDC */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#if defined(LTDC)
#define GPIO_AF8_LTDC ((uint8_t)0x08) /* LTDC Alternate Function mapping */
#endif /* LTDC */
#if defined(HSPI1)
#define GPIO_AF8_HSPI1 ((uint8_t)0x08) /* HSPI1 Alternate Function mapping */
#endif /* HSPI1 */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */
#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */
#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */
#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */
#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */
#if defined(OCTOSPI2)
#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */
#endif /* OCTOSPI2 */
#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
#if defined(USB_OTG_HS)
#define GPIO_AF10_USB_HS ((uint8_t)0x0A) /* USB_HS Alternate Function mapping */
#endif /* USB_OTG_HS */
#if defined(GFXTIM)
#define GPIO_AF10_GFXTIM ((uint8_t)0x0A) /* GFXTIM Alternate Function mapping */
#endif /* GFXTIM */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /*!< UCPD1 Alternate Function mapping */
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */
#define GPIO_AF11_LPGPIO ((uint8_t)0x0B) /*!< LPGPIO Alternate Function mapping */
#define GPIO_AF11_FMC_NBL1 ((uint8_t)0x0B) /*!< FMC_NBL1 Alternate Function mapping */
#if defined(UCPD1)
#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */
#endif /* UCPD1 */
#if defined(SDMMC2)
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#endif /* SDMMC2 */
#define GPIO_AF11_LPGPIO1 ((uint8_t)0x0B) /* LPGPIO1 Alternate Function mapping */
#if defined(FMC_BASE)
#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */
#endif /* FMC_BASE */
#if defined(DSI)
#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */
#endif /* DSI */
#if defined(GFXTIM)
#define GPIO_AF11_GFXTIM ((uint8_t)0x0B) /* GFXTIM Alternate Function mapping */
#endif /* GFXTIM */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#if defined(FMC_BASE)
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#endif /* FMC_BASE */
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#if defined(SDMMC2)
#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */
#endif /* SDMMC2 */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */
#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
#if defined(SAI2)
#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
#endif /* SAI2 */
#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */
#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */
#if defined(GFXTIM)
#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /* GFXTIM Alternate Function mapping */
#endif /* GFXTIM */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */
#define GPIO_AF14_SDMMC2 ((uint8_t)0x0E) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */
/**
* @}
*/
@ -245,11 +304,10 @@ typedef struct
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{
*/
#if (defined(STM32U575xx) || defined(STM32U585xx))
/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */
#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */
/**
* @}
*/

750
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.c Normal file
View File

@ -0,0 +1,750 @@
/**
******************************************************************************
* @file stm32u5xx_hal_gpu2d.c
* @author MCD Application Team
* @brief GPU2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the GPU2D peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Peripheral control is exclusively done by the accompanying middleware library.
*** Interrupt mode IO operation ***
===================================
[..]
(#) Configure the GPU2D hardware to perform graphics operation using the Third Party MW
Library APIs.
(#) Submit command List to the hardware.
(#) Wait indefinitely for the completion of submitted Command List by GPU2D hardware.
(#) Use HAL_GPU2D_IRQHandler() called under GPU2D_IRQHandler() interrupt subroutine.
(#) At the end of Command List execution HAL_GPU2D_IRQHandler() function is executed
and user can add his own function by customization of function pointer
(#) CommandListCpltCallback (member of GPU2D handle structure) to notify the upper level
about the completion of Command List execution.
(#) Callback HAL_GPU2D_CommandListCpltCallback is invoked when the GPU2D hardware executes
the programmed command list (Command List execution completion).
(++) This callback is called when the compilation defines USE_HAL_GPU2D_REGISTER_CALLBACKS
is set to 0 or not defined.
(++) This callback should be implemented in the application side. It should notify
the upper level that the programmed command list is completed.
(#) To control the GPU2D state, use the following function: HAL_GPU2D_GetState().
(#) To read the GPU2D error code, use the following function: HAL_GPU2D_GetError().
*** GPU2D HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in GPU2D HAL driver :
(+) __HAL_GPU2D_RESET_HANDLE_STATE: Reset GPU2D handle state.
(+) __HAL_GPU2D_GET_FLAG: Get the GPU2D pending flags.
(+) __HAL_GPU2D_CLEAR_FLAG: Clear the GPU2D pending flags.
(+) __HAL_GPU2D_GET_IT_SOURCE: Check whether the specified GPU2D interrupt is enabled or not.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function @ref HAL_GPU2D_RegisterCallback() to register a user callback.
(#) Function @ref HAL_GPU2D_RegisterCallback() allows to register following callbacks:
(+) CommandListCpltCallback : callback for Command List completion.
(+) MspInitCallback : GPU2D MspInit.
(+) MspDeInitCallback : GPU2D MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function @ref HAL_GPU2D_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_GPU2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) CommandListCpltCallback : callback for Command List completion.
(+) MspInitCallback : GPU2D MspInit.
(+) MspDeInitCallback : GPU2D MspDeInit.
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_GPU2D_RegisterCallback before calling @ref HAL_GPU2D_DeInit
or @ref HAL_GPU2D_Init function.
When The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
[..]
(@) You can refer to the GPU2D HAL driver header file for more useful macros
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#ifdef HAL_GPU2D_MODULE_ENABLED
#if defined (GPU2D)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup GPU2D GPU2D
* @brief GPU2D HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
* @{
*/
/** @defgroup GPU2D_Write_Read Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPU2D register
* @param __INSTANCE__ GPU2D Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define GPU2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(*(__IO uint32_t *)(__INSTANCE__\
+ __REG__), __VALUE__)
/**
* @brief Read a value in GPU2D register
* @param __INSTANCE__ GPU2D Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define GPU2D_ReadReg(__INSTANCE__, __REG__) READ_REG(*(__IO uint32_t *)(__INSTANCE__ + __REG__))
/**
* @}
*/
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Functions GPU2D Exported Functions
* @{
*/
/** @defgroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the GPU2D
(+) De-initialize the GPU2D
@endverbatim
* @{
*/
/**
* @brief Initialize the GPU2D according to the specified
* parameters in the GPU2D_InitTypeDef and create the associated handle.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d)
{
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
if (hgpu2d->State == HAL_GPU2D_STATE_RESET)
{
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers in HAL_GPU2D_STATE_RESET only */
hgpu2d->CommandListCpltCallback = HAL_GPU2D_CommandListCpltCallback;
if (hgpu2d->MspInitCallback == NULL)
{
hgpu2d->MspInitCallback = HAL_GPU2D_MspInit;
}
/* Init the low level hardware */
hgpu2d->MspInitCallback(hgpu2d);
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
/* Init the low level hardware */
HAL_GPU2D_MspInit(hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Allocate lock resource and initialize it */
hgpu2d->Lock = HAL_UNLOCKED;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset the CommandListCpltCallback handler */
hgpu2d->CommandListCpltCallback = NULL;
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Update error code */
hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
/* Initialize the GPU2D state*/
hgpu2d->State = HAL_GPU2D_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return HAL_OK;
}
/**
* @brief Deinitializes the GPU2D peripheral registers to their default reset
* values.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
/* Process locked */
__HAL_LOCK(hgpu2d);
if (hgpu2d->State == HAL_GPU2D_STATE_READY)
{
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
if (hgpu2d->MspDeInitCallback == NULL)
{
hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit;
}
/* DeInit the low level hardware */
hgpu2d->MspDeInitCallback(hgpu2d);
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
/* Carry on with de-initialization of low level hardware */
HAL_GPU2D_MspDeInit(hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
}
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset the CommandListCpltCallback handler */
hgpu2d->CommandListCpltCallback = NULL;
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Update error code */
hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
/* Reset the GPU2D state*/
hgpu2d->State = HAL_GPU2D_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return HAL_OK;
}
/**
* @brief Initializes the GPU2D MSP.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_MspInit can be implemented in the user file.
*/
}
/**
* @brief DeInitializes the GPU2D MSP.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_MspDeInit can be implemented in the user file.
*/
}
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User GPU2D callback
* To be used instead of the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
* @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
* @param pCallback pointer to the callback function
* @note Weak predefined callback is defined for HAL_GPU2D_MSPINIT_CB_ID and HAL_GPU2D_MSPDEINIT_CB_ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
pGPU2D_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
/* Check the pCallback parameter is valid or not */
if (pCallback == NULL)
{
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
|| (hgpu2d->State == HAL_GPU2D_STATE_RESET))
{
switch (CallbackID)
{
case HAL_GPU2D_MSPINIT_CB_ID:
hgpu2d->MspInitCallback = pCallback;
break;
case HAL_GPU2D_MSPDEINIT_CB_ID:
hgpu2d->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Unregister a GPU2D callback
* GPU2D Callback is redirected to the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
* @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
* @note Callback pointers will be set to legacy weak predefined callbacks for HAL_GPU2D_MSPINIT_CB_ID and
* HAL_GPU2D_MSPDEINIT_CB_ID
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
|| (HAL_GPU2D_STATE_RESET == hgpu2d->State))
{
switch (CallbackID)
{
case HAL_GPU2D_MSPINIT_CB_ID:
hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; /* Legacy weak Msp Init */
break;
case HAL_GPU2D_MSPDEINIT_CB_ID:
hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; /* Legacy weak Msp DeInit */
break;
default :
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Register GPU2D Command List Complete Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param pCallback pointer to the Command List Complete Callback function
* @note Weak predefined callback is defined for Command List Complete
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
pGPU2D_CommandListCpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
/* Check the CallbackID is valid or not */
if (pCallback == NULL)
{
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
|| (HAL_GPU2D_STATE_RESET == hgpu2d->State))
{
hgpu2d->CommandListCpltCallback = pCallback;
}
else
{
status = HAL_ERROR;
}
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Unregister a GPU2D Command List Complete Callback
* GPU2D Command List Complete Callback is redirected to the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @note Callback pointer will be invalidate (NULL value)
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
|| (hgpu2d->State == HAL_GPU2D_STATE_RESET))
{
hgpu2d->CommandListCpltCallback = NULL; /* Invalidate the Callback pointer */
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/** @defgroup GPU2D_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Read GPU2D Register value.
(+) Write a value to GPU2D Register.
(+) handle GPU2D interrupt request.
(+) Command List Complete Transfer Complete callback.
@endverbatim
* @{
*/
/**
* @brief Read GPU2D Register. Helper function for the higher-level library.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param offset The register offset from GPU2D base address to read.
* @retval Register value
*/
uint32_t HAL_GPU2D_ReadRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset)
{
uint32_t value;
/* Check the GPU2D handle validity */
assert_param(hgpu2d != NULL);
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
assert_param(IS_GPU2D_OFFSET(offset));
/* No locking is required since reading a register is an atomic operation
* and doesn't incur a state change in hal_gpu2d. */
value = GPU2D_ReadReg(hgpu2d->Instance, offset);
return value;
}
/**
* @brief Write a value to GPU2D Register. Helper function for the higher-level library.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param offset The register offset from GPU2D base address to write.
* @param value The value to be written to provided register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value)
{
/* Check the GPU2D handle validity */
assert_param(hgpu2d != NULL);
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
assert_param(IS_GPU2D_OFFSET(offset));
/* No locking is required since writing a register is an atomic operation
* and doesn't incur a state change in hal_gpu2d. */
GPU2D_WriteReg(hgpu2d->Instance, offset, value);
return HAL_OK;
}
/**
* @brief Handle GPU2D interrupt request.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
{
uint32_t isr_flags = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_ITCTRL);
/* Command List Complete Interrupt management */
if ((isr_flags & GPU2D_FLAG_CLC) != 0U)
{
uint32_t last_cl_id;
/* Clear the completion flag */
__HAL_GPU2D_CLEAR_FLAG(hgpu2d, GPU2D_FLAG_CLC);
last_cl_id = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_CLID);
/* Command List Complete Callback */
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
if (hgpu2d->CommandListCpltCallback != NULL)
{
hgpu2d->CommandListCpltCallback(hgpu2d, last_cl_id);
}
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
HAL_GPU2D_CommandListCpltCallback(hgpu2d, last_cl_id);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
}
}
/**
* @brief Handle GPU2D Error interrupt request.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
{
HAL_GPU2D_ErrorCallback(hgpu2d);
}
/**
* @brief Command List Complete callback.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param CmdListID Command list ID that got completed.
* @retval None
*/
__weak void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
UNUSED(CmdListID);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_CommandListCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Error handler callback.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_ErrorCallback can be implemented in the user file.
The default implementation stops the execution as an error is considered
fatal and non recoverable.
*/
for (;;)
{
/* infinite loop */
}
}
/**
* @}
*/
/** @defgroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to:
(+) Get the GPU2D state
(+) Get the GPU2D error code
@endverbatim
* @{
*/
/**
* @brief Return the GPU2D state
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval GPU2D state
*/
HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d)
{
return hgpu2d->State;
}
/**
* @brief Return the GPU2D error code
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for GPU2D.
* @retval GPU2D Error Code
*/
uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d)
{
return hgpu2d->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* GPU2D */
#endif /* HAL_GPU2D_MODULE_ENABLED */

320
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.h Normal file
View File

@ -0,0 +1,320 @@
/**
******************************************************************************
* @file stm32u5xx_hal_gpu2d.h
* @author MCD Application Team
* @brief Header file of GPU2D HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_GPU2D_H
#define STM32U5xx_HAL_GPU2D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#if defined (GPU2D)
/** @addtogroup GPU2D GPU2D
* @brief GPU2D HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Types GPU2D Exported Types
* @{
*/
/**
* @brief HAL GPU2D State enumeration definition
*/
typedef enum
{
HAL_GPU2D_STATE_RESET = 0x00U, /*!< GPU2D not yet initialized or disabled */
HAL_GPU2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_GPU2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_GPU2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_GPU2D_STATE_ERROR = 0x04U
} HAL_GPU2D_StateTypeDef;
/**
* @brief GPU2D_TypeDef definition
*/
typedef uint32_t GPU2D_TypeDef;
/**
* @brief GPU2D handle Structure definition
*/
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
typedef struct __GPU2D_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
{
GPU2D_TypeDef Instance; /*!< GPU2D register base address. */
HAL_LockTypeDef Lock; /*!< GPU2D lock. */
HAL_GPU2D_StateTypeDef State; /*!< GPU2D transfer state. */
uint32_t ErrorCode; /*!< GPU2D error code. */
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
void (* CommandListCpltCallback)(struct __GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); /*!< GPU2D Command Complete Callback */
void (* MspInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp Init callback */
void (* MspDeInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp DeInit callback */
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
} GPU2D_HandleTypeDef;
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL GPU2D Callback ID enumeration definition
*/
typedef enum
{
HAL_GPU2D_MSPINIT_CB_ID = 0x00U, /*!< GPU2D MspInit callback ID */
HAL_GPU2D_MSPDEINIT_CB_ID = 0x01U, /*!< GPU2D MspDeInit callback ID */
} HAL_GPU2D_CallbackIDTypeDef;
/** @defgroup HAL_GPU2D_Callback_pointer_definition HAL GPU2D Callback pointer definition
* @brief HAL GPU2D Callback pointer definition
* @{
*/
typedef void (*pGPU2D_CallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d); /*!< pointer to an GPU2D Callback function */
typedef void (*pGPU2D_CommandListCpltCallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdID); /*!< pointer to an GPU2D Command List Complete Callback function */
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Constants GPU2D Exported Constants
* @{
*/
/** @defgroup GPU2D_Error_Code_definition GPU2D Error Code definition
* @brief GPU2D Error Code definition
* @{
*/
#define HAL_GPU2D_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_GPU2D_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
#define HAL_GPU2D_ERROR_INVALID_CALLBACK (0x00000002U) /*!< Invalid callback error */
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/** @defgroup GPU2D_Interrupt_configuration_definition GPU2D Interrupt configuration definition
* @brief GPU2D Interrupt definition
* @{
*/
#define GPU2D_IT_CLC 0x00000001U /*!< Command List Complete Interrupt */
/**
* @}
*/
/** @defgroup GPU2D_Flag_definition GPU2D Flag definition
* @brief GPU2D Flags definition
* @{
*/
#define GPU2D_FLAG_CLC 0x00000001U /*!< Command List Complete Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Macros GPU2D Exported Macros
* @{
*/
/** @brief Reset GPU2D handle state
* @param __HANDLE__: specifies the GPU2D handle.
* @retval None
*/
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_GPU2D_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
(__HANDLE__)->CommandListCpltCallback = NULL; \
} while(0)
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPU2D_STATE_RESET)
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Interrupt & Flag management */
/**
* @brief Get the GPU2D pending flags.
* @param __HANDLE__: GPU2D handle
* @param __FLAG__: flag to check.
* This parameter can be one of the following values:
* @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask
* @retval The state of FLAG.
*/
#define __HAL_GPU2D_GET_FLAG(__HANDLE__, __FLAG__) (READ_REG(*(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
+ GPU2D_ITCTRL)) & (__FLAG__))
/**
* @brief Clear the GPU2D pending flags.
* @param __HANDLE__: GPU2D handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask
* @retval None
*/
#define __HAL_GPU2D_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \
__IO uint32_t *tmpreg = \
(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
+ GPU2D_ITCTRL); \
CLEAR_BIT(*tmpreg, __FLAG__); \
} while(0U)
/**
* @brief Check whether the specified GPU2D interrupt source is enabled or not.
* @param __HANDLE__: GPU2D handle
* @param __INTERRUPT__: specifies the GPU2D interrupt source to check.
* This parameter can be one of the following values:
* @arg GPU2D_IT_CLC: Command List Complete interrupt mask
* @retval The state of INTERRUPT source.
*/
#define __HAL_GPU2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_REG(*(__IO uint32_t *)\
((uint32_t)(__HANDLE__)->Instance\
+ GPU2D_ITCTRL)) & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPU2D_Exported_Functions GPU2D Exported Functions
* @{
*/
/** @addtogroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d);
HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
pGPU2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
pGPU2D_CommandListCpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/** @addtogroup GPU2D_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
uint32_t HAL_GPU2D_ReadRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset);
HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value);
void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID);
void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d);
/**
* @}
*/
/** @addtogroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d);
uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d);
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup GPU2D_Private_Constants GPU2D Private Constants
* @{
*/
#define GPU2D_ITCTRL (0x0F8U) /*!< GPU2D Interrupt Control Register Offset */
#define GPU2D_CLID (0x148U) /*!< GPU2D Last Command List Identifier Register Offset */
#define GPU2D_BREAKPOINT (0x080U) /*!< GPU2D Breakpoint Register Offset */
#define GPU2D_SYS_INTERRUPT (0xff8U) /*!< GPU2D System Interrupt Register Offset */
/** @defgroup GPU2D_Offset GPU2D Last Register Offset
* @{
*/
#define GPU2D_OFFSET 0x1000U /*!< Last GPU2D Register Offset */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
* @{
*/
#define IS_GPU2D_OFFSET(OFFSET) ((OFFSET) < GPU2D_OFFSET)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPU2D) */
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_GPU2D_H */

540
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c
View File

@ -123,9 +123,50 @@
#define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
#define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */
#define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */
#if defined (HSPI1)
#define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */
#endif /* HSPI1 */
/* Definitions for GTZC TZSC & TZIC ALL register values */
/* TZSC1 / TZIC1 instances */
#if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx)
#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL)
#define TZSC1_SECCFGR2_ALL (0x000007FFUL)
#define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL)
#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL)
#define TZSC1_PRIVCFGR2_ALL (0x000007FFUL)
#define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL)
#define TZIC1_IER1_ALL (0x00EFFFFFUL)
#define TZIC1_IER2_ALL (0x000007FFUL)
#define TZIC1_IER3_ALL (0x0FFFFFFFUL)
#define TZIC1_IER4_ALL (0xFF1FC01FUL)
#define TZIC1_FCR1_ALL (0x00EFFFFFUL)
#define TZIC1_FCR2_ALL (0x000007FFUL)
#define TZIC1_FCR3_ALL (0x0FFFFFFFUL)
#define TZIC1_FCR4_ALL (0xFF1FC01FUL)
#elif defined(STM32U5F9xx) || defined(STM32U5G9xx)
#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL)
#define TZSC1_SECCFGR2_ALL (0x00000FFFUL)
#define TZSC1_SECCFGR3_ALL (0x1FFFFFFFUL)
#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL)
#define TZSC1_PRIVCFGR2_ALL (0x00000FFFUL)
#define TZSC1_PRIVCFGR3_ALL (0x1FFFFFFFUL)
#define TZIC1_IER1_ALL (0x00EFFFFFUL)
#define TZIC1_IER2_ALL (0x00000FFFUL)
#define TZIC1_IER3_ALL (0x1FFFFFFFUL)
#define TZIC1_IER4_ALL (0xFFDFC01FUL)
#define TZIC1_FCR1_ALL (0x00EFFFFFUL)
#define TZIC1_FCR2_ALL (0x00000FFFUL)
#define TZIC1_FCR3_ALL (0x1FFFFFFFUL)
#define TZIC1_FCR4_ALL (0xFFDFC01FUL)
#else
#define TZSC1_SECCFGR1_ALL (0x001FFFFFUL)
#define TZSC1_SECCFGR2_ALL (0x000001FFUL)
#define TZSC1_SECCFGR3_ALL (0x007FFFFFUL)
@ -143,6 +184,7 @@
#define TZIC1_FCR2_ALL (0x000001FFUL)
#define TZIC1_FCR3_ALL (0x007FFFFFUL)
#define TZIC1_FCR4_ALL (0x3F0FC01FUL)
#endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */
/* TZSC2 / TZIC2 instances */
#define TZSC2_SECCFGR1_ALL (0x00001BFFUL)
@ -526,9 +568,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
uint32_t MemBaseAddress,
MPCWM_ConfigTypeDef *pMPCWM_Desc)
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
const MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
uint32_t register_address;
uint32_t reg_value;
@ -538,11 +579,15 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
/* check entry parameters */
if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
|| (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE))
&& (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
|| ((pMPCWM_Desc->Offset % granularity) != 0U)
|| ((pMPCWM_Desc->Length % granularity) != 0U))
if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) ||
#if defined (FMC_BANK3)
(((MemBaseAddress == BKPSRAM_BASE) || (MemBaseAddress == FMC_BANK3)) &&
#else
((MemBaseAddress == BKPSRAM_BASE) &&
#endif /* FMC_BANK3 */
(pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) ||
((pMPCWM_Desc->Offset % granularity) != 0U) ||
((pMPCWM_Desc->Length % granularity) != 0U))
{
return HAL_ERROR;
}
@ -564,6 +609,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
}
break;
#if defined (FMC_BANK1)
case FMC_BANK1:
size = TZSC_MPCWM1_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
@ -578,6 +624,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
}
break;
#endif /* FMC_BANK1 */
#if defined (FMC_BANK3)
case FMC_BANK3:
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
* (Parameter already checked)
@ -585,6 +633,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
size = TZSC_MPCWM3_MEM_SIZE;
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
break;
#endif /* FMC_BANK3 */
case BKPSRAM_BASE:
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
* (Parameter already checked)
@ -592,6 +641,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
size = TZSC_MPCWM4_MEM_SIZE;
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
break;
#if defined (OCTOSPI2_BASE)
case OCTOSPI2_BASE:
size = TZSC_MPCWM5_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
@ -606,15 +656,30 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
}
break;
#endif /* OCTOSPI2_BASE */
#if defined (HSPI1)
case HSPI1_BASE:
size = TZSC_MPCWM6_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
{
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
}
else
{
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
* (Parameter already checked)
*/
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
}
break;
#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
}
if ((pMPCWM_Desc->Offset > size)
|| ((pMPCWM_Desc->Offset
+ pMPCWM_Desc->Length)
> size))
if ((pMPCWM_Desc->Offset > size) ||
((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size))
{
return HAL_ERROR;
}
@ -642,12 +707,13 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
* @brief Get a TZSC-MPCWM area configuration.
* @param MemBaseAddress WM identifier.
* @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
* When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of
* two MPCWM_ConfigTypeDef structures.
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
uint32_t MemBaseAddress,
MPCWM_ConfigTypeDef *pMPCWM_Desc)
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
uint32_t register_address;
uint32_t reg_value;
@ -660,18 +726,29 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
case OCTOSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
break;
#if defined (FMC_BANK1)
case FMC_BANK1:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
break;
#endif /* FMC_BANK1 */
#if defined (FMC_BANK3)
case FMC_BANK3:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
break;
#endif /* FMC_BANK3 */
case BKPSRAM_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
break;
#if defined (OCTOSPI2_BASE)
case OCTOSPI2_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
break;
#endif /* OCTOSPI2_BASE */
#if defined (HSPI1)
case HSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
break;
#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
@ -692,10 +769,17 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
if ((MemBaseAddress != FMC_BANK3) && (MemBaseAddress != BKPSRAM_BASE))
if ((MemBaseAddress != BKPSRAM_BASE)
#if defined (FMC_BANK3)
&& (MemBaseAddress != FMC_BANK3)
#endif /* FMC_BANK3 */
)
{
/* Here MemBaseAddress = OCTOSPI1_BASE, OCTOSPI2_BASE
* or FMC_BANK1 (already checked)
/* Here MemBaseAddress = OCTOSPI1_BASE, and the following memories if applicable :
* - OCTOSPI2_BASE
* - FMC_BANK1
* - FMC_BANK3
* - HSPI1
* Now take care of the second area, present on these sub-blocks
*/
switch (MemBaseAddress)
@ -703,12 +787,21 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
case OCTOSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
break;
#if defined (FMC_BANK1)
case FMC_BANK1:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
break;
#endif /* FMC_BANK1 */
#if defined (OCTOSPI2_BASE)
case OCTOSPI2_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
break;
#endif /* OCTOSPI2_BASE */
#if defined (HSPI1)
case HSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
break;
#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
@ -724,8 +817,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
/* read configuration register and update the descriptor for second area*/
reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
GTZC_TZSC_MPCWM_CFGR_SEC);
pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
}
@ -767,7 +860,7 @@ void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
* @param TZSC_Instance TZSC sub-block instance.
* @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
*/
uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance)
uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
{
return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
}
@ -799,10 +892,9 @@ uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance)
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
MPCBB_ConfigTypeDef *pMPCBB_desc)
const MPCBB_ConfigTypeDef *pMPCBB_desc)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
uint32_t reg_value;
uint32_t mem_size;
uint32_t size_in_superblocks;
uint32_t i;
@ -810,24 +902,25 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
/* check entry parameters */
if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
#if defined (SRAM3_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
|| ((pMPCBB_desc->SecureRWIllegalMode
!= GTZC_MPCBB_SRWILADIS_ENABLE)
&& (pMPCBB_desc->SecureRWIllegalMode
!= GTZC_MPCBB_SRWILADIS_DISABLE))
|| ((pMPCBB_desc->InvertSecureState
!= GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
&& (pMPCBB_desc->InvertSecureState
!= GTZC_MPCBB_INVSECSTATE_INVERTED)))
#endif /* SRAM3_BASE */
&& !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
#if defined (SRAM5_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
#endif /* SRAM6_BASE */
)
|| ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
&& (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
|| ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
&& (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
{
return HAL_ERROR;
}
/* write InvertSecureState and SecureRWIllegalMode properties */
/* assume their Position/Mask is identical for all sub-blocks */
reg_value = pMPCBB_desc->InvertSecureState;
reg_value |= pMPCBB_desc->SecureRWIllegalMode;
if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB1;
@ -838,46 +931,40 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
mpcbb_ptr = GTZC_MPCBB2;
mem_size = GTZC_MEM_SIZE(SRAM2);
}
#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB3;
mem_size = GTZC_MEM_SIZE(SRAM3);
}
else
#endif /* SRAM3_BASE */
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
/* Here MemBaseAddress is inside SRAM4 (parameter already checked) */
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB5;
mem_size = GTZC_MEM_SIZE(SRAM5);
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB6;
mem_size = GTZC_MEM_SIZE(SRAM6);
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
}
/* translate mem_size in number of super-blocks */
size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t size_mask;
/* write configuration and lock register information */
MODIFY_REG(mpcbb_ptr->CR,
GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
if (size_in_superblocks == 32U)
{
size_mask = 0xFFFFFFFFU;
}
else
{
size_mask = (1UL << size_in_superblocks) - 1U;
}
/* limitation: code not portable with memory > 512K */
MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
/* write SECCFGR register information */
for (i = 0U; i < size_in_superblocks; i++)
{
WRITE_REG(mpcbb_ptr->SECCFGR[i],
pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
}
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* write PRIVCFGR register information */
for (i = 0U; i < size_in_superblocks; i++)
{
@ -885,6 +972,40 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
}
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t size_mask;
uint32_t reg_value;
/* write SECCFGR register information */
for (i = 0U; i < size_in_superblocks; i++)
{
WRITE_REG(mpcbb_ptr->SECCFGR[i],
pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
}
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
if (size_in_superblocks >= 32U)
{
size_mask = 0xFFFFFFFFU;
MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]);
}
else
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
{
size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U;
}
/* limitation: code not portable with memory > 512K */
MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
/* write InvertSecureState and SecureRWIllegalMode properties */
reg_value = pMPCBB_desc->InvertSecureState;
reg_value |= pMPCBB_desc->SecureRWIllegalMode;
/* write configuration and lock register information */
MODIFY_REG(mpcbb_ptr->CR,
GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
return HAL_OK;
}
@ -906,8 +1027,17 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
/* check entry parameters */
if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
#if defined (SRAM3_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
#endif /* SRAM3_BASE */
&& !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
#if defined (SRAM5_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
#endif /* SRAM6_BASE */
)
{
return HAL_ERROR;
}
@ -924,16 +1054,36 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
mpcbb_ptr = GTZC_MPCBB2;
mem_size = GTZC_MEM_SIZE(SRAM2);
}
#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB3;
mem_size = GTZC_MEM_SIZE(SRAM3);
}
else
#endif /* SRAM3_BASE */
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB5;
mem_size = GTZC_MEM_SIZE(SRAM5);
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB6;
mem_size = GTZC_MEM_SIZE(SRAM6);
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
}
/* translate mem_size in number of super-blocks */
size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
@ -946,9 +1096,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
reg_value = READ_REG(mpcbb_ptr->CR);
pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
if (size_in_superblocks == 32U)
if (size_in_superblocks >= 32U)
{
size_mask = 0xFFFFFFFFU;
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2)
& 0x000FFFFFUL;
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
}
else
{
@ -977,13 +1131,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
* @param NbBlocks Number of blocks to configure
* (Block size is 512 Bytes).
* @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
* with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
* and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
* with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
* and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
uint32_t *pMemAttributes)
const uint32_t *pMemAttributes)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
uint32_t base_address;
@ -1026,6 +1180,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
mpcbb_ptr = GTZC_MPCBB2;
base_address = SRAM2_BASE_S;
}
#if defined (SRAM3_BASE)
else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
{
@ -1038,6 +1193,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
mpcbb_ptr = GTZC_MPCBB3;
base_address = SRAM3_BASE_S;
}
#endif /* SRAM3_BASE */
else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U)
{
@ -1050,6 +1206,34 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
mpcbb_ptr = GTZC_MPCBB4;
base_address = SRAM4_BASE_S;
}
#if defined (SRAM5_BASE)
else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB5;
base_address = SRAM5_BASE_NS;
}
else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB5;
base_address = SRAM5_BASE_S;
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB6;
base_address = SRAM6_BASE_NS;
}
else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB6;
base_address = SRAM6_BASE_S;
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@ -1067,13 +1251,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* secure configuration */
if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC)
{
SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
do_attr_change = 1U;
}
else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC)
{
CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
@ -1086,12 +1270,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* privilege configuration */
if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV)
{
SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
}
else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV)
{
CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
@ -1129,8 +1313,8 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
* (must be 512 Bytes aligned).
* @param NbBlocks Number of blocks to get configuration.
* @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
* with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
* and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
* with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
* and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
@ -1177,6 +1361,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
mpcbb_ptr = GTZC_MPCBB2_S;
base_address = SRAM2_BASE_S;
}
#if defined (SRAM3_BASE)
else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM3, end_address)))
{
@ -1189,6 +1374,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
mpcbb_ptr = GTZC_MPCBB3_S;
base_address = SRAM3_BASE_S;
}
#endif /* SRAM3_BASE */
else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM4, end_address)))
{
@ -1201,6 +1387,34 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
mpcbb_ptr = GTZC_MPCBB4_S;
base_address = SRAM4_BASE_S;
}
#if defined (SRAM5_BASE)
else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM5, end_address)))
{
mpcbb_ptr = GTZC_MPCBB5_NS;
base_address = SRAM5_BASE_NS;
}
else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM5, end_address)))
{
mpcbb_ptr = GTZC_MPCBB5_S;
base_address = SRAM5_BASE_S;
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM6, end_address)))
{
mpcbb_ptr = GTZC_MPCBB6_NS;
base_address = SRAM6_BASE_NS;
}
else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM6, end_address)))
{
mpcbb_ptr = GTZC_MPCBB6_S;
base_address = SRAM6_BASE_S;
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@ -1216,9 +1430,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U))
>> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U))
>> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK;
pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U))
>> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK;
offset_bit_start++;
if (offset_bit_start == 32U)
@ -1240,19 +1454,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
* @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
* with for each element:
* value 0 super-block is unlocked, value 1 super-block is locked
* (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
* GTZC_MCPBB_SUPERBLOCK_LOCKED values).
* (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
* GTZC_MPCBB_SUPERBLOCK_LOCKED values).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes)
const uint32_t *pLockAttributes)
{
__IO uint32_t *reg_mpcbb;
uint32_t base_address;
uint32_t superblock_start;
uint32_t offset_bit_start;
uint32_t i;
uint32_t i = 0U;
/* firstly check that MemAddress is well 16KBytes aligned */
if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
@ -1267,7 +1481,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB1_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
@ -1276,28 +1489,46 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB2_S->CFGLOCKR1;
}
#if defined (SRAM3_BASE)
else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
&& (IS_ADDRESS_IN(SRAM3, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM3);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB3_S->CFGLOCKR1;
}
#endif /* SRAM3_BASE */
else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
&& (IS_ADDRESS_IN(SRAM4, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM4);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB4_S->CFGLOCKR1;
}
#if defined (SRAM5_BASE)
else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
&& (IS_ADDRESS_IN(SRAM5, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM5);
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB5_S->CFGLOCKR1;
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
&& (IS_ADDRESS_IN(SRAM6, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM6);
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB6_S->CFGLOCKR1;
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@ -1307,13 +1538,14 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
offset_bit_start = superblock_start % 32U;
for (i = 0U; i < NbSuperBlocks; i++)
/* First 32 super-blocks */
while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
{
if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED)
{
SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED)
{
CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
@ -1323,8 +1555,36 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
}
offset_bit_start++;
i++;
}
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
{
/* Point to second configuration lock register */
reg_mpcbb++;
/* Remaining super-blocks */
for (; i < NbSuperBlocks; i++)
{
if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED)
{
SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED)
{
CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
else
{
break;
}
offset_bit_start++;
}
}
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
/* an unexpected value in pLockAttributes array leads to an error status */
if (i != NbSuperBlocks)
{
@ -1342,19 +1602,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
* @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
* with for each element:
* value 0 super-block is unlocked, value 1 super-block is locked
* (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
* GTZC_MCPBB_SUPERBLOCK_LOCKED values).
* (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
* GTZC_MPCBB_SUPERBLOCK_LOCKED values).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes)
{
uint32_t reg_mpcbb;
__IO uint32_t *reg_mpcbb;
uint32_t base_address;
uint32_t superblock_start;
uint32_t offset_bit_start;
uint32_t i;
uint32_t i = 0U;
/* firstly check that MemAddress is well 16KBytes aligned */
if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
@ -1369,8 +1629,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1;
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB1_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
&& (IS_ADDRESS_IN(SRAM2, (MemAddress
@ -1379,9 +1638,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1;
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB2_S->CFGLOCKR1;
}
#if defined (SRAM3_BASE)
else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
&& (IS_ADDRESS_IN(SRAM3, (MemAddress
+ (NbSuperBlocks
@ -1389,9 +1648,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM3);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1;
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB3_S->CFGLOCKR1;
}
#endif /* SRAM3_BASE */
else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
&& (IS_ADDRESS_IN(SRAM4, (MemAddress
+ (NbSuperBlocks
@ -1399,25 +1658,64 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM4);
/* limitation: code not portable with memory > 512K */
reg_mpcbb = GTZC_MPCBB4_S->CFGLOCKR1;
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB4_S->CFGLOCKR1;
}
#if defined (SRAM5_BASE)
else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
&& (IS_ADDRESS_IN(SRAM5, (MemAddress
+ (NbSuperBlocks
* GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM5);
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB5_S->CFGLOCKR1;
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
&& (IS_ADDRESS_IN(SRAM6, (MemAddress
+ (NbSuperBlocks
* GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM6);
reg_mpcbb = (__IO uint32_t *)&GTZC_MPCBB6_S->CFGLOCKR1;
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
}
/* get start coordinates of the configuration */
/* Get start coordinates of the configuration */
superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
offset_bit_start = superblock_start % 32U;
for (i = 0U; i < NbSuperBlocks; i++)
while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
{
pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
>> (offset_bit_start % 32U);
offset_bit_start++;
i++;
}
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
{
/* Point to second configuration lock register */
reg_mpcbb++;
/* Remaining super-blocks */
for (; i < NbSuperBlocks; i++)
{
pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
>> (offset_bit_start % 32U);
offset_bit_start++;
}
}
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
return HAL_OK;
}
@ -1438,14 +1736,28 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
{
SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM3_BASE*/
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@ -1457,7 +1769,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
/**
* @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
* @param MemBaseAddress MPCBB identifier.
* @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
* @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
@ -1472,14 +1784,28 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
{
*pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#if defined (SRAM3_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM3_BASE */
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM5_BASE */
#if defined (SRAM6_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM6_BASE */
else
{
return HAL_ERROR;
@ -1629,7 +1955,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
}
reg_value = READ_REG(GTZC_TZIC1->SR3);
for (i = 64; i < 96U; i++)
for (i = 64U; i < 96U; i++)
{
pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
}

135
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.h
View File

@ -41,19 +41,25 @@ extern "C" {
*/
/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */
#define GTZC_MCPBB_NB_VCTR_REG_MAX (32U)
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U)
#if defined (SRAM5_BASE)
#define GTZC_MPCBB_NB_VCTR_REG_MAX (52U) /* Up to 52 super-blocks */
#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (2U) /* More than one 32-bit needed */
#else
#define GTZC_MPCBB_NB_VCTR_REG_MAX (32U) /* Up to 32 super-blocks */
#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U) /* One 32-bit needed */
#endif /* SRAM5_BASE */
typedef struct
{
uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for
uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for
a super-block. Each bit corresponds to a block
inside the super-block. 0 means non-secure,
1 means secure */
uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for
uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for
a super-block. Each bit corresponds to a block
inside the super-block. 0 means non-privilege,
1 means privilege */
uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of
uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of
a super-block (32 blocks). 0 means unlocked,
1 means locked */
} MPCBB_Attribute_ConfigTypeDef;
@ -190,7 +196,9 @@ typedef struct
#define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos)
#define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos)
#define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
#if defined (USART2)
#define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos)
#endif /* USART2 */
#define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos)
#define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos)
#define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos)
@ -200,7 +208,18 @@ typedef struct
#define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos)
#define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos)
#define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos)
#if defined (UCPD1)
#define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos)
#endif /* UCPD1 */
#if defined (USART6)
#define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos)
#endif /* USART6 */
#if defined (I2C5)
#define GTZC_PERIPH_I2C5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C5_Pos)
#endif /* I2C5 */
#if defined (I2C6)
#define GTZC_PERIPH_I2C6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C6_Pos)
#endif /* I2C6 */
#define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos)
#define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
#define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
@ -209,47 +228,113 @@ typedef struct
#define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos)
#define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos)
#define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos)
#if defined (SAI2)
#define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos)
#endif /* SAI2 */
#if defined (LTDC) || defined (USB_DRD_FS)
#define GTZC_PERIPH_LTDCUSB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LTDCUSB_Pos)
#endif /* LTDC || USB_DRD_FS */
#if defined (DSI)
#define GTZC_PERIPH_DSI (GTZC1_PERIPH_REG2 | GTZC_CFGR2_DSI_Pos)
#endif /* DSI */
#if defined (GFXTIM)
#define GTZC_PERIPH_GFXTIM (GTZC1_PERIPH_REG2 | GTZC_CFGR2_GFXTIM_Pos)
#endif /* GFXTIM */
#define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos)
#define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos)
#define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos)
#define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos)
#define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos)
#if defined (DMA2D)
#define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos)
#endif /* DMA2D */
#define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos)
#define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos)
#define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos)
#define GTZC_PERIPH_DCMI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos)
#define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos)
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos)
#endif /* (USB_OTG_FS) || (USB_OTG_HS) */
#if defined (AES)
#define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos)
#endif /* AES */
#define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos)
#define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos)
#if defined (PKA)
#define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos)
#endif /* PKA */
#if defined (SAES)
#define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos)
#endif /* SAES */
#if defined (OCTOSPIM)
#define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos)
#endif /* OCTOSPIM */
#define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos)
#if defined (SDMMC2)
#define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos)
#endif /* SDMMC2 */
#if defined (FMC_BASE)
#define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos)
#endif /* FMC_BASE */
#define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos)
#if defined (OCTOSPI2)
#define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos)
#endif /* OCTOSPI2 */
#define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos)
#if defined (GPU2D)
#define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos)
#endif /* GPU2D */
#if defined (GFXMMU)
#define GTZC_PERIPH_GFXMMU (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_Pos)
#define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos)
#endif /* GFXMMU */
#if defined (HSPI1)
#define GTZC_PERIPH_HSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HSPI1_REG_Pos)
#endif /* HSPI1 */
#if defined (DCACHE2)
#define GTZC_PERIPH_DCACHE2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE2_REG_Pos)
#endif /* DCACHE2 */
#if defined (JPEG)
#define GTZC_PERIPH_JPEG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_JPEG_Pos)
#endif /* JPEG */
#define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos)
#define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos)
#define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos)
#if defined (OTFDEC2)
#define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos)
#endif /* OTFDEC2 */
#if defined (OTFDEC1)
#define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos)
#endif /* OTFDEC1 */
#define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos)
#define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos)
#define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos)
#if defined (FMC_BASE)
#define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos)
#endif /* FMC_BASE */
#define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos)
#if defined (OCTOSPI2)
#define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos)
#endif /* OCTOSPI2 */
#if defined (HSPI1)
#define GTZC_PERIPH_HSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_HSPI1_MEM_Pos)
#endif /* HSPI1 */
#if defined (SRAM6_BASE)
#define GTZC_PERIPH_SRAM6 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos)
#define GTZC_PERIPH_MPCBB6_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos)
#endif /* SRAM6_BASE */
#define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos)
#define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
#define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos)
#define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos)
#if defined (SRAM3_BASE)
#define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos)
#endif /* SRAM3_BASE */
#define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos)
#if defined (SRAM5_BASE)
#define GTZC_PERIPH_SRAM5 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM5_Pos)
#define GTZC_PERIPH_MPCBB5_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB5_REG_Pos)
#endif /* SRAM5_BASE */
/* GTZC2 */
#define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
@ -365,17 +450,17 @@ typedef struct
/* user-oriented definitions for MPCBB */
#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */
#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U)
#define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U)
#define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U)
#define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U)
#define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U)
#define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U)
#define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U)
#define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U)
#define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U)
#define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U)
#define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U)
#define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U)
/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */
#define GTZC_MCPBB_LOCK_OFF (0U)
#define GTZC_MCPBB_LOCK_ON (1U)
#define GTZC_MPCBB_LOCK_OFF (0U)
#define GTZC_MPCBB_LOCK_ON (1U)
/**
* @}
@ -481,7 +566,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
* @}
*/
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @addtogroup GTZC_Exported_Functions_Group2
* @brief MPCWM Initialization and Configuration functions
@ -489,7 +574,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
MPCWM_ConfigTypeDef *pMPCWM_Desc);
const MPCWM_ConfigTypeDef *pMPCWM_Desc);
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
MPCWM_ConfigTypeDef *pMPCWM_Desc);
/**
@ -502,45 +587,45 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd
*/
void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance);
uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance);
uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance);
/**
* @}
*/
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/** @addtogroup GTZC_Exported_Functions_Group4
* @brief MPCBB Initialization and Configuration functions
* @{
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
MPCBB_ConfigTypeDef *pMPCBB_desc);
const MPCBB_ConfigTypeDef *pMPCBB_desc);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
MPCBB_ConfigTypeDef *pMPCBB_desc);
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
uint32_t *pMemAttributes);
const uint32_t *pMemAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
uint32_t *pMemAttributes);
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes);
const uint32_t *pLockAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
uint32_t *pLockState);
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
*/
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @addtogroup GTZC_Exported_Functions_Group5
* @brief TZIC functions
@ -568,7 +653,7 @@ void HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
* @}
*/
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}

33
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c
View File

@ -123,7 +123,7 @@
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
This is why, for driver implementation simplicity's sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@ -158,9 +158,9 @@
[..]
(#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
Use function HAL_HASH_RegisterCallback() to register a user callback.
(#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
(#) Function HAL_HASH_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : callback for input completion.
(+) DgstCpltCallback : callback for digest computation completion.
(+) ErrorCallback : callback for error.
@ -169,9 +169,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
(#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : callback for input completion.
@ -180,13 +180,13 @@
(+) MspInitCallback : HASH MspInit.
(+) MspDeInitCallback : HASH MspDeInit.
(#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
(#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
reset to the legacy weak (surcharged) functions in the HAL_HASH_Init
and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
@ -194,8 +194,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
or @ref HAL_HASH_Init function.
using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit
or HAL_HASH_Init function.
When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@ -2941,6 +2941,14 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
return HAL_OK;
}
} /* if (polling_step == 1) */
else
{
/* otherwise, carry on in interrupt-mode */
hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
to be fed to the Peripheral */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
the next interruption */
}
/* Process Unlock */
@ -3556,3 +3564,4 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/**
* @}
*/

1
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.h
View File

@ -627,3 +627,4 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
#endif /* STM32U5xx_HAL_HASH_H */

1
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.c
View File

@ -1037,3 +1037,4 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
/**
* @}
*/

1
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.h
View File

@ -172,3 +172,4 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
#endif /* STM32U5xx_HAL_HASH_EX_H */

3590
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.c
View File

File diff suppressed because it is too large Load Diff

314
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.h
View File

@ -27,7 +27,7 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_ll_usb.h"
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
@ -53,11 +53,35 @@ typedef enum
HAL_HCD_STATE_TIMEOUT = 0x04
} HCD_StateTypeDef;
#if defined (USB_DRD_FS)
typedef USB_DRD_TypeDef HCD_TypeDef;
typedef USB_DRD_CfgTypeDef HCD_InitTypeDef;
typedef USB_DRD_HCTypeDef HCD_HCTypeDef;
typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef;
typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef;
#else
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
#endif /* defined (USB_DRD_FS) */
#if defined (USB_DRD_FS)
typedef enum
{
HCD_HCD_STATE_DISCONNECTED = 0x00U,
HCD_HCD_STATE_CONNECTED = 0x01U,
HCD_HCD_STATE_RESETED = 0x02U,
HCD_HCD_STATE_RUN = 0x03U,
HCD_HCD_STATE_SUSPEND = 0x04U,
HCD_HCD_STATE_RESUME = 0x05U,
} HCD_HostStateTypeDef;
/* PMA lookup Table size depending on PMA Size
* 8Bytes each Block 32Bit in each word
*/
#define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))
#endif /* defined (USB_DRD_FS) */
/**
* @}
*/
@ -74,6 +98,13 @@ typedef struct
HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
#if defined (USB_DRD_FS)
uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */
uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */
uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/
uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */
HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */
#endif /* defined (USB_DRD_FS) */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
__IO uint32_t ErrorCode; /*!< HCD Error code */
@ -159,14 +190,29 @@ typedef struct
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
& (__INTERRUPT__)) == (__INTERRUPT__))
#if defined (USB_DRD_FS)
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#else
#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#endif /* defined (USB_DRD_FS) */
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#if defined (USB_DRD_FS)
#define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
#define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)
#else
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT)
#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT)
#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN)
#endif /* defined (USB_DRD_FS) */
/**
* @}
*/
@ -186,6 +232,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t speed, uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
#if defined (USB_DRD_FS)
HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
#endif /* defined (USB_DRD_FS) */
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
@ -248,6 +297,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n
uint8_t token, uint8_t *pbuff,
uint16_t length, uint8_t do_ping);
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t addr, uint8_t PortNbr);
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
/* Non-Blocking mode: Interrupt */
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
@ -255,6 +309,10 @@ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
#if defined (USB_DRD_FS)
void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd);
#endif /* defined (USB_DRD_FS) */
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
HCD_URBStateTypeDef urb_state);
/**
@ -268,6 +326,11 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
#if defined (USB_DRD_FS)
HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd);
#endif /* defined (USB_DRD_FS) */
/**
* @}
*/
@ -283,9 +346,21 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
#if defined (USB_DRD_FS)
/* PMA Allocation functions **********************************************/
/** @addtogroup PMA Allocation
* @{
*/
HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint16_t ch_kind, uint16_t mps);
HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
#endif /* defined (USB_DRD_FS) */
/**
* @}
@ -295,6 +370,238 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/** @defgroup HCD_Private_Macros HCD Private Macros
* @{
*/
#if defined (USB_DRD_FS)
#define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
/** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel
* @{
*/
#define HCD_LOGICAL_CH_NOT_OPENED 0xFFU
#define HCD_FREE_CH_NOT_FOUND 0xFFU
/**
* @}
*/
/** @defgroup HCD_ENDP_Kind HCD Endpoint Kind
* @{
*/
#define HCD_SNG_BUF 0U
#define HCD_DBL_BUF 1U
/**
* @}
*/
/* Set Channel */
#define HCD_SET_CHANNEL USB_DRD_SET_CHEP
/* Get Channel Register */
#define HCD_GET_CHANNEL USB_DRD_GET_CHEP
/**
* @brief free buffer used from the application realizing it to the line
* toggles bit SW_BUF in the double buffered endpoint register
* @param USBx USB device.
* @param bChNum, bDir
* @retval None
*/
#define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
/**
* @brief Set the Setup bit in the corresponding channel, when a Setup
transaction is needed.
* @param USBx USB device.
* @param bChNum
* @retval None
*/
#define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
/**
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
* /STAT_RX[1:0])
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @retval status
*/
#define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS
#define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS
/**
* @brief Sets/clears CH_KIND bit in the Channel register.
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @retval None
*/
#define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND
#define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND
#define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND
#define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND
/**
* @brief Clears bit ERR_RX in the Channel register
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @retval None
*/
#define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR
/**
* @brief Clears bit ERR_TX in the Channel register
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @retval None
*/
#define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @retval None
*/
#define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR
#define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @retval None
*/
#define HCD_RX_DTOG USB_DRD_RX_DTOG
#define HCD_TX_DTOG USB_DRD_TX_DTOG
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @retval None
*/
#define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
#define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
/**
* @brief sets counter for the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @param wCount Counter value.
* @retval None
*/
#define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
#define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
/**
* @brief gets counter of the tx buffer.
* @param USBx USB peripheral instance register address.
* @param bChNum channel Number.
* @retval Counter value
*/
#define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
/**
* @brief gets counter of the rx buffer.
* @param Instance USB peripheral instance register address.
* @param bChNum channel Number.
* @retval Counter value
*/
__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
{
uint32_t HostCoreSpeed;
__IO uint32_t count = 10U;
/* Get Host core Speed */
HostCoreSpeed = USB_GetHostSpeed(Instance);
/* Count depends on device LS */
if (HostCoreSpeed == USB_DRD_SPEED_LS)
{
count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U;
}
if (count > 15U)
{
count = HCD_MAX(10U, (count - 15U));
}
/* WA: few cycles for RX PMA descriptor to update */
while (count > 0U)
{
count--;
}
return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum));
}
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bChNum Endpoint Number.
* @param bDir endpoint dir EP_DBUF_OUT = OUT
* EP_DBUF_IN = IN
* @param wCount: Counter value
* @retval None
*/
#define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
#define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
#define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT
/**
* @brief gets counter of the rx buffer0.
* @param Instance USB peripheral instance register address.
* @param bChNum channel Number.
* @retval Counter value
*/
__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
/* WA: few cycles for RX PMA descriptor to update */
while (count > 0U)
{
count--;
}
return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum));
}
/**
* @brief gets counter of the rx buffer1.
* @param Instance USB peripheral instance register address.
* @param bChNum channel Number.
* @retval Counter value
*/
__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
/* WA: few cycles for RX PMA descriptor to update */
while (count > 0U)
{
count--;
}
return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum));
}
#endif /* defined (USB_DRD_FS) */
/**
* @}
*/
@ -306,7 +613,10 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */
#ifdef __cplusplus
}

1710
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.c
View File

File diff suppressed because it is too large Load Diff

114
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.h
View File

@ -47,29 +47,30 @@ extern "C" {
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization
section in Reference manual */
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
@ -199,12 +200,16 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
#endif /*HAL_DMA_MODULE_ENABLED*/
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@ -215,21 +220,37 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
__IO uint32_t Devaddress; /*!< I2C Target device address */
__IO uint32_t Memaddress; /*!< I2C Target memory address */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
@ -258,8 +279,11 @@ typedef enum
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
@ -441,10 +465,10 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
@ -551,19 +575,19 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
@ -603,12 +627,14 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
@ -640,6 +666,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
#if defined(HAL_DMA_MODULE_ENABLED)
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
@ -660,6 +687,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @}
*/
@ -688,9 +716,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
@ -765,8 +793,10 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))

60
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.c
View File

@ -5,10 +5,10 @@
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + I2C Extended Filter Mode Functions
* + I2C Extended WakeUp Mode Functions
* + I2C I2C Extended FastModePlus Functions
* + I2C I2C Extended Autonomous Mode Functions
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
* + Autonomous Mode Functions
*
******************************************************************************
* @attention
@ -33,6 +33,7 @@
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
(+) Configure Autonomous mode
##### How to use this driver #####
==============================================================================
@ -76,12 +77,12 @@
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
* @brief I2C Extended Filter Mode Functions
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Extended Noise Filters functions #####
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@ -185,17 +186,16 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
return HAL_BUSY;
}
}
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
* @brief I2C Extended WakeUp Mode Functions
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### Extended WakeUp Mode functions #####
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@ -281,17 +281,16 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
return HAL_BUSY;
}
}
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
* @brief I2C Extended FastModePlus Functions
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Extended FastModePlus functions #####
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@ -353,12 +352,12 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group4 I2C Extended Autonomous Mode Functions
* @brief I2C Extended Autonomous Mode Functions
/** @defgroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions
* @brief Autonomous Mode Functions
*
@verbatim
===============================================================================
##### Extended Autonomous Mode functions #####
##### Autonomous Mode functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Autonomous Mode
@ -375,7 +374,8 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t
* the configuration information of the autonomous mode for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig)
HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c,
const I2C_AutonomousModeConfTypeDef *sConfig)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
@ -385,16 +385,18 @@ HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C
hi2c->State = HAL_I2C_STATE_BUSY;
/* Check the parameters */
assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection));
assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity));
/* Disable the selected I2C peripheral to be able to configure AUTOCR */
__HAL_I2C_DISABLE(hi2c);
/* I2Cx AUTOCR Configuration */
WRITE_REG(hi2c->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) |
sConfig->TriggerPolarity));
WRITE_REG(hi2c->Instance->AUTOCR,
(sConfig->TriggerState | \
((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \
sConfig->TriggerPolarity));
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
@ -420,10 +422,14 @@ HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C
* the configuration information of the autonomous mode for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig)
HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c,
I2C_AutonomousModeConfTypeDef *sConfig)
{
uint32_t autocr_tmp;
/* Check the parameters */
assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance));
autocr_tmp = hi2c->Instance->AUTOCR;
sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN);
@ -455,6 +461,9 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c)
hi2c->State = HAL_I2C_STATE_BUSY;
/* Check the parameters */
assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance));
/* Disable the selected I2C peripheral to be able to clear AUTOCR */
__HAL_I2C_DISABLE(hi2c);
@ -475,11 +484,6 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c)
return HAL_ERROR;
}
}
/**
* @}
*/
/**
* @}
*/

82
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.h
View File

@ -40,8 +40,7 @@ extern "C" {
* @{
*/
/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition I2C Autonomous Mode Configuration Structure
definition
/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration Structure definition
* @brief I2C Autonomous Mode Configuration structure definition
* @{
*/
@ -91,8 +90,8 @@ typedef struct
/** @defgroup I2CEx_AutonomousMode_FunctionalState I2C Extended Autonomous Mode State
* @{
*/
#define I2C_AUTO_MODE_DISABLE (0x00000000U) /* Autonomous mode disable */
#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /* Autonomous mode enable */
#define I2C_AUTO_MODE_DISABLE (0x00000000U) /*!< Autonomous mode disable */
#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /*!< Autonomous mode enable */
/**
* @}
*/
@ -100,67 +99,67 @@ typedef struct
/** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection
* @{
*/
#define I2C_TRIG_GRP1 (0x10000000U) /* Trigger Group for I2C1, I2C2 and I2C4 */
#define I2C_TRIG_GRP2 (0x20000000U) /* Trigger Group for I2C3 */
#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */
#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
/* HW Trigger signal is GPDMA_CH0_TRG */
#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
/* HW Trigger signal is GPDMA_CH1_TRG */
/*!< HW Trigger signal is GPDMA_CH0_TRG */
#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is GPDMA_CH2_TRG */
/*!< HW Trigger signal is GPDMA_CH1_TRG */
#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is GPDMA_CH3_TRG */
/*!< HW Trigger signal is GPDMA_CH2_TRG */
#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI5_TRG */
/*!< HW Trigger signal is GPDMA_CH3_TRG */
#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI9_TRG */
/*!< HW Trigger signal is EXTI5_TRG */
#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM1_CH1_TRG */
/*!< HW Trigger signal is EXTI9_TRG */
#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM2_CH1_TRG */
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP1_TRG */
/*!< HW Trigger signal is LPTIM2_CH1_TRG */
#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP2_TRG */
/*!< HW Trigger signal is COMP1_TRG */
#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_ALRA_TRG */
/*!< HW Trigger signal is COMP2_TRG */
#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_WUT_TRG */
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
/* HW Trigger signal is LPDMA_CH0_TRG */
#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
/* HW Trigger signal is LPDMA_CH1_TRG */
/*!< HW Trigger signal is LPDMA_CH0_TRG */
#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPDMA_CH2_TRG */
/*!< HW Trigger signal is LPDMA_CH1_TRG */
#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPDMA_CH3_TRG */
/*!< HW Trigger signal is LPDMA_CH2_TRG */
#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI5_TRG */
/*!< HW Trigger signal is LPDMA_CH3_TRG */
#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI8_TRG */
/*!< HW Trigger signal is EXTI5_TRG */
#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM1_CH1_TRG */
/*!< HW Trigger signal is EXTI8_TRG */
#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM3_CH1_TRG */
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP1_TRG */
/*!< HW Trigger signal is LPTIM3_CH1_TRG */
#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP2_TRG */
/*!< HW Trigger signal is COMP1_TRG */
#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_ALRA_TRG */
/*!< HW Trigger signal is COMP2_TRG */
#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_WUT_TRG */
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
/**
* @}
*/
/** @defgroup I2CEx_AutonomousMode_TriggerPolarity I2C Extended Autonomous Mode Trigger Polarity
/** @defgroup I2CEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity
* @{
*/
#define I2C_TRIG_POLARITY_RISING (0x00000000U) /* I2C HW Trigger signal on rising edge */
#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /* I2C HW Trigger signal on falling edge */
#define I2C_TRIG_POLARITY_RISING (0x00000000U) /*!< I2C HW Trigger signal on rising edge */
#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C HW Trigger signal on falling edge */
/**
* @}
*/
@ -183,7 +182,7 @@ typedef struct
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
@ -193,7 +192,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
@ -202,7 +201,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus);
@ -210,11 +209,13 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group4 I2C Extended Autonomous Mode Functions
/** @addtogroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c,
const I2C_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c,
I2C_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
/**
* @}
@ -278,6 +279,9 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \
((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG ))
#define IS_I2C_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_I2C_GRP1_INSTANCE(__INSTANCE__) || \
IS_I2C_GRP2_INSTANCE(__INSTANCE__))
#define IS_I2C_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == I2C_TRIG_POLARITY_RISING) || \
((__POLARITY__) == I2C_TRIG_POLARITY_FALLING))
/**

34
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.c
View File

@ -34,7 +34,7 @@
cache invalidate maintenance operation, error management and TrustZone
security support.
(+) The ICACHE provides additionnaly the possibility to remap input address
(+) The ICACHE provides additionally the possibility to remap input address
falling into up to four memory regions (used to remap aliased code in
external memories to the internal Code region, for execution)
@ -44,10 +44,13 @@
[..]
The ICACHE HAL driver can be used as follows:
(#) Enable and disable the Instruction Cache with respectively
@ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable()
(#) Optionally configure the Instruction Cache mode with
@ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration
does not suit the application requirements.
(#) Configure the Instruction Cache mode with @ref HAL_ICACHE_ConfigAssociativityMode()
(#) Enable and disable the Instruction Cache with respectively
@ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable().
Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
(#) Initiate the cache maintenance invalidation procedure with either
@ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT()
@ -233,9 +236,9 @@ HAL_StatusTypeDef HAL_ICACHE_Disable(void)
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Reset BSYENDF before to disable the instruction cache */
/* that starts a cache invalidation procedure */
CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Make sure BSYENDF is reset before to disable the instruction cache */
/* as it automatically starts a cache invalidation procedure */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
@ -259,6 +262,15 @@ HAL_StatusTypeDef HAL_ICACHE_Disable(void)
return status;
}
/**
* @brief Check whether the Instruction Cache is enabled or not.
* @retval Status (0: disabled, 1: enabled)
*/
uint32_t HAL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);
}
/**
* @brief Invalidate the Instruction Cache.
* @note This function waits for the end of cache invalidation procedure
@ -277,7 +289,7 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
else
{
/* Make sure BSYENDF is reset before to start cache invalidation */
CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
@ -307,7 +319,7 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
}
else
{
/* Make sure BSYENDF is reset */
/* Make sure BSYENDF is reset before to start cache invalidation */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Enable end of cache invalidation interrupt */
@ -475,7 +487,7 @@ void HAL_ICACHE_IRQHandler(void)
/* Disable error interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
/* Clear ICACHE error pending flag */
/* Clear ERR pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
/* Instruction cache error interrupt user callback */
@ -488,7 +500,7 @@ void HAL_ICACHE_IRQHandler(void)
/* Disable end of cache invalidation interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Clear ICACHE busyend pending flag */
/* Clear BSYENDF pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Instruction cache busyend interrupt user callback */

1
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.h
View File

@ -226,6 +226,7 @@ typedef struct
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_ICACHE_Enable(void);
HAL_StatusTypeDef HAL_ICACHE_Disable(void);
uint32_t HAL_ICACHE_IsEnabled(void);
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
HAL_StatusTypeDef HAL_ICACHE_DeInit(void);

125
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c
View File

@ -125,8 +125,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
Use Function HAL_IRDA_RegisterCallback() to register a user callback.
Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@ -141,9 +141,9 @@
and a pointer to the user callback function.
[..]
Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@ -158,13 +158,13 @@
(+) MspDeInitCallback : IRDA MspDeInit.
[..]
By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@ -173,8 +173,8 @@
in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
or @ref HAL_IRDA_Init() function.
using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
or HAL_IRDA_Init() function.
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
@ -182,6 +182,7 @@
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -243,8 +244,11 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
#if defined(HAL_DMA_MODULE_ENABLED)
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
#endif /* HAL_DMA_MODULE_ENABLED */
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
#if defined(HAL_DMA_MODULE_ENABLED)
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
@ -255,6 +259,7 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
#endif /* HAL_DMA_MODULE_ENABLED */
static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
@ -462,6 +467,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
* @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@ -490,8 +497,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_READY)
{
@ -576,15 +581,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hirda);
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
* @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@ -604,9 +608,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hirda);
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
@ -692,9 +693,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hirda);
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
@ -800,10 +798,10 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
* @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint8_t *pdata8bits;
uint16_t *pdata16bits;
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
@ -830,7 +828,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
pdata8bits = NULL;
pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
}
else
{
@ -979,7 +977,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
@ -1051,8 +1049,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the IRDA Parity Error and Data Register not empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
/* Enable the IRDA Parity Error and Data Register not empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
}
else
{
/* Enable the IRDA Data Register not empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@ -1065,6 +1071,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
}
}
#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
@ -1076,7 +1083,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
uint16_t nbByte = Size;
@ -1272,8 +1279,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the UART Parity Error Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
/* Enable the UART Parity Error Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@ -1365,7 +1375,10 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the IRDA DMA Rx request */
@ -1447,6 +1460,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
return HAL_OK;
}
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief Abort ongoing transfers (blocking mode).
@ -1468,6 +1482,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
#if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
@ -1517,6 +1532,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
}
}
}
#endif /* HAL_DMA_MODULE_ENABLED */
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0U;
@ -1553,6 +1569,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
#if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
@ -1577,6 +1594,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
}
}
}
#endif /* HAL_DMA_MODULE_ENABLED */
/* Reset Tx transfer counter */
hirda->TxXferCount = 0U;
@ -1606,6 +1624,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
#if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
@ -1630,6 +1649,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
}
}
}
#endif /* HAL_DMA_MODULE_ENABLED */
/* Reset Rx transfer counter */
hirda->RxXferCount = 0U;
@ -1667,6 +1687,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
#if defined(HAL_DMA_MODULE_ENABLED)
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
@ -1745,6 +1766,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
}
}
}
#endif /* HAL_DMA_MODULE_ENABLED */
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if (abortcplt == 1U)
@ -1796,6 +1818,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
#if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
@ -1834,6 +1857,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
}
}
else
#endif /* HAL_DMA_MODULE_ENABLED */
{
/* Reset Tx transfer counter */
hirda->TxXferCount = 0U;
@ -1875,6 +1899,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
#if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
@ -1916,6 +1941,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
}
}
else
#endif /* HAL_DMA_MODULE_ENABLED */
{
/* Reset Rx transfer counter */
hirda->RxXferCount = 0U;
@ -2024,6 +2050,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
IRDA_EndRxTransfer(hirda);
#if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
@ -2055,6 +2082,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
}
else
#endif /* HAL_DMA_MODULE_ENABLED */
{
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
@ -2256,7 +2284,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
uint32_t temp1;
@ -2273,7 +2301,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
}
@ -2361,21 +2389,21 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
case IRDA_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
default:
ret = HAL_ERROR;
@ -2385,7 +2413,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
hirda->Instance->BRR = tmpreg;
hirda->Instance->BRR = (uint16_t)tmpreg;
}
else
{
@ -2443,11 +2471,12 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
}
/**
* @brief Handle IRDA Communication Timeout.
* @brief Handle IRDA Communication Timeout. It waits
* until a flag is no longer in the specified status.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param Flag Specifies the IRDA flag to check.
* @param Status Flag status (SET or RESET)
* @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
@ -2481,6 +2510,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
}
#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
@ -2495,7 +2525,7 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
/* At end of Tx process, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
}
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
@ -2514,6 +2544,7 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
}
#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA IRDA transmit process complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
@ -2837,6 +2868,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
HAL_IRDA_AbortReceiveCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @brief Send an amount of data in interrupt mode.
@ -2848,7 +2880,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
uint16_t *tmp;
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
@ -2865,7 +2897,7 @@ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
hirda->pTxBuffPtr += 2U;
}
@ -2973,3 +3005,4 @@ static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
* @}
*/

19
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.h
View File

@ -143,7 +143,7 @@ typedef struct
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
@ -157,10 +157,12 @@ typedef struct
uint16_t Mask; /*!< USART RX RDR register mask */
#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
#endif /* HAL_DMA_MODULE_ENABLED */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
@ -266,7 +268,9 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
#if defined(HAL_DMA_MODULE_ENABLED)
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#endif /* HAL_DMA_MODULE_ENABLED */
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
@ -827,15 +831,17 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
#endif /* HAL_DMA_MODULE_ENABLED */
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
@ -865,8 +871,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
*/
/* Peripheral State and Error functions ***************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
/**
* @}
@ -889,3 +895,4 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
#endif
#endif /* STM32U5xx_HAL_IRDA_H */

95
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda_ex.h
View File

@ -203,7 +203,7 @@ extern "C" {
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#elif defined(USART2)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@ -316,6 +316,98 @@ extern "C" {
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* USART6 */
/** @brief Compute the mask to apply to retrieve the received data
@ -390,3 +482,4 @@ extern "C" {
#endif
#endif /* STM32U5xx_HAL_IRDA_EX_H */

26
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c
View File

@ -128,14 +128,16 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register needs up to 5 LSI clock periods divided by the clock
prescaler to be updated. The number of LSI clock periods is upper-rounded to
6 for the timeout value calculation.
The timeout value is also calculated using the highest prescaler (256) and
/* Status register needs up to 5 LSI clock periods to be updated. However a
synchronisation is added on prescaled LSI clock rising edge, so we only
consider a highest prescaler cycle.
The timeout value is calculated using the highest prescaler (1024) and
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
@ -224,20 +226,16 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
if (hiwdg->Init.EWI == IWDG_EWI_DISABLE)
{
/* EWI comparator value different from 0,
* Disable the early wakeup interrupt
/* EWI comparator value equal 0, disable the early wakeup interrupt
* acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register
* Set Watchdog Early Wakeup Comparator to 0x00
*/
* Set Watchdog Early Wakeup Comparator to 0x00 */
hiwdg->Instance->EWCR = IWDG_EWCR_EWIC;
}
else
{
/* EWI comparator value different from 0,
* Enable the early wakeup interrupt
/* EWI comparator value different from 0, enable the early wakeup interrupt,
* acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register
* Set Watchdog Early Wakeup Comparator value
*/
* Set Watchdog Early Wakeup Comparator value */
hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI;
}

2
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.h
View File

@ -66,7 +66,7 @@ typedef struct
typedef struct __IWDG_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_IWDG_REGISTER_CALLBACKS) */
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
{
IWDG_TypeDef *Instance; /*!< Register base address */

588
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.c
View File

File diff suppressed because it is too large Load Diff

95
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.h
View File

@ -27,6 +27,9 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/* Include low level driver */
#include "stm32u5xx_ll_lptim.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
@ -104,7 +107,7 @@ typedef struct
uint32_t Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter can be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
Min_Data = 0x0001 and Max_Data = 0xFFFF. */
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
values is done immediately or after the end of current period.
@ -230,10 +233,10 @@ typedef struct
void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Update event detection Callback */
void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter register write complete Callback */
void (* UpdateEventHalfCpltCallback)(struct __LPTIM_HandleTypeDef *hlptim);/*!< Update event half complete detection Callback */
void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Error Callback */
void (* IC_CaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Input capture Callback */
void (* IC_CaptureHalfCpltCallback)(struct __LPTIM_HandleTypeDef *htim); /*!< Input Capture half complete Callback */
void (* IC_OverCaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Over capture Callback */
void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Error Callback */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
} LPTIM_HandleTypeDef;
@ -255,10 +258,10 @@ typedef enum
HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Update event detection Callback ID */
HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU, /*!< Repetition counter register write complete Callback ID */
HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID = 0x0BU, /*!< Update event half complete detection Callback ID */
HAL_LPTIM_IC_CAPTURE_CB_ID = 0x0CU, /*!< Input capture Callback ID */
HAL_LPTIM_IC_CAPTURE_HALF_CB_ID = 0x0DU, /*!< Input capture half complete Callback ID */
HAL_LPTIM_OVER_CAPTURE_CB_ID = 0x0EU, /*!< Over capture Callback ID */
HAL_LPTIM_ERROR_CB_ID = 0x0FU, /*!< LPTIM Error Callback ID */
HAL_LPTIM_ERROR_CB_ID = 0x0CU, /*!< LPTIM Error Callback ID */
HAL_LPTIM_IC_CAPTURE_CB_ID = 0x0DU, /*!< Input capture Callback ID */
HAL_LPTIM_IC_CAPTURE_HALF_CB_ID = 0x0EU, /*!< Input capture half complete Callback ID */
HAL_LPTIM_OVER_CAPTURE_CB_ID = 0x0FU, /*!< Over capture Callback ID */
} HAL_LPTIM_CallbackIDTypeDef;
/**
@ -464,9 +467,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
/** @defgroup LPTIM_Channel LPTIM Channel
* @{
*/
#define LPTIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
#define LPTIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
#define LPTIM_CHANNEL_ALL 0x00000013U /*!< Global Capture/compare channel identifier */
#define LPTIM_CHANNEL_1 LL_LPTIM_CHANNEL_CH1 /*!< Capture/compare channel 1 identifier */
#define LPTIM_CHANNEL_2 LL_LPTIM_CHANNEL_CH2 /*!< Capture/compare channel 2 identifier */
/**
* @}
*/
@ -703,10 +705,15 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
* @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag.
* @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag.
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag.
* @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag.
* @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag.
* @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag.
* @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag.
* @retval The state of the specified flag (SET or RESET).
*/
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
@ -721,10 +728,15 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
* @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag.
* @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag.
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag.
* @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag.
* @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag.
* @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag.
* @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag.
* @retval None.
*/
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@ -739,10 +751,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt.
* @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt.
* @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt.
* @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt.
* @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is enabled.
*/
@ -758,10 +774,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt.
* @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt.
* @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt.
* @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt.
* @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is enabled.
*/
@ -799,10 +819,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt.
* @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt.
* @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt.
* @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt.
* @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt.
* @retval Interrupt status.
*/
@ -838,7 +862,7 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
* @{
*/
/* Config functions **********************************************************/
HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig,
HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
uint32_t Channel);
/* Start/Stop operation functions *********************************************/
@ -849,7 +873,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Chann
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
uint32_t Length);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
@ -895,7 +919,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################## Input Capture Mode ###############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig,
HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
@ -914,9 +938,10 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Ch
* @{
*/
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
/**
* @}
*/
@ -959,7 +984,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
* @{
*/
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
@ -1048,17 +1073,16 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
((__AUTORELOAD__) <= 0x0000FFFFUL))
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
((__PERIOD__) <= 0x0000FFFFUL))
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define IS_LPTIM_CHANNELS(__INSTANCE__, __CHANNEL__) (((__CHANNEL__) == LPTIM_CHANNEL_1) || \
((__CHANNEL__) == LPTIM_CHANNEL_2))
#define IS_LPTIM_OC_POLARITY(__OCPOLARITY__) (((__OCPOLARITY__) == LPTIM_OCPOLARITY_LOW) || \
((__OCPOLARITY__) == LPTIM_OCPOLARITY_HIGH))
#define IS_LPTIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_ICPSC_DIV1) ||\
@ -1132,18 +1156,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
(((((__INSTANCE__) == LPTIM1_NS) || ((__INSTANCE__) == LPTIM1_S)) && \
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
((__CHANNEL__) == LPTIM_CHANNEL_2) || \
((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \
((__CHANNEL__) == LPTIM_CHANNEL_2))) \
|| \
((((__INSTANCE__) == LPTIM2_NS) || ((__INSTANCE__) == LPTIM2_S)) && \
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
((__CHANNEL__) == LPTIM_CHANNEL_2) || \
((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \
((__CHANNEL__) == LPTIM_CHANNEL_2))) \
|| \
((((__INSTANCE__) == LPTIM3_NS) || ((__INSTANCE__) == LPTIM3_S)) && \
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
((__CHANNEL__) == LPTIM_CHANNEL_2) || \
((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \
((__CHANNEL__) == LPTIM_CHANNEL_2))) \
|| \
((((__INSTANCE__) == LPTIM4_NS) || ((__INSTANCE__) == LPTIM4_S)) && \
((__CHANNEL__) == LPTIM_CHANNEL_1)))

2215
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c Normal file
View File

File diff suppressed because it is too large Load Diff

719
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.h Normal file
View File

@ -0,0 +1,719 @@
/**
******************************************************************************
* @file stm32u5xx_hal_ltdc.h
* @author MCD Application Team
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_LTDC_H
#define STM32U5xx_HAL_LTDC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
#if defined (LTDC)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Types LTDC Exported Types
* @{
*/
#define MAX_LAYER 2U
/**
* @brief LTDC color structure definition
*/
typedef struct
{
uint8_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Reserved; /*!< Reserved 0xFF */
} LTDC_ColorTypeDef;
/**
* @brief LTDC Init structure definition
*/
typedef struct
{
uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
This parameter can be one value of @ref LTDC_HS_POLARITY */
uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
This parameter can be one value of @ref LTDC_VS_POLARITY */
uint32_t DEPolarity; /*!< configures the data enable polarity.
This parameter can be one of value of @ref LTDC_DE_POLARITY */
uint32_t PCPolarity; /*!< configures the pixel clock polarity.
This parameter can be one of value of @ref LTDC_PC_POLARITY */
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must be a number between
Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
This parameter must be a number between
Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
This parameter must be a number between
Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
This parameter must be a number between
Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
uint32_t TotalWidth; /*!< configures the total width.
This parameter must be a number between
Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
uint32_t TotalHeigh; /*!< configures the total height.
This parameter must be a number between
Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
} LTDC_InitTypeDef;
/**
* @brief LTDC Layer structure definition
*/
typedef struct
{
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
This parameter must be a number between
Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Alpha0; /*!< Configures the default alpha value.
This parameter must be a number between
Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
uint32_t BlendingFactor2; /*!< Select the blending factor 2.
This parameter can be one of value of @ref LTDC_BlendingFactor2 */
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0x1FFF. */
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
This parameter must be a number between
Min_Data = 0x000 and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
} LTDC_LayerCfgTypeDef;
/**
* @brief HAL LTDC State structures definition
*/
typedef enum
{
HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
} HAL_LTDC_StateTypeDef;
/**
* @brief LTDC handle Structure definition
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
typedef struct __LTDC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
{
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
LTDC_InitTypeDef Init; /*!< LTDC parameters */
LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
HAL_LockTypeDef Lock; /*!< LTDC Lock */
__IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
__IO uint32_t ErrorCode; /*!< LTDC Error code */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */
void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */
void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */
void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */
void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
} LTDC_HandleTypeDef;
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LTDC Callback ID enumeration definition
*/
typedef enum
{
HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */
HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */
HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */
HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */
HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */
} HAL_LTDC_CallbackIDTypeDef;
/**
* @brief HAL LTDC Callback pointer definition
*/
typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
* @{
*/
/** @defgroup LTDC_Error_Code LTDC Error Code
* @{
*/
#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */
#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup LTDC_Layer LTDC Layer
* @{
*/
#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */
#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */
/**
* @}
*/
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{
*/
#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{
*/
#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
* @{
*/
#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/**
* @}
*/
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{
*/
#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/**
* @}
*/
/** @defgroup LTDC_SYNC LTDC SYNC
* @{
*/
#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */
#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
/**
* @}
*/
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
* @{
*/
#define LTDC_COLOR 0x000000FFU /*!< Color mask */
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{
*/
#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{
*/
#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
/**
* @}
*/
/** @defgroup LTDC_Alpha LTDC Alpha
* @{
*/
#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */
/**
* @}
*/
/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
* @{
*/
#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */
#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
/**
* @}
*/
/** @defgroup LTDC_Interrupts LTDC Interrupts
* @{
*/
#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */
#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */
#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */
#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */
/**
* @}
*/
/** @defgroup LTDC_Flags LTDC Flags
* @{
*/
#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */
#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */
#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */
#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */
/**
* @}
*/
/** @defgroup LTDC_Reload_Type LTDC Reload Type
* @{
*/
#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
* @{
*/
/** @brief Reset LTDC handle state.
* @param __HANDLE__ LTDC handle
* @retval None
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @brief Enable the LTDC.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
/**
* @brief Disable the LTDC.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
/**
* @brief Enable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be enabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
|= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be disabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
&= ~(uint32_t)LTDC_LxCR_LEN)
/**
* @brief Reload immediately all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
/**
* @brief Reload during vertical blanking period all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
/* Interrupt & Flag management */
/**
* @brief Get the LTDC pending flags.
* @param __HANDLE__ LTDC handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clears the LTDC pending flags.
* @param __HANDLE__ LTDC handle
* @param __FLAG__ Specify the flag to clear.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enables the specified LTDC interrupts.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disables the specified LTDC interrupts.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified LTDC interrupt has occurred or not.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt source to check.
* This parameter can be one of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval The state of INTERRUPT (SET or RESET).
*/
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/**
* @}
*/
/* Include LTDC HAL Extension module */
#include "stm32u5xx_hal_ltdc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
* @{
*/
/** @addtogroup LTDC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
pLTDC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions *************************************************/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\
((uint32_t)((__HANDLE__)->Instance))\
+ 0x84U + (0x80U*(__LAYER__)))))
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
|| ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
|| ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
|| ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
|| ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LTDC_Private_Functions LTDC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC */
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_LTDC_H */

151
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.c Normal file
View File

@ -0,0 +1,151 @@
/**
******************************************************************************
* @file stm32u5xx_hal_ltdc_ex.c
* @author MCD Application Team
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
#if defined (LTDC) && defined (DSI)
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
VidCfg->VerticalActive - 1U;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
/**
* @}
*/

83
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.h Normal file
View File

@ -0,0 +1,83 @@
/**
******************************************************************************
* @file stm32u5xx_hal_ltdc_ex.h
* @author MCD Application Team
* @brief Header file of LTDC HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_LTDC_EX_H
#define STM32U5xx_HAL_LTDC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
#if defined (LTDC) && defined (DSI)
#include "stm32u5xx_hal_dsi.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup LTDCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDCEx_Exported_Functions
* @{
*/
/** @addtogroup LTDCEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_LTDC_EX_H */

41
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c
View File

@ -237,7 +237,11 @@
/** @defgroup MDF_Private_Constants MDF Private Constants
* @{
*/
#if defined(STM32U535xx) || defined(STM32U545xx)
#define MDF_INSTANCE_NUMBER 3U /* 2 instances for MDF1 and 1 instance for ADF1 */
#else /* defined(STM32U535xx) || defined(STM32U545xx) */
#define MDF_INSTANCE_NUMBER 7U /* 6 instances for MDF1 and 1 instance for ADF1 */
#endif /* defined(STM32U535xx) || defined(STM32U545xx) */
/**
* @}
*/
@ -913,7 +917,7 @@ HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf)
* @param pFilterConfig Filter configuration parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig)
HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -1135,7 +1139,7 @@ HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t T
* @param pValue Acquisition value on 24 MSB.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GetAcqValue(MDF_HandleTypeDef *hmdf, int32_t *pValue)
HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue)
{
HAL_StatusTypeDef status = HAL_OK;
@ -1290,7 +1294,7 @@ HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf)
* @param pFilterConfig Filter configuration parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig)
HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -1470,8 +1474,8 @@ HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf)
* @param pDmaConfig DMA configuration parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig,
MDF_DmaConfigTypeDef *pDmaConfig)
HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig,
const MDF_DmaConfigTypeDef *pDmaConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -1686,7 +1690,7 @@ HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf)
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GenerateTrgo(MDF_HandleTypeDef *hmdf)
HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
@ -1766,7 +1770,7 @@ HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay)
* This value is between Min_Data = 0 and Max_Data = 127.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GetDelay(MDF_HandleTypeDef *hmdf, uint32_t *pDelay)
HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay)
{
HAL_StatusTypeDef status = HAL_OK;
@ -1843,7 +1847,7 @@ HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain)
* This parameter is between Min_Data = -16 and Max_Data = 24.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GetGain(MDF_HandleTypeDef *hmdf, int32_t *pGain)
HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain)
{
HAL_StatusTypeDef status = HAL_OK;
@ -1919,7 +1923,7 @@ HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset)
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_GetOffset(MDF_HandleTypeDef *hmdf, int32_t *pOffset)
HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset)
{
HAL_StatusTypeDef status = HAL_OK;
@ -2346,7 +2350,7 @@ HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf)
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig)
HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -2502,7 +2506,7 @@ HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf)
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig)
HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -2624,7 +2628,7 @@ HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf)
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig)
HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -2835,7 +2839,7 @@ HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf)
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig)
HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -3233,7 +3237,7 @@ __weak void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf)
* @param hmdf MDF handle.
* @retval MDF state.
*/
HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf)
HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf)
{
/* Return MDF state */
return hmdf->State;
@ -3244,7 +3248,7 @@ HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf)
* @param hmdf MDF handle.
* @retval MDF error code.
*/
uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf)
uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf)
{
/* Return MDF error code */
return hmdf->ErrorCode;
@ -3281,6 +3285,7 @@ static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const
{
handle_number = 1U;
}
#if !defined(STM32U535xx) && !defined(STM32U545xx)
else if (pInstance == MDF1_Filter2)
{
handle_number = 2U;
@ -3301,6 +3306,12 @@ static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const
{
handle_number = 6U;
}
#else /* !defined(STM32U535xx) && !defined(STM32U545xx) */
else /* ADF1_Filter0 */
{
handle_number = 2U;
}
#endif /* !defined(STM32U535xx) && !defined(STM32U545xx) */
return handle_number;
}

59
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.h
View File

@ -83,7 +83,9 @@ typedef struct
{
uint32_t InterleavedFilters; /*!< Number of filters in interleaved mode with filter 0.
This parameter must be a number between Min_Data = 0
and Max_Data = 5.
and Max_Data = 1 for STM32U535xx/STM32U545xx devices.
This parameter must be a number between Min_Data = 0
and Max_Data = 5 for other devices.
@note This parameter is not used for ADF instance */
uint32_t ProcClockDivider; /*!< Processing clock divider.
This parameter must be a number between Min_Data = 1
@ -467,6 +469,7 @@ typedef struct
#define MDF_BITSTREAM1_RISING MDF_BSMXCR_BSSEL_1 /*!< @note Not available for ADF instance */
#define MDF_BITSTREAM1_FALLING (MDF_BSMXCR_BSSEL_0 | \
MDF_BSMXCR_BSSEL_1) /*!< @note Not available for ADF instance */
#if !defined(STM32U535xx) && !defined(STM32U545xx)
#define MDF_BITSTREAM2_RISING MDF_BSMXCR_BSSEL_2 /*!< @note Not available for ADF instance */
#define MDF_BITSTREAM2_FALLING (MDF_BSMXCR_BSSEL_0 | \
MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */
@ -483,6 +486,7 @@ typedef struct
#define MDF_BITSTREAM5_FALLING (MDF_BSMXCR_BSSEL_0 | \
MDF_BSMXCR_BSSEL_1 | \
MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */
#endif /* !defined(STM32U535xx) && !defined(STM32U545xx) */
/**
* @}
*/
@ -668,8 +672,10 @@ typedef struct
#define MDF_DATA_SOURCE_BSMX 0x00000000U /*!< Data from bitstream matrix */
#define MDF_DATA_SOURCE_ADCITF1 MDF_DFLTCICR_DATSRC_1 /*!< Data from ADC interface 1.
@note Not available for ADF instance */
#if defined(ADC2)
#define MDF_DATA_SOURCE_ADCITF2 MDF_DFLTCICR_DATSRC /*!< Data from ADC interface 2.
@note Not available for ADF instance */
#endif /* ADC2 */
/**
* @}
*/
@ -837,24 +843,24 @@ HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf);
/** @addtogroup MDF_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
HAL_StatusTypeDef HAL_MDF_GetAcqValue(MDF_HandleTypeDef *hmdf, int32_t *pValue);
HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue);
HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam);
HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig,
MDF_DmaConfigTypeDef *pDmaConfig);
HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig,
const MDF_DmaConfigTypeDef *pDmaConfig);
HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_GenerateTrgo(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay);
HAL_StatusTypeDef HAL_MDF_GetDelay(MDF_HandleTypeDef *hmdf, uint32_t *pDelay);
HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay);
HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain);
HAL_StatusTypeDef HAL_MDF_GetGain(MDF_HandleTypeDef *hmdf, int32_t *pGain);
HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain);
HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset);
HAL_StatusTypeDef HAL_MDF_GetOffset(MDF_HandleTypeDef *hmdf, int32_t *pOffset);
HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset);
HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel,
uint32_t *pAmbientNoise);
HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
@ -881,10 +887,10 @@ HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf);
/** @addtogroup MDF_Exported_Functions_Group4
* @{
*/
HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig);
HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig);
HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig);
HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig);
HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf);
/**
* @}
@ -894,10 +900,10 @@ HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf);
/** @addtogroup MDF_Exported_Functions_Group5
* @{
*/
HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig);
HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig);
HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo);
HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf);
HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig);
HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig);
HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf);
void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo);
/**
@ -910,8 +916,8 @@ void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t Threshol
*/
void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf);
void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf);
HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf);
uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf);
HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf);
uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf);
/**
* @}
*/
@ -924,15 +930,26 @@ uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf);
/** @defgroup MDF_Private_Macros MDF Private Macros
* @{
*/
#if defined(STM32U535xx) || defined(STM32U545xx)
#define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \
((PARAM) == MDF1_Filter1))
#else /* defined(STM32U535xx) || defined(STM32U545xx) */
#define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \
((PARAM) == MDF1_Filter1) || \
((PARAM) == MDF1_Filter2) || \
((PARAM) == MDF1_Filter3) || \
((PARAM) == MDF1_Filter4) || \
((PARAM) == MDF1_Filter5))
#endif /* defined(STM32U535xx) || defined(STM32U545xx) */
#define IS_ADF_INSTANCE(PARAM) ((PARAM) == ADF1_Filter0)
#if defined(STM32U535xx) || defined(STM32U545xx)
#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \
((PARAM) == MDF_BITSTREAM0_FALLING) || \
((PARAM) == MDF_BITSTREAM1_RISING) || \
((PARAM) == MDF_BITSTREAM1_FALLING))
#else /* defined(STM32U535xx) || defined(STM32U545xx) */
#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \
((PARAM) == MDF_BITSTREAM0_FALLING) || \
((PARAM) == MDF_BITSTREAM1_RISING) || \
@ -945,8 +962,13 @@ uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf);
((PARAM) == MDF_BITSTREAM4_FALLING) || \
((PARAM) == MDF_BITSTREAM5_RISING) || \
((PARAM) == MDF_BITSTREAM5_FALLING))
#endif /* defined(STM32U535xx) || defined(STM32U545xx) */
#if defined(STM32U535xx) || defined(STM32U545xx)
#define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 1U)
#else /* defined(STM32U535xx) || defined(STM32U545xx) */
#define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 5U)
#endif /* defined(STM32U535xx) || defined(STM32U545xx) */
#define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U))
@ -1043,9 +1065,14 @@ uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf);
#define IS_MDF_SNAPSHOT_FORMAT(PARAM) (((PARAM) == MDF_SNAPSHOT_23BITS) || \
((PARAM) == MDF_SNAPSHOT_16BITS))
#if defined(ADC2)
#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \
((PARAM) == MDF_DATA_SOURCE_ADCITF1) || \
((PARAM) == MDF_DATA_SOURCE_ADCITF2))
#else /* ADC2 */
#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \
((PARAM) == MDF_DATA_SOURCE_ADCITF1))
#endif /* ADC2 */
#define IS_ADF_DATA_SOURCE(PARAM) ((PARAM) == MDF_DATA_SOURCE_BSMX)

533
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c
View File

@ -64,7 +64,7 @@
SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
(#) Initialize the SDMMC peripheral interface with defaullt configuration.
(#) Initialize the SDMMC peripheral interface with default configuration.
The initialization process is done at 400KHz. You can change or adapt
this frequency by adjusting the "ClockDiv" field.
The MMC Card frequency (SDMMC_CK) is computed as follows:
@ -188,7 +188,7 @@
The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
Use Functions HAL_MMC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@ -201,7 +201,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@ -215,12 +215,12 @@
(+) MspDeInitCallback : MMC MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
reset to the legacy weak (surcharged) functions in the HAL_MMC_Init
and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@ -228,14 +228,15 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
or @ref HAL_MMC_Init function.
using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit
or HAL_MMC_Init function.
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -258,7 +259,7 @@
* @{
*/
#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE
#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
@ -268,7 +269,7 @@
#define MMC_EXT_CSD_PWR_CL_52_POS 0
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
#else
#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE
#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
@ -279,6 +280,11 @@
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/
#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216
#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS 0
#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX 217
#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8
/* Frequencies used in the driver for clock divider calculation */
#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
@ -446,8 +452,15 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
/* wait 74 Cycles: required power up waiting time before starting
the MMC initialization sequence */
sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
if (Init.ClockDiv != 0U)
{
sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
}
if (sdmmc_clk != 0U)
{
HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
}
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
@ -584,7 +597,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout)
uint32_t NumberOfBlocks,
uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@ -612,7 +626,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
& 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
@ -778,7 +793,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
@ -788,7 +803,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
uint32_t data;
uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
const uint8_t *tempbuff = pData;
if (NULL == pData)
{
@ -974,8 +989,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@ -1087,7 +1102,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
@ -1201,8 +1216,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@ -1316,7 +1331,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
@ -1451,7 +1466,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd,
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
& 0x000000FFU) != 0x0U)
{
if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
{
@ -1830,6 +1846,9 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
/**
* @brief Register a User MMC Callback
* To be used instead of the weak (surcharged) predefined callback
* @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in
* HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID
* and HAL_MMC_MSP_DEINIT_CB_ID.
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@ -1856,9 +1875,6 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hmmc);
if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@ -1921,14 +1937,15 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmmc);
return status;
}
/**
* @brief Unregister a User MMC Callback
* MMC Callback is redirected to the weak (surcharged) predefined callback
* @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in
* HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID
* and HAL_MMC_MSP_DEINIT_CB_ID.
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@ -1946,9 +1963,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hmmc);
if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@ -2011,8 +2025,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmmc);
return status;
}
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
@ -2641,35 +2653,90 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
uint32_t error_code;
uint32_t tickstart;
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
hmmc->State = HAL_MMC_STATE_READY;
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
CardState = HAL_MMC_GetCardState(hmmc);
if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
if (hmmc->State == HAL_MMC_STATE_BUSY)
{
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
__SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/*we will send the CMD12 in all cases in order to stop the data transfers*/
/*In case the data transfer just finished , the external memory will not respond and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/
/*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/
/*Other scenario will return HAL_ERROR*/
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
error_code = hmmc->ErrorCode;
if ((error_code != HAL_MMC_ERROR_NONE) && (error_code != HAL_MMC_ERROR_CMD_RSP_TIMEOUT))
{
return HAL_ERROR;
}
tickstart = HAL_GetTick();
if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
{
if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE)
{
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
{
if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
}
if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT)
{
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND))
{
if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
}
}
else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
{
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
{
if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
}
else
{
/* Nothing to do*/
}
/*The reason of all these while conditions previously is that we need to wait the SDMMC and clear the appropriate flags that will be set depending of the abort/non abort of the memory */
/*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result in next SDMMC read/write operation to fail */
/*SDMMC ready for clear data flags*/
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
hmmc->State = HAL_MMC_STATE_READY;
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
}
return HAL_OK;
}
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
@ -3102,6 +3169,343 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui
}
}
/**
* @brief Switch the device from Standby State to Sleep State.
* @param hmmc pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate,
sleep_timeout,
timeout,
count,
response = 0U ;
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Field SLEEP_NOTIFICATION_TIME [216] */
sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >>
MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU);
/* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */
/* In HAL, the tick interrupt occurs each ms */
if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
{
sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
}
timeout = (((1UL << sleep_timeout) / 100U) + 1U);
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= timeout)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
(uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* Switch the device in stand-by mode */
(void)SDMMC_CmdSelDesel(hmmc->Instance, 0U);
/* Field S_A_TIEMOUT [217] */
sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >>
MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU);
/* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
/* In HAL, the tick interrupt occurs each ms */
if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
{
sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
}
timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
{
/* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */
errorstate = SDMMC_CmdSleepMmc(hmmc->Instance,
((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U)));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= timeout)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
}
}
else
{
errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
}
}
}
else
{
/* Nothing to do */
}
}
}
}
}
else
{
/* Nothing to do */
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
else
{
return HAL_TIMEOUT;
}
}
else
{
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Switch the device from Sleep State to Standby State.
* @param hmmc pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
uint32_t sleep_timeout;
uint32_t timeout;
uint32_t count;
uint32_t response = 0U;
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Field S_A_TIEMOUT [217] */
sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) &
0x000000FFU);
/* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
/* In HAL, the tick interrupt occurs each ms */
if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
{
sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
}
timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
/* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */
errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= timeout)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
if (errorstate == HAL_MMC_ERROR_NONE)
{
if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
{
/* Switch the device in transfer mode */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER)
{
/* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
(uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
}
else
{
/* NOthing to do */
}
}
}
else
{
errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
}
}
}
else
{
errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
}
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
else
{
return HAL_TIMEOUT;
}
}
else
{
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
@ -3361,7 +3765,8 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel
}
/* Poll on SDMMC flags */
while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
SDMMC_FLAG_DATAEND))
{
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
@ -3479,7 +3884,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count;
uint32_t data;
uint8_t *tmp;
const uint8_t *tmp;
tmp = hmmc->pTxBuffPtr;
@ -3582,13 +3987,21 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
/* High Speed Clock should be less or equal to 52MHz*/
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
if (sdmmc_clk == 0U)
{
errorstate = SDMMC_ERROR_INVALID_PARAMETER;
}
else
{
Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ);
if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ)
{
Init.ClockDiv = 0;
}
else
{
Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U;
}
(void)SDMMC_Init(hmmc->Instance, Init);
SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);

40
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.h
View File

@ -63,15 +63,18 @@ typedef enum
*/
typedef uint32_t HAL_MMC_CardStateTypeDef;
#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */
#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready (can't be checked by CMD13) */
#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */
#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */
#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */
#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */
/**
* @}
*/
@ -118,7 +121,7 @@ typedef struct
HAL_LockTypeDef Lock; /*!< MMC locking object */
uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
@ -640,19 +643,20 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks,
uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
@ -724,6 +728,14 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui
* @}
*/
/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management
* @{
*/
HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup MMC_Private_Types MMC Private Types
* @{

1
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc_ex.c
View File

@ -30,6 +30,7 @@
HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/

63
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.c
View File

@ -69,25 +69,25 @@
The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
Use Functions HAL_NAND_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@ -95,8 +95,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
or @ref HAL_NAND_Init function.
using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
or HAL_NAND_Init function.
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@ -516,8 +516,8 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead)
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@ -674,8 +674,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead)
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@ -842,8 +842,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite)
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
uint8_t *buff = pBuffer;
const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@ -995,8 +995,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite)
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@ -1004,7 +1004,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
uint16_t *buff = pBuffer;
const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@ -1159,8 +1159,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumSpareAreaToRead)
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
@ -1324,7 +1324,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
@ -1489,8 +1489,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@ -1499,7 +1499,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
uint8_t *buff = pBuffer;
const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@ -1652,8 +1652,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@ -1662,7 +1662,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
uint16_t *buff = pBuffer;
const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@ -1813,7 +1813,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
* @param pAddress pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress;
@ -1869,7 +1869,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
@ -2180,7 +2180,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
* the configuration information for NAND module.
* @retval HAL state
*/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
{
return hnand->State;
}
@ -2191,7 +2191,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
* the configuration information for NAND module.
* @retval NAND status
*/
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
{
uint32_t data;
uint32_t deviceaddress;
@ -2239,4 +2239,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
* @}
*/

41
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.h
View File

@ -106,7 +106,7 @@ typedef struct
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
Please check the Read Mode sequence in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
@ -126,7 +126,7 @@ typedef struct
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
@ -214,27 +214,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
@ -264,8 +264,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
* @{
*/
/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
/**
* @}
*/
@ -375,4 +375,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
#endif
#endif /* STM32U5xx_HAL_NAND_H */

254
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.c
View File

@ -66,25 +66,25 @@
The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
Use Functions HAL_NOR_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@ -92,8 +92,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
or @ref HAL_NOR_Init function.
using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
or HAL_NOR_Init function.
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@ -126,6 +126,11 @@
*/
/* Constants to define address to set to write a command */
#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA
#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA
#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555
#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
@ -229,6 +234,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR handle parameter */
if (hnor == NULL)
@ -262,7 +268,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
(void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
@ -301,11 +308,32 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Get the value of the command set */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
{
(void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
return HAL_NOR_ReturnToReadMode(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_PROTECTED;
}
else
{
/* Get the value of the command set */
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
NOR_CMD_DATA_CFI);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
}
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
status = HAL_NOR_ReturnToReadMode(hnor);
}
return status;
}
/**
@ -380,7 +408,7 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
* @param Timeout Maximum timeout value
* @retval None
*/
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
__weak void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
@ -428,7 +456,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
{
return HAL_BUSY;
}
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@ -457,9 +489,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
/* Send read ID command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_AUTO_SELECT);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_AUTO_SELECT);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@ -515,7 +560,11 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
return HAL_BUSY;
}
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@ -589,7 +638,11 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
{
return HAL_BUSY;
}
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@ -618,9 +671,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_READ_RESET);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_READ_RESET);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@ -699,9 +765,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
/* Send program data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_PROGRAM);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@ -758,7 +836,11 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
{
return HAL_BUSY;
}
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@ -787,9 +869,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_READ_RESET);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_READ_RESET);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@ -882,10 +977,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
}
else
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
}
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
@ -985,14 +1090,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
/* Send block erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
}
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
@ -1070,15 +1187,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
/* Send NOR chip erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
NOR_CMD_DATA_CHIP_ERASE);
}
}
else
{
@ -1118,7 +1248,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
{
return HAL_BUSY;
}
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@ -1145,8 +1279,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
}
/* Send read CFI query command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
NOR_CMD_DATA_CFI);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
}
/* read the NOR CFI information */
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
@ -1380,7 +1521,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
* the configuration information for NOR module.
* @retval NOR controller state
*/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
{
return hnor->State;
}
@ -1394,7 +1535,7 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpsr1;
@ -1509,4 +1650,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @}
*/

7
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.h
View File

@ -183,7 +183,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout);
/**
* @}
*/
@ -233,8 +233,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
*/
/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
@ -322,4 +322,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
#endif
#endif /* STM32U5xx_HAL_NOR_H */

17
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.c
View File

@ -118,7 +118,7 @@
and a pointer to the user callback function.
(++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspdeInit.
(+++) All Callbacks
@ -904,10 +904,11 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
*
*/
HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
{
HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
__IO uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */
__IO const uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or
LPOTR */
/* Check the OPAMP handle allocation */
/* Value can be retrieved in HAL_OPAMP_STATE_READY state */
@ -941,11 +942,11 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopa
if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
(hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
{
tmp_opamp_reg_trimming = &OPAMP->OTR;
tmp_opamp_reg_trimming = &(hopamp->Instance->OTR);
}
else
{
tmp_opamp_reg_trimming = &OPAMP->LPOTR;
tmp_opamp_reg_trimming = &(hopamp->Instance->LPOTR);
}
/* Get factory trimming */
@ -992,7 +993,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopa
* @param hopamp : OPAMP handle
* @retval HAL state
*/
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp)
{
/* Check the OPAMP handle allocation */
if (hopamp == NULL)
@ -1028,7 +1029,7 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User OPAMP Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used instead of the weak (overridden) predefined callback
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
@ -1095,7 +1096,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OP
/**
* @brief Unregister a User OPAMP Callback
* OPAMP Callback is redirected to the weak (surcharged) predefined callback
* OPAMP Callback is redirected to the weak (overridden) predefined callback
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:

7
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.h
View File

@ -182,7 +182,6 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
#define OPAMP_NONINVERTINGINPUT_IO0 0x00000000U /*!< OPAMP non-inverting input connected to dedicated IO pin */
#define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VP_SEL /*!< OPAMP non-inverting input connected internally to DAC channel */
/**
* @}
*/
@ -190,11 +189,9 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
* @{
*/
#define OPAMP_INVERTINGINPUT_IO0 0x00000000U /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */
#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VM_SEL_0 /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */
#define OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VM_SEL_1 /*!< OPAMP inverting input not connected externally (PGA mode only) */
/**
* @}
*/
@ -386,7 +383,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
/**
* @}
@ -397,7 +394,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopa
*/
/* Peripheral State functions **************************************************/
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp);
/**
* @}

3
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.c
View File

@ -47,6 +47,7 @@
* @{
*/
#if defined(OPAMP2)
/** @addtogroup OPAMPEx_Exported_Functions_Group1
* @brief Extended operation functions
*
@ -366,7 +367,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA
/**
* @}
*/
#endif /* OPAMP2 */
/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
* @brief Peripheral Control functions

2
targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.h
View File

@ -42,6 +42,7 @@ extern "C" {
* @{
*/
#if defined(OPAMP2)
/* I/O operation functions *****************************************************/
/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
* @{
@ -51,6 +52,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA
/**
* @}
*/
#endif /* OPAMP2 */
/* Peripheral Control functions ************************************************/
/** @addtogroup OPAMPEx_Exported_Functions_Group2

Some files were not shown because too many files have changed in this diff Show More