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Code Issues Projects Releases Wiki Activity

Merge remote-tracking branch 'upstream/master'

pull/401/head
tkuyucu 2014-07-15 16:21:12 +02:00
parent 1243bb3c32 1da17bd076
commit 9f0849d0ea
680 changed files with 252159 additions and 13332 deletions
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1
README.md
View File

@ -42,6 +42,7 @@ NXP:
* [DipCortex-M0](https://mbed.org/platforms/DipCortex-M0/) (Cortex-M0)
* [DipCortex-M3](https://mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
* [BlueBoard-LPC11U24](https://mbed.org/platforms/BlueBoard-LPC11U24/) (Cortex-M0)
* LPCCAPPUCCINO (Cortex-M0)
Freescale:
* FRDM-K20D50M (Cortex-M4)

2
libraries/USBDevice/USBDevice/USBEndpoints.h
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@ -39,7 +39,7 @@ typedef enum {
/* Include configuration for specific target */
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088)
#include "USBEndpoints_LPC17_LPC23.h"
#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X)
#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
#include "USBEndpoints_LPC11U.h"
#elif defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)
#include "USBEndpoints_KL25Z.h"

49
libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp
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@ -16,9 +16,9 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC1347) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPC11U68)
#if defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC1347) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPC11U68) || defined(TARGET_LPC1549)
#if defined(TARGET_LPC1347)
#if defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
#define USB_IRQ USB_IRQ_IRQn
#elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPC11U68)
#define USB_IRQ USB_IRQn
@ -27,6 +27,9 @@
#include "USBHAL.h"
USBHAL * USBHAL::instance;
#if defined(TARGET_LPC1549)
static uint8_t usbmem[2048] __attribute__((aligned(2048)));
#endif
// Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
#define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
@ -42,12 +45,21 @@ USBHAL * USBHAL::instance;
#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
// USB RAM
#if defined(TARGET_LPC1549)
#define USB_RAM_START ((uint32_t)usbmem)
#define USB_RAM_SIZE sizeof(usbmem)
#else
#define USB_RAM_START (0x20004000)
#define USB_RAM_SIZE (0x00000800)
#endif
// SYSAHBCLKCTRL
#if defined(TARGET_LPC1549)
#define CLK_USB (1UL<<23)
#else
#define CLK_USB (1UL<<14)
#define CLK_USBRAM (1UL<<27)
#endif
// USB Information register
#define FRAME_NR(a) ((a) & 0x7ff) // Frame number
@ -145,6 +157,37 @@ USBHAL::USBHAL(void) {
epCallback[6] = &USBHAL::EP4_OUT_callback;
epCallback[7] = &USBHAL::EP4_IN_callback;
#if defined(TARGET_LPC1549)
/* Set USB PLL input to system oscillator */
LPC_SYSCON->USBPLLCLKSEL = 0x01;
/* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
LPC_SYSCON->USBPLLCTRL = (0x3 | (1UL << 6));
/* Powerup USB PLL */
LPC_SYSCON->PDRUNCFG &= ~(CLK_USB);
/* Wait for PLL to lock */
while(!(LPC_SYSCON->USBPLLSTAT & 0x01));
/* enable USB main clock */
LPC_SYSCON->USBCLKSEL = 0x02;
LPC_SYSCON->USBCLKDIV = 1;
/* Enable AHB clock to the USB block. */
LPC_SYSCON->SYSAHBCLKCTRL1 |= CLK_USB;
/* power UP USB Phy */
LPC_SYSCON->PDRUNCFG &= ~(1UL << 9);
/* Reset USB block */
LPC_SYSCON->PRESETCTRL1 |= (CLK_USB);
LPC_SYSCON->PRESETCTRL1 &= ~(CLK_USB);
#else
#if defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501)
// USB_VBUS input with pull-down
LPC_IOCON->PIO0_3 = 0x00000009;
@ -158,7 +201,7 @@ USBHAL::USBHAL(void) {
// Ensure device disconnected (DCON not set)
LPC_USB->DEVCMDSTAT = 0;
#endif
// to ensure that the USB host sees the device as
// disconnected if the target CPU is reset.
wait(0.3);

5
libraries/USBHost/USBHost/USBHostConf.h
View File

@ -58,6 +58,11 @@
*/
#define USBHOST_3GMODULE 1
/*
* Enable USB MIDI
*/
#define USBHOST_MIDI 1
/*
* Maximum number of interfaces of a usb device
*/

362
libraries/USBHost/USBHostMIDI/USBHostMIDI.cpp Normal file
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@ -0,0 +1,362 @@
/* Copyright (c) 2014 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "USBHostMIDI.h"
#if USBHOST_MIDI
#include "dbg.h"
#define SET_LINE_CODING 0x20
USBHostMIDI::USBHostMIDI() {
host = USBHost::getHostInst();
size_bulk_in = 0;
size_bulk_out = 0;
init();
}
void USBHostMIDI::init() {
dev = NULL;
bulk_in = NULL;
bulk_out = NULL;
dev_connected = false;
midi_intf = -1;
midi_device_found = false;
sysExBufferPos = 0;
}
bool USBHostMIDI::connected() {
return dev_connected;
}
bool USBHostMIDI::connect() {
if (dev_connected) {
return true;
}
for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
if ((dev = host->getDevice(i)) != NULL) {
USB_DBG("Trying to connect MIDI device\r\n");
if (host->enumerate(dev, this)) {
break;
}
if (midi_device_found) {
bulk_in = dev->getEndpoint(midi_intf, BULK_ENDPOINT, IN);
bulk_out = dev->getEndpoint(midi_intf, BULK_ENDPOINT, OUT);
if (!bulk_in || !bulk_out) {
break;
}
USB_INFO("New MIDI device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, midi_intf);
dev->setName("MIDI", midi_intf);
host->registerDriver(dev, midi_intf, this, &USBHostMIDI::init);
size_bulk_in = bulk_in->getSize();
size_bulk_out = bulk_out->getSize();
bulk_in->attach(this, &USBHostMIDI::rxHandler);
host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
dev_connected = true;
return true;
}
}
}
init();
return false;
}
void USBHostMIDI::rxHandler() {
uint8_t *midi;
if (bulk_in) {
int length = bulk_in->getLengthTransferred();
if (bulk_in->getState() == USB_TYPE_IDLE || bulk_in->getState() == USB_TYPE_FREE) {
// MIDI event handling
for (int i = 0; i < length; i += 4) {
if (i + 4 > length) {
// length shortage, ignored.
break;
}
// read each four bytes
midi = &buf[i];
// process MIDI message
// switch by code index number
switch (midi[0] & 0xf) {
case 0: // miscellaneous function codes
miscellaneousFunctionCode(midi[1], midi[2], midi[3]);
break;
case 1: // cable events
cableEvent(midi[1], midi[2], midi[3]);
break;
case 2: // two bytes system common messages
systemCommonTwoBytes(midi[1], midi[2]);
break;
case 3: // three bytes system common messages
systemCommonThreeBytes(midi[1], midi[2], midi[3]);
break;
case 4: // SysEx starts or continues
sysExBuffer[sysExBufferPos++] = midi[1];
if (sysExBufferPos >= 64) {
systemExclusive(sysExBuffer, sysExBufferPos, true);
sysExBufferPos = 0;
}
sysExBuffer[sysExBufferPos++] = midi[2];
if (sysExBufferPos >= 64) {
systemExclusive(sysExBuffer, sysExBufferPos, true);
sysExBufferPos = 0;
}
sysExBuffer[sysExBufferPos++] = midi[3];
// SysEx continues. don't send
break;
case 5: // SysEx ends with single byte
sysExBuffer[sysExBufferPos++] = midi[1];
systemExclusive(sysExBuffer, sysExBufferPos, false);
sysExBufferPos = 0;
break;
case 6: // SysEx ends with two bytes
sysExBuffer[sysExBufferPos++] = midi[1];
if (sysExBufferPos >= 64) {
systemExclusive(sysExBuffer, sysExBufferPos, true);
sysExBufferPos = 0;
}
sysExBuffer[sysExBufferPos++] = midi[2];
systemExclusive(sysExBuffer, sysExBufferPos, false);
sysExBufferPos = 0;
break;
case 7: // SysEx ends with three bytes
sysExBuffer[sysExBufferPos++] = midi[1];
if (sysExBufferPos >= 64) {
systemExclusive(sysExBuffer, sysExBufferPos, true);
sysExBufferPos = 0;
}
sysExBuffer[sysExBufferPos++] = midi[2];
if (sysExBufferPos >= 64) {
systemExclusive(sysExBuffer, sysExBufferPos, true);
sysExBufferPos = 0;
}
sysExBuffer[sysExBufferPos++] = midi[3];
systemExclusive(sysExBuffer, sysExBufferPos, false);
sysExBufferPos = 0;
break;
case 8:
noteOff(midi[1] & 0xf, midi[2], midi[3]);
break;
case 9:
if (midi[3]) {
noteOn(midi[1] & 0xf, midi[2], midi[3]);
} else {
noteOff(midi[1] & 0xf, midi[2], midi[3]);
}
break;
case 10:
polyKeyPress(midi[1] & 0xf, midi[2], midi[3]);
break;
case 11:
controlChange(midi[1] & 0xf, midi[2], midi[3]);
break;
case 12:
programChange(midi[1] & 0xf, midi[2]);
break;
case 13:
channelPressure(midi[1] & 0xf, midi[2]);
break;
case 14:
pitchBend(midi[1] & 0xf, midi[2] | (midi[3] << 7));
break;
case 15:
singleByte(midi[1]);
break;
}
}
// read another message
host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
}
}
}
bool USBHostMIDI::sendMidiBuffer(uint8_t data0, uint8_t data1, uint8_t data2, uint8_t data3) {
if (bulk_out) {
uint8_t midi[4];
midi[0] = data0;
midi[1] = data1;
midi[2] = data2;
midi[3] = data3;
if (host->bulkWrite(dev, bulk_out, (uint8_t *)midi, 4) == USB_TYPE_OK) {
return true;
}
}
return false;
}
bool USBHostMIDI::sendMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3) {
return sendMidiBuffer(0, data1, data2, data3);
}
bool USBHostMIDI::sendCableEvent(uint8_t data1, uint8_t data2, uint8_t data3) {
return sendMidiBuffer(1, data1, data2, data3);
}
bool USBHostMIDI::sendSystemCommmonTwoBytes(uint8_t data1, uint8_t data2) {
return sendMidiBuffer(2, data1, data2, 0);
}
bool USBHostMIDI::sendSystemCommmonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3) {
return sendMidiBuffer(3, data1, data2, 0);
}
bool USBHostMIDI::sendSystemExclusive(uint8_t *buffer, int length) {
uint8_t midi[64];
int midiLength;
int midiPos;
if (bulk_out) {
for (int i = 0; i < length; i += 48) {
if (i + 48 >= length) {
// contains last data
midiLength = (((length - i) + 2) / 3) * 4;
for (int pos = i; pos < length; pos += 3) {
midiPos = (pos + 2) / 3 * 4;
if (pos + 3 >= length) {
// last data
switch (pos % 3) {
case 0:
midi[midiPos ] = 7;
midi[midiPos + 1] = buffer[pos ];
midi[midiPos + 2] = buffer[pos + 1];
midi[midiPos + 3] = buffer[pos + 2];
break;
case 1:
midi[midiPos ] = 5;
midi[midiPos + 1] = buffer[pos ];
midi[midiPos + 2] = 0;
midi[midiPos + 3] = 0;
break;
case 2:
midi[midiPos ] = 6;
midi[midiPos + 1] = buffer[pos ];
midi[midiPos + 2] = buffer[pos + 1];
midi[midiPos + 3] = 0;
break;
}
} else {
// has more data
midi[midiPos ] = 4;
midi[midiPos + 1] = buffer[pos ];
midi[midiPos + 2] = buffer[pos + 1];
midi[midiPos + 3] = buffer[pos + 2];
}
}
} else {
// has more data
midiLength = 64;
for (int pos = i; pos < length; pos += 3) {
midiPos = (pos + 2) / 3 * 4;
midi[midiPos ] = 4;
midi[midiPos + 1] = buffer[pos ];
midi[midiPos + 2] = buffer[pos + 1];
midi[midiPos + 3] = buffer[pos + 2];
}
}
if (host->bulkWrite(dev, bulk_out, (uint8_t *)midi, midiLength) != USB_TYPE_OK) {
return false;
}
}
return true;
}
return false;
}
bool USBHostMIDI::sendNoteOff(uint8_t channel, uint8_t note, uint8_t velocity) {
return sendMidiBuffer(8, channel & 0xf | 0x80, note & 0x7f, velocity & 0x7f);
}
bool USBHostMIDI::sendNoteOn(uint8_t channel, uint8_t note, uint8_t velocity) {
return sendMidiBuffer(9, channel & 0xf | 0x90, note & 0x7f, velocity & 0x7f);
}
bool USBHostMIDI::sendPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure) {
return sendMidiBuffer(10, channel & 0xf | 0xa0, note & 0x7f, pressure & 0x7f);
}
bool USBHostMIDI::sendControlChange(uint8_t channel, uint8_t key, uint8_t value) {
return sendMidiBuffer(11, channel & 0xf | 0xb0, key & 0x7f, value & 0x7f);
}
bool USBHostMIDI::sendProgramChange(uint8_t channel, uint8_t program) {
return sendMidiBuffer(12, channel & 0xf | 0xc0, program & 0x7f, 0);
}
bool USBHostMIDI::sendChannelPressure(uint8_t channel, uint8_t pressure) {
return sendMidiBuffer(13, channel & 0xf | 0xd0, pressure & 0x7f, 0);
}
bool USBHostMIDI::sendPitchBend(uint8_t channel, uint16_t value) {
return sendMidiBuffer(14, channel & 0xf | 0xe0, value & 0x7f, (value >> 7) & 0x7f);
}
bool USBHostMIDI::sendSingleByte(uint8_t data) {
return sendMidiBuffer(15, data, 0, 0);
}
/*virtual*/ void USBHostMIDI::setVidPid(uint16_t vid, uint16_t pid)
{
// we don't check VID/PID for this driver
}
/*virtual*/ bool USBHostMIDI::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
{
// USB MIDI class/subclass
if ((midi_intf == -1) &&
(intf_class == AUDIO_CLASS) &&
(intf_subclass == 0x03)) {
midi_intf = intf_nb;
return true;
}
// vendor specific device
if ((midi_intf == -1) &&
(intf_class == 0xff) &&
(intf_subclass == 0x03)) {
midi_intf = intf_nb;
return true;
}
return false;
}
/*virtual*/ bool USBHostMIDI::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
{
if (intf_nb == midi_intf) {
if (type == BULK_ENDPOINT) {
midi_device_found = true;
return true;
}
}
return false;
}
#endif

353
libraries/USBHost/USBHostMIDI/USBHostMIDI.h Normal file
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@ -0,0 +1,353 @@
/* Copyright (c) 2014 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef USBHOSTMIDI_H
#define USBHOSTMIDI_H
#include "USBHostConf.h"
#if USBHOST_MIDI
#include "USBHost.h"
/**
* A class to communicate a USB MIDI device
*/
class USBHostMIDI : public IUSBEnumerator {
public:
/**
* Constructor
*/
USBHostMIDI();
/**
* Check if a USB MIDI device is connected
*
* @returns true if a midi device is connected
*/
bool connected();
/**
* Try to connect a midi device
*
* @return true if connection was successful
*/
bool connect();
/**
* Attach a callback called when miscellaneous function code is received
*
* @param ptr function pointer
* prototype: void onMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3);
*/
inline void attachMiscellaneousFunctionCode(void (*fn)(uint8_t, uint8_t, uint8_t)) {
miscellaneousFunctionCode = fn;
}
/**
* Attach a callback called when cable event is received
*
* @param ptr function pointer
* prototype: void onCableEvent(uint8_t data1, uint8_t data2, uint8_t data3);
*/
inline void attachCableEvent(void (*fn)(uint8_t, uint8_t, uint8_t)) {
cableEvent = fn;
}
/**
* Attach a callback called when system exclusive is received
*
* @param ptr function pointer
* prototype: void onSystemCommonTwoBytes(uint8_t data1, uint8_t data2);
*/
inline void attachSystemCommonTwoBytes(void (*fn)(uint8_t, uint8_t)) {
systemCommonTwoBytes = fn;
}
/**
* Attach a callback called when system exclusive is received
*
* @param ptr function pointer
* prototype: void onSystemCommonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3);
*/
inline void attachSystemCommonThreeBytes(void (*fn)(uint8_t, uint8_t, uint8_t)) {
systemCommonThreeBytes = fn;
}
/**
* Attach a callback called when system exclusive is received
*
* @param ptr function pointer
* prototype: void onSystemExclusive(uint8_t *data, uint16_t length, bool hasNextData);
*/
inline void attachSystemExclusive(void (*fn)(uint8_t *, uint16_t, bool)) {
systemExclusive = fn;
}
/**
* Attach a callback called when note on is received
*
* @param ptr function pointer
* prototype: void onNoteOn(uint8_t channel, uint8_t note, uint8_t velocity);
*/
inline void attachNoteOn(void (*fn)(uint8_t, uint8_t, uint8_t)) {
noteOn = fn;
}
/**
* Attach a callback called when note off is received
*
* @param ptr function pointer
* prototype: void onNoteOff(uint8_t channel, uint8_t note, uint8_t velocity);
*/
inline void attachNoteOff(void (*fn)(uint8_t, uint8_t, uint8_t)) {
noteOff = fn;
}
/**
* Attach a callback called when poly keypress is received
*
* @param ptr function pointer
* prototype: void onPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure);
*/
inline void attachPolyKeyPress(void (*fn)(uint8_t, uint8_t, uint8_t)) {
polyKeyPress = fn;
}
/**
* Attach a callback called when control change is received
*
* @param ptr function pointer
* prototype: void onControlChange(uint8_t channel, uint8_t key, uint8_t value);
*/
inline void attachControlChange(void (*fn)(uint8_t, uint8_t, uint8_t)) {
controlChange = fn;
}
/**
* Attach a callback called when program change is received
*
* @param ptr function pointer
* prototype: void onProgramChange(uint8_t channel, uint8_t program);
*/
inline void attachProgramChange(void (*fn)(uint8_t, uint8_t)) {
programChange = fn;
}
/**
* Attach a callback called when channel pressure is received
*
* @param ptr function pointer
* prototype: void onChannelPressure(uint8_t channel, uint8_t pressure);
*/
inline void attachChannelPressure(void (*fn)(uint8_t, uint8_t)) {
channelPressure = fn;
}
/**
* Attach a callback called when pitch bend is received
*
* @param ptr function pointer
* prototype: void onPitchBend(uint8_t channel, uint16_t value);
*/
inline void attachPitchBend(void (*fn)(uint8_t, uint16_t)) {
pitchBend = fn;
}
/**
* Attach a callback called when single byte is received
*
* @param ptr function pointer
* prototype: void onSingleByte(uint8_t value);
*/
inline void attachSingleByte(void (*fn)(uint8_t)) {
singleByte = fn;
}
/**
* Send a cable event with 3 bytes event
*
* @param data1 0-255
* @param data2 0-255
* @param data3 0-255
* @return true if message sent successfully
*/
bool sendMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3);
/**
* Send a cable event with 3 bytes event
*
* @param data1 0-255
* @param data2 0-255
* @param data3 0-255
* @return true if message sent successfully
*/
bool sendCableEvent(uint8_t data1, uint8_t data2, uint8_t data3);
/**
* Send a system common message with 2 bytes event
*
* @param data1 0-255
* @param data2 0-255
* @return true if message sent successfully
*/
bool sendSystemCommmonTwoBytes(uint8_t data1, uint8_t data2);
/**
* Send a system common message with 3 bytes event
*
* @param data1 0-255
* @param data2 0-255
* @param data3 0-255
* @return true if message sent successfully
*/
bool sendSystemCommmonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3);
/**
* Send a system exclusive event
*
* @param buffer, starts with 0xF0, and end with 0xf7
* @param length
* @return true if message sent successfully
*/
bool sendSystemExclusive(uint8_t *buffer, int length);
/**
* Send a note off event
*
* @param channel 0-15
* @param note 0-127
* @param velocity 0-127
* @return true if message sent successfully
*/
bool sendNoteOff(uint8_t channel, uint8_t note, uint8_t velocity);
/**
* Send a note on event
*
* @param channel 0-15
* @param note 0-127
* @param velocity 0-127 (0 means note off)
* @return true if message sent successfully
*/
bool sendNoteOn(uint8_t channel, uint8_t note, uint8_t velocity);
/**
* Send a poly keypress event
*
* @param channel 0-15
* @param note 0-127
* @param pressure 0-127
* @return true if message sent successfully
*/
bool sendPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure);
/**
* Send a control change event
*
* @param channel 0-15
* @param key 0-127
* @param value 0-127
* @return true if message sent successfully
*/
bool sendControlChange(uint8_t channel, uint8_t key, uint8_t value);
/**
* Send a program change event
*
* @param channel 0-15
* @param program 0-127
* @return true if message sent successfully
*/
bool sendProgramChange(uint8_t channel, uint8_t program);
/**
* Send a channel pressure event
*
* @param channel 0-15
* @param pressure 0-127
* @return true if message sent successfully
*/
bool sendChannelPressure(uint8_t channel, uint8_t pressure);
/**
* Send a control change event
*
* @param channel 0-15
* @param key 0(lower)-8191(center)-16383(higher)
* @return true if message sent successfully
*/
bool sendPitchBend(uint8_t channel, uint16_t value);
/**
* Send a single byte event
*
* @param data 0-255
* @return true if message sent successfully
*/
bool sendSingleByte(uint8_t data);
protected:
//From IUSBEnumerator
virtual void setVidPid(uint16_t vid, uint16_t pid);
virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
private:
USBHost * host;
USBDeviceConnected * dev;
USBEndpoint * bulk_in;
USBEndpoint * bulk_out;
uint32_t size_bulk_in;
uint32_t size_bulk_out;
bool dev_connected;
void init();
uint8_t buf[64];
void rxHandler();
uint16_t sysExBufferPos;
uint8_t sysExBuffer[64];
void (*miscellaneousFunctionCode)(uint8_t, uint8_t, uint8_t);
void (*cableEvent)(uint8_t, uint8_t, uint8_t);
void (*systemCommonTwoBytes)(uint8_t, uint8_t);
void (*systemCommonThreeBytes)(uint8_t, uint8_t, uint8_t);
void (*systemExclusive)(uint8_t *, uint16_t, bool);
void (*noteOff)(uint8_t, uint8_t, uint8_t);
void (*noteOn)(uint8_t, uint8_t, uint8_t);
void (*polyKeyPress)(uint8_t, uint8_t, uint8_t);
void (*controlChange)(uint8_t, uint8_t, uint8_t);
void (*programChange)(uint8_t, uint8_t);
void (*channelPressure)(uint8_t, uint8_t);
void (*pitchBend)(uint8_t, uint16_t);
void (*singleByte)(uint8_t);
bool sendMidiBuffer(uint8_t data0, uint8_t data1, uint8_t data2, uint8_t data3);
int midi_intf;
bool midi_device_found;
};
#endif /* USBHOST_MIDI */
#endif /* USBHOSTMIDI_H */

6
libraries/dsp/cmsis_dsp/SupportFunctions/math_helper.c
View File

@ -164,7 +164,8 @@ void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
{
uint32_t i;
int32_t diff, diffCrnt = 0;
int32_t diff;
uint32_t diffCrnt = 0;
uint32_t maxDiff = 0;
for (i = 0; i < numSamples; i++)
@ -192,7 +193,8 @@ uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
{
uint32_t i;
int32_t diff, diffCrnt = 0;
int32_t diff;
uint32_t diffCrnt = 0;
uint32_t maxDiff = 0;
for (i = 0; i < numSamples; i++)

4
libraries/dsp/dsp/Sine_f32.cpp
View File

@ -34,7 +34,7 @@ Sine_f32::Sine_f32(uint32_t frequency, uint32_t sample_rate, float32_t amplitude
}
void Sine_f32::process(float32_t *sgn_in, float32_t *sgn_out) {
for (int i=0; i<_block_size; i++) {
for (uint32_t i=0; i<_block_size; i++) {
*sgn_out = *sgn_in + (_amplitude * arm_sin_f32(_x));
sgn_in++; sgn_out++;
_x += _dx;
@ -42,7 +42,7 @@ void Sine_f32::process(float32_t *sgn_in, float32_t *sgn_out) {
}
void Sine_f32::generate(float32_t *sgn) {
for (int i=0; i<_block_size; i++) {
for (uint32_t i=0; i<_block_size; i++) {
*sgn = (_amplitude * arm_sin_f32(_x));
sgn++;
_x += _dx;

2
libraries/mbed/api/mbed.h
View File

@ -16,7 +16,7 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 84
#define MBED_LIBRARY_VERSION 86
#include "platform.h"

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/MK20D5.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/MK20D5.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/MK20D5.sct → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/startup_MK20D5.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/sys.cpp → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_GCC_ARM/MK20D5.ld → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis_nvic.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis_nvic.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/system_MK20D5.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/system_MK20D5.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
View File

12
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/TOOLCHAIN_ARM_STD/nRF51822.sct
View File

@ -1,24 +1,24 @@
;WITHOUT SOFTDEVICE:
;LR_IROM1 0x00000000 0x00040000 {
; ER_IROM1 0x00000000 0x00040000 {
;LR_IROM1 0x00000000 0x00040000 {
; ER_IROM1 0x00000000 0x00040000 {
; *.o (RESET, +First)
; *(InRoot$$Sections)
; .ANY (+RO)
; }
; RW_IRAM1 0x20000000 0x00004000 {
; RW_IRAM1 0x20000000 0x00004000 {
; .ANY (+RW +ZI)
; }
;}
;
;WITH SOFTDEVICE:
LR_IROM1 0x14000 0x002C000 {
ER_IROM1 0x14000 0x002C000 {
LR_IROM1 0x16000 0x002A000 {
ER_IROM1 0x16000 0x002A000 {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20002000 0x00002000 {
RW_IRAM1 0x20002000 0x00002000 {
.ANY (+RW +ZI)
}
}

152
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/TOOLCHAIN_GCC_ARM/NRF51822.ld Normal file
View File

@ -0,0 +1,152 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00016000, LENGTH = 0x2A000
RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000
}
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.Vectors))
*(.text*)
*(.init)
*(.fini)
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
*(.eh_frame*)
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
*(.preinit_array)
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
*(SORT(.init_array.*))
*(.init_array)
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
*(SORT(.fini_array.*))
*(.fini_array)
PROVIDE_HIDDEN (__fini_array_end = .);
*(.jcr)
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

262
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.s Normal file
View File

@ -0,0 +1,262 @@
/*
Copyright (c) 2013, Nordic Semiconductor ASA
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
NOTE: Template files (including this one) are application specific and therefore
expected to be copied into the application project folder prior to its use!
*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 2048
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 2048
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .Vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long POWER_CLOCK_IRQHandler /*POWER_CLOCK */
.long RADIO_IRQHandler /*RADIO */
.long UART0_IRQHandler /*UART0 */
.long SPI0_TWI0_IRQHandler /*SPI0_TWI0 */
.long SPI1_TWI1_IRQHandler /*SPI1_TWI1 */
.long 0 /*Reserved */
.long GPIOTE_IRQHandler /*GPIOTE */
.long ADC_IRQHandler /*ADC */
.long TIMER0_IRQHandler /*TIMER0 */
.long TIMER1_IRQHandler /*TIMER1 */
.long TIMER2_IRQHandler /*TIMER2 */
.long RTC0_IRQHandler /*RTC0 */
.long TEMP_IRQHandler /*TEMP */
.long RNG_IRQHandler /*RNG */
.long ECB_IRQHandler /*ECB */
.long CCM_AAR_IRQHandler /*CCM_AAR */
.long WDT_IRQHandler /*WDT */
.long RTC1_IRQHandler /*RTC1 */
.long QDEC_IRQHandler /*QDEC */
.long LPCOMP_IRQHandler /*LPCOMP */
.long SWI0_IRQHandler /*SWI0 */
.long SWI1_IRQHandler /*SWI1 */
.long SWI2_IRQHandler /*SWI2 */
.long SWI3_IRQHandler /*SWI3 */
.long SWI4_IRQHandler /*SWI4 */
.long SWI5_IRQHandler /*SWI5 */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.size __Vectors, . - __Vectors
/* Reset Handler */
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
.equ NRF_POWER_RAMON_RAMxON_ONMODE_Msk, 0x3
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.fnstart
/* Make sure ALL RAM banks are powered on */
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R1
STR R2, [R0]
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC0
.LC1:
subs r3, 4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .LC1
.LC0:
LDR R0, =SystemInit
BLX R0
LDR R0, =_start
BX R0
.pool
.cantunwind
.fnend
.size Reset_Handler,.-Reset_Handler
.section ".text"
/* Dummy Exception Handlers (infinite loops which can be modified) */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ POWER_CLOCK_IRQHandler
IRQ RADIO_IRQHandler
IRQ UART0_IRQHandler
IRQ SPI0_TWI0_IRQHandler
IRQ SPI1_TWI1_IRQHandler
IRQ GPIOTE_IRQHandler
IRQ ADC_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ RTC0_IRQHandler
IRQ TEMP_IRQHandler
IRQ RNG_IRQHandler
IRQ ECB_IRQHandler
IRQ CCM_AAR_IRQHandler
IRQ WDT_IRQHandler
IRQ RTC1_IRQHandler
IRQ QDEC_IRQHandler
IRQ LPCOMP_IRQHandler
IRQ SWI0_IRQHandler
IRQ SWI1_IRQHandler
IRQ SWI2_IRQHandler
IRQ SWI3_IRQHandler
IRQ SWI4_IRQHandler
IRQ SWI5_IRQHandler
.end

235
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld Normal file
View File

@ -0,0 +1,235 @@
/*Based on following file*/
/*
* GENERATED FILE - DO NOT EDIT
* (c) Code Red Technologies Ltd, 2008-13
* (c) NXP Semiconductors 2013-2014
* Generated linker script file for LPC11U68
* Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
*/
MEMORY
{
/* Define each memory region */
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
}
/* Define a symbol for the top of each memory region */
__top_MFlash256 = 0x0 + 0x40000;
__top_Ram0_32 = 0x10000000 + 0x8000;
__top_Ram1_2 = 0x20000000 + 0x800;
__top_Ram2USB_2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(4);
/* C++ constructors etc */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > MFlash256
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
__exidx_end = .;
_etext = .;
/* possible MTB section for Ram1_2 */
.mtb_buffer_RAM2 (NOLOAD) :
{
KEEP(*(.mtb.$RAM2*))
KEEP(*(.mtb.$RAM1_2*))
} > Ram1_2
/* DATA section for Ram1_2 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_2)
*(.data.$RAM2*)
*(.data.$Ram1_2*)
. = ALIGN(4) ;
} > Ram1_2 AT>MFlash256
/* possible MTB section for Ram2USB_2 */
.mtb_buffer_RAM3 (NOLOAD) :
{
KEEP(*(.mtb.$RAM3*))
KEEP(*(.mtb.$RAM2USB_2*))
} > Ram2USB_2
/* DATA section for Ram2USB_2 */
.data_RAM3 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2USB_2)
*(.data.$RAM3*)
*(.data.$Ram2USB_2*)
. = ALIGN(4) ;
} > Ram2USB_2 AT>MFlash256
/* MAIN DATA SECTION */
/* Default MTB section */
.mtb_buffer_default (NOLOAD) :
{
KEEP(*(.mtb*))
} > Ram0_32
.uninit_RESERVED : ALIGN(4)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > Ram0_32
/* Main DATA section (Ram0_32) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > Ram0_32 AT>MFlash256
/* BSS section for Ram1_2 */
.bss_RAM2 : ALIGN(4)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_2*)
. = ALIGN(4) ;
} > Ram1_2
/* BSS section for Ram2USB_2 */
.bss_RAM3 : ALIGN(4)
{
*(.bss.$RAM3*)
*(.bss.$Ram2USB_2*)
. = ALIGN(4) ;
} > Ram2USB_2
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_32
/* NOINIT section for Ram1_2 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_2*)
. = ALIGN(4) ;
} > Ram1_2
/* NOINIT section for Ram2USB_2 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2USB_2*)
. = ALIGN(4) ;
} > Ram2USB_2
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > Ram0_32
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_Ram0_32 - 0);
}

181
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp Normal file
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extern "C" {
#include "LPC11U6x.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM0
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC11U68
PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
I2C1_IRQHandler, // 10 - I2C1
USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
I2C0_IRQHandler, // 15 - I2C0
TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
USART0_IRQHandler, // 21 - USART0
USB_IRQHandler, // 22 - USB IRQ
USB_FIQHandler, // 23 - USB FIQ
ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
RTC_IRQHandler, // 25 - Real Time CLock interrpt
BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
DMA_IRQHandler, // 28 - DMA interrupt
ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
0, // 31 - Reserved
};
/* End Vector */
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
/* Reset entry point*/
extern "C" void software_init_hook(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
SystemInit();
if (software_init_hook)
software_init_hook();
else {
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {}
AFTER_VECTORS void HardFault_Handler (void) {}
AFTER_VECTORS void MemManage_Handler (void) {}
AFTER_VECTORS void BusFault_Handler (void) {}
AFTER_VECTORS void UsageFault_Handler(void) {}
AFTER_VECTORS void SVC_Handler (void) {}
AFTER_VECTORS void DebugMon_Handler (void) {}
AFTER_VECTORS void PendSV_Handler (void) {}
AFTER_VECTORS void SysTick_Handler (void) {}
AFTER_VECTORS void IntDefaultHandler (void) {}
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
}
#include <stdlib.h>
void *operator new(size_t size) {return malloc(size);}
void *operator new[](size_t size){return malloc(size);}
void operator delete(void *p) {free(p);}
void operator delete[](void *p) {free(p);}

237
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld Normal file
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@ -0,0 +1,237 @@
/*Based on following file*/
/*
* GENERATED FILE - DO NOT EDIT
* (c) Code Red Technologies Ltd, 2008-13
* (c) NXP Semiconductors 2013-2014
* Generated linker script file for LPC11U68
* Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
}
/* Define a symbol for the top of each memory region */
__top_MFlash256 = 0x0 + 0x40000;
__top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;
__top_Ram1_2 = 0x20000000 + 0x800;
__top_Ram2USB_2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
KEEP(*(.isr_vector))
*(.text.ResetISR)
*(.text.SystemInit)
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(4);
/* C++ constructors etc */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > MFlash256
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
__exidx_end = .;
_etext = .;
/* possible MTB section for Ram1_2 */
.mtb_buffer_RAM2 (NOLOAD) :
{
KEEP(*(.mtb.$RAM2*))
KEEP(*(.mtb.$RAM1_2*))
} > Ram1_2
/* DATA section for Ram1_2 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_2)
*(.data.$RAM2*)
*(.data.$Ram1_2*)
. = ALIGN(4) ;
} > Ram1_2 AT>MFlash256
/* possible MTB section for Ram2USB_2 */
.mtb_buffer_RAM3 (NOLOAD) :
{
KEEP(*(.mtb.$RAM3*))
KEEP(*(.mtb.$RAM2USB_2*))
} > Ram2USB_2
/* DATA section for Ram2USB_2 */
.data_RAM3 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2USB_2)
*(.data.$RAM3*)
*(.data.$Ram2USB_2*)
. = ALIGN(4) ;
} > Ram2USB_2 AT>MFlash256
/* MAIN DATA SECTION */
/* Default MTB section */
.mtb_buffer_default (NOLOAD) :
{
KEEP(*(.mtb*))
} > Ram0_32
.uninit_RESERVED : ALIGN(4)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > Ram0_32
/* Main DATA section (Ram0_32) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > Ram0_32 AT>MFlash256
/* BSS section for Ram1_2 */
.bss_RAM2 : ALIGN(4)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_2*)
. = ALIGN(4) ;
} > Ram1_2
/* BSS section for Ram2USB_2 */
.bss_RAM3 : ALIGN(4)
{
*(.bss.$RAM3*)
*(.bss.$Ram2USB_2*)
. = ALIGN(4) ;
} > Ram2USB_2
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_32
/* NOINIT section for Ram1_2 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_2*)
. = ALIGN(4) ;
} > Ram1_2
/* NOINIT section for Ram2USB_2 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2USB_2*)
. = ALIGN(4) ;
} > Ram2USB_2
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > Ram0_32
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_Ram0_32 - 0);
}

93
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.s Normal file
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//*****************************************************************************
// aeabi_romdiv_patch.s
// - Provides "patch" versions of the aeabi integer divide functions to
// replace the standard ones pulled in from the C library, which vector
// integer divides onto the rom division functions contained in
// specific NXP MCUs such as LPC11Uxx and LPC12xx.
// - Note that this patching will only occur if "__USE_ROMDIVIDE" is
// defined for the project build for both the compiler and assembler.
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2013
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#if defined(__USE_ROMDIVIDE)
// Note that the romdivide "divmod" functions are not actually called from
// the below code, as these functions are actually just wrappers to the
// main romdivide "div" functions which push the quotient and remainder onto
// the stack, so as to be compatible with the way that C returns structures.
//
// This is not needed for the aeabi "divmod" functions, as the compiler
// automatically generates code that handles the return values being passed
// back in registers when it generates inline calls to __aeabi_idivmod and
// __aeabi_uidivmod routines.
.syntax unified
.text
// ========= __aeabi_idiv & __aeabi_idivmod =========
.align 2
.section .text.__aeabi_idiv
.global __aeabi_idiv
.set __aeabi_idivmod, __aeabi_idiv // make __aeabi_uidivmod an alias
.global __aeabi_idivmod
.global pDivRom_idiv // pointer to the romdivide 'idiv' functione
.func
.thumb_func
.type __aeabi_idiv, %function
__aeabi_idiv:
push {r4, lr}
ldr r3, =pDivRom_idiv
ldr r3, [r3, #0] // Load address of function
blx r3 // Call divide function
pop {r4, pc}
.endfunc
// ======== __aeabi_uidiv & __aeabi_uidivmod ========
.align 2
.section .text.__aeabi_uidiv
.global __aeabi_uidiv
.set __aeabi_uidivmod, __aeabi_uidiv // make __aeabi_uidivmod an alias
.global __aeabi_uidivmod
.global pDivRom_uidiv // pointer to the romdivide 'uidiv' function
.func
.thumb_func
.type __aeabi_uidiv, %function
__aeabi_uidiv:
push {r4, lr}
ldr r3, =pDivRom_uidiv
ldr r3, [r3, #0] // Load address of function
blx r3 // Call divide function
pop {r4, pc}
.endfunc
#endif // (__USE_ROMDIVIDE)

85
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c Normal file
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//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2013 Code Red Technologies Ltd.
//
// mtb.c
//
// Optionally defines an array to be used as a buffer for Micro Trace
// Buffer (MTB) instruction trace on Cortex-M0+ parts
//
// Version : 130502
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
/*******************************************************************
* Symbols controlling behavior of this code...
*
* __MTB_DISABLE
* If this symbol is defined, then the buffer array for the MTB
* will not be created.
*
* __MTB_BUFFER_SIZE
* Symbol specifying the sizer of the buffer array for the MTB.
* This must be a power of 2 in size, and fit into the available
* RAM. The MTB buffer will also be aligned to its 'size'
* boundary and be placed at the start of a RAM bank (which
* should ensure minimal or zero padding due to alignment).
*
* __MTB_RAM_BANK
* Allows MTB Buffer to be placed into specific RAM bank. When
* this is not defined, the "default" (first if there are
* several) RAM bank is used.
*******************************************************************/
// Ignore with none Code Red tools
#if defined (__CODE_RED)
// Allow MTB to be removed by setting a define (via command line)
#if !defined (__MTB_DISABLE)
// Allow for MTB buffer size being set by define set via command line
// Otherwise provide small default buffer
#if !defined (__MTB_BUFFER_SIZE)
#define __MTB_BUFFER_SIZE 128
#endif
// Check that buffer size requested is >0 bytes in size
#if (__MTB_BUFFER_SIZE > 0)
// Pull in MTB related macros
#include <cr_mtb_buffer.h>
// Check if MYTB buffer is to be placed in specific RAM bank
#if defined(__MTB_RAM_BANK)
// Place MTB buffer into explicit bank of RAM
__CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK);
#else
// Place MTB buffer into 'default' bank of RAM
__CR_MTB_BUFFER(__MTB_BUFFER_SIZE);
#endif // defined(__MTB_RAM_BANK)
#endif // (__MTB_BUFFER_SIZE > 0)
#endif // !defined (__MTB_DISABLE)
#endif // defined (__CODE_RED)

201
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp Normal file
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extern "C" {
#include "LPC11U6x.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
// Patch the AEABI integer divide functions to use MCU's romdivide library
#ifdef __USE_ROMDIVIDE
// Location in memory that holds the address of the ROM Driver table
#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))
// Variables to store addresses of idiv and udiv functions within MCU ROM
unsigned int *pDivRom_idiv;
unsigned int *pDivRom_uidiv;
#endif
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM0
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC11U68
PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
I2C1_IRQHandler, // 10 - I2C1
USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
I2C0_IRQHandler, // 15 - I2C0
TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
USART0_IRQHandler, // 21 - USART0
USB_IRQHandler, // 22 - USB IRQ
USB_FIQHandler, // 23 - USB FIQ
ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
RTC_IRQHandler, // 25 - Real Time CLock interrpt
BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
DMA_IRQHandler, // 28 - DMA interrupt
ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
0, // 31 - Reserved
};
/* End Vector */
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
/* Reset entry point*/
extern "C" void software_init_hook(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
// Patch the AEABI integer divide functions to use MCU's romdivide library
#ifdef __USE_ROMDIVIDE
// Get address of Integer division routines function table in ROM
unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
// Get addresses of integer divide routines in ROM
// These address are then used by the code in aeabi_romdiv_patch.s
pDivRom_idiv = (unsigned int *)div_ptr[0];
pDivRom_uidiv = (unsigned int *)div_ptr[1];
#endif
SystemInit();
if (software_init_hook)
software_init_hook();
else {
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {}
AFTER_VECTORS void HardFault_Handler (void) {}
AFTER_VECTORS void MemManage_Handler (void) {}
AFTER_VECTORS void BusFault_Handler (void) {}
AFTER_VECTORS void UsageFault_Handler(void) {}
AFTER_VECTORS void SVC_Handler (void) {}
AFTER_VECTORS void DebugMon_Handler (void) {}
AFTER_VECTORS void PendSV_Handler (void) {}
AFTER_VECTORS void SysTick_Handler (void) {}
AFTER_VECTORS void IntDefaultHandler (void) {}
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
}
#include <stdlib.h>
void *operator new(size_t size) {return malloc(size);}
void *operator new[](size_t size){return malloc(size);}
void operator delete(void *p) {free(p);}
void operator delete[](void *p) {free(p);}

2
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c
View File

@ -474,7 +474,7 @@ static void power_up_config(uint32_t val)
*/
void SystemInit (void) {
#if (CLOCK_SETUP)
volatile uint32_t i, tmp;
volatile uint32_t i;
#endif
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;

151
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld Normal file
View File

@ -0,0 +1,151 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text.Reset_Handler)
/* Only vectors and code running at reset are safe to be in first 512
bytes since RAM can be mapped into this area for RAM based interrupt
vectors. */
. = 0x00000200;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

6
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h
View File

@ -1502,7 +1502,11 @@ typedef struct { /*!< C_CAN0 Structure
__IO uint32_t CANIF2_ARB1; /*!< Message interface 1 arbitration 1 */
__IO uint32_t CANIF2_ARB2; /*!< Message interface 1 arbitration 2 */
__IO uint32_t CANIF2_MCTRL; /*!< Message interface 1 message control */
__I uint32_t RESERVED2[25];
__IO uint32_t CANIF2_DA1; /*!< Message interface 2 data A1 */
__IO uint32_t CANIF2_DA2; /*!< Message interface 2 data A2 */
__IO uint32_t CANIF2_DB1; /*!< Message interface 2 data B1 */
__IO uint32_t CANIF2_DB2; /*!< Message interface 2 data B2 */
__I uint32_t RESERVED2[21];
__I uint32_t CANTXREQ1; /*!< Transmission request 1 */
__I uint32_t CANTXREQ2; /*!< Transmission request 2 */
__I uint32_t RESERVED3[6];

214
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/LPC1549.ld Normal file
View File

@ -0,0 +1,214 @@
/*Based on following file*/
/*
* GENERATED FILE - DO NOT EDIT
* (c) Code Red Technologies Ltd, 2008-13
* (c) NXP Semiconductors 2013-2014
* Generated linker script file for LPC1549
* Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Tue Jun 10 00:20:53 JST 2014
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
Ram0_16 (rwx) : ORIGIN = 0x2000000+0x100, LENGTH = 0x4000-0x100 /* 16K bytes */
Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes */
Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes */
}
/* Define a symbol for the top of each memory region */
__top_MFlash256 = 0x0 + 0x40000;
__top_Ram0_16 = 0x2000000 + 0x4000;
__top_Ram1_16 = 0x2004000 + 0x4000;
__top_Ram2_4 = 0x2008000 + 0x1000;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(4);
/* C++ constructors etc */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > MFlash256
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
__exidx_end = .;
_etext = .;
/* DATA section for Ram1_16 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_16)
*(.data.$RAM2*)
*(.data.$Ram1_16*)
. = ALIGN(4) ;
} > Ram1_16 AT>MFlash256
/* DATA section for Ram2_4 */
.data_RAM3 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2_4)
*(.data.$RAM3*)
*(.data.$Ram2_4*)
. = ALIGN(4) ;
} > Ram2_4 AT>MFlash256
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(4)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > Ram0_16
/* Main DATA section (Ram0_16) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > Ram0_16 AT>MFlash256
/* BSS section for Ram1_16 */
.bss_RAM2 : ALIGN(4)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_16*)
. = ALIGN(4) ;
} > Ram1_16
/* BSS section for Ram2_4 */
.bss_RAM3 : ALIGN(4)
{
*(.bss.$RAM3*)
*(.bss.$Ram2_4*)
. = ALIGN(4) ;
} > Ram2_4
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_16
/* NOINIT section for Ram1_16 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_16*)
. = ALIGN(4) ;
} > Ram1_16
/* NOINIT section for Ram2_4 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2_4*)
. = ALIGN(4) ;
} > Ram2_4
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > Ram0_16
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_Ram0_16 - 0);
}

219
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp Normal file
View File

@ -0,0 +1,219 @@
extern "C" {
#include "LPC15xx.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
void ResetISR (void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0A_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0B_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1A_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1B_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP3_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_ALARM_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_WAKE_IRQHandler(void) ALIAS(IntDefaultHandler);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC15xx
WDT_IRQHandler, // 0 - Windowed watchdog timer
BOD_IRQHandler, // 1 - BOD
FMC_IRQHandler, // 2 - Flash controller
EEPROM_IRQHandler, // 3 - EEPROM controller
DMA_IRQHandler, // 4 - DMA
GINT0_IRQHandler, // 5 - GINT0
GINT1_IRQHandler, // 6 - GINT1
PIN_INT0_IRQHandler, // 7 - PIO INT0
PIN_INT1_IRQHandler, // 8 - PIO INT1
PIN_INT2_IRQHandler, // 9 - PIO INT2
PIN_INT3_IRQHandler, // 10 - PIO INT3
PIN_INT4_IRQHandler, // 11 - PIO INT4
PIN_INT5_IRQHandler, // 12 - PIO INT5
PIN_INT6_IRQHandler, // 13 - PIO INT6
PIN_INT7_IRQHandler, // 14 - PIO INT7
RIT_IRQHandler, // 15 - RIT
SCT0_IRQHandler, // 16 - State configurable timer
SCT1_IRQHandler, // 17 - State configurable timer
SCT2_IRQHandler, // 18 - State configurable timer
SCT3_IRQHandler, // 19 - State configurable timer
MRT_IRQHandler, // 20 - Multi-Rate Timer
UART0_IRQHandler, // 21 - UART0
UART1_IRQHandler, // 22 - UART1
UART2_IRQHandler, // 23 - UART2
I2C0_IRQHandler, // 24 - I2C0 controller
SPI0_IRQHandler, // 25 - SPI0 controller
SPI1_IRQHandler, // 26 - SPI1 controller
CAN_IRQHandler, // 27 - C_CAN0
USB_IRQHandler, // 28 - USB IRQ
USB_FIQHandler, // 29 - USB FIQ
USBWakeup_IRQHandler, // 30 - USB wake-up
ADC0A_IRQHandler, // 31 - ADC0 sequence A completion
ADC0B_IRQHandler, // 32 - ADC0 sequence B completion
ADC0_THCMP_IRQHandler, // 33 - ADC0 threshold compare
ADC0_OVR_IRQHandler, // 34 - ADC0 overrun
ADC1A_IRQHandler, // 35 - ADC1 sequence A completion
ADC1B_IRQHandler, // 36 - ADC1 sequence B completion
ADC1_THCMP_IRQHandler, // 37 - ADC1 threshold compare
ADC1_OVR_IRQHandler, // 38 - ADC1 overrun
DAC_IRQHandler, // 39 - DAC
ACMP0_IRQHandler, // 40 - Analog Comparator 0
ACMP1_IRQHandler, // 41 - Analog Comparator 1
ACMP2_IRQHandler, // 42 - Analog Comparator 2
ACMP3_IRQHandler, // 43 - Analog Comparator 3
QEI_IRQHandler, // 44 - QEI
RTC_ALARM_IRQHandler, // 45 - RTC alarm
RTC_WAKE_IRQHandler, // 46 - RTC wake-up
};
/* End Vector */
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
/* Reset entry point*/
extern "C" void software_init_hook(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
SystemInit();
if (software_init_hook)
software_init_hook();
else {
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {}
AFTER_VECTORS void HardFault_Handler (void) {}
AFTER_VECTORS void MemManage_Handler (void) {}
AFTER_VECTORS void BusFault_Handler (void) {}
AFTER_VECTORS void UsageFault_Handler(void) {}
AFTER_VECTORS void SVC_Handler (void) {}
AFTER_VECTORS void DebugMon_Handler (void) {}
AFTER_VECTORS void PendSV_Handler (void) {}
AFTER_VECTORS void SysTick_Handler (void) {}
AFTER_VECTORS void IntDefaultHandler (void) {}
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
}
#include <stdlib.h>
void *operator new(size_t size) {return malloc(size);}
void *operator new[](size_t size){return malloc(size);}
void operator delete(void *p) {free(p);}
void operator delete[](void *p) {free(p);}

3
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_functions.s
View File

@ -77,7 +77,6 @@ __mbed_dcc_irq:
Reset_Handler:
.extern __libc_init_array
.extern SystemInit
.extern __wrap_main
LDR R0, =SystemInit
MOV LR, PC
BX R0
@ -86,7 +85,7 @@ Reset_Handler:
MOV LR, PC
BX R0
LDR R0, =__wrap_main
LDR R0, =main
BX R0
__mbed_reset:

3018
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h
View File

File diff suppressed because it is too large Load Diff

12
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini Normal file
View File

@ -0,0 +1,12 @@
FUNC void Setup (unsigned int region) {
region &= 0xFF000000;
_WDWORD(0x40043100, region); // Set the shadow pointer
_WDWORD(0xE000ED08, 0); // Set the vector table offset to 0
SP = _RDWORD(0); // Setup Stack Pointer
PC = _RDWORD(4); // Setup Program Counter
}
LOAD %L INCREMENTAL
Setup(0x14000000); // Get ready to execute image in QSPI

13
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/startup_LPC43xx.s
View File

@ -29,7 +29,8 @@
; * this code.
; */
__initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX
; __initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX (IRAM1)
__initial_sp EQU 0x10092000 ; Top of first RAM segment for LPC43XX (IRAM2)
PRESERVE8
THUMB
@ -121,19 +122,21 @@ __Vectors DCD __initial_sp ; 0 Top of Stack
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]

284
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld
View File

@ -1,19 +1,281 @@
/*
* LPC43XX Dual core Blinky stand-alone Cortex-M4 LD script
*/
/* mbed - LPC4330_M4 linker script
* Based linker script generated by Code Red Technologies Red Suite 7.0
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
RO_MEM (rx) : ORIGIN = 0x14000000, LENGTH = 0x40000 /* 256K */
RW_MEM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
RW_MEM1 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x4000 /* 16K */
SH_MEM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8k */
FAT12_MEM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 /* 8k */
RamLoc128 (rwx) : ORIGIN = 0x10000118, LENGTH = 0x1FEE8 /* 128K bytes */
RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */
RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes */
RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes */
RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes */
SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes */
}
/* Define a symbol for the top of each memory region */
__top_RamLoc128 = 0x10000000 + 0x20000;
__top_RamLoc72 = 0x10080000 + 0x12000;
__top_RamAHB32 = 0x20000000 + 0x8000;
__top_RamAHB16 = 0x20008000 + 0x4000;
__top_RamAHB_ETB16 = 0x2000c000 + 0x4000;
__top_SPIFI = 0x14000000 + 0x400000;
__top_RW_MEM = 0x10000000 + 0x8000;
ENTRY(ResetISR)
INCLUDE "lpc43xx_dualcore_lib.ld"
INCLUDE "lpc43xx_dualcore.ld"
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
LONG(LOADADDR(.data_RAM4));
LONG( ADDR(.data_RAM4));
LONG( SIZEOF(.data_RAM4));
LONG(LOADADDR(.data_RAM5));
LONG( ADDR(.data_RAM5));
LONG( SIZEOF(.data_RAM5));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
LONG( ADDR(.bss_RAM4));
LONG( SIZEOF(.bss_RAM4));
LONG( ADDR(.bss_RAM5));
LONG( SIZEOF(.bss_RAM5));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
} >SPIFI
.text : ALIGN(4)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
/* C++ constructors etc */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > SPIFI
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SPIFI
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SPIFI
__exidx_end = .;
_etext = .;
/* DATA section for RamLoc72 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$RamLoc72)
*(.data.$RAM2*)
*(.data.$RamLoc72*)
. = ALIGN(4) ;
} > RamLoc72 AT>SPIFI
/* DATA section for RamAHB32 */
.data_RAM3 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$RamAHB32)
*(.data.$RAM3*)
*(.data.$RamAHB32*)
. = ALIGN(4) ;
} > RamAHB32 AT>SPIFI
/* DATA section for RamAHB16 */
.data_RAM4 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM4)
*(.ramfunc.$RamAHB16)
*(.data.$RAM4*)
*(.data.$RamAHB16*)
. = ALIGN(4) ;
} > RamAHB16 AT>SPIFI
/* DATA section for RamAHB_ETB16 */
.data_RAM5 : ALIGN(4)
{
FILL(0xff)
*(.ramfunc.$RAM5)
*(.ramfunc.$RamAHB_ETB16)
*(.data.$RAM5*)
*(.data.$RamAHB_ETB16*)
. = ALIGN(4) ;
} > RamAHB_ETB16 AT>SPIFI
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(4)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > RamLoc128
/* Main DATA section (RamLoc128) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > RamLoc128 AT>SPIFI
/* BSS section for RamLoc72 */
.bss_RAM2 : ALIGN(4)
{
*(.bss.$RAM2*)
*(.bss.$RamLoc72*)
. = ALIGN(4) ;
} > RamLoc72
/* BSS section for RamAHB32 */
.bss_RAM3 : ALIGN(4)
{
*(.bss.$RAM3*)
*(.bss.$RamAHB32*)
. = ALIGN(4) ;
} > RamAHB32
/* BSS section for RamAHB16 */
.bss_RAM4 : ALIGN(4)
{
*(.bss.$RAM4*)
*(.bss.$RamAHB16*)
. = ALIGN(4) ;
} > RamAHB16
/* BSS section for RamAHB_ETB16 */
.bss_RAM5 : ALIGN(4)
{
*(.bss.$RAM5*)
*(.bss.$RamAHB_ETB16*)
. = ALIGN(4) ;
} > RamAHB_ETB16
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
} > RamLoc128
/* NOINIT section for RamLoc72 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM2*)
*(.noinit.$RamLoc72*)
. = ALIGN(4) ;
} > RamLoc72
/* NOINIT section for RamAHB32 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM3*)
*(.noinit.$RamAHB32*)
. = ALIGN(4) ;
} > RamAHB32
/* NOINIT section for RamAHB16 */
.noinit_RAM4 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM4*)
*(.noinit.$RamAHB16*)
. = ALIGN(4) ;
} > RamAHB16
/* NOINIT section for RamAHB_ETB16 */
.noinit_RAM5 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM5*)
*(.noinit.$RamAHB_ETB16*)
. = ALIGN(4) ;
} > RamAHB_ETB16
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc128
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc128 - 0);
}

495
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp
View File

@ -1,10 +1,10 @@
// *****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2011-12 Code Red Technologies Ltd.
//
// LPC43xx Microcontroller Startup code for use with Red Suite
@ -12,62 +12,58 @@
// Version : 120430
//
// Software License Agreement
//
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
// CODE RED TECHNOLOGIES LTD.
//
// *****************************************************************************
#if defined(__cplusplus)
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
// *****************************************************************************
//*****************************************************************************
//
// The entry point for the C++ library startup
//
// *****************************************************************************
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias(# f)))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
//#if defined (__USE_CMSIS)
// Code Red - if CMSIS is being used, then SystemInit() routine
// will be called by startup code rather than in application's main()
#if defined (__USE_CMSIS)
#include "LPC43xx.h"
//#endif
#if defined(OS_UCOS_III)
extern void OS_CPU_PendSVHandler(void);
extern void OS_CPU_SysTickHandler (void);
#endif
// *****************************************************************************
#if defined(__cplusplus)
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
// *****************************************************************************
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
// *****************************************************************************
void ResetISR(void);
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
@ -79,18 +75,19 @@ WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
// *****************************************************************************
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
// *****************************************************************************
//*****************************************************************************
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
void MX_CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLASHEEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
void EZH_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
@ -105,8 +102,8 @@ void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
@ -130,157 +127,130 @@ void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void M0s_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
// *****************************************************************************
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
// *****************************************************************************
#if defined(__REDLIB__)
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
// *****************************************************************************
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
// *****************************************************************************
//*****************************************************************************
extern void _vStackTop(void);
// *****************************************************************************
//
// Application can define Stack size (If not defined, default stack size will
// used
//
// *****************************************************************************
#ifndef STACK_SIZE
#define STACK_SIZE (0x200)
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
// *****************************************************************************
//
// Application can define Heap size (If not defined, default Heap size will
// used
//
// *****************************************************************************
#ifndef HEAP_SIZE
#define HEAP_SIZE (0x4000)
#endif
unsigned int __vStack[STACK_SIZE / sizeof(unsigned int)] __attribute__((section("STACK,\"aw\",%nobits@")));
unsigned int __vHeap[HEAP_SIZE / sizeof(unsigned int)] __attribute__((section("HEAP,\"aw\",%nobits@")));
// *****************************************************************************
#if defined(__cplusplus)
} // extern "C"
#endif
// *****************************************************************************
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
// *****************************************************************************
extern void(*const g_pfnVectors[]) (void);
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void(*const g_pfnVectors[]) (void) = {
// Core Level - CM4/CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
#if defined(OS_UCOS_III)
OS_CPU_PendSVHandler, // uCOS-III PendSV handler
OS_CPU_SysTickHandler, // uCOS-III SysTick handler
#else
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
#endif
void (* const g_pfnVectors[])(void) = {
// Core Level - CM4
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC18xx/43xx
DAC_IRQHandler, // 16 D/A Converter
MX_CORE_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY)
DMA_IRQHandler, // 18 General Purpose DMA
0, // 19 Reserved
FLASHEEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
ETH_IRQHandler, // 21 Ethernet
SDIO_IRQHandler, // 22 SD/MMC
LCD_IRQHandler, // 23 LCD
USB0_IRQHandler, // 24 USB0
USB1_IRQHandler, // 25 USB1
SCT_IRQHandler, // 26 State Configurable Timer
RIT_IRQHandler, // 27 Repetitive Interrupt Timer
TIMER0_IRQHandler, // 28 Timer0
TIMER1_IRQHandler, // 29 Timer 1
TIMER2_IRQHandler, // 30 Timer 2
TIMER3_IRQHandler, // 31 Timer 3
MCPWM_IRQHandler, // 32 Motor Control PWM
ADC0_IRQHandler, // 33 A/D Converter 0
I2C0_IRQHandler, // 34 I2C0
I2C1_IRQHandler, // 35 I2C1
SPI_IRQHandler, // 36 SPI (LPC43XX ONLY)
ADC1_IRQHandler, // 37 A/D Converter 1
SSP0_IRQHandler, // 38 SSP0
SSP1_IRQHandler, // 39 SSP1
UART0_IRQHandler, // 40 UART0
UART1_IRQHandler, // 41 UART1
UART2_IRQHandler, // 42 UART2
UART3_IRQHandler, // 43 USRT3
I2S0_IRQHandler, // 44 I2S0
I2S1_IRQHandler, // 45 I2S1
SPIFI_IRQHandler, // 46 SPI Flash Interface
SGPIO_IRQHandler, // 47 SGPIO (LPC43XX ONLY)
GPIO0_IRQHandler, // 48 GPIO0
GPIO1_IRQHandler, // 49 GPIO1
GPIO2_IRQHandler, // 50 GPIO2
GPIO3_IRQHandler, // 51 GPIO3
GPIO4_IRQHandler, // 52 GPIO4
GPIO5_IRQHandler, // 53 GPIO5
GPIO6_IRQHandler, // 54 GPIO6
GPIO7_IRQHandler, // 55 GPIO7
GINT0_IRQHandler, // 56 GINT0
GINT1_IRQHandler, // 57 GINT1
EVRT_IRQHandler, // 58 Event Router
CAN1_IRQHandler, // 59 C_CAN1
0, // 60 Reserved
0, // 61 Reserved
ATIMER_IRQHandler, // 62 ATIMER
RTC_IRQHandler, // 63 RTC
0, // 64 Reserved
WDT_IRQHandler, // 65 WDT
0, // 66 Reserved
CAN0_IRQHandler, // 67 C_CAN0
QEI_IRQHandler, // 68 QEI
};
// Chip Level - LPC43
DAC_IRQHandler, // 16
M0CORE_IRQHandler, // 17
DMA_IRQHandler, // 18
EZH_IRQHandler, // 19
FLASH_EEPROM_IRQHandler, // 20
ETH_IRQHandler, // 21
SDIO_IRQHandler, // 22
LCD_IRQHandler, // 23
USB0_IRQHandler, // 24
USB1_IRQHandler, // 25
SCT_IRQHandler, // 26
RIT_IRQHandler, // 27
TIMER0_IRQHandler, // 28
TIMER1_IRQHandler, // 29
TIMER2_IRQHandler, // 30
TIMER3_IRQHandler, // 31
MCPWM_IRQHandler, // 32
ADC0_IRQHandler, // 33
I2C0_IRQHandler, // 34
I2C1_IRQHandler, // 35
SPI_IRQHandler, // 36
ADC1_IRQHandler, // 37
SSP0_IRQHandler, // 38
SSP1_IRQHandler, // 39
UART0_IRQHandler, // 40
UART1_IRQHandler, // 41
UART2_IRQHandler, // 42
UART3_IRQHandler, // 43
I2S0_IRQHandler, // 44
I2S1_IRQHandler, // 45
SPIFI_IRQHandler, // 46
SGPIO_IRQHandler, // 47
GPIO0_IRQHandler, // 48
GPIO1_IRQHandler, // 49
GPIO2_IRQHandler, // 50
GPIO3_IRQHandler, // 51
GPIO4_IRQHandler, // 52
GPIO5_IRQHandler, // 53
GPIO6_IRQHandler, // 54
GPIO7_IRQHandler, // 55
GINT0_IRQHandler, // 56
GINT1_IRQHandler, // 57
EVRT_IRQHandler, // 58
CAN1_IRQHandler, // 59
0, // 60
VADC_IRQHandler, // 61
ATIMER_IRQHandler, // 62
RTC_IRQHandler, // 63
0, // 64
WDT_IRQHandler, // 65
M0s_IRQHandler, // 66
CAN0_IRQHandler, // 67
QEI_IRQHandler, // 68
};
// *****************************************************************************
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
// *****************************************************************************
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int *) start;
unsigned int *pulSrc = (unsigned int *) romstart;
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
@ -288,49 +258,94 @@ void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int *) start;
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
// *****************************************************************************
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
// *****************************************************************************
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
// *****************************************************************************
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//
// *****************************************************************************
extern "C" void software_init_hook(void) __attribute__((weak));
//*****************************************************************************
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
// *************************************************************
// The following conditional block of code manually resets as
// much of the peripheral set of the LPC43 as possible. This is
// done because the LPC43 does not provide a means of triggering
// a full system reset under debugger control, which can cause
// problems in certain circumstances when debugging.
//
// You can prevent this code block being included if you require
// (for example when creating a final executable which you will
// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
//
#ifndef DONT_RESET_ON_RESTART
// Disable interrupts
__asm volatile ("cpsid i");
// equivalent to CMSIS '__disable_irq()' function
unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
// LPC_RGU->RESET_CTRL0 @ 0x40053100
// LPC_RGU->RESET_CTRL1 @ 0x40053104
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
// Write to LPC_RGU->RESET_CTRL0
*(RESET_CONTROL+0) = 0x10DF0000;
// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
// USB1_RST|USB0_RST|LCD_RST
// Write to LPC_RGU->RESET_CTRL1
*(RESET_CONTROL+1) = 0x01DFF7FF;
// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
// Clear all pending interrupts in the NVIC
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
unsigned int irqpendloop;
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
*(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF;
}
// Reenable interrupts
__asm volatile ("cpsie i");
// equivalent to CMSIS '__enable_irq()' function
#endif // ifndef DONT_RESET_ON_RESTART
// *************************************************************
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
/* Call SystemInit() for clocking/memory setup prior to scatter load */
SystemInit();
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
@ -345,107 +360,141 @@ ResetISR(void) {
bss_init(ExeAddr, SectionLen);
}
if (software_init_hook) // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
else {
#if defined(__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
/*
* Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/
// CPACR is located at address 0xE000ED88
asm("LDR.W R0, =0xE000ED88");
// Read CPACR
asm("LDR R1, [R0]");
// Set bits 20-23 to enable CP10 and CP11 coprocessors
asm(" ORR R1, R1, #(0xF << 20)");
// Write back the modified value to the CPACR
asm("STR R1, [R0]");
#endif // (__VFP_FP__) && !(__SOFTFP__)
#if defined(__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
}
// ******************************
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
// CMSIS : SCB->VTOR = <address of vector table>
*pSCB_VTOR = (unsigned int)g_pfnVectors;
}
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
// Call C++ library initialisation
//
while (1) {}
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
// *****************************************************************************
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
// *****************************************************************************
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{
while (1) {}
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void)
{
while (1) {}
while(1)
{
}
}
// *****************************************************************************
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
// *****************************************************************************
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{
while (1) {}
while(1)
{
}
}
// *****************************************************************************
//
// Heap overflow check function required by REDLib_V2 library
//
// *****************************************************************************
extern unsigned int *_pvHeapStart;
unsigned int __check_heap_overflow (void * new_end_of_heap)
{
return (new_end_of_heap >= (void *)&__vHeap[HEAP_SIZE/sizeof(unsigned int)]);
}

262
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c
View File

@ -35,8 +35,11 @@
#define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
/* Clock variables */
//uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN; /*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock = 204000000;
#if (CLOCK_SETUP)
uint32_t SystemCoreClock = MAX_CLOCK_FREQ;
#else
uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN;
#endif
#if !defined(CORE_M0)
/* SCU pin definitions for pin muxing */
@ -45,32 +48,80 @@ typedef struct {
uint16_t mode; /* SCU pin mode and function */
} PINMUX_GRP_T;
/* Local functions */
static void SystemCoreClockUpdate(void);
static void SystemSetupClock(void);
static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
static void SystemSetupMemory(void);
static void WaitUs(uint32_t us);
/* Pins to initialize before clocks are configured */
static const PINMUX_GRP_T pre_clock_mux[] = {
/* SPIFI pins */
{SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, // P3_3 SPIFI CLK
{SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, // P3_4 SPIFI D3
{SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, // P3_5 SPIFI D2
{SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, // P3_6 SPIFI D1
{SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, // P3_7 SPIFI D0
{SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} // P3_8 SPIFI CS/SSEL
{SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
{SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
{SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
{SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
{SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
{SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
};
/* Pins to initialize after clocks are configured */
static const PINMUX_GRP_T post_clock_mux[] = {
/* Boot pins */
{SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, // P1_1 BOOT0
{SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, // P1_2 BOOT1
{SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, // P2_8 BOOT2
{SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)} // P2_9 BOOT3
{SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
{SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
{SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
{SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
/* Micromint Bambino 200/210 */
{SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
{SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
{SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
/* Micromint Bambino 210 */
{SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
{SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
};
#if (CLOCK_SETUP)
/* Structure for initial base clock states */
struct CLK_BASE_STATES {
CGU_BASE_CLK_T clk; /* Base clock */
CGU_CLKIN_T clkin; /* Base clock source */
uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
};
/* Initial base clock states are mostly on */
static const struct CLK_BASE_STATES clock_states[] = {
{CLK_BASE_SAFE, CLKIN_IRC, 0},
{CLK_BASE_APB1, CLKIN_MAINPLL, 0},
{CLK_BASE_APB3, CLKIN_MAINPLL, 0},
{CLK_BASE_USB0, CLKIN_USBPLL, 1},
{CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
{CLK_BASE_SPI, CLKIN_MAINPLL, 0},
{CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
#if defined(USE_RMII)
{CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
#else
{CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
#endif
{CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
{CLK_BASE_SSP0, CLKIN_MAINPLL, 0},
{CLK_BASE_SSP1, CLKIN_MAINPLL, 0},
{CLK_BASE_UART0, CLKIN_MAINPLL, 0},
{CLK_BASE_UART1, CLKIN_MAINPLL, 0},
{CLK_BASE_UART2, CLKIN_MAINPLL, 0},
{CLK_BASE_UART3, CLKIN_MAINPLL, 0},
{CLK_BASE_OUT, CLKINPUT_PD, 0},
{CLK_BASE_APLL, CLKINPUT_PD, 0},
{CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
{CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
/* Clocks derived from dividers */
{CLK_BASE_LCD, CLKIN_IDIVC, 0},
{CLK_BASE_USB1, CLKIN_IDIVD, 1}
};
#endif /* defined(CLOCK_SETUP) */
/* Local functions */
static uint32_t SystemGetMainPLLHz(void);
static void SystemSetupClock(void);
static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
static void SystemSetupMemory(void);
static void WaitUs(uint32_t us);
#endif /* !defined(CORE_M0) */
/*
@ -79,33 +130,34 @@ static const PINMUX_GRP_T post_clock_mux[] = {
void SystemInit(void)
{
#if !defined(CORE_M0)
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
/* Initialize vector table in flash */
#if defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
SCB->VTOR = (unsigned int) &__Vectors;
#elif defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
SCB->VTOR = (unsigned int) &__vector_table;
#elif defined(TOOLCHAIN_GCC_ARM)
extern void *__isr_vector;
*pSCB_VTOR = (unsigned int) &__isr_vector;
SCB->VTOR = (unsigned int) &__isr_vector;
#else /* defined(__GNUC__) and others */
extern void *g_pfnVectors;
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
SCB->VTOR = (unsigned int) &g_pfnVectors;
#endif
#if !defined(TOOLCHAIN_GCC)
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
/* Initialize floating point */
fpuInit();
#endif
#endif
SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
SystemSetupClock(); /* Configure processor and peripheral clocks */
SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
SystemSetupMemory(); /* Configure external memory */
@ -119,44 +171,125 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
uint32_t reg, div, rate;
/* Get main PLL rate */
rate = SystemGetMainPLLHz();
/* Get clock divider */
reg = LPC_CCU1->CLKCCU[CLK_MX_MXCORE].CFG;
if (((reg >> 5) & 0x7) == 0) {
div = 1;
}
else {
div = 2;
}
rate = rate / div;
SystemCoreClock = rate;
}
/* Returns the frequency of the main PLL */
uint32_t SystemGetMainPLLHz(void)
{
uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
uint32_t freq = CRYSTAL_MAIN_FREQ_IN;
uint32_t msel, nsel, psel, direct, fbsel;
uint32_t m, n, p;
const uint8_t ptab[] = {1, 2, 4, 8};
msel = (PLLReg >> 16) & 0xFF;
nsel = (PLLReg >> 12) & 0x3;
psel = (PLLReg >> 8) & 0x3;
direct = (PLLReg >> 7) & 0x1;
fbsel = (PLLReg >> 6) & 0x1;
m = msel + 1;
n = nsel + 1;
p = ptab[psel];
if (direct || fbsel) {
return m * (freq / n);
}
return (m / (2 * p)) * (freq / n);
}
#if !defined(CORE_M0)
/*
* SystemSetupClock() - Set processor and peripheral clocks
*
* Clock Frequency Source
* CLK_BASE_MX 204 MHz CLKIN_MAINPLL (CLKIN_PLL1)
* CLK_BASE_SPIFI 102 MHz CLKIN_IDIVE
* CLK_BASE_USB0 480 MHz CLKIN_USBPLL (Disabled) (CLKIN_PLL0USB)
* CLK_BASE_USB1 60 MHz CLKIN_IDIVE (Disabled)
* 120 MHz CLKIN_IDIVD (Disabled)
*
* 12 MHz CLKIN_IDIVB
* 12 MHz CLKIN_IDIVC
*
*/
void SystemSetupClock(void)
{
#if (CLOCK_SETUP)
/* Switch main clock to Internal RC (IRC) */
LPC_CGU->BASE_CLK[CLK_BASE_MX] = ((1 << 11) | (CLKIN_IRC << 24));
uint32_t i;
/* Switch main clock to Internal RC (IRC) while setting up PLL1 */
LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
/* Enable the oscillator and wait 100 us */
LPC_CGU->XTAL_OSC_CTRL = 0;
WaitUs(100);
#if (SPIFI_INIT)
/* Switch IDIVA clock to IRC and connect to SPIFI clock */
LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = ((1 << 11) | (CLKIN_IRC << 24));
LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVA << 24));
/* Setup SPIFI control register and no-opcode mode */
LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
LPC_SPIFI->IDATA = 0xA5;
/* Switch IDIVE clock to IRC and connect to SPIFI clock */
LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
#endif /* SPIFI_INIT */
/* Power down PLL1 */
LPC_CGU->PLL1_CTRL |= 1;
/* Configure PLL1 (MAINPLL) for main clock */
LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
/* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
// LPC_CGU->PLL1_CTRL = (DIRECT << 7) | (PSEL << 8) | (1 << 11) | (P(NSEL-1) << 12) | ((MSEL-1) << 16) | (CLKIN_PLL1 << 24);
LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16) | (CLKIN_PLL1 << 24);
LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
| (CLKIN_MAINPLL << 24);
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
WaitUs(100);
/* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16) | (CLKIN_PLL1 << 24);
LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
| (CLKIN_MAINPLL << 24);
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
/* Switch main clock to PLL1 */
LPC_CGU->BASE_CLK[CLK_BASE_MX] = ((1 << 11) | (CLKIN_PLL1 << 24));
SystemCoreClock = 204000000;
/* Connect main clock to PLL1 */
LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
/* Set USB PLL dividers for 480 MHz (for USB0) */
LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL = 0x0000081D | (CLKIN_CRYSTAL << 24);
/* Set IDIVE clock to PLL1/2 = 102 MHz */
LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
/* Set IDIVD clock to ((USBPLL/4) / 2) = 60 MHz (for USB1) */
LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = (3 << 2) | (1 << 11) | (CLKIN_USBPLL << 24); /* USBPLL/4 */
LPC_CGU->IDIV_CTRL[CLK_IDIV_D] = (1 << 2) | (1 << 11) | (CLKIN_IDIVA << 24); /* IDIVA/2 */
/* Configure remaining integer dividers */
LPC_CGU->IDIV_CTRL[CLK_IDIV_B] = (0 << 2) | (1 << 11) | (CLKIN_IRC << 24); /* IRC */
LPC_CGU->IDIV_CTRL[CLK_IDIV_C] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
/* Connect base clocks */
for (i = 0; i < COUNT_OF(clock_states); i++) {
LPC_CGU->BASE_CLK[clock_states[i].clk] =
( clock_states[i].powerdn << 0)
| (1 << 11) | (clock_states[i].clkin << 24);
}
#endif /* CLOCK_SETUP */
}
@ -165,7 +298,7 @@ void SystemSetupClock(void)
*/
void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
{
uint16_t i;
uint32_t i;
for (i = 0; i < n; i++) {
*(mux[i].reg) = mux[i].mode;
@ -188,35 +321,36 @@ void SystemSetupMemory(void)
*/
void fpuInit(void)
{
// from ARM TRM manual:
// ; CPACR is located at address 0xE000ED88
// LDR.W R0, =0xE000ED88
// ; Read CPACR
// LDR R1, [R0]
// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
// ORR R1, R1, #(0xF << 20)
// ; Write back the modified value to the CPACR
// STR R1, [R0]
/*
* from ARM TRM manual:
* ; CPACR is located at address 0xE000ED88
* LDR.W R0, =0xE000ED88
* ; Read CPACR
* LDR R1, [R0]
* ; Set bits 20-23 to enable CP10 and CP11 coprocessors
* ORR R1, R1, #(0xF << 20)
* ; Write back the modified value to the CPACR
* STR R1, [R0]
*/
volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
volatile uint32_t Cpacr;
volatile uint32_t Mvfr0;
volatile uint32_t Mvfr1;
char vfpPresent = 0;
volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
volatile uint32_t Cpacr;
volatile uint32_t Mvfr0;
volatile uint32_t Mvfr1;
char vfpPresent = 0;
Mvfr0 = *regMvfr0;
Mvfr1 = *regMvfr1;
Mvfr0 = *regMvfr0;
Mvfr1 = *regMvfr1;
vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
if (vfpPresent) {
Cpacr = *regCpacr;
Cpacr |= (0xF << 20);
*regCpacr = Cpacr; // enable CP10 and CP11 for full access
}
vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
if (vfpPresent) {
Cpacr = *regCpacr;
Cpacr |= (0xF << 20);
*regCpacr = Cpacr; /* enable CP10 and CP11 for full access */
}
}
#endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */

1
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h
View File

@ -81,6 +81,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx.h
View File

@ -76,7 +76,7 @@
*/
#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
#define STM32F030
/* #define STM32F030 */
/* #define STM32F031 */
#define STM32F051
/* #define STM32F072 */

220
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/system_stm32f0xx.c
View File

@ -3,11 +3,11 @@
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V1.0.1
* @date 29-May-2012
* @date 12-January-2014
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F0xx devices,
* and is generated by the clock configuration tool
* STM32f0xx_Clock_Configuration_V1.0.1.xls
* STM32F0xx_Clock_Configuration_V1.0.1.xls
*
* 1. This file provides two functions and one global variable to be called from
* user application:
@ -40,52 +40,44 @@
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* System Clock source | PLL(HSI)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 48000000
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
* | (external 8 MHz clock) | (internal 8 MHz)
* | 2- PLL_HSE_XTAL |
* | (external 8 MHz xtal) |
*-----------------------------------------------------------------------------
* HCLK(Hz) | 48000000
* SYSCLK(MHz) | 48 | 48
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
* AHBCLK (MHz) | 48 | 48
*-----------------------------------------------------------------------------
* APB Prescaler | 1
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | NA
*----------------------------------------------------------------------------
* PLLMUL | 12
*-----------------------------------------------------------------------------
* PREDIV | 2
*-----------------------------------------------------------------------------
* I2S input clock(Hz) | 48000000
* |
* To achieve the following I2S config: |
* - Master clock output (MCKO): OFF |
* - Frame wide : 16bit |
* - Audio sampling freq (KHz) : 44.1 |
* - Error % : 0.2674 |
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 1
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
* APBCLK (MHz) | 48 | 48
*-----------------------------------------------------------------------------
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
@ -127,6 +119,10 @@
* @{
*/
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
/**
* @}
*/
@ -145,7 +141,11 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
* @{
*/
static void SetSysClock(void);
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif
uint8_t SetSysClock_PLL_HSI(void);
/**
* @}
@ -191,7 +191,8 @@ void SystemInit (void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
}
@ -275,35 +276,136 @@ void SystemCoreClockUpdate (void)
}
/**
* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
* settings.
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
* @param None
* @retval None
*/
static void SetSysClock(void)
void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
/* 1- Try to start with HSE and external clock */
#if USE_PLL_HSE_EXTC != 0
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
/* 2- If fail try to start with HSE and external xtal */
#if USE_PLL_HSE_XTAL != 0
if (SetSysClock_PLL_HSE(0) == 0)
#endif
{
/* 3- If fail start with HSI clock */
if (SetSysClock_PLL_HSI() == 0)
{
while(1)
{
// [TODO] Put something here to tell the user that a problem occured...
}
}
}
}
/* At this stage the HSI is already enabled and used as System clock source */
// Output clock on MCO pin (PA8) for debugging purpose
/*
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_0);
// Output clock on MCO pin
// Warning: only RCC_MCOPrescaler_1 is available on STM32F030x8 devices
RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
*/
}
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
__IO uint32_t StartUpCounter = 0;
__IO uint32_t HSEStatus = 0;
/* Bypass HSE: can be done only if HSE is OFF */
RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
if (bypass != 0)
{
RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
}
else
{
RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
}
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
/* Check if HSE has started correctly */
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* HCLK = SYSCLK / 1 */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK / 1 */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
/* PLL configuration */
/* PLL configuration
PLLCLK = 48 MHz (xtal 8 MHz * 6) */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6
| RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */
| RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
return 1; // OK
}
else
{
return 0; // FAIL
}
}
#endif
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSI(void)
{
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* PLL configuration
PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12
| RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */
| RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
@ -321,6 +423,8 @@ static void SetSysClock(void)
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
return 1; // OK
}
/**

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/system_stm32f0xx.h
View File

@ -94,6 +94,8 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void);
/**
* @}
*/

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F303VC/system_stm32f30x.c
View File

@ -141,7 +141,7 @@
* @{
*/
uint32_t SystemCoreClock = 72000000; /* Default with HSI. Will be updated if HSE is used */
uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
@ -153,8 +153,6 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
* @{
*/
void SetSysClock(void);
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif
@ -208,9 +206,6 @@ void SystemInit(void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
@ -218,6 +213,9 @@ void SystemInit(void)
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
}
/**
@ -344,7 +342,7 @@ void SetSysClock(void)
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// Select the clock to output
RCC_MCOConfig(RCC_MCOSource_SYSCLK);
RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
*/
}

1
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F303VC/system_stm32f30x.h
View File

@ -65,6 +65,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void);
/**
* @}

124
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/hal_tick.c Normal file
View File

@ -0,0 +1,124 @@
/**
******************************************************************************
* @file hal_tick.c
* @author MCD Application Team
* @brief Initialization of HAL tick
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "hal_tick.h"
TIM_HandleTypeDef TimMasterHandle;
uint32_t PreviousVal = 0;
void us_ticker_irq_handler(void);
void timer_irq_handler(void) {
// Channel 1 for mbed timeout
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
us_ticker_irq_handler();
}
// Channel 2 for HAL tick
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
if ((val - PreviousVal) >= HAL_TICK_DELAY) {
// Increment HAL variable
HAL_IncTick();
// Prepare next interrupt
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
PreviousVal = val;
#if 0 // For DEBUG only
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
#endif
}
}
}
// Reconfigure the HAL tick using a standard timer instead of systick.
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
// Enable timer clock
TIM_MST_RCC;
// Reset timer
TIM_MST_RESET_ON;
TIM_MST_RESET_OFF;
// Configure time base
TimMasterHandle.Instance = TIM_MST;
TimMasterHandle.Init.Period = 0xFFFFFFFF;
if ( SystemCoreClock == 16000000 ) {
TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 1000000) - 1; // 1 µs tick
} else {
TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
}
TimMasterHandle.Init.ClockDivision = 0;
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimMasterHandle.Init.RepetitionCounter = 0;
HAL_TIM_OC_Init(&TimMasterHandle);
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
NVIC_EnableIRQ(TIM_MST_IRQ);
// Channel 1 for mbed timeout
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
// Channel 2 for HAL tick
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
#if 0 // For DEBUG only
__GPIOB_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
#endif
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

60
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/hal_tick.h Normal file
View File

@ -0,0 +1,60 @@
/**
******************************************************************************
* @file hal_tick.h
* @author MCD Application Team
* @brief Initialization of HAL tick
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HAL_TICK_H
#define __HAL_TICK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32f4xx.h"
#include "cmsis_nvic.h"
#define TIM_MST TIM5
#define TIM_MST_IRQ TIM5_IRQn
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
#define HAL_TICK_DELAY (1000) // 1 ms
#ifdef __cplusplus
}
#endif
#endif // __HAL_TICK_H
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

38
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f407xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f407xx.h
* @author MCD Application Team
* @version V2.0.0
* @date 18-February-2014
* @version V2.1.0
* @date 19-June-2014
* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -948,6 +948,8 @@ USB_OTG_HostChannelTypeDef;
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@ -4498,6 +4500,25 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@ -7895,6 +7916,19 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32F4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
#define FMC_IRQn FSMC_IRQn
/* Aliases for __IRQHandler */
#define FMC_IRQHandler FSMC_IRQHandler
/**
* @}

20
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.0.0
* @date 18-February-2014
* @version V2.1.0RC2
* @date 14-May-2014
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -70,7 +70,7 @@
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE)
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
#define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -82,7 +82,8 @@
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE, STM32F401VE Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -98,12 +99,12 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.0.0
* @brief CMSIS Device version number V2.1.0RC2
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x02) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
@ -137,6 +138,8 @@
#include "stm32f401xc.h"
#elif defined(STM32F401xE)
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
@ -196,6 +199,9 @@ typedef enum
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f4xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}

189
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal.c
View File

@ -2,11 +2,11 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
*
@verbatim
==============================================================================
##### How to use this driver #####
@ -15,7 +15,7 @@
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs categories:
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@ -65,12 +65,12 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32F4xx HAL Driver version number V1.0.0
* @brief STM32F4xx HAL Driver version number V1.1.0RC2
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION_RC (0x02) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16)\
|(__STM32F4xx_HAL_VERSION_SUB2 << 8 )\
@ -90,7 +90,7 @@
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
#define CMP_PD_BitNumber ((uint8_t)0x00)
#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static __IO uint32_t uwTick;
@ -114,7 +114,23 @@ static __IO uint32_t uwTick;
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) de-Initializes common part of the HAL
(+) Configure The time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) Systick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
@ -123,18 +139,17 @@ static __IO uint32_t uwTick;
* @brief This function is used to initialize the HAL Library; it must be the first
* instruction to be executed in the main program (before to call any other
* HAL function), it performs the following:
* - Configure the Flash prefetch, instruction and Data caches
* - Configures the SysTick to generate an interrupt each 1 millisecond,
* which is clocked by the HSI (at this stage, the clock is not yet
* configured and thus the system is running from the internal HSI at 16 MHz)
* - Set NVIC Group Priority to 4
* - Calls the HAL_MspInit() callback function defined in user file
* stm32f4xx_hal_msp.c to do the global low level hardware initialization
* Configure the Flash prefetch, instruction and Data caches.
* Configures the SysTick to generate an interrupt each 1 millisecond,
* which is clocked by the HSI (at this stage, the clock is not yet
* configured and thus the system is running from the internal HSI at 16 MHz).
* Set NVIC Group Priority to 4.
* Calls the HAL_MspInit() callback function defined in user file
* "stm32f4xx_hal_msp.c" to do the global low level hardware initialization
*
* @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @note
* @param None
* @retval HAL status
*/
@ -153,11 +168,11 @@ HAL_StatusTypeDef HAL_Init(void)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
HAL_SYSTICK_Config(HSI_VALUE/ 1000);
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
/* Init the low level hardware */
HAL_MspInit();
@ -206,7 +221,7 @@ __weak void HAL_MspInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
*/
}
/**
@ -221,6 +236,34 @@ __weak void HAL_MspDeInit(void)
*/
}
/**
* @brief This function configures the source of the time base.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The the SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
@ -228,67 +271,107 @@ __weak void HAL_MspDeInit(void)
/** @defgroup HAL_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) provide a tick value in millisecond
(+) provide a blocking delay in millisecond
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
(+) Enable/Disable Debug module during Sleep mode
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief This function is called from SysTick ISR each 1 millisecond, to increment
* a global variable "uwTick" used as time base.
* @param None
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in Systick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param None
* @retval None
*/
void HAL_IncTick(void)
__weak void HAL_IncTick(void)
{
uwTick++;
}
/**
* @brief Povides a tick value in millisecond.
* @param Non
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param None
* @retval tick value
*/
uint32_t HAL_GetTick(void)
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
return uwTick;
}
/**
* @brief Provides a blocking delay in millisecond.
* @note Care must be taken when using HAL_Delay(), this function provides accurate delay
* (in milliseconds) based on variable incremented in SysTick ISR. This implies that
* if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt
* must have higher priority (numerically lower) than the peripheral interrupt.
* Otherwise the caller ISR process will be blocked. To change the SysTick interrupt
* priority you have to use HAL_NVIC_SetPriority() function.
* @param Delay : specifies the delay time length, in milliseconds.
* @brief This function provides accurate delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note ThiS function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @retval None
*/
void HAL_Delay(__IO uint32_t Delay)
__weak void HAL_Delay(__IO uint32_t Delay)
{
uint32_t timingdelay;
timingdelay = HAL_GetTick() + Delay;
while(HAL_GetTick() < timingdelay)
uint32_t tickstart = 0;
tickstart = HAL_GetTick();
while((HAL_GetTick() - tickstart) < Delay)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param None
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param None
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Returns the HAL revision
* @param None
@ -320,7 +403,7 @@ uint32_t HAL_GetDEVID(void)
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @brief Enable the Debug Module during SLEEP mode
* @param None
* @retval None
*/
@ -330,7 +413,7 @@ void HAL_EnableDBGSleepMode(void)
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @brief Disable the Debug Module during SLEEP mode
* @param None
* @retval None
*/
@ -340,7 +423,7 @@ void HAL_DisableDBGSleepMode(void)
}
/**
* @brief Enable the Debug Module during STOP mode
* @brief Enable the Debug Module during STOP mode
* @param None
* @retval None
*/
@ -350,7 +433,7 @@ void HAL_EnableDBGStopMode(void)
}
/**
* @brief Disable the Debug Module during STOP mode
* @brief Disable the Debug Module during STOP mode
* @param None
* @retval None
*/
@ -360,7 +443,7 @@ void HAL_DisableDBGStopMode(void)
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @brief Enable the Debug Module during STANDBY mode
* @param None
* @retval None
*/
@ -370,7 +453,7 @@ void HAL_EnableDBGStandbyMode(void)
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @brief Disable the Debug Module during STANDBY mode
* @param None
* @retval None
*/

11
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@ -152,11 +152,14 @@ HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
uint32_t HAL_GetTick(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);

23
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@ -63,7 +63,7 @@
(#) Configure the ADC regular channels group features, use HAL_ADC_Init()
and HAL_ADC_ConfigChannel() functions.
(#) Three mode of operations are available within this driver :
(#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@ -89,7 +89,7 @@
==============================
[..]
(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
of data to be transfered at each end of conversion
of data to be transferred at each end of conversion
(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* last transfer and End of conversion selection).
*
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@ -780,7 +780,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
* the configuration information for the specified ADC.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
@ -846,7 +846,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
* @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
@ -1221,7 +1221,8 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/**
* @brief DMA transfer complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
@ -1245,7 +1246,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
@ -1257,7 +1259,8 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAError(DMA_HandleTypeDef *hdma)

59
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
@ -139,9 +139,9 @@ typedef struct
*/
typedef struct
{
uint32_t Channel; /*!< The ADC channel to configure
uint32_t Channel; /*!< The ADC channel to configure.
This parameter can be a value of @ref ADC_channels */
uint32_t Rank; /*!< The rank in the regular group sequencer
uint32_t Rank; /*!< The rank in the regular group sequencer.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
This parameter can be a value of @ref ADC_sampling_times */
@ -154,14 +154,14 @@ typedef struct
typedef struct
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
This parameter can be a value of @ref ADC_analog_watchdog_selection. */
This parameter can be a value of @ref ADC_analog_watchdog_selection */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel
This parameter can be a value of @ref ADC_channels. */
This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
is interrupt mode or in polling mode.
This parameter can be set to ENABLE or DISABLE */
@ -202,46 +202,6 @@ typedef struct
* @}
*/
/** @defgroup ADC_delay_between_2_sampling_phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
/**
* @}
*/
/** @defgroup ADC_Resolution
* @{
*/
@ -538,6 +498,13 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset ADC handle state
* @param __HANDLE__: ADC handle
* @retval None
*/
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
/**
* @brief Enable the ADC peripheral.
* @param __HANDLE__: ADC handle

42
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@ -24,22 +24,21 @@
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
(++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
(++) Configure and enable two DMA streams stream for managing data
(+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams stream for managing data
transfer from peripheral to memory (output stream)
(++) Associate the initilalized DMA handle to the CRYP DMA handle
(+++) Associate the initilalized DMA handle to the ADC DMA handle
using __HAL_LINKDMA()
(++) Configure the priority and enable the NVIC for the transfer complete
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
priority than the input stream.
(#) Configure the ADC Prescaler, conversion resolution and data alignment
using the HAL_ADC_Init() function.
(#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
and HAL_ADC_ConfigChannel() functions.
(#) Three mode of operations are available within this driver :
(#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@ -66,7 +65,7 @@
==============================
[..]
(+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
of data to be transfered at each end of conversion
of data to be transferred at each end of conversion
(+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
@ -79,7 +78,7 @@
(+) Select the Multi mode ADC regular channels features (dual or triple mode)
and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
(+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
of data to be transfered at each end of conversion
of data to be transferred at each end of conversion
(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
@ -409,10 +408,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
* the configuration information for the specified ADC.
* @param InjectedRank: the ADC injected rank.
* This parameter can be one of the following values:
* @arg ADC_InjectedChannel_1: Injected Channel1 selected
* @arg ADC_InjectedChannel_2: Injected Channel2 selected
* @arg ADC_InjectedChannel_3: Injected Channel3 selected
* @arg ADC_InjectedChannel_4: Injected Channel4 selected
* @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
* @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
* @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
* @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
* @retval None
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
@ -463,7 +462,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
* the configuration information for the specified ADC.
* @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
@ -538,7 +537,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
* @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
{
@ -774,7 +773,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/**
* @brief DMA transfer complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
@ -798,7 +798,8 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
@ -810,7 +811,8 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)

58
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
@ -61,8 +61,8 @@
*/
typedef struct
{
uint32_t InjectedChannel; /*!< Configure the ADC injected channel
This parameter can be a value of @ref ADC_channels. */
uint32_t InjectedChannel; /*!< Configure the ADC injected channel.
This parameter can be a value of @ref ADC_channels */
uint32_t InjectedRank; /*!< The rank in the injected group sequencer
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
@ -77,9 +77,9 @@ typedef struct
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
This parameter can be a value of @ref ADC_External_trigger_Source_Injected. */
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */
uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
This parameter can be a value of @ref ADC_External_trigger_Source_Injected */
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */
}ADC_InjectionConfTypeDef;
/**
@ -88,11 +88,11 @@ typedef struct
typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
This parameter can be a value of @ref ADC_Common_mode */
This parameter can be a value of @ref ADCEx_Common_mode */
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases */
}ADC_MultiModeTypeDef;
/* Exported constants --------------------------------------------------------*/
@ -152,6 +152,46 @@ typedef struct
* @}
*/
/** @defgroup ADCEx_delay_between_2_sampling_phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
/**
* @}
*/
/** @defgroup ADCEx_External_trigger_edge_Injected
* @{
*/

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_can.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@ -771,10 +771,9 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
* @brief Receives a correct CAN frame.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param FIFONumber: FIFO Number value
* @param Timeout: Specify Timeout value
* @param FIFONumber: FIFO Number value
* @param Timeout: Specify Timeout value
* @retval HAL status
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
@ -881,7 +880,6 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
* the configuration information for the specified CAN.
* @param FIFONumber: Specify the FIFO number
* @retval HAL status
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
@ -1229,7 +1227,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
##### Peripheral State and Error functions #####
==============================================================================
[..]
This subsection provides functions allowing to
This subsection provides functions allowing to :
(+) Check the CAN state.
(+) Check CAN Errors detected during interrupt process

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_can.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -152,7 +152,7 @@ typedef struct
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
uint32_t BankNumber; /*!< Select the start slave bank filter
uint32_t BankNumber; /*!< Select the start slave bank filter.
This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
}CAN_FilterConfTypeDef;
@ -579,6 +579,12 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset CAN handle state
* @param __HANDLE__: specifies the CAN Handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupts.
* @param __HANDLE__: CAN handle

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_conf_template.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f4xx_hal_conf.h.
@ -76,7 +76,7 @@
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
//#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
@ -99,11 +99,11 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External crystal in Hz */
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@ -115,13 +115,21 @@
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the external oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -131,9 +139,10 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1

70
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@ -16,40 +16,18 @@
==============================================================================
[..]
*** How to configure Interrupts using Cortex HAL driver ***
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provide functions allowing to configure the NVIC interrupts (IRQ).
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M4 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
==========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
==========================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
==========================================================================================================================
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programing manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
@ -59,12 +37,12 @@
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure Systick using Cortex HAL driver ***
*** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for 1 msec interrupts.
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
@ -153,7 +131,7 @@
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provide the Cortex HAL driver functions allowing to configure Interrupts
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
@ -191,8 +169,8 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
/**
* @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number
* This parameter can be an enumerator of @ref IRQn_Type enumeration
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
@ -219,8 +197,8 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number
* This parameter can be an enumerator of @ref IRQn_Type enumeration
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval None
*/
@ -232,8 +210,8 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number
* This parameter can be an enumerator of @ref IRQn_Type enumeration
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval None
*/
@ -298,8 +276,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
/**
* @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number
* This parameter can be an enumerator of @ref IRQn_Type enumeration
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
@ -341,8 +319,8 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number
* This parameter can be an enumerator of @ref IRQn_Type enumeration
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
@ -355,8 +333,8 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of @ref IRQn_Type enumeration
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval None
*/
@ -369,7 +347,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of @ref IRQn_Type enumeration
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

25
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_crc.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -105,7 +105,8 @@
/**
* @brief Initializes the CRC according to the specified
* parameters in the CRC_InitTypeDef and creates the associated handle.
* @param hcrc: CRC handle
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
* the configuration information for CRC
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
@ -137,7 +138,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/**
* @brief DeInitializes the CRC peripheral.
* @param hcrc: CRC handle
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
* the configuration information for CRC
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
@ -169,7 +171,8 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/**
* @brief Initializes the CRC MSP.
* @param hcrc: CRC handle
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
* the configuration information for CRC
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
@ -181,7 +184,8 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
/**
* @brief DeInitializes the CRC MSP.
* @param hcrc: CRC handle
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
* the configuration information for CRC
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
@ -215,7 +219,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
/**
* @brief Computes the 32-bit CRC of 32-bit data buffer using combination
* of the previous CRC value and the new one.
* @param hcrc: CRC handle
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
* the configuration information for CRC
* @param pBuffer: pointer to the buffer containing the data to be computed
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
@ -249,7 +254,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
/**
* @brief Computes the 32-bit CRC of 32-bit data buffer independently
* of the previous CRC value.
* @param hcrc: CRC handle
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
* the configuration information for CRC
* @param pBuffer: Pointer to the buffer containing the data to be computed
* @param BufferLength: Length of the buffer to be computed
* @retval 32-bit CRC
@ -304,7 +310,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/**
* @brief Returns the CRC state.
* @param hcrc: CRC handle
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
* the configuration information for CRC
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)

10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_crc.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@ -85,6 +85,12 @@ typedef struct
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset CRC handle state
* @param __HANDLE__: CRC handle
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Resets CRC Data Register.
* @param __HANDLE__: CRC handle

217
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@ -29,18 +29,15 @@
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
(++) Enable the DMAx interface clock using
(+++) __DMAx_CLK_ENABLE()
(++) Configure and enable two DMA streams one for managing data transfer from
(+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams one for managing data transfer from
memory to peripheral (input stream) and another stream for managing data
transfer from peripheral to memory (output stream)
(++) Associate the initilalized DMA handle to the CRYP DMA handle
(+++) Associate the initilalized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(++) Configure the priority and enable the NVIC for the transfer complete
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
(+++) HAL_NVIC_SetPriority()
(+++) HAL_NVIC_EnableIRQ()
priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
(#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
(##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
@ -51,13 +48,13 @@
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
i.e. they process the data and wait till the processing is finished
i.e. they process the data and wait till the processing is finished,
e.g. HAL_CRYP_AESCBC_Encrypt()
(##) Interrupt mode: encryption and decryption APIs are not blocking functions
i.e. they process the data under interrupt
i.e. they process the data under interrupt,
e.g. HAL_CRYP_AESCBC_Encrypt_IT()
(##) DMA mode: encryption and decryption APIs are not blocking functions
i.e. the data transfer is ensured by DMA
i.e. the data transfer is ensured by DMA,
e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
(#)When the processing function is called at first time after HAL_CRYP_Init()
@ -161,7 +158,8 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
/**
* @brief Initializes the CRYP according to the specified
* parameters in the CRYP_InitTypeDef and creates the associated handle.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
@ -204,7 +202,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
/**
* @brief DeInitializes the CRYP peripheral.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
@ -243,7 +242,8 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
/**
* @brief Initializes the CRYP MSP.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
@ -255,7 +255,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
/**
* @brief DeInitializes CRYP MSP.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
@ -291,7 +292,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
/**
* @brief Initializes the CRYP peripheral in AES ECB encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@ -344,7 +346,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@ -400,7 +403,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in AES CTR encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@ -458,7 +462,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@ -545,7 +550,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@ -633,7 +639,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
/**
* @brief Initializes the CRYP peripheral in AES CTR decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@ -688,7 +695,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
/**
* @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@ -788,7 +796,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@ -890,7 +899,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@ -993,7 +1003,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@ -1121,7 +1132,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -1257,7 +1269,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -1361,7 +1374,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@ -1415,7 +1429,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@ -1472,7 +1487,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@ -1530,7 +1546,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pPlainData: Pointer to the plaintext buffer
@ -1613,7 +1630,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pPlainData: Pointer to the plaintext buffer
@ -1699,7 +1717,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -1768,10 +1787,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
==============================================================================
[..] This section provides functions allowing to:
(+) Encrypt plaintext using DES using ECB or CBC chaining modes
(+) Decrypt cyphertext using using ECB or CBC chaining modes
(+) Decrypt cyphertext using ECB or CBC chaining modes
[..] Three processing functions are available:
(+) polling mode
(+) interrupt mode
(+) Polling mode
(+) Interrupt mode
(+) DMA mode
@endverbatim
@ -1780,7 +1799,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -1819,7 +1839,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -1858,7 +1879,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -1897,7 +1919,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -1936,7 +1959,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2020,7 +2044,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2105,7 +2130,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2189,7 +2215,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2273,7 +2300,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2315,7 +2343,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2357,7 +2386,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2399,7 +2429,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2451,11 +2482,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
##### TDES processing functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Encrypt plaintext using TDES using ECB or CBC chaining modes
(+) Decrypt cyphertext using TDES using ECB or CBC chaining modes
(+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
(+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
[..] Three processing functions are available:
(+) polling mode
(+) interrupt mode
(+) Polling mode
(+) Interrupt mode
(+) DMA mode
@endverbatim
@ -2465,7 +2496,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2505,7 +2537,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2545,7 +2578,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2585,7 +2619,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@ -2624,7 +2659,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2708,7 +2744,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2791,7 +2828,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2874,7 +2912,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@ -2957,7 +2996,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -2999,7 +3039,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -3041,7 +3082,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@ -3083,7 +3125,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@ -3145,7 +3188,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Input FIFO transfer completed callbacks.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
@ -3157,7 +3201,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
/**
* @brief Output FIFO transfer completed callbacks.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
@ -3169,7 +3214,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
/**
* @brief CRYP error callbacks.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
@ -3198,7 +3244,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
/**
* @brief This function handles CRYP interrupt request.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
@ -3286,7 +3333,8 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
/**
* @brief Returns the CRYP state.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL state
*/
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
@ -3352,7 +3400,8 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief Writes the Key in Key registers.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Key: Pointer to Key buffer
* @param KeySize: Size of Key
* @retval None
@ -3410,7 +3459,8 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySiz
/**
* @brief Writes the InitVector/InitCounter in IV registers.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param InitVector: Pointer to InitVector/InitCounter buffer
* @param IVSize: Size of the InitVector/InitCounter
* @retval None
@ -3448,7 +3498,8 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u
/**
* @brief Process Data: Writes Input data in polling mode and read the output data
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the Input buffer
* @param Ilength: Length of the Input buffer, must be a multiple of 16.
* @param Output: Pointer to the returned buffer
@ -3510,7 +3561,8 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In
/**
* @brief Process Data: Write Input data in polling mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the Input buffer
* @param Ilength: Length of the Input buffer, must be a multiple of 8
* @param Output: Pointer to the returned buffer
@ -3565,7 +3617,8 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8
/**
* @brief Set the DMA configuration and start the DMA transfer
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr: address of the Input buffer
* @param Size: Size of the Input buffer, must be a multiple of 16.
* @param outputaddr: address of the Output buffer
@ -3602,7 +3655,8 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin
/**
* @brief Sets the CRYP peripheral in DES ECB mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/
@ -3628,7 +3682,8 @@ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
/**
* @brief Sets the CRYP peripheral in DES CBC mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/
@ -3657,7 +3712,8 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
/**
* @brief Sets the CRYP peripheral in TDES ECB mode.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/
@ -3682,7 +3738,8 @@ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
/**
* @brief Sets the CRYP peripheral in TDES CBC mode
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/

85
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@ -53,59 +53,57 @@
/** @addtogroup CRYP
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief CRYP Configuration Structure definition
* @brief CRYP Configuration Structure definition
*/
typedef struct
{
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
This parameter can be a value of @ref CRYP_Key_Size */
uint8_t* pKey; /*!< The key used for encryption/decryption */
uint8_t* pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
uint8_t IVSize; /*!< The size of initialization vector.
This parameter (called nonce size in CCM) is used only
in AES-128/192/256 encryption/decryption CCM mode */
uint8_t TagSize; /*!< The size of returned authentication TAG.
This parameter is used only in AES-128/192/256
encryption/decryption CCM mode */
uint8_t* Header; /*!< The header used in GCM and CCM modes */
uint16_t HeaderSize; /*!< The size of header buffer in bytes */
uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
}CRYP_InitTypeDef;
/**
* @brief HAL CRYP State structures definition
*/
* @brief HAL CRYP State structures definition
*/
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
}HAL_CRYP_STATETypeDef;
/**
* @brief HAL CRYP phase structures definition
*/
* @brief HAL CRYP phase structures definition
*/
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
@ -115,32 +113,31 @@ typedef enum
}HAL_PhaseTypeDef;
/**
* @brief CRYP handle Structure definition
* @brief CRYP handle Structure definition
*/
typedef struct
{
{
CRYP_InitTypeDef Init; /*!< CRYP required parameters */
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
__IO uint16_t CrypInCount; /*!< Counter of inputed data */
__IO uint16_t CrypOutCount; /*!< Counter of outputed data */
HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
HAL_LockTypeDef Lock; /*!< CRYP locking object */
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
}CRYP_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@ -151,7 +148,7 @@ typedef struct
/** @defgroup CRYP_Key_Size
* @{
*/
*/
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
@ -210,7 +207,6 @@ typedef struct
* @}
*/
/** @defgroup CRYP_Flags
* @{
*/
@ -229,7 +225,7 @@ typedef struct
interrupt status */
/**
* @}
*/
*/
/**
* @}
@ -237,6 +233,12 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset CRYP handle state
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
/**
* @brief Enable/Disable the CRYP peripheral.
* @param None
@ -253,13 +255,12 @@ typedef struct
#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)
/**
* @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
* @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,
* @param MODE: The algorithm mode.
* @retval None
*/
#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)
/** @brief Check whether the specified CRYP flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@ -304,7 +305,7 @@ typedef struct
#include "stm32f4xx_hal_cryp_ex.h"
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions **********************************/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
@ -368,10 +369,10 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
/* Processing functions ********************************************************/
/* Processing functions ******************************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
/* Peripheral State functions **************************************************/
/* Peripheral State functions ************************************************/
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
/* MSP functions *************************************************************/

64
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@ -153,7 +153,8 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input
/**
* @brief Initializes the CRYP peripheral in AES CCM encryption mode then
* encrypt pPlainData. The cypher data are available in pCypherData.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pCypherData: Pointer to the cyphertext buffer
@ -407,7 +408,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
/**
* @brief Initializes the CRYP peripheral in AES GCM encryption mode then
* encrypt pPlainData. The cypher data are available in pCypherData.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pCypherData: Pointer to the cyphertext buffer
@ -504,7 +506,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
/**
* @brief Initializes the CRYP peripheral in AES GCM decryption mode then
* decrypted pCypherData. The cypher data are available in pPlainData.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the cyphertext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -596,7 +599,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
/**
* @brief Computes the authentication TAG.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Size: Total length of the plain/cyphertext buffer
* @param AuthTag: Pointer to the authentication buffer
* @param Timeout: Timeout duration
@ -704,7 +708,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t S
/**
* @brief Computes the authentication TAG for AES CCM mode.
* @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param AuthTag: Pointer to the authentication buffer
* @param Timeout: Timeout duration
* @retval HAL status
@ -795,7 +800,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A
/**
* @brief Initializes the CRYP peripheral in AES CCM decryption mode then
* decrypted pCypherData. The cypher data are available in pPlainData.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pCypherData: Pointer to the cyphertext buffer
@ -1046,7 +1052,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
/**
* @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pCypherData: Pointer to the cyphertext buffer
@ -1196,7 +1203,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pCypherData: Pointer to the cyphertext buffer
@ -1494,7 +1502,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the cyphertext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -1641,7 +1650,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
* then decrypted pCypherData. The cypher data are available in pPlainData.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -1930,7 +1940,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pCypherData: Pointer to the cyphertext buffer
@ -2026,7 +2037,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
/**
* @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pCypherData: Pointer to the cyphertext buffer
@ -2279,7 +2291,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
/**
* @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer.
* @param Size: Length of the cyphertext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -2368,7 +2381,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
/**
* @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA
* then decrypted pCypherData. The cypher data are available in pPlainData.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@ -2621,7 +2635,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
/**
* @brief This function handles CRYP interrupt request.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
@ -2707,7 +2722,8 @@ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief Writes the Key in Key registers.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Key: Pointer to Key buffer
* @param KeySize: Size of Key
* @retval None
@ -2765,7 +2781,8 @@ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32
/**
* @brief Writes the InitVector/InitCounter in IV registers.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param InitVector: Pointer to InitVector/InitCounter buffer
* @param IVSize: Size of the InitVector/InitCounter
* @retval None
@ -2803,7 +2820,8 @@ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *Init
/**
* @brief Process Data: Writes Input data in polling mode and read the Output data.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the Input buffer.
* @param Ilength: Length of the Input buffer, must be a multiple of 16
* @param Output: Pointer to the returned buffer
@ -2865,7 +2883,8 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui
/**
* @brief Sets the header phase
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the Input buffer.
* @param Ilength: Length of the Input buffer, must be a multiple of 16
* @param Timeout: Timeout value
@ -2947,7 +2966,8 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp,
/**
* @brief Sets the DMA configuration and start the DMA transfert.
* @param hcryp: CRYP handle
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr: Address of the Input buffer
* @param Size: Size of the Input buffer, must be a multiple of 16
* @param outputaddr: Address of the Output buffer

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention

100
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@ -116,7 +116,7 @@
==============================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
of data to be transfered at each end of conversion
of data to be transferred at each end of conversion
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
@ -430,9 +430,9 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
@ -448,27 +448,18 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
if(Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN1;
@ -493,9 +484,18 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN2;
/* Case of use of channel 2 */
switch(Alignment)
{
@ -556,20 +556,42 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the selected DAC channel DMA request */
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
/* Disable the Peripharal */
__HAL_DAC_DISABLE(hdac, Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Disable the DMA Channel */
/* Channel1 is used */
if(Channel == DAC_CHANNEL_1)
{
status = HAL_DMA_Abort(hdac->DMA_Handle1);
}
else /* Channel2 is used for */
{
status = HAL_DMA_Abort(hdac->DMA_Handle2);
}
/* Check if DMA Channel effectively disabled */
if(status == HAL_ERROR)
{
/* Update ADC state machine to error */
hdac->State = HAL_DAC_STATE_ERROR;
}
else
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
}
/* Return function status */
return HAL_OK;
return status;
}
/**
@ -732,7 +754,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
@ -776,9 +797,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Alignment: Specifies the data alignment.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register.
* @retval HAL status
*/
@ -858,7 +879,8 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
@ -872,7 +894,8 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
@ -884,7 +907,8 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)

117
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@ -59,8 +59,8 @@
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL State structures definition
*/
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
@ -68,39 +68,37 @@ typedef enum
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
}HAL_DAC_StateTypeDef;
/**
* @brief DAC handle Structure definition
*/
* @brief DAC handle Structure definition
*/
typedef struct
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
}DAC_HandleTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_ChannelConfTypeDef;
/* Exported constants --------------------------------------------------------*/
@ -111,12 +109,12 @@ typedef struct
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
/**
* @}
*/
/** @defgroup DAC_trigger_selection
/** @defgroup DAC_trigger_selection
* @{
*/
@ -186,7 +184,7 @@ typedef struct
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
@ -195,7 +193,7 @@ typedef struct
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
((FLAG) == DAC_FLAG_DMAUDR2))
@ -207,67 +205,104 @@ typedef struct
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
((IT) == DAC_IT_DMAUDR2))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Enable the DAC peripheral */
/** @brief Reset DAC handle state
* @param __HANDLE__: specifies the DAC handle.
* @retval None
*/
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
/** @brief Enable the DAC channel
* @param __HANDLE__: specifies the DAC handle.
* @param __DAC_Channel__: specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/* Disable the DAC peripheral */
/** @brief Disable the DAC channel
* @param __HANDLE__: specifies the DAC handle
* @param __DAC_Channel__: specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/* Set DHR12R1 alignment */
/** @brief Set DHR12R1 alignment
* @param __ALIGNEMENT__: specifies the DAC alignement
* @retval None
*/
#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
/* Set DHR12R2 alignment */
/** @brief Set DHR12R2 alignment
* @param __ALIGNEMENT__: specifies the DAC alignement
* @retval None
*/
#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
/* Set DHR12RD alignment */
/** @brief Set DHR12RD alignment
* @param __ALIGNEMENT__: specifies the DAC alignement
* @retval None
*/
#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
/* Enable the DAC interrupt */
/** @brief Enable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/* Disable the DAC interrupt */
/** @brief Disable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/* Get the selected DAC's flag status */
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__: specifies the DAC handle.
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/* Clear the DAC's flag */
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__: specifies the DAC handle.
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
/* Include DAC HAL Extension module */
#include "stm32f4xx_hal_dac_ex.h"
#include "stm32f4xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions ***********************************/
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions *********************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
/* I/O operation functions ******************************************************/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
/* Peripheral Control functions *************************************************/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
/* Peripheral State functions ***************************************************/
/* Peripheral State functions *************************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);

25
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@ -123,8 +123,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* DAC_CHANNEL_1 / DAC_CHANNEL_2
* @param Amplitude: Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
@ -172,8 +171,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* DAC_CHANNEL_1 / DAC_CHANNEL_2
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
@ -221,9 +219,9 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
* the configuration information for the specified DAC.
* @param Alignment: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* DAC_ALIGN_8B_R: 8bit right data alignment selected
* DAC_ALIGN_12B_L: 12bit left data alignment selected
* DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
* @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
@ -317,7 +315,8 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
@ -331,7 +330,8 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
@ -343,7 +343,8 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dcmi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@ -39,9 +39,9 @@
window from the received image using HAL_DCMI_ConfigCrop()
and HAL_DCMI_EnableCROP() functions
(#) The capture can be stopped using the following HAL_DCMI_Stop() function.
(#) The capture can be stopped using HAL_DCMI_Stop() function.
(#) To control DCMI state you can use the following function : HAL_DCMI_GetState()
(#) To control DCMI state you can use the function HAL_DCMI_GetState().
*** DCMI HAL driver macros list ***
=============================================
@ -217,7 +217,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
* values.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
@ -290,7 +290,7 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
* @param pData: The destination memory Buffer address (LCD Frame buffer).
* @param Length: The length of capture to be transferred.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
@ -363,6 +363,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
* @brief Disable DCMI DMA request and Disable DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
{
@ -417,7 +418,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
* @brief Handles DCMI interrupt request.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI.
* @retval HAL status
* @retval None
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
{
@ -593,7 +594,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
(+) ENABLE/DISABLE the CROP feature.
(+) Enable/Disable the CROP feature.
@endverbatim
* @{
@ -640,7 +641,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
* @brief Disable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
{
@ -666,7 +667,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
* @brief Enable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
{
@ -736,7 +737,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
@ -789,7 +791,8 @@ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)

147
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dcmi.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
@ -59,17 +59,16 @@
/* Exported types ------------------------------------------------------------*/
/**
* @brief DCMI Error source
*/
* @brief DCMI Error source
*/
typedef enum
{
DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */
DCMI_OVERRUN = 2, /*!< DCMI Overrun */
}DCMI_ErrorTypeDef;
}DCMI_ErrorTypeDef;
/**
* @brief DCMI Embedded Synchronisation CODE Init structure definition
* @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
@ -77,11 +76,10 @@ typedef struct
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
}DCMI_CodesInitTypeDef;
/**
* @brief DCMI Init structure definition
* @brief DCMI Init structure definition
*/
typedef struct
{
@ -102,17 +100,16 @@ typedef struct
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_MODE_JPEG */
This parameter can be a value of @ref DCMI_MODE_JPEG */
}DCMI_InitTypeDef;
/**
* @brief HAL DCMI State structures definition
* @brief HAL DCMI State structures definition
*/
typedef enum
{
@ -121,35 +118,34 @@ typedef enum
HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */
}HAL_DCMI_StateTypeDef;
/**
* @brief DCMI handle Structure definition
*/
* @brief DCMI handle Structure definition
*/
typedef struct
{
{
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
DCMI_InitTypeDef Init; /*!< DCMI parameters */
HAL_LockTypeDef Lock; /*!< DCMI locking object */
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
__IO uint32_t XferCount; /*!< DMA transfer counter */
__IO uint32_t XferSize; /*!< DMA transfer size */
uint32_t XferTransferNumber; /*!< DMA transfer number */
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
DCMI_InitTypeDef Init; /*!< DCMI parameters */
HAL_LockTypeDef Lock; /*!< DCMI locking object */
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
__IO uint32_t XferCount; /*!< DMA transfer counter */
__IO uint32_t XferSize; /*!< DMA transfer size */
uint32_t XferTransferNumber; /*!< DMA transfer number */
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
__IO uint32_t ErrorCode; /*!< DCMI Error code */
}DCMI_HandleTypeDef;
__IO uint32_t ErrorCode; /*!< DCMI Error code */
}DCMI_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@ -162,13 +158,13 @@ typedef struct
*/
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
*/
*/
/** @defgroup DCMI_Capture_Mode
/** @defgroup DCMI_Capture_Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
@ -180,8 +176,7 @@ typedef struct
((MODE) == DCMI_MODE_SNAPSHOT))
/**
* @}
*/
*/
/** @defgroup DCMI_Synchronization_Mode
* @{
@ -190,17 +185,16 @@ typedef struct
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
((MODE) == DCMI_SYNCHRO_EMBEDDED))
/**
* @}
*/
*/
/** @defgroup DCMI_PIXCK_Polarity
/** @defgroup DCMI_PIXCK_Polarity
* @{
*/
*/
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
@ -208,12 +202,11 @@ typedef struct
((POLARITY) == DCMI_PCKPOLARITY_RISING))
/**
* @}
*/
*/
/** @defgroup DCMI_VSYNC_Polarity
/** @defgroup DCMI_VSYNC_Polarity
* @{
*/
*/
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
@ -221,10 +214,9 @@ typedef struct
((POLARITY) == DCMI_VSPOLARITY_HIGH))
/**
* @}
*/
*/
/** @defgroup DCMI_HSYNC_Polarity
/** @defgroup DCMI_HSYNC_Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
@ -234,11 +226,11 @@ typedef struct
((POLARITY) == DCMI_HSPOLARITY_HIGH))
/**
* @}
*/
*/
/** @defgroup DCMI_MODE_JPEG
* @{
*/
*/
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
@ -246,11 +238,11 @@ typedef struct
((JPEG_MODE) == DCMI_JPEG_ENABLE))
/**
* @}
*/
*/
/** @defgroup DCMI_Capture_Rate
* @{
*/
*/
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
@ -260,12 +252,11 @@ typedef struct
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
/**
* @}
*/
*/
/** @defgroup DCMI_Extended_Data_Mode
* @{
*/
*/
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
@ -277,11 +268,11 @@ typedef struct
((DATA) == DCMI_EXTEND_DATA_14B))
/**
* @}
*/
*/
/** @defgroup DCMI_Window_Coordinate
* @{
*/
*/
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
@ -297,11 +288,11 @@ typedef struct
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
/**
* @}
*/
*/
/** @defgroup DCMI_interrupt_sources
/** @defgroup DCMI_interrupt_sources
* @{
*/
*/
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
@ -317,13 +308,14 @@ typedef struct
((IT) == DCMI_IT_LINE))
/**
* @}
*/
*/
/** @defgroup DCMI_Flags
/** @defgroup DCMI_Flags
* @{
*/
*/
/**
* @brief DCMI SR register
* @brief DCMI SR register
*/
#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)
#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)
@ -368,6 +360,13 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset DCMI handle state
* @param __HANDLE__: specifies the DCMI handle.
* @retval None
*/
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
/**
* @brief Enable the DCMI.
* @param __HANDLE__: DCMI handle
@ -455,15 +454,15 @@ typedef struct
*/
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
/* Exported functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Initialization and de-initialization functions *******************************/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
/* IO operation functions *******************************************************/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
@ -472,12 +471,12 @@ void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
/* Peripheral Control functions *************************************************/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
/* Peripheral State functions ***************************************************/
/* Peripheral State functions *************************************************/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);

10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_def.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@ -79,10 +79,10 @@ typedef enum
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
(__DMA_HANDLE_).Parent = (__HANDLE__); \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#if (USE_RTOS == 1)

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@ -47,7 +47,7 @@
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e a member of DMA handle structure).
[..]
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.

86
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@ -54,36 +54,36 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief DMA Configuration Structure definition
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
This parameter can be a value of @ref DMA_Channel_selection */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Stream */
data transfer is configured on the selected Stream */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
This parameter can be a value of @ref DMA_Priority_level */
@ -92,80 +92,75 @@ typedef struct
This parameter can be a value of @ref DMA_FIFO_direct_mode
@note The Direct mode (FIFO mode disabled) cannot be used if the
memory-to-memory data transfer is configured on the selected stream */
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref DMA_FIFO_threshold_level */
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
It specifies the amount of data to be transferred in a single non interruptable
transaction.
transaction.
This parameter can be a value of @ref DMA_Memory_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
It specifies the amount of data to be transferred in a single non interruptable
transaction.
This parameter can be a value of @ref DMA_Peripheral_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
}DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
}HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief DMA handle Structure definition
*/
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
{
DMA_Stream_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
}DMA_HandleTypeDef;
}DMA_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@ -178,7 +173,7 @@ typedef struct __DMA_HandleTypeDef
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
@ -418,6 +413,13 @@ typedef struct __DMA_HandleTypeDef
*/
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset DMA handle state
* @param __HANDLE__: specifies the DMA handle.
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Return the current DMA Stream FIFO filled level.
* @param __HANDLE__: DMA handle

33
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma2d.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@ -71,15 +71,15 @@
*** DMA2D HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DMA2D HAL driver.
Below the list of most used macros in DMA2D HAL driver :
(+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
(+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
(+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
(+) __HAL_DMA2D_CLEAR_FLAG: Clears the DMA2D pending flags.
(+) __HAL_DMA2D_ENABLE_IT: Enables the specified DMA2D interrupts.
(+) __HAL_DMA2D_DISABLE_IT: Disables the specified DMA2D interrupts.
(+) __HAL_DMA2D_GET_IT_SOURCE: Checks whether the specified DMA2D interrupt has occurred or not.
(+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
(+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
(+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
(+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@ -320,8 +320,8 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
(+) Abort DMA2D transfer.
(+) Suspend DMA2D transfer.
(+) Continue DMA2D transfer.
(+) polling for transfer complete.
(+) handles DMA2D interrupt request.
(+) Poll for transfer complete.
(+) handle DMA2D interrupt request.
@endverbatim
* @{
@ -827,8 +827,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
/**
* @brief Configure the DMA2D Layer according to the specified
* parameters in the DMA2D_InitTypeDef and create the associated handle.
* @param hdma2d: DMA2D handle
* @param LayerIdx: DMA2D Layer index
* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@ -931,7 +932,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
* the configuration information for the DMA2D.
* @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx: DMA2D Layer index
* @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@ -1013,7 +1014,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf
* @brief Enable the DMA2D CLUT Transfer.
* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx: DMA2D Layer index
* @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@ -1041,7 +1042,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
* @brief Disable the DMA2D CLUT Transfer.
* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx: DMA2D Layer index
* @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@ -1070,7 +1071,7 @@ HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t La
* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param Line: Line Watermark configuration.
* @retval None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
@ -1108,7 +1109,7 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
This subsection provides functions allowing to :
(+) Check the DMA2D state
(+) Get error code

98
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma2d.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
@ -58,121 +58,116 @@
/* Exported types ------------------------------------------------------------*/
#define MAX_DMA2D_LAYER 2
/**
* @brief DMA2D color Structure definition
* @brief DMA2D color Structure definition
*/
typedef struct
{
uint32_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Green; /*!< Configures the green value.
uint32_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Red; /*!< Configures the red value.
uint32_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
} DMA2D_ColorTypeDef;
/**
* @brief DMA2D CLUT Structure definition
* @brief DMA2D CLUT Structure definition
*/
typedef struct
{
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address. */
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
This parameter can be one value of @ref DMA2D_CLUT_CM */
uint32_t Size; /*!< configures the DMA2D CLUT size.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
} DMA2D_CLUTCfgTypeDef;
/**
* @brief DMA2D Init structure definition
* @brief DMA2D Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_Mode */
uint32_t ColorMode; /*!< configures the color format of the output image.
This parameter can be one value of @ref DMA2D_Color_Mode */
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
} DMA2D_InitTypeDef;
/**
* @brief DMA2D Layer structure definition
* @brief DMA2D Layer structure definition
*/
typedef struct
{
uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
This parameter can be one value of @ref DMA2D_Input_Color_Mode */
uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
This parameter can be one value of @ref DMA2D_ALPHA_MODE */
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
} DMA2D_LayerCfgTypeDef;
/**
* @brief HAL DMA2D State structures definition
*/
* @brief HAL DMA2D State structures definition
*/
typedef enum
{
HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
}HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
{
DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D Lock */
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
__IO uint32_t ErrorCode; /*!< DMA2D Error code */
} DMA2D_HandleTypeDef;
} DMA2D_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Constants
* @{
*/
*/
/** @defgroup DMA2D_Layer
* @{
*/
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
/**
* @}
*/
@ -182,12 +177,12 @@ typedef struct __DMA2D_HandleTypeDef
*/
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
*/
/** @defgroup DMA2D_Mode
* @{
*/
@ -200,7 +195,7 @@ typedef struct __DMA2D_HandleTypeDef
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
/**
* @}
*/
*/
/** @defgroup DMA2D_Color_Mode
* @{
@ -242,7 +237,7 @@ typedef struct __DMA2D_HandleTypeDef
* @}
*/
/** @defgroup DMA2D_OFFSET
/** @defgroup DMA2D_Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
@ -303,7 +298,7 @@ typedef struct __DMA2D_HandleTypeDef
* @}
*/
/** @defgroup DMA2D_CLUT_SIZE
/** @defgroup DMA2D_Size_Clut
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
@ -321,8 +316,8 @@ typedef struct __DMA2D_HandleTypeDef
#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
/**
* @}
*/
*/
/** @defgroup DMA2D_Interrupts
* @{
*/
@ -339,7 +334,7 @@ typedef struct __DMA2D_HandleTypeDef
/**
* @}
*/
/** @defgroup DMA2D_Flag
* @{
*/
@ -361,6 +356,13 @@ typedef struct __DMA2D_HandleTypeDef
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset DMA2D handle state
* @param __HANDLE__: specifies the DMA2D handle.
* @retval None
*/
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
/**
* @brief Enable the DMA2D.
* @param __HANDLE__: DMA2D handle

10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@ -21,7 +21,7 @@
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
@endverbatim
******************************************************************************
@ -217,8 +217,8 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
* @param Address: The new address
* @param memory: the memory to be changed, This parameter can be one of
* the following values:
* @arg MEMORY0
* @arg MEMORY1
* MEMORY0 /
* MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention

112
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_eth.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@ -152,7 +152,8 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
/**
* @brief Initializes the Ethernet MAC and DMA according to default
* parameters.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
@ -389,7 +390,8 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/**
* @brief De-Initializes the ETH peripheral.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
@ -412,7 +414,8 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
/**
* @brief Initializes the DMA Tx descriptors in chain mode.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param DMATxDescTab: Pointer to the first Tx desc list
* @param TxBuff: Pointer to the first TxBuffer list
* @param TxBuffCount: Number of the used Tx desc in the list
@ -478,7 +481,8 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
/**
* @brief Initializes the DMA Rx descriptors in chain mode.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param DMARxDescTab: Pointer to the first Rx desc list
* @param RxBuff: Pointer to the first RxBuffer list
* @param RxBuffCount: Number of the used Rx desc in the list
@ -547,7 +551,8 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
/**
* @brief Initializes the ETH MSP.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
@ -559,7 +564,8 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
/**
* @brief DeInitializes ETH MSP.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
@ -588,7 +594,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_ETH_GetReceivedFrame_IT();
(+) Read from an External PHY register
HAL_ETH_ReadPHYRegister();
(+) Writo to an External PHY register
(+) Write to an External PHY register
HAL_ETH_WritePHYRegister();
@endverbatim
@ -598,7 +604,8 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
/**
* @brief Sends an Ethernet frame.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param FrameLength: Amount of data to be sent
* @retval HAL status
*/
@ -711,7 +718,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
/**
* @brief Checks for received frames.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
@ -789,7 +797,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
/**
* @brief Gets the Received frame in interrupt mode.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
@ -873,7 +882,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
/**
* @brief This function handles ETH interrupt request.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
@ -932,7 +942,8 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/**
* @brief Tx Transfer completed callbacks.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
@ -944,7 +955,8 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
/**
* @brief Rx Transfer completed callbacks.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
@ -956,7 +968,8 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
/**
* @brief Ethernet transfer error callbacks
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
@ -968,15 +981,15 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
/**
* @brief Reads a PHY register
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
* @arg PHY_BCR: Transceiver Basic Control Register
* @arg PHY_BSR: Transceiver Basic Status Register
* @arg More PHY register could be read depending on the used PHY
* PHY_BCR: Transceiver Basic Control Register,
* PHY_BSR: Transceiver Basic Status Register.
* More PHY register could be read depending on the used PHY
* @param RegValue: PHY register value
* @retval HAL_TIMEOUT: in case of timeout
* MACMIIDR register value: Data read from the selected PHY register (correct read )
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
@ -1037,11 +1050,12 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
/**
* @brief Writes to a PHY register.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
* @arg PHY_BCR: Transceiver Control Register
* @arg More PHY register could be written depending on the used PHY
* PHY_BCR: Transceiver Control Register.
* More PHY register could be written depending on the used PHY
* @param RegValue: the value to write
* @retval HAL status
*/
@ -1129,7 +1143,8 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
/**
* @brief Enables Ethernet MAC and DMA reception/transmission
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
@ -1167,7 +1182,8 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
/**
* @brief Stop Ethernet MAC and DMA reception/transmission
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
@ -1205,7 +1221,8 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
/**
* @brief Set ETH MAC Configuration.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param macconf: MAC Configuration structure
* @retval HAL status
*/
@ -1371,7 +1388,8 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/**
* @brief Sets ETH DMA Configuration.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param dmaconf: DMA Configuration structure
* @retval HAL status
*/
@ -1478,7 +1496,8 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
/**
* @brief Return the ETH HAL state
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL state
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
@ -1493,7 +1512,8 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
/**
* @brief Configures Ethernet MAC and DMA with default parameters.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param err: Ethernet Init error
* @retval HAL status
*/
@ -1749,7 +1769,8 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/**
* @brief Configures the selected MAC address.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param MacAddr: The MAC address to configure
* This parameter can be one of the following values:
* @arg ETH_MAC_Address0: MAC Address0
@ -1779,7 +1800,8 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint
/**
* @brief Enables the MAC transmission.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
@ -1798,7 +1820,8 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
/**
* @brief Disables the MAC transmission.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
@ -1817,7 +1840,8 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
/**
* @brief Enables the MAC reception.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
@ -1836,7 +1860,8 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
/**
* @brief Disables the MAC reception.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
@ -1855,7 +1880,8 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
/**
* @brief Enables the DMA transmission.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
@ -1866,7 +1892,8 @@ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
/**
* @brief Disables the DMA transmission.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
@ -1877,7 +1904,8 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
/**
* @brief Enables the DMA reception.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
@ -1888,7 +1916,8 @@ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
/**
* @brief Disables the DMA reception.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
@ -1899,7 +1928,8 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
/**
* @brief Clears the ETHERNET transmit FIFO.
* @param heth: ETH handle
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)

96
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_eth.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@ -85,24 +85,24 @@ typedef struct
and the mode (half/full-duplex).
This parameter can be a value of @ref ETH_AutoNegotiation */
uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
This parameter can be a value of @ref ETH_Speed */
uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref ETH_Duplex_Mode */
uint16_t PhyAddress; /*!< Ethernet PHY address
uint16_t PhyAddress; /*!< Ethernet PHY address.
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode
uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
This parameter can be a value of @ref ETH_Rx_Mode */
uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software
uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
This parameter can be a value of @ref ETH_Checksum_Mode */
uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface
uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
@ -124,78 +124,78 @@ typedef struct
When disabled, the MAC can send up to 16384 bytes.
This parameter can be a value of @ref ETH_Jabber */
uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
This parameter can be a value of @ref ETH_Inter_Frame_Gap */
uint32_t CarrierSense; /*!< Selects or not the Carrier Sense
uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
This parameter can be a value of @ref ETH_Carrier_Sense */
uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn
uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
in Half-Duplex mode
in Half-Duplex mode.
This parameter can be a value of @ref ETH_Receive_Own */
uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
This parameter can be a value of @ref ETH_Loop_Back_Mode */
uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
This parameter can be a value of @ref ETH_Checksum_Offload */
uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
when a collision occurs (Half-Duplex mode)
when a collision occurs (Half-Duplex mode).
This parameter can be a value of @ref ETH_Retry_Transmission */
uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
uint32_t BackOffLimit; /*!< Selects the BackOff limit value
uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
This parameter can be a value of @ref ETH_Back_Off_Limit */
uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
This parameter can be a value of @ref ETH_Deferral_Check */
uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering)
uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
This parameter can be a value of @ref ETH_Receive_All */
uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode
uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
This parameter can be a value of @ref ETH_Source_Addr_Filter */
uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref ETH_Pass_Control_Frames */
uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
This parameter can be a value of @ref ETH_Destination_Addr_Filter */
uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
This parameter can be a value of @ref ETH_Promiscuous_Mode */
uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table
uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table
uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame
uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame
automatic retransmission of PAUSE Frame.
This parameter can be a value of @ref ETH_Pause_Low_Threshold */
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address)
unicast address and unique multicast address).
This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
@ -207,7 +207,7 @@ typedef struct
This parameter can be a value of @ref ETH_Transmit_Flow_Control */
uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
comparison and filtering
comparison and filtering.
This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
@ -221,54 +221,54 @@ typedef struct
typedef struct
{
uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
This parameter can be a value of @ref ETH_Receive_Store_Forward */
uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
This parameter can be a value of @ref ETH_Flush_Received_Frame */
uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
This parameter can be a value of @ref ETH_Transmit_Store_Forward */
uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
This parameter can be a value of @ref ETH_Forward_Error_Frames */
uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
and length less than 64 bytes) including pad-bytes and CRC)
This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
This parameter can be a value of @ref ETH_Receive_Threshold_Control */
uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
frame of Transmit data even before obtaining the status for the first frame.
This parameter can be a value of @ref ETH_Second_Frame_Operate */
uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
This parameter can be a value of @ref ETH_Address_Aligned_Beats */
uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
This parameter can be a value of @ref ETH_Fixed_Burst */
uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format
uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
This parameter can be a value of @ref ETH_DMA_Arbitration */
} ETH_DMAInitTypeDef;
@ -1290,9 +1290,9 @@ typedef struct
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
/**
* @brief ETH_DMA_Enhanced_descriptor_format
*/
/** @defgroup ETH_DMA_Enhanced_descriptor_format
* @{
*/
#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
@ -1700,6 +1700,12 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset ETH handle state
* @param __HANDLE__: specifies the ETH handle.
* @retval None
*/
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle

36
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -212,7 +212,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
@ -387,11 +387,11 @@ void HAL_FLASH_IRQHandler(void)
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: Bank number which has been requested to erase
* - Sectors Erase: Sector which has been erased
* Mass Erase: Bank number which has been requested to erase
* Sectors Erase: Sector which has been erased
* (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
* - Program: Address which was selected for data program
* @retval none
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
@ -403,10 +403,10 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
/**
* @brief FLASH operation error interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: Bank number which has been requested to erase
* - Sectors Erase: Sector number which returned an error
* - Program: Address which was selected for data program
* @retval none
* Mass Erase: Bank number which has been requested to erase
* Sectors Erase: Sector number which returned an error
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
@ -437,7 +437,7 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
/**
* @brief Unlock the FLASH control register access
* @param None
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
@ -458,7 +458,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void)
/**
* @brief Locks the FLASH control register access
* @param None
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
@ -472,7 +472,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
/**
* @brief Unlock the FLASH Option Control Registers access.
* @param None
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
@ -493,7 +493,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
/**
* @brief Lock the FLASH Option Control Registers access.
* @param None
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
@ -506,7 +506,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
/**
* @brief Launch the option byte loading.
* @param None
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
@ -529,7 +529,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time Errors of the FLASH peripheral.
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
@ -558,7 +558,7 @@ FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operationtimeout
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention

38
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@ -30,7 +30,7 @@
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Erase function: Erase sector, erase all sectors
(++) There is two mode of erase :
(++) There are two modes of erase :
(+++) Polling Mode using HAL_FLASHEx_Erase()
(+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
@ -154,7 +154,7 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
* contains the configuration information on faulty sector in case of error
* (0xFFFFFFFF means that all the sectors have been correctly erased)
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
{
@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
* @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
@ -277,7 +277,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
@ -361,7 +361,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
* @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
* contains the configuration information for the programming.
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
{
@ -440,7 +440,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
* @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
*
* @param None
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
{
@ -466,7 +466,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
* @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
*
* @param None
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
{
@ -522,7 +522,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
* @arg FLASH_BANK_2: Bank2 to be erased
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
{
@ -801,7 +801,7 @@ static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
* @arg FLASH_BANK_2: WRP on all sectors of bank2
* @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
{
@ -865,7 +865,7 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t Sec
* @arg FLASH_BANK_2: WRP on all sectors of bank2
* @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
{
@ -1014,7 +1014,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: WRP on all sectors of bank1
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
{
@ -1050,7 +1050,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: WRP on all sectors of bank1
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
{
@ -1080,7 +1080,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
* This parameter can be one of the following values:
* @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
* @arg OB_PCROP_Sector_All
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
{
@ -1108,7 +1108,7 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
* This parameter can be one of the following values:
* @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
* @arg OB_PCROP_Sector_All
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
{
@ -1140,7 +1140,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
*
* @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
*
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
{
@ -1174,7 +1174,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
* This parameter can be one of the following values:
* @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
{
@ -1210,7 +1210,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
* @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
* @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
* @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
{

43
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
@ -61,19 +61,19 @@
*/
typedef struct
{
uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase.
uint32_t TypeErase; /*!< Mass erase or sector Erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t Banks; /*!< Banks: Select banks to erase when Mass erase is enabled
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
This parameter must be a value of @ref FLASHEx_Banks */
uint32_t Sector; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
This parameter must be a value of @ref FLASHEx_Sectors */
uint32_t NbSectors; /*!< NbSectors: Number of sectors to be erased.
uint32_t NbSectors; /*!< Number of sectors to be erased.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
uint32_t VoltageRange;/*!< VoltageRange: The device voltage range which defines the erase parallelism
uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
This parameter must be a value of @ref FLASHEx_Voltage_Range */
} FLASH_EraseInitTypeDef;
@ -83,26 +83,25 @@ typedef struct
*/
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
uint32_t Banks; /*!< Banks: Select banks for WRP activation/deactivation of all sectors
uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
This parameter must be a value of @ref FLASHEx_Banks */
uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level..
uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint32_t BORLevel; /*!< BORLevel: Set the BOR Level.
uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
} FLASH_OBProgramInitTypeDef;
@ -112,27 +111,27 @@ typedef struct
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
uint32_t OptionType; /*!< Option byte to be configured for extension.
This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
uint32_t PCROPState; /*!< PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
#if defined (STM32F401xC) || defined (STM32F401xE)
uint16_t Sectors; /*!< Sectors: specifies the sector(s) set for PCROP
uint16_t Sectors; /*!< specifies the sector(s) set for PCROP.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
#endif /* STM32F401xC || STM32F401xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
uint32_t Banks; /*!< Banks: Select banks for PCROP activation/deactivation of all sectors
uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors.
This parameter must be a value of @ref FLASHEx_Banks */
uint16_t SectorsBank1; /*!< SectorsBank1: specifies the sector(s) set for PCROP for Bank1
uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
uint16_t SectorsBank2; /*!< SectorsBank2: specifies the sector(s) set for PCROP for Bank2
uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
uint8_t BootConfig; /*!< Specifies Option bytes for boot config.
This parameter can be a value of @ref FLASHEx_Dual_Boot */
#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */

137
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio.c
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@ -2,18 +2,18 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
*
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
@ -22,7 +22,7 @@
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
@ -31,27 +31,27 @@
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
(+) The external interrupt/event controller consists of up to 23 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
[..]
(#) Enable the GPIO AHB clock using the following function: __GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
@ -65,7 +65,7 @@
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
@ -213,14 +213,17 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)) ;
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
GPIOx->AFR[position >> 3] |= temp;
temp = GPIOx->AFR[position >> 3];
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
GPIOx->MODER |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
@ -229,18 +232,23 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
GPIOx->OSPEEDR |= (GPIO_Init->Speed << (position * 2));
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
temp |= (GPIO_Init->Speed << (position * 2));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
GPIOx->OTYPER |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
GPIOx->PUPDR |= ((GPIO_Init->Pull) << (position * 2));
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
temp |= ((GPIO_Init->Pull) << (position * 2));
GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
@ -249,35 +257,44 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Enable SYSCFG Clock */
__SYSCFG_CLK_ENABLE();
temp = ((uint32_t)0x0F) << (4 * (position & 0x03));
SYSCFG->EXTICR[position >> 2] &= ~temp;
SYSCFG->EXTICR[position >> 2] |= ((uint32_t)(__HAL_GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent);
temp = SYSCFG->EXTICR[position >> 2];
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
temp |= ((uint32_t)(__HAL_GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
SYSCFG->EXTICR[position >> 2] = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
EXTI->IMR |= iocurrent;
temp |= iocurrent;
}
EXTI->IMR = temp;
temp = EXTI->EMR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
EXTI->EMR |= iocurrent;
temp |= iocurrent;
}
EXTI->EMR = temp;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
temp = EXTI->RTSR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
EXTI->RTSR |= iocurrent;
temp |= iocurrent;
}
EXTI->RTSR = temp;
temp = EXTI->FTSR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
EXTI->FTSR |= iocurrent;
temp |= iocurrent;
}
EXTI->FTSR = temp;
}
}
}
@ -324,7 +341,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
/*------------------------- EXTI Mode Configuration --------------------*/
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
@ -396,8 +412,8 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_BIT_RESET: to clear the port pin
* @arg GPIO_BIT_SET: to set the port pin
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
@ -431,6 +447,45 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
GPIOx->ODR ^= GPIO_Pin;
}
/**
* @brief Locks GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family
* @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
if(GPIOx->LCKR & GPIO_LCKR_LCKK)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin: Specifies the pins connected EXTI line

24
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@ -73,7 +73,7 @@ typedef struct
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_Alternat_function_selection */
}GPIO_InitTypeDef;
@ -177,7 +177,6 @@ typedef enum
/**
* @}
*/
/** @defgroup GPIO_speed_define
* @brief GPIO Output Maximum frequency
* @{
@ -216,7 +215,7 @@ typedef enum
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
* This parameter can be EXTI_Linex where x can be(0..15)
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
@ -224,7 +223,7 @@ typedef enum
/**
* @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..15)
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
@ -232,7 +231,7 @@ typedef enum
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be EXTI_Linex where x can be(0..15)
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
@ -240,7 +239,7 @@ typedef enum
/**
* @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..15)
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
@ -255,10 +254,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/* IO operation functions *******************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention

83
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@ -148,7 +148,8 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
/**
* @brief Initializes the HASH according to the specified parameters in the
HASH_HandleTypeDef and creates the associated handle.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
@ -192,7 +193,8 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
/**
* @brief DeInitializes the HASH peripheral.
* @note This API must be called before starting a new processing.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
@ -229,7 +231,8 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Initializes the HASH MSP.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
@ -241,7 +244,8 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
/**
* @brief DeInitializes HASH MSP.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
@ -253,7 +257,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Input data transfer complete callback.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
@ -265,7 +270,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Data transfer Error callback.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
@ -278,7 +284,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Digest computation complete callback. It is used only with interrupt.
* @note This callback is not relevant with DMA.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
@ -311,9 +318,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
* @param Size: Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware
@ -388,7 +395,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/**
* @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
@ -434,9 +442,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@ -510,7 +518,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -575,8 +584,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -727,9 +736,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@ -880,7 +889,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
/**
* @brief This function handles HASH interrupt request.
* @param hhash: hash handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
@ -923,11 +933,11 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
/**
* @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -974,7 +984,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/**
* @brief Returns the computed digest in MD5 mode
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
* @param Timeout: Timeout value
* @retval HAL status
@ -1026,11 +1037,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
/**
* @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -1078,7 +1089,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Returns the computed digest in SHA1 mode.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @param Timeout: Timeout value
* @retval HAL status
@ -1150,7 +1162,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then processes pInBuffer. The digest is available in pOutBuffer
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -1294,7 +1307,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -1460,7 +1474,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then enables DMA to control data transfer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -1526,7 +1541,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then enables DMA to control data transfer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -1609,7 +1625,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief return the HASH state
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL state
*/
HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)

82
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_HASH_H
@ -56,72 +56,68 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HASH Configuration Structure definition
* @brief HASH Configuration Structure definition
*/
typedef struct
{
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref HASH_Data_Type */
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
uint8_t* pKey; /*!< The key is used only in HMAC operation */
}HASH_InitTypeDef;
/**
* @brief HAL State structures definition
* @brief HAL State structures definition
*/
typedef enum
{
HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */
HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */
HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */
}HAL_HASH_STATETypeDef;
/**
* @brief HAL phase structures definition
*/
* @brief HAL phase structures definition
*/
typedef enum
{
HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */
HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */
}HAL_HASHPhaseTypeDef;
/**
* @brief HASH Handle Structure definition
*/
* @brief HASH Handle Structure definition
*/
typedef struct
{
{
HASH_InitTypeDef Init; /*!< HASH required parameters */
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
__IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
__IO uint32_t HashInCount; /*!< Counter of inputed data */
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
HAL_LockTypeDef Lock; /*!< HASH locking object */
__IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */
} HASH_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@ -130,9 +126,9 @@ typedef struct
* @{
*/
/** @defgroup HASH_Algo_Selection
/** @defgroup HASH_Algo_Selection
* @{
*/
*/
#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
@ -146,7 +142,7 @@ typedef struct
* @}
*/
/** @defgroup HASH_Algorithm_Mode
/** @defgroup HASH_Algorithm_Mode
* @{
*/
#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
@ -158,9 +154,9 @@ typedef struct
* @}
*/
/** @defgroup HASH_Data_Type
/** @defgroup HASH_Data_Type
* @{
*/
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
@ -174,7 +170,7 @@ typedef struct
* @}
*/
/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
* @{
*/
#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
@ -186,9 +182,9 @@ typedef struct
* @}
*/
/** @defgroup HASH_flags_definition
/** @defgroup HASH_flags_definition
* @{
*/
*/
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
@ -196,9 +192,9 @@ typedef struct
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
/**
* @}
*/
*/
/** @defgroup HASH_interrupts_definition
/** @defgroup HASH_interrupts_definition
* @{
*/
#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
@ -213,6 +209,12 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset HASH handle state
* @param __HANDLE__: specifies the HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
/** @brief Check whether the specified HASH flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:

63
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@ -143,9 +143,9 @@ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param pOutBuffer: Pointer to the output buffer (hashed buffer).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
@ -219,9 +219,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param pOutBuffer: Pointer to the output buffer (hashed buffer).
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
@ -296,7 +296,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -341,7 +342,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -406,9 +408,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param pOutBuffer: Pointer to the output buffer (hashed buffer).
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@ -549,9 +551,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then processes pInBuffer. The digest is available in pOutBuffer
* @param hhash: HASH handle
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param pOutBuffer: Pointer to the output buffer (hashed buffer).
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@ -715,7 +717,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -858,7 +861,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -1000,7 +1004,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief This function handles HASH interrupt request.
* @param hhash: hash handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
@ -1045,11 +1050,11 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
/**
* @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -1096,8 +1101,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Returns the computed digest in SHA224
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
* @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@ -1147,11 +1154,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
/**
* @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -1198,8 +1205,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Returns the computed digest in SHA256.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
* @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@ -1269,7 +1278,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then enables DMA to control data transfer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@ -1335,7 +1345,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then enables DMA to control data transfer.
* @param hhash: HASH handle
* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention

191
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -25,9 +25,9 @@
(#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
(##) Enable the HCD/USB Low Level interface clock using
(+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
(+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
(##) Enable the HCD/USB Low Level interface clock using the following macros
(+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
(+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
@ -113,8 +113,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
/**
* @brief Initialize the host driver
* @param hhcd : HCD handle
* @retval HAL state
* @param hhcd: HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
@ -151,27 +151,27 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/**
* @brief Initialize a host channel
* @param hhcd : HCD handle
* @param ch_num : Channel number
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
* @param epnum : Endpoint number
* @param epnum: Endpoint number.
* This parameter can be a value from 1 to 15
* @param dev_address : Current device address
* This parameter can be a value from 0 to 255
* @param speed : Current device speed
* This parameter can be one of the these values:
* @arg HCD_SPEED_HIGH: High speed mode
* @arg HCD_SPEED_FULL: Full speed mode
* @arg HCD_SPEED_LOW: Low speed mode
* @param ep_type : Endpoint Type
* This parameter can be one of the these values:
* @arg EP_TYPE_CTRL: Control type
* @arg EP_TYPE_ISOC: Isochrounous type
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
* @param mps : Max Packet Size
* @param speed: Current device speed.
* This parameter can be one of these values:
* HCD_SPEED_HIGH: High speed mode,
* HCD_SPEED_FULL: Full speed mode,
* HCD_SPEED_LOW: Low speed mode
* @param ep_type: Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type,
* EP_TYPE_ISOC: Isochrounous type,
* EP_TYPE_BULK: Bulk type,
* EP_TYPE_INTR: Interrupt type
* @param mps: Max Packet Size.
* This parameter can be a value from 0 to32K
* @retval HAL state
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
@ -209,10 +209,10 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
/**
* @brief Halt a host channel
* @param hhcd : HCD handle
* @param ch_num : Channel number
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
* @retval HAL state
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
uint8_t ch_num)
@ -227,8 +227,8 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
}
/**
* @brief DeInitialize the host driver
* @param hhcd : HCD handle
* @retval HAL state
* @param hhcd: HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
{
@ -294,30 +294,27 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhhcd)
/**
* @brief Submit a new URB for processing
* @param hhcd : HCD handle
* @param ch_num : Channel number
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
* @param direction : Channel number
* This parameter can be one of the these values:
* 0 : Output
* 1 : Input
* @param ep_type : Endpoint Type
* This parameter can be one of the these values:
* @arg EP_TYPE_CTRL: Control type
* @arg EP_TYPE_ISOC: Isochrounous type
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
* @param token : Endpoint Type
* This parameter can be one of the these values:
* @arg 0: HC_PID_SETUP
* @arg 1: HC_PID_DATA1
* @param pbuff : pointer to URB data
* @param length : Length of URB data
* @param do_ping : activate do ping protocol (for high speed only)
* This parameter can be one of the these values:
* 0 : do ping inactive
* 1 : do ping active
* @retval HAL state
* @param direction: Channel number.
* This parameter can be one of these values:
* 0 : Output / 1 : Input
* @param ep_type: Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type/
* EP_TYPE_ISOC: Isochrounous type/
* EP_TYPE_BULK: Bulk type/
* EP_TYPE_INTR: Interrupt type/
* @param token: Endpoint Type.
* This parameter can be one of these values:
* 0: HC_PID_SETUP / 1: HC_PID_DATA1
* @param pbuff: pointer to URB data
* @param length: Length of URB data
* @param do_ping: activate do ping protocol (for high speed only).
* This parameter can be one of these values:
* 0 : do ping inactive / 1 : do ping active
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
@ -442,7 +439,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
/**
* @brief This function handles HCD interrupt request.
* @param hhcd: HCD handle
* @retval none
* @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
@ -583,16 +580,16 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
/**
* @brief Notify URB state change callback.
* @param hhcd: HCD handle
* @param chnum : Channel number
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @param urb_state:
* This parameter can be one of the these values:
* @arg URB_IDLE
* @arg URB_DONE
* @arg URB_NOTREADY
* @arg URB_NYET
* @arg URB_ERROR
* @arg URB_STALL
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
@ -623,8 +620,8 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
/**
* @brief Start the host driver
* @param hhcd : HCD handle
* @retval HAL state
* @param hhcd: HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
@ -637,8 +634,8 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
/**
* @brief Stop the host driver
* @param hhcd : HCD handle
* @retval HAL state
* @param hhcd: HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
@ -651,8 +648,8 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
/**
* @brief Reset the host port
* @param hhcd : HCD handle
* @retval HAL state
* @param hhcd: HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
{
@ -671,7 +668,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@ -680,7 +677,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
/**
* @brief Return the HCD state
* @param hhcd : HCD handle
* @param hhcd: HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
@ -690,17 +687,17 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
/**
* @brief Return URB state for a channel
* @param hhcd : HCD handle
* @param chnum : Channel number
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval URB state
* This parameter can be one of the these values:
* @arg URB_IDLE
* @arg URB_DONE
* @arg URB_NOTREADY
* @arg URB_NYET
* @arg URB_ERROR
* @arg URB_STALL
* @retval URB state.
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@ -710,8 +707,8 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
/**
* @brief Return the last host transfer size
* @param hhcd : HCD handle
* @param chnum : Channel number
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
@ -722,20 +719,20 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
/**
* @brief Return the Host Channel state
* @param hhcd : HCD handle
* @param chnum : Channel number
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
* This parameter can be one of the these values:
* @arg HC_IDLE
* @arg HC_XFRC
* @arg HC_HALTED
* @arg HC_NYET
* @arg HC_NAK
* @arg HC_STALL
* @arg HC_XACTERR
* @arg HC_BBLERR
* @arg HC_DATATGLERR
* HC_IDLE/
* HC_XFRC/
* HC_HALTED/
* HC_NYET/
* HC_NAK/
* HC_STALL/
* HC_XACTERR/
* HC_BBLERR/
* HC_DATATGLERR/
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@ -744,8 +741,8 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
/**
* @brief Return the current Host frame number
* @param hhcd : HCD handle
* @retval current Host frame number
* @param hhcd: HCD handle
* @retval Current Host frame number
*/
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
{
@ -754,7 +751,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
/**
* @brief Return the Host enumeration speed
* @param hhcd : HCD handle
* @param hhcd: HCD handle
* @retval Enumeration speed
*/
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
@ -769,7 +766,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
/**
* @brief This function handles Host Channel IN interrupt requests.
* @param hhcd: HCD handle
* @param chnum : Channel number
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
@ -908,7 +905,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
/**
* @brief This function handles Host Channel OUT interrupt requests.
* @param hhcd: HCD handle
* @param chnum : Channel number
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
@ -1100,7 +1097,7 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
/**
* @brief This function handles Host Port interrupt requests.
* @param hhcd: HCD handle
* @retval none
* @retval None
*/
static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention

225
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@ -36,18 +36,18 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream
(+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
the DMA Tx or Rx Stream
(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
(#) Initialize the I2C registers by calling the HAL_I2C_Init() API:
(+++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_I2C_MspInit(&hi2c) API.
(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
(GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three mode of operations are available within this driver :
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@ -141,9 +141,9 @@
(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
(+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
(+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag
(+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt
(+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt
(+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@ -270,8 +270,8 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
/**
* @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and create the associated handle.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
@ -348,8 +348,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/**
* @brief DeInitializes the I2C peripheral.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
@ -383,8 +383,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/**
* @brief I2C MSP Init.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
@ -396,8 +396,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/**
* @brief I2C MSP DeInit
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
This subsection provides a set of functions allowing to manage the I2C data
transfers.
(#) There is two mode of transfer:
(#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@ -457,7 +457,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2C_MemTxCpltCallback()
(++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_MasterTxCpltCallback()
@ -472,8 +472,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/**
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@ -570,8 +570,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/**
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@ -762,8 +762,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/**
* @brief Transmits in slave mode an amount of data in blocking mode.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@ -867,8 +867,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/**
* @brief Receive in slave mode an amount of data in blocking mode
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@ -959,8 +959,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
/**
* @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@ -1030,8 +1030,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/**
* @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@ -1129,8 +1129,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/**
* @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@ -1182,8 +1182,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
/**
* @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@ -1235,8 +1235,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
/**
* @brief Transmit in master mode an amount of data in no-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@ -1311,8 +1311,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/**
* @brief Receive in master mode an amount of data in no-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@ -1398,8 +1398,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/**
* @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@ -1483,8 +1483,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
/**
* @brief Receive in slave mode an amount of data in no-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@ -1549,8 +1549,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
}
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -1649,8 +1649,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/**
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -1842,8 +1842,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
/**
* @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -1915,8 +1915,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/**
* @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -2018,8 +2018,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
}
/**
* @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -2096,8 +2096,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/**
* @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -2189,8 +2189,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/**
* @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param Trials: Number of trials
* @param Timeout: Timeout duration
@ -2299,8 +2299,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/**
* @brief This function handles I2C event interrupt request.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
@ -2404,8 +2404,8 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
/**
* @brief This function handles I2C error interrupt request.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
@ -2474,8 +2474,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
/**
* @brief Master Tx Transfer completed callbacks.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
@ -2487,8 +2487,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
/**
* @brief Master Rx Transfer completed callbacks.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
@ -2499,8 +2499,8 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
}
/** @brief Slave Tx Transfer completed callbacks.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
@ -2512,8 +2512,8 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Slave Rx Transfer completed callbacks.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
@ -2525,8 +2525,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Memory Tx Transfer completed callbacks.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
@ -2538,8 +2538,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Memory Rx Transfer completed callbacks.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
@ -2551,8 +2551,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief I2C error callbacks.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
@ -2574,7 +2574,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@ -2583,7 +2583,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Returns the I2C state.
* @param hi2c : I2C handle
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
@ -2608,8 +2609,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle TXE flag for Master
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
@ -2635,8 +2636,8 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle BTF flag for Master transmitter
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
@ -2691,8 +2692,8 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle RXNE flag for Master
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
@ -2759,8 +2760,8 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle BTF flag for Master receiver
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
@ -2835,8 +2836,8 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle TXE flag for Slave
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
@ -2858,8 +2859,8 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle BTF flag for Slave transmitter
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
@ -2881,8 +2882,8 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle RXNE flag for Slave
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
@ -2904,8 +2905,8 @@ static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle BTF flag for Slave receiver
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
@ -2927,8 +2928,8 @@ static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle ADD flag for Slave
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
@ -2946,8 +2947,8 @@ static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle STOPF flag for Slave
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
@ -2981,8 +2982,8 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
}
/**
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
@ -3016,8 +3017,8 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
}
/**
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @retval HAL status
*/
@ -3077,8 +3078,8 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
/**
* @brief Master sends target device address for read request.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @retval HAL status
*/
@ -3169,8 +3170,8 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
/**
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -3239,8 +3240,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
/**
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@ -3622,8 +3623,8 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function handles I2C Communication Timeout.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param Flag: specifies the I2C flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@ -3679,8 +3680,8 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/**
* @brief This function handles I2C Communication Timeout for Master addressing phase.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param Flag: specifies the I2C flag to check.
* @param Timeout: Timeout duration
* @retval HAL status

13
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@ -80,7 +80,7 @@ typedef struct
This parameter can be a 7-bit address. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_general_call_addressing_mode. */
This parameter can be a value of @ref I2C_general_call_addressing_mode */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
@ -268,6 +268,13 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset I2C handle state
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
/** @brief Enable or disable the specified I2C interrupts.
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.

16
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @version V1.1.0RC2
* @date 14-May-2014
* @brief I2C Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C extension peripheral:
@ -14,8 +14,8 @@
##### I2C peripheral extension features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32F427X and
STM32F429X devices contains the following additional features
[..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/
429xx/439xx devices contains the following additional features :
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
@ -100,9 +100,9 @@
/**
* @brief Configures I2C Analog noise filter.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter : new state of the Analog filter.
* @param AnalogFilter: new state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
@ -139,9 +139,9 @@ HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_
/**
* @brief Configures I2C Digital noise filter.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
* @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)

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