diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/CMakeLists.txt index 2eef6f6493..b37fb96f27 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/CMakeLists.txt +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/CMakeLists.txt @@ -12,6 +12,7 @@ target_link_libraries(mbed-m2354-tfm set(bl2 true) set(mcuboot_image_number 2) set(region_defs_h_path "${CMAKE_CURRENT_SOURCE_DIR}/partition/region_defs.h") +set(partition_mcu_h_path "${CMAKE_CURRENT_SOURCE_DIR}/partition/partition_M2354_im.h") set(update_stage_sdh true) set(update_stage_flash false) @@ -35,8 +36,8 @@ target_compile_definitions(mbed-m2354-tfm INTERFACE NU_TFM_S_BL2=$,1,0> NU_TFM_S_MCUBOOT_IMAGE_NUMBER=${mcuboot_image_number} - # TODO: Fix escape sequence in NU_TFM_S_REGION_DEFS_H_PATH - #NU_TFM_S_REGION_DEFS_H_PATH=\"${region_defs_h_path}\" + NU_TFM_S_REGION_DEFS_H_PATH="${region_defs_h_path}" + NU_TFM_S_PARTITION_MCU_H_PATH="${partition_mcu_h_path}" NU_TFM_S_UPDATE_STAGE_SDH=$,1,0> NU_TFM_S_UPDATE_STAGE_FLASH=$,1,0> ) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/partition_M2354_im.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/partition_M2354_im.h new file mode 100644 index 0000000000..98a36ac5b8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/partition_M2354_im.h @@ -0,0 +1,693 @@ +/**************************************************************************//** + * @file partition_M2354.h + * @version V3.00 + * @brief SAU configuration for secure/nonsecure region settings. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef PARTITION_M2354 +#define PARTITION_M2354 + +#include "region_defs.h" +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + + +/* + SRAMNSSET +*/ +/* +// Bit 0..18 +// Secure SRAM Size <0=> 0 KB +// <0x4000=> 16KB +// <0x8000=> 32KB +// <0xc000=> 48KB +// <0x10000=> 64KB +// <0x14000=> 80KB +// <0x18000=> 96KB +// <0x1C000=> 112KB +// <0x20000=> 128KB +// <0x24000=> 144KB +// <0x28000=> 160KB +// <0x2C000=> 176KB +// <0x30000=> 192KB +// <0x34000=> 208KB +// <0x38000=> 224KB +// <0x3C000=> 240KB +// <0x40000=> 256KB +*/ +#define SCU_SECURE_SRAM_SIZE S_DATA_SIZE +#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE) + + + +/*--------------------------------------------------------------------------------------------------------*/ + +/* + NSBA +*/ +#define FMC_INIT_NSBA 1 +/* +// Secure Flash ROM Size <0x800-0x80000:0x800> +*/ + +#define FMC_SECURE_ROM_SIZE (FLASH_AREA_0_OFFSET + FLASH_S_PARTITION_SIZE) + +#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE) + +/*--------------------------------------------------------------------------------------------------------*/ + + +/* +// Peripheral Secure Attribution Configuration +*/ + +/* + PNSSET0 +*/ +/* +// Module 0..31 +// USBH <0=> Secure <1=> Non-Secure +// SD0 <0=> Secure <1=> Non-Secure +// EBI <0=> Secure <1=> Non-Secure +// PDMA1 <0=> Secure <1=> Non-Secure +*/ +#if NU_SDH_CMSIS_FLASH +#define SCU_INIT_PNSSET0_VAL 0xFFFFDFFF +#else +#define SCU_INIT_PNSSET0_VAL 0xFFFFFFFF +#endif +/* + PNSSET1 +*/ +/* +// Module 0..31 +// CRC <0=> Secure <1=> Non-Secure +// CRPT <0=> Secure <1=> Non-Secure +*/ +#define SCU_INIT_PNSSET1_VAL 0xFFFFFFFF +/* + PNSSET2 +*/ +/* +// Module 0..31 +// EWDT <0=> Secure <1=> Non-Secure +// EADC <0=> Secure <1=> Non-Secure +// ACMP01 <0=> Secure <1=> Non-Secure +// +// DAC <0=> Secure <1=> Non-Secure +// I2S0 <0=> Secure <1=> Non-Secure +// OTG <0=> Secure <1=> Non-Secure +// TIMER +// TMR23 <0=> Secure <1=> Non-Secure +// TMR45 <0=> Secure <1=> Non-Secure +// +// EPWM +// EPWM0 <0=> Secure <1=> Non-Secure +// EPWM1 <0=> Secure <1=> Non-Secure +// +// BPWM +// BPWM0 <0=> Secure <1=> Non-Secure +// BPWM1 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_PNSSET2_VAL 0xFFFFFFFF +/* + PNSSET3 +*/ +/* +// Module 0..31 +// SPI +// QSPI0 <0=> Secure <1=> Non-Secure +// SPI0 <0=> Secure <1=> Non-Secure +// SPI1 <0=> Secure <1=> Non-Secure +// SPI2 <0=> Secure <1=> Non-Secure +// SPI3 <0=> Secure <1=> Non-Secure +// +// UART +// UART0 <0=> Secure <1=> Non-Secure +// UART1 <0=> Secure <1=> Non-Secure +// UART2 <0=> Secure <1=> Non-Secure +// UART3 <0=> Secure <1=> Non-Secure +// UART4 <0=> Secure <1=> Non-Secure +// UART5 <0=> Secure <1=> Non-Secure +// +*/ +#ifdef SECURE_UART1 +#define SCU_INIT_PNSSET3_VAL (0xFFFFFFFF & ~BIT17) +#else +#define SCU_INIT_PNSSET3_VAL 0xFFFFFFFF +#endif +/* + PNSSET4 +*/ +/* +// Module 0..31 +// I2C +// I2C0 <0=> Secure <1=> Non-Secure +// I2C1 <0=> Secure <1=> Non-Secure +// I2C2 <0=> Secure <1=> Non-Secure +// +// Smart Card +// SC0 <0=> Secure <1=> Non-Secure +// SC1 <0=> Secure <1=> Non-Secure +// SC2 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_PNSSET4_VAL 0xFFFFFFFF +/* + PNSSET5 +*/ +/* +// Module 0..31 +// CAN0 <0=> Secure <1=> Non-Secure +// QEI +// QEI0 <0=> Secure <1=> Non-Secure +// QEI1 <0=> Secure <1=> Non-Secure +// +// ECAP +// ECAP0 <0=> Secure <1=> Non-Secure +// ECAP1 <0=> Secure <1=> Non-Secure +// +// TRNG <0=> Secure <1=> Non-Secure +// LCD <0=> Secure <1=> Non-Secure +*/ +#define SCU_INIT_PNSSET5_VAL (0xFFFFFFFF & ~BIT25) +/* + PNSSET6 +*/ +/* +// Module 0..31 +// USBD <0=> Secure <1=> Non-Secure +// USCI +// USCI0 <0=> Secure <1=> Non-Secure +// USCI1 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_PNSSET6_VAL 0xFFFFFFFF +/* +// +*/ + + + +/* +// GPIO Secure Attribution Configuration +*/ + +/* + IONSSET +*/ + +/* +// Bit 0..31 +// PA +// PA0 <0=> Secure <1=> Non-Secure +// PA1 <0=> Secure <1=> Non-Secure +// PA2 <0=> Secure <1=> Non-Secure +// PA3 <0=> Secure <1=> Non-Secure +// PA4 <0=> Secure <1=> Non-Secure +// PA5 <0=> Secure <1=> Non-Secure +// PA6 <0=> Secure <1=> Non-Secure +// PA7 <0=> Secure <1=> Non-Secure +// PA8 <0=> Secure <1=> Non-Secure +// PA9 <0=> Secure <1=> Non-Secure +// PA10 <0=> Secure <1=> Non-Secure +// PA11 <0=> Secure <1=> Non-Secure +// PA12 <0=> Secure <1=> Non-Secure +// PA13 <0=> Secure <1=> Non-Secure +// PA14 <0=> Secure <1=> Non-Secure +// PA15 <0=> Secure <1=> Non-Secure +// + +*/ +#define SCU_INIT_IONSSET0_VAL 0xFFFFFFFF + +/* +// Bit 0..31 +// PB +// PB0 <0=> Secure <1=> Non-Secure +// PB1 <0=> Secure <1=> Non-Secure +// PB2 <0=> Secure <1=> Non-Secure +// PB3 <0=> Secure <1=> Non-Secure +// PB4 <0=> Secure <1=> Non-Secure +// PB5 <0=> Secure <1=> Non-Secure +// PB6 <0=> Secure <1=> Non-Secure +// PB7 <0=> Secure <1=> Non-Secure +// PB8 <0=> Secure <1=> Non-Secure +// PB9 <0=> Secure <1=> Non-Secure +// PB10 <0=> Secure <1=> Non-Secure +// PB11 <0=> Secure <1=> Non-Secure +// PB12 <0=> Secure <1=> Non-Secure +// PB13 <0=> Secure <1=> Non-Secure +// PB14 <0=> Secure <1=> Non-Secure +// PB15 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET1_VAL 0xFFFFFFFF + + +/* +// Bit 0..31 +// PC +// PC0 <0=> Secure <1=> Non-Secure +// PC1 <0=> Secure <1=> Non-Secure +// PC2 <0=> Secure <1=> Non-Secure +// PC3 <0=> Secure <1=> Non-Secure +// PC4 <0=> Secure <1=> Non-Secure +// PC5 <0=> Secure <1=> Non-Secure +// PC6 <0=> Secure <1=> Non-Secure +// PC7 <0=> Secure <1=> Non-Secure +// PC8 <0=> Secure <1=> Non-Secure +// PC9 <0=> Secure <1=> Non-Secure +// PC10 <0=> Secure <1=> Non-Secure +// PC11 <0=> Secure <1=> Non-Secure +// PC12 <0=> Secure <1=> Non-Secure +// PC13 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET2_VAL 0xFFFFFFFF + +/* +// Bit 0..31 +// PD +// PD0 <0=> Secure <1=> Non-Secure +// PD1 <0=> Secure <1=> Non-Secure +// PD2 <0=> Secure <1=> Non-Secure +// PD3 <0=> Secure <1=> Non-Secure +// PD4 <0=> Secure <1=> Non-Secure +// PD5 <0=> Secure <1=> Non-Secure +// PD6 <0=> Secure <1=> Non-Secure +// PD7 <0=> Secure <1=> Non-Secure +// PD8 <0=> Secure <1=> Non-Secure +// PD9 <0=> Secure <1=> Non-Secure +// PD10 <0=> Secure <1=> Non-Secure +// PD11 <0=> Secure <1=> Non-Secure +// PD12 <0=> Secure <1=> Non-Secure +// PD14 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET3_VAL 0xFFFFFFFF + + +/* +// Bit 0..31 +// PE +// PE0 <0=> Secure <1=> Non-Secure +// PE1 <0=> Secure <1=> Non-Secure +// PE2 <0=> Secure <1=> Non-Secure +// PE3 <0=> Secure <1=> Non-Secure +// PE4 <0=> Secure <1=> Non-Secure +// PE5 <0=> Secure <1=> Non-Secure +// PE6 <0=> Secure <1=> Non-Secure +// PE7 <0=> Secure <1=> Non-Secure +// PE8 <0=> Secure <1=> Non-Secure +// PE9 <0=> Secure <1=> Non-Secure +// PE10 <0=> Secure <1=> Non-Secure +// PE11 <0=> Secure <1=> Non-Secure +// PE12 <0=> Secure <1=> Non-Secure +// PE13 <0=> Secure <1=> Non-Secure +// PE14 <0=> Secure <1=> Non-Secure +// PE15 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET4_VAL 0xFFFFFFFF + + +/* +// Bit 0..31 +// PF +// PF0 <0=> Secure <1=> Non-Secure +// PF1 <0=> Secure <1=> Non-Secure +// PF2 <0=> Secure <1=> Non-Secure +// PF3 <0=> Secure <1=> Non-Secure +// PF4 <0=> Secure <1=> Non-Secure +// PF5 <0=> Secure <1=> Non-Secure +// PF6 <0=> Secure <1=> Non-Secure +// PF7 <0=> Secure <1=> Non-Secure +// PF8 <0=> Secure <1=> Non-Secure +// PF9 <0=> Secure <1=> Non-Secure +// PF10 <0=> Secure <1=> Non-Secure +// PF11 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET5_VAL 0xFFFFFFFF + + +/* +// Bit 0..31 +// PG +// PG2 <0=> Secure <1=> Non-Secure +// PG3 <0=> Secure <1=> Non-Secure +// PG4 <0=> Secure <1=> Non-Secure +// PG9 <0=> Secure <1=> Non-Secure +// PG10 <0=> Secure <1=> Non-Secure +// PG11 <0=> Secure <1=> Non-Secure +// PG12 <0=> Secure <1=> Non-Secure +// PG13 <0=> Secure <1=> Non-Secure +// PG14 <0=> Secure <1=> Non-Secure +// PG15 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET6_VAL 0xFFFFFFFF + +/* +// Bit 0..31 +// PH +// PH4 <0=> Secure <1=> Non-Secure +// PH5 <0=> Secure <1=> Non-Secure +// PH6 <0=> Secure <1=> Non-Secure +// PH7 <0=> Secure <1=> Non-Secure +// PH8 <0=> Secure <1=> Non-Secure +// PH9 <0=> Secure <1=> Non-Secure +// PH10 <0=> Secure <1=> Non-Secure +// PH11 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET7_VAL 0xFFFFFFFF + +/* +// +*/ + + + +/* +// Assign GPIO Interrupt to Secure or Non-secure Vector +*/ + + +/* + Initialize GPIO ITNS (Interrupts 0..31) +*/ + +/* +// Bit 0..31 +// GPA <0=> Secure <1=> Non-Secure +// GPB <0=> Secure <1=> Non-Secure +// GPC <0=> Secure <1=> Non-Secure +// GPD <0=> Secure <1=> Non-Secure +// GPE <0=> Secure <1=> Non-Secure +// GPF <0=> Secure <1=> Non-Secure +// GPG <0=> Secure <1=> Non-Secure +// GPH <0=> Secure <1=> Non-Secure +// EINT0 <0=> Secure <1=> Non-Secure +// EINT1 <0=> Secure <1=> Non-Secure +// EINT2 <0=> Secure <1=> Non-Secure +// EINT3 <0=> Secure <1=> Non-Secure +// EINT4 <0=> Secure <1=> Non-Secure +// EINT5 <0=> Secure <1=> Non-Secure +// EINT6 <0=> Secure <1=> Non-Secure +// EINT7 <0=> Secure <1=> Non-Secure +*/ +#define SCU_INIT_IONSSET_VAL 0xFFFFFFFF +/* +// +*/ + + +/* ---------------------------------------------------------------------------------------------------- */ + +/* +// Secure Attribute Unit (SAU) Control +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// To enable Secure Attribute Unit (SAU). +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// All Memory Attribute When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// To set the ALLNS bit in SAU CTRL. +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + + +/* +// Enable and Set Secure/Non-Secure region +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// SAU Region 0 +// Setup SAU Region 0 +*/ +#define SAU_INIT_REGION0 0 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */ +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */ +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// SAU Region 1 +// Setup SAU Region 1 +*/ +#define SAU_INIT_REGION1 0 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x10040000 +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x1007FFFF +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// SAU Region 2 +// Setup SAU Region 2 +*/ +#define SAU_INIT_REGION2 0 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x2000F000 +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2000FFFF +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// SAU Region 3 +// Setup SAU Region 3 +*/ +#define SAU_INIT_REGION3 1 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x3f000 +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x3f7ff +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 1 +/* +// +*/ + +/* + SAU Region 4 + Setup SAU Region 4 +*/ +#define SAU_INIT_REGION4 1 +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */ + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x100FFFFF /* end address of SAU region 4 */ + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* + +*/ + +/* + SAU Region 5 + Setup SAU Region 5 +*/ +#define SAU_INIT_REGION5 1 + +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00807E00 + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00807FFF + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 1 +/* + +*/ + +/* + SAU Region 6 + Setup SAU Region 6 +*/ +#define SAU_INIT_REGION6 1 + +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 NON_SECURE_SRAM_BASE + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x3004FFFF + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* + +*/ + +/* + SAU Region 7 + Setup SAU Region 7 +*/ +#define SAU_INIT_REGION7 1 + +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x50000000 + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x5FFFFFFF + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* + +*/ + +/* +// +*/ + +/* +// Setup behavior of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* Assign HardFault to be always secure for safe */ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +#endif /* PARTITION_M2354 */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/nu_tfm_import_define.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/nu_tfm_import_define.h new file mode 100644 index 0000000000..a323212862 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/nu_tfm_import_define.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __NU_TFM_IMPORT_DEFINE_H__ +#define __NU_TFM_IMPORT_DEFINE_H__ + +/* Update NU_TFM_S_BL2 and friends on redoing TF-M import + * + * We expect NU_TFM_S_BL2 and friends are passed along from build tool, esp. Mbed CLI2, + * If not, NU_TFM_S_BL2 and friends must update manually. */ + +#ifndef NU_TFM_S_BL2 +#define NU_TFM_S_BL2 1 +#endif + +#ifndef NU_TFM_S_MCUBOOT_IMAGE_NUMBER +#define NU_TFM_S_MCUBOOT_IMAGE_NUMBER 2 +#endif + +#ifndef NU_TFM_S_UPDATE_STAGE_SDH +#define NU_TFM_S_UPDATE_STAGE_SDH 1 +#endif + +#ifndef NU_TFM_S_UPDATE_STAGE_FLASH +#define NU_TFM_S_UPDATE_STAGE_FLASH 0 +#endif + +#ifndef NU_TFM_S_REGION_DEFS_H_PATH +#define NU_TFM_S_REGION_DEFS_H_PATH "../TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h" +#endif + +#ifndef NU_TFM_S_PARTITION_MCU_H_PATH +#define NU_TFM_S_PARTITION_MCU_H_PATH "../TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/partition_M2354_im.h" +#endif + +/* TF-M exported partition/ header files depend on below defines */ +#if NU_TFM_S_BL2 +#define BL2 +#endif +#define MCUBOOT_IMAGE_NUMBER NU_TFM_S_MCUBOOT_IMAGE_NUMBER +#define NU_UPDATE_STAGE_SDH NU_TFM_S_UPDATE_STAGE_SDH +#define NU_UPDATE_STAGE_FLASH NU_TFM_S_UPDATE_STAGE_FLASH + +#endif /* __NU_TFM_IMPORT_DEFINE_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/nu_tfm_import_undefine.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/nu_tfm_import_undefine.h new file mode 100644 index 0000000000..75f584ac6d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/nu_tfm_import_undefine.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __NU_TFM_IMPORT_UNDEFINE_H__ +#define __NU_TFM_IMPORT_UNDEFINE_H__ + +/* Avoid polluting name space, esp. BL2 */ +#undef BL2 +#undef MCUBOOT_IMAGE_NUMBER +#undef NU_UPDATE_STAGE_SDH +#undef NU_UPDATE_STAGE_FLASH + +#endif /* __NU_TFM_IMPORT_UNDEFINE_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354.h index f778f10e78..80e29ca882 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354.h +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354.h @@ -8,22 +8,24 @@ * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. ******************************************************************************/ -#ifndef PARTITION_M2354 -#define PARTITION_M2354 - -#include "partition_M2354_mem.h" - -#ifdef __cplusplus -extern "C" -{ -#endif +#ifndef PARTITION_M2354_WRAPPER +#define PARTITION_M2354_WRAPPER /* Since 6.0, Mbed OS doesn't support secure build and target platform code is basically TrustZone-unaware. - * So make this file trivial. */ - -#ifdef __cplusplus -} -#endif - -#endif /* PARTITION_M2354 */ + * However, some BSP driver code are still TrustZone-aware. To avoid make big change on them, import + * mcu partition header from TF-M. + * + * For example, LCD will incorrectly resolve to LCD_S without `SCU_INIT_PNSSET5_VAL` define: + * + * #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT27) + * # define LCD LCD_NS + * #else + * # define LCD LCD_S + * #endif + * + */ +#include "nu_tfm_import_define.h" +#include NU_TFM_S_PARTITION_MCU_H_PATH +#include "nu_tfm_import_undefine.h" +#endif /* PARTITION_M2354_WRAPPER */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.h index 7955907c21..f7a97d36a2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.h +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.h @@ -33,46 +33,9 @@ * (already there or via copy). */ -/* Update NU_TFM_S_BL2 and friends on redoing TF-M import - * - * We expect NU_TFM_S_BL2 and friends are passed along from build tool, esp. Mbed CLI2, - * If not, NU_TFM_S_BL2 and friends must update manually. */ - -#ifndef NU_TFM_S_BL2 -#define NU_TFM_S_BL2 1 -#endif - -#ifndef NU_TFM_S_MCUBOOT_IMAGE_NUMBER -#define NU_TFM_S_MCUBOOT_IMAGE_NUMBER 2 -#endif - -#ifndef NU_TFM_S_UPDATE_STAGE_SDH -#define NU_TFM_S_UPDATE_STAGE_SDH 1 -#endif - -#ifndef NU_TFM_S_UPDATE_STAGE_FLASH -#define NU_TFM_S_UPDATE_STAGE_FLASH 0 -#endif - -#ifndef NU_TFM_S_REGION_DEFS_H_PATH -#define NU_TFM_S_REGION_DEFS_H_PATH "../TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h" -#endif - -/* TF-M exported region_defs.h depends on BL2 and MCUBOOT_IMAGE_NUMBER, so the - * following order is significant. */ -#if NU_TFM_S_BL2 -#define BL2 -#endif -#define MCUBOOT_IMAGE_NUMBER NU_TFM_S_MCUBOOT_IMAGE_NUMBER +#include "nu_tfm_import_define.h" #include NU_TFM_S_REGION_DEFS_H_PATH -#define NU_UPDATE_STAGE_SDH NU_TFM_S_UPDATE_STAGE_SDH -#define NU_UPDATE_STAGE_FLASH NU_TFM_S_UPDATE_STAGE_FLASH - -/* Avoid polluting name space, esp. BL2 */ -#undef BL2 -#undef MCUBOOT_IMAGE_NUMBER -#undef NU_UPDATE_STAGE_SDH -#undef NU_UPDATE_STAGE_FLASH +#include "nu_tfm_import_undefine.h" /* Resolve MBED_ROM_START and friends *