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Merge pull request #7606 from bcostm/PULL_REQUEST_CUBE_UPDATE_F1_V1.6.1 

STM32F1: update to CubeF1 V1.6.1
pull/7495/head
Martin Kojtal 2018-08-01 15:00:21 +02:00 committed by GitHub
parent 03ad9d63ec b47e599281
commit 9df48f561b
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GPG Key ID: 4AEE18F83AFDEB23
128 changed files with 4043 additions and 2368 deletions
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1736
targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32cubef1.html Normal file
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targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html
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targets/TARGET_STM/TARGET_STM32F1/device/stm32_assert_template.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @version $VERSION$
* @date $DATE$
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.

4
targets/TARGET_STM/TARGET_STM32F1/device/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @version V1.1.1
* @date 12-May-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************

111
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -71,11 +69,11 @@
* @{
*/
/**
* @brief STM32F1xx HAL Driver version number V1.1.0
* @brief STM32F1xx HAL Driver version number V1.1.2
*/
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
@ -95,6 +93,8 @@
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
@ -114,12 +114,12 @@ __IO uint32_t uwTick;
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface, the NVIC allocation and initial clock
configuration. It initializes the source of time base also when timeout
is needed and the backup domain when enabled.
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) de-Initializes common part of the HAL.
(+) Configure The time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) Systick timer is used by default as source of time base, but user
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
@ -172,7 +172,7 @@ HAL_StatusTypeDef HAL_Init(void)
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
/* Init the low level hardware */
@ -183,7 +183,7 @@ HAL_StatusTypeDef HAL_Init(void)
}
/**
* @brief This function de-Initializes common part of the HAL and stops the source
* @brief This function de-Initializes common part of the HAL and stops the systick.
* of time base.
* @note This function is optional.
* @retval HAL status
@ -210,12 +210,12 @@ HAL_StatusTypeDef HAL_DeInit(void)
}
/**
* @brief Initializes the MSP.
* @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
@ -226,7 +226,7 @@ __weak void HAL_MspInit(void)
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
@ -240,20 +240,31 @@ __weak void HAL_MspDeInit(void)
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The the SysTick interrupt must have higher priority (numerically lower)
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
HAL_SYSTICK_Config(SystemCoreClock/1000U);
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
@ -290,14 +301,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in Systick ISR.
* in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick++;
uwTick += uwTickFreq;
}
/**
@ -311,6 +322,44 @@ __weak uint32_t HAL_GetTick(void)
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @retval Status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
}
return status;
}
/**
* @brief Return tick frequency.
* @retval tick period in Hz
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
@ -319,21 +368,21 @@ __weak uint32_t HAL_GetTick(void)
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(__IO uint32_t Delay)
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guarantee minimum wait */
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait++;
wait += (uint32_t)(uwTickFreq);
}
while((HAL_GetTick() - tickstart) < wait)
while ((HAL_GetTick() - tickstart) < wait)
{
}
}
@ -351,7 +400,7 @@ __weak void HAL_Delay(__IO uint32_t Delay)
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
@ -367,12 +416,12 @@ __weak void HAL_SuspendTick(void)
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Returns the HAL revision
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
* @retval version 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
@ -392,7 +441,7 @@ uint32_t HAL_GetHalVersion(void)
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
@ -408,7 +457,7 @@ uint32_t HAL_GetREVID(void)
*/
uint32_t HAL_GetDEVID(void)
{
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
/**
@ -516,7 +565,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void)
/**
* @brief Return the unique device identifier (UID based on 96 bits)
* @param UID: pointer to 3 words array.
* @param UID pointer to 3 words array.
* @retval Device identifier
*/
void HAL_GetUID(uint32_t *UID)

38
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@ -41,7 +39,7 @@
#define __STM32F1xx_HAL_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -58,6 +56,27 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
@ -256,6 +275,12 @@
* @}
*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
@ -272,7 +297,7 @@ HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
@ -282,8 +307,11 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_adc.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_adc.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_can.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:

6
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_can.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -557,7 +555,7 @@ typedef struct
* @param __HANDLE__: specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
* @arg CAN_FLAG_RQCP0: Request MailBox0 Flag // MBED patch
* @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
* @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
@ -591,7 +589,7 @@ typedef struct
* @param __HANDLE__: specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
* @arg CAN_FLAG_RQCP0: Request MailBox0 Flag // MBED patch
* @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
* @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_can_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of CAN HAL Extension module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_cec.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_cec.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention

95
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f1xx_hal_conf.h.
@ -42,7 +40,7 @@
#define __STM32F1xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
@ -93,14 +91,14 @@
*/
#if !defined (HSE_VALUE)
#if defined(USE_STM3210C_EVAL)
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#else
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@ -109,14 +107,14 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@ -125,11 +123,11 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -232,135 +230,146 @@
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f1xx_hal_rcc.h"
#include "stm32f1xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f1xx_hal_gpio.h"
#include "stm32f1xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f1xx_hal_dma.h"
#include "stm32f1xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f1xx_hal_eth.h"
#include "stm32f1xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f1xx_hal_can.h"
#include "stm32f1xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f1xx_hal_cec.h"
#include "stm32f1xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f1xx_hal_cortex.h"
#include "stm32f1xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f1xx_hal_adc.h"
#include "stm32f1xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f1xx_hal_crc.h"
#include "stm32f1xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f1xx_hal_dac.h"
#include "stm32f1xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f1xx_hal_flash.h"
#include "stm32f1xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f1xx_hal_sram.h"
#include "stm32f1xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f1xx_hal_nor.h"
#include "stm32f1xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f1xx_hal_i2c.h"
#include "stm32f1xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f1xx_hal_i2s.h"
#include "stm32f1xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f1xx_hal_iwdg.h"
#include "stm32f1xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f1xx_hal_pwr.h"
#include "stm32f1xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f1xx_hal_rtc.h"
#include "stm32f1xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f1xx_hal_pccard.h"
#include "stm32f1xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f1xx_hal_sd.h"
#include "stm32f1xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f1xx_hal_nand.h"
#include "stm32f1xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f1xx_hal_spi.h"
#include "stm32f1xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f1xx_hal_tim.h"
#include "stm32f1xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f1xx_hal_uart.h"
#include "stm32f1xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f1xx_hal_usart.h"
#include "stm32f1xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f1xx_hal_irda.h"
#include "stm32f1xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f1xx_hal_smartcard.h"
#include "stm32f1xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f1xx_hal_wwdg.h"
#include "stm32f1xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f1xx_hal_pcd.h"
#include "stm32f1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f1xx_hal_hcd.h"
#include "stm32f1xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f1xx_hal_mmc.h"
#include "stm32f1xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/* ALL MBED targets use same stm32_assert.h */
// MBED patch: all targets use the same assert file
#include "stm32_assert.h"
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
//#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
//void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_cortex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_cortex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_crc.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_crc.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_dac.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_dac.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

70
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_def.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@ -41,13 +39,13 @@
#define __STM32F1xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
#if defined(USE_HAL_LEGACY)
#include "stm32_hal_legacy.h"
#include "stm32_hal_legacy.h" // MBED patch
#endif
#include <stdio.h>
@ -85,7 +83,7 @@ typedef enum
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U)
#define UNUSED(x) ((void)(x))
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
@ -105,10 +103,10 @@ typedef enum
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1U)
/* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release"
/* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release"
#else
#define __HAL_LOCK(__HANDLE__) \
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
@ -120,41 +118,41 @@ typedef enum
} \
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined ( __CC_ARM )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
@ -171,14 +169,14 @@ typedef enum
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC HAL_StatusTypeDef
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
@ -186,7 +184,7 @@ typedef enum
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif

6
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_dma.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief DMA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
@ -869,7 +867,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
/* Peripheral to Memory */
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Channel destination address */
@ -878,7 +876,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
}
/* Memory to Peripheral */
/* Peripheral to Memory */
else
{
/* Configure DMA Channel source address */

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_dma.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention

190
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_eth.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@ -183,7 +181,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
uint32_t err = ETH_SUCCESS;
/* Check the ETH peripheral state */
if(heth == NULL)
if (heth == NULL)
{
return HAL_ERROR;
}
@ -194,7 +192,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
if(heth->State == HAL_ETH_STATE_RESET)
if (heth->State == HAL_ETH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
@ -218,9 +216,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_SWRESET)
{
heth->State= HAL_ETH_STATE_TIMEOUT;
heth->State = HAL_ETH_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -241,12 +239,12 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
hclk = HAL_RCC_GetHCLKFreq();
/* Set CR bits depending on hclk value */
if((hclk >= 20000000U)&&(hclk < 35000000U))
if ((hclk >= 20000000U) && (hclk < 35000000U))
{
/* CSR Clock Range between 20-35 MHz */
tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
}
else if((hclk >= 35000000U)&&(hclk < 60000000U))
else if ((hclk >= 35000000U) && (hclk < 60000000U))
{
/* CSR Clock Range between 35-60 MHz */
tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
@ -262,7 +260,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
@ -280,7 +278,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/* Delay to assure PHY reset */
HAL_Delay(PHY_RESET_DELAY);
if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
if ((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
@ -291,7 +289,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_LINKED_STATE)
{
/* In case of write timeout */
err = ETH_ERROR;
@ -299,18 +297,19 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_TIMEOUT;
}
} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
}
while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
/* Enable Auto-Negotiation */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
@ -334,7 +333,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
{
/* In case of write timeout */
err = ETH_ERROR;
@ -342,7 +341,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -350,10 +349,11 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
return HAL_TIMEOUT;
}
} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
}
while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
/* Read the result of the auto-negotiation */
if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
if ((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
@ -369,7 +369,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
}
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
if ((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
if ((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
{
/* Set Ethernet speed to 10M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_10M;
@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
/* Set MAC Speed and Duplex Mode */
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
if (HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
(uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
{
/* In case of write timeout */
@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
ETH_MACDMAConfig(heth, err);
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Return function status */
return HAL_OK;
@ -443,7 +443,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
HAL_ETH_MspDeInit(heth);
/* Set ETH HAL state to Disabled */
heth->State= HAL_ETH_STATE_RESET;
heth->State = HAL_ETH_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(heth);
@ -476,7 +476,7 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
heth->TxDesc = DMATxDescTab;
/* Fill each DMATxDesc descriptor with the right values */
for(i=0U; i < TxBuffCount; i++)
for (i = 0U; i < TxBuffCount; i++)
{
/* Get the pointer on the ith member of the Tx Desc list */
dmatxdesc = DMATxDescTab + i;
@ -485,7 +485,7 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
dmatxdesc->Status = ETH_DMATXDESC_TCH;
/* Set Buffer1 address pointer */
dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_TX_BUF_SIZE]);
if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
{
@ -494,10 +494,10 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (TxBuffCount-1U))
if (i < (TxBuffCount - 1U))
{
/* Set next descriptor address register with next descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1U);
}
else
{
@ -510,7 +510,7 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -543,10 +543,10 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
heth->RxDesc = DMARxDescTab;
/* Fill each DMARxDesc descriptor with the right values */
for(i=0U; i < RxBuffCount; i++)
for (i = 0U; i < RxBuffCount; i++)
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
DMARxDesc = DMARxDescTab + i;
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARXDESC_OWN;
@ -555,19 +555,19 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_RX_BUF_SIZE]);
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
/* Enable Ethernet DMA Rx Descriptor interrupt */
DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (RxBuffCount-1U))
if (i < (RxBuffCount - 1U))
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1U);
}
else
{
@ -580,7 +580,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -657,6 +657,10 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
{
uint32_t bufcount = 0U, size = 0U, i = 0U;
/* Process Locked */
// MBED patch
//__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
@ -665,22 +669,30 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
/* Set ETH HAL state to READY */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
// MBED patch
//__HAL_UNLOCK(heth);
return HAL_ERROR;
}
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
if (((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
{
/* OWN bit set */
heth->State = HAL_ETH_STATE_BUSY_TX;
/* Process Unlocked */
// MBED patch
//__HAL_UNLOCK(heth);
return HAL_ERROR;
}
/* Get the number of needed Tx buffers for the current frame */
if (FrameLength > ETH_TX_BUF_SIZE)
{
bufcount = FrameLength/ETH_TX_BUF_SIZE;
bufcount = FrameLength / ETH_TX_BUF_SIZE;
if (FrameLength % ETH_TX_BUF_SIZE)
{
bufcount++;
@ -693,17 +705,17 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
if (bufcount == 1U)
{
/* Set LAST and FIRST segment */
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
heth->TxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
/* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* Point to next descriptor */
heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
}
else
{
for (i=0U; i< bufcount; i++)
for (i = 0U; i < bufcount; i++)
{
/* Clear FIRST and LAST segment bits */
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
@ -717,11 +729,11 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
/* Program size */
heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
if (i == (bufcount-1U))
if (i == (bufcount - 1U))
{
/* Setting the last segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_LS;
size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
size = FrameLength - (bufcount - 1U) * ETH_TX_BUF_SIZE;
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
}
@ -744,6 +756,10 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
@ -758,15 +774,19 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
{
uint32_t framelength = 0U;
/* Process Locked */
// MBED patch
//__HAL_LOCK(heth);
/* Check the ETH state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Check if segment is not owned by DMA */
/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
if (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
{
/* Check if last segment */
if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
if (((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
{
/* increment segment count */
(heth->RxFrameInfos).SegCount++;
@ -774,7 +794,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
/* Check if last segment is first segment: one segment contains the frame */
if ((heth->RxFrameInfos).SegCount == 1U)
{
(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
}
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
@ -786,35 +806,43 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
/* point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
heth->RxDesc = (ETH_DMADescTypeDef *)((heth->RxDesc)->Buffer2NextDescAddr);
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/* Check if first segment */
else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
else if ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
{
(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
(heth->RxFrameInfos).LSRxDesc = NULL;
(heth->RxFrameInfos).SegCount = 1U;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
/* Check if intermediate segment */
else
{
(heth->RxFrameInfos).SegCount++;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
}
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_ERROR;
}
@ -829,6 +857,10 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
{
uint32_t descriptorscancounter = 0U;
/* Process Locked */
// MBED patch
//__HAL_LOCK(heth);
/* Set ETH HAL State to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
@ -840,12 +872,12 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
/* Check if first segment in frame */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
if ((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
heth->RxFrameInfos.SegCount = 1U;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
/* Check if intermediate segment */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
@ -854,7 +886,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
/* Should be last segment */
else
@ -875,14 +907,18 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
@ -891,6 +927,10 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_ERROR;
}
@ -939,7 +979,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
/* ETH DMA Error */
if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
{
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
@ -1021,7 +1061,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_RD)
if (heth->State == HAL_ETH_STATE_BUSY_RD)
{
return HAL_BUSY;
}
@ -1035,8 +1075,8 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII address register value */
tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
@ -1047,12 +1087,12 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
tickstart = HAL_GetTick();
/* Check for the Busy flag */
while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
if ((HAL_GetTick() - tickstart) > PHY_READ_TO)
{
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -1093,7 +1133,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_WR)
if (heth->State == HAL_ETH_STATE_BUSY_WR)
{
return HAL_BUSY;
}
@ -1107,8 +1147,8 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII register address value */
tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
@ -1122,12 +1162,12 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
tickstart = HAL_GetTick();
/* Check for the Busy flag */
while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO)
{
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -1170,7 +1210,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
* @{
*/
/**
/**
* @brief Enables Ethernet MAC and DMA reception/transmission
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
@ -1200,7 +1240,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
ETH_DMAReceptionEnable(heth);
/* Set the ETH state to READY*/
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -1263,7 +1303,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State= HAL_ETH_STATE_BUSY;
heth->State = HAL_ETH_STATE_BUSY;
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
@ -1406,7 +1446,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
}
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -1430,7 +1470,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State= HAL_ETH_STATE_BUSY;
heth->State = HAL_ETH_STATE_BUSY;
/* Check parameters */
assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
@ -1490,7 +1530,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
(heth->Instance)->DMABMR = tmpreg1;
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
@ -1574,7 +1614,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
}
@ -1789,7 +1829,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMABMR = tmpreg1;
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
/* Enable the Ethernet Rx Interrupt */
__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);

30
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_eth.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@ -40,7 +38,7 @@
#define __STM32F1xx_HAL_ETH_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -355,7 +353,7 @@
/* ETHERNET Missed frames counter Shift */
#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
/**
/**
* @}
*/
@ -379,7 +377,7 @@ typedef enum
HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_ETH_StateTypeDef;
} HAL_ETH_StateTypeDef;
/**
* @brief ETH Init Structure definition
@ -415,7 +413,7 @@ typedef struct
} ETH_InitTypeDef;
/**
/**
* @brief ETH MAC Configuration Structure definition
*/
@ -633,7 +631,7 @@ typedef struct
} ETH_HandleTypeDef;
/**
/**
* @}
*/
@ -654,7 +652,7 @@ typedef struct
#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
/* Ethernet driver receive buffers are organized in a chained linked-list, when
/* Ethernet driver receive buffers are organized in a chained linked-list, when
an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
to the driver receive buffers memory.
@ -672,16 +670,16 @@ typedef struct
/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
packet */
#ifndef ETH_RX_BUF_SIZE
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
#endif
/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
#ifndef ETH_RXBUFNB
#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#endif
/* Ethernet driver transmit buffers are organized in a chained linked-list, when
/* Ethernet driver transmit buffers are organized in a chained linked-list, when
an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
driver transmit buffers memory to the TxFIFO.
@ -699,15 +697,15 @@ typedef struct
/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
packet */
#ifndef ETH_TX_BUF_SIZE
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
#endif
/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
#ifndef ETH_TXBUFNB
#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
/**
/**
* @}
*/
@ -842,7 +840,7 @@ typedef struct
/**
* @}
*/
/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
* @{
*/
#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
@ -2039,7 +2037,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
/**

33
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_flash.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -674,31 +672,36 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
HAL_StatusTypeDef status = HAL_OK;
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
}
else
{
return HAL_ERROR;
}
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{
status = HAL_ERROR;
}
}
#if defined(FLASH_BANK2_END)
if (HAL_IS_BIT_SET(FLASH->CR2, FLASH_CR2_LOCK))
if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)
{
/* Authorize the FLASH BANK2 Registers access */
WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
}
else
{
return HAL_ERROR;
}
/* Verify Flash BANK2 is unlocked */
if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)
{
status = HAL_ERROR;
}
}
#endif /* FLASH_BANK2_END */
return HAL_OK;
return status;
}
/**

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_flash.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention

40
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_gpio.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -263,11 +261,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
case GPIO_MODE_EVT_RISING_FALLING:
/* Check the GPIO pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
if(GPIO_Init->Pull == GPIO_NOPULL)
if (GPIO_Init->Pull == GPIO_NOPULL)
{
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
}
else if(GPIO_Init->Pull == GPIO_PULLUP)
else if (GPIO_Init->Pull == GPIO_PULLUP)
{
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
@ -299,11 +297,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
@ -314,7 +312,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Configure the interrupt mask */
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
SET_BIT(EXTI->IMR, iocurrent);
}
@ -324,7 +322,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
}
/* Configure the event mask */
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
SET_BIT(EXTI->EMR, iocurrent);
}
@ -334,7 +332,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
}
/* Enable or disable the rising trigger */
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
SET_BIT(EXTI->RTSR, iocurrent);
}
@ -344,7 +342,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
}
/* Enable or disable the falling trigger */
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
SET_BIT(EXTI->FTSR, iocurrent);
}
@ -391,7 +389,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
/* CRL/CRH default value is floating input(0x04) shifted to correct position */
MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset);
/* ODR default value is 0 */
CLEAR_BIT(GPIOx->ODR, iocurrent);
@ -401,7 +399,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp = AFIO->EXTICR[position >> 2U];
tmp &= 0x0FU << (4U * (position & 0x03U));
if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = 0x0FU << (4U * (position & 0x03U));
CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);
@ -445,7 +443,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
@ -475,17 +473,17 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_BIT_RESET: to clear the port pin
* @arg GPIO_BIT_SET: to set the port pin
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
@ -501,7 +499,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
@ -519,7 +517,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
@ -538,7 +536,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
{
return HAL_OK;
}
@ -556,7 +554,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);

18
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_gpio.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@ -40,7 +38,7 @@
#define __STM32F1xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -75,7 +73,7 @@ typedef struct
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
}GPIO_InitTypeDef;
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
@ -84,7 +82,7 @@ typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
}GPIO_PinState;
} GPIO_PinState;
/**
* @}
*/
@ -164,7 +162,7 @@ typedef enum
* @}
*/
/** @defgroup GPIO_pull_define GPIO pull define
/** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
@ -249,10 +247,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);

4
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_gpio_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief GPIO Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
@ -103,7 +101,7 @@ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource
assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
/* Apply the new configuration */
MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT)|(AFIO_EVCR_PIN), (GPIO_PortSource)|(GPIO_PinSource));
MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
}
/**

182
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
@ -40,7 +38,7 @@
#define __STM32F1xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -53,9 +51,7 @@
/** @defgroup GPIOEx GPIOEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
@ -141,145 +137,126 @@
* @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
* @retval None
*/
#define __HAL_AFIO_REMAP_SPI1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
/**
* @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
* @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
* @retval None
*/
#define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
/**
* @brief Enable the remapping of I2C1 alternate function SCL and SDA.
* @note ENABLE: Remap (SCL/PB8, SDA/PB9)
* @retval None
*/
#define __HAL_AFIO_REMAP_I2C1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
/**
* @brief Disable the remapping of I2C1 alternate function SCL and SDA.
* @note DISABLE: No remap (SCL/PB6, SDA/PB7)
* @retval None
*/
#define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
/**
* @brief Enable the remapping of USART1 alternate function TX and RX.
* @note ENABLE: Remap (TX/PB6, RX/PB7)
* @retval None
*/
#define __HAL_AFIO_REMAP_USART1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
/**
* @brief Disable the remapping of USART1 alternate function TX and RX.
* @note DISABLE: No remap (TX/PA9, RX/PA10)
* @retval None
*/
#define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
/**
* @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
* @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
* @retval None
*/
#define __HAL_AFIO_REMAP_USART2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
/**
* @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
* @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
* @retval None
*/
#define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
/**
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
* @retval None
*/
#define __HAL_AFIO_REMAP_USART3_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
* @retval None
*/
#define __HAL_AFIO_REMAP_USART3_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
/**
* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
* @retval None
*/
#define __HAL_AFIO_REMAP_USART3_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM1_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM1_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
/**
* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM1_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM2_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
/**
* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM2_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
@ -287,9 +264,7 @@
* @note TIM3_ETR on PE0 is not re-mapped.
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM3_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
@ -297,9 +272,7 @@
* @note TIM3_ETR on PE0 is not re-mapped.
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM3_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
/**
* @brief Disable the remapping of TIM3 alternate function channels 1 to 4
@ -307,9 +280,7 @@
* @note TIM3_ETR on PE0 is not re-mapped.
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM3_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP); \
}while(0U)
#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
/**
* @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
@ -317,7 +288,7 @@
* @note TIM4_ETR on PE0 is not re-mapped.
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
/**
* @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
@ -325,7 +296,7 @@
* @note TIM4_ETR on PE0 is not re-mapped.
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
@ -334,27 +305,22 @@
* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
* @retval None
*/
#define __HAL_AFIO_REMAP_CAN1_1() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1); \
}while(0U)
#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
/**
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
* @retval None
*/
#define __HAL_AFIO_REMAP_CAN1_2() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2); \
}while(0U)
#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
/**
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
* @retval None
*/
#define __HAL_AFIO_REMAP_CAN1_3() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3); \
}while(0U)
#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
#endif
/**
@ -365,7 +331,7 @@
* @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
* @retval None
*/
#define __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
/**
* @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
@ -375,7 +341,7 @@
* @note DISABLE: No remapping of PD0 and PD1
* @retval None
*/
#define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
/**
@ -384,7 +350,7 @@
* @note This function is available only in high density value line devices.
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
/**
* @brief Disable the remapping of TIM5CH4.
@ -392,7 +358,7 @@
* @note This function is available only in high density value line devices.
* @retval None
*/
#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
#endif
#if defined(AFIO_MAPR_ETH_REMAP)
@ -402,7 +368,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_REMAP_ETH_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
/**
* @brief Disable the remapping of Ethernet MAC connections with the PHY.
@ -410,7 +376,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
#endif
#if defined(AFIO_MAPR_CAN2_REMAP)
@ -421,7 +387,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_REMAP_CAN2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
/**
* @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
@ -429,7 +395,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
#endif
#if defined(AFIO_MAPR_MII_RMII_SEL)
@ -439,7 +405,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
/**
* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
@ -447,7 +413,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_ETH_MII() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
#endif
/**
@ -455,28 +421,28 @@
* @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
/**
* @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
* @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
/**
* @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
* @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
/**
* @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
* @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
@ -485,14 +451,14 @@
* @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
/**
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
* @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
#endif
#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
@ -502,14 +468,14 @@
* @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
/**
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
* @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
* @retval None
*/
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
#endif
/**
@ -517,36 +483,29 @@
* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
* @retval None
*/
#define __HAL_AFIO_REMAP_SWJ_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); \
}while(0U)
#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
/**
* @brief Enable the Serial wire JTAG configuration
* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
* @retval None
*/
#define __HAL_AFIO_REMAP_SWJ_NONJTRST() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); \
}while(0U)
#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
/**
* @brief Enable the Serial wire JTAG configuration
* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
* @retval None
*/
#define __HAL_AFIO_REMAP_SWJ_NOJTAG() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); \
}while(0U)
#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
/**
* @brief Disable the Serial wire JTAG configuration
* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
* @retval None
*/
#define __HAL_AFIO_REMAP_SWJ_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); \
}while(0U)
#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
#if defined(AFIO_MAPR_SPI3_REMAP)
@ -556,7 +515,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_REMAP_SPI3_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
/**
* @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
@ -564,7 +523,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
#endif
#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
@ -575,7 +534,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
/**
* @brief Control of TIM2_ITR1 internal mapping.
@ -583,7 +542,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
#endif
#if defined(AFIO_MAPR_PTP_PPS_REMAP)
@ -594,7 +553,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
/**
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
@ -602,7 +561,7 @@
* @note This bit is available only in connectivity line devices and is reserved otherwise.
* @retval None
*/
#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
#endif
#if defined(AFIO_MAPR2_TIM9_REMAP)
@ -883,6 +842,31 @@
((__GPIOx__) == (GPIOF))? 5U :6U)
#endif
#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg |= REMAP_PIN; \
AFIO->MAPR = tmpreg; \
}while(0U)
#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg &= ~REMAP_PIN; \
AFIO->MAPR = tmpreg; \
}while(0U)
#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
tmpreg &= ~REMAP_PIN_MASK; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg |= REMAP_PIN; \
AFIO->MAPR = tmpreg; \
}while(0U)
#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \
tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
tmpreg |= DBGAFR_SWJCFG; \
AFIO->MAPR = tmpreg; \
}while(0U)
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_hcd.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_hcd.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention

104
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_i2c.c
* @author MCD Application Team
* @version V1.1.1
* @date 12-May-2017
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@ -406,6 +404,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
{
return HAL_ERROR;
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
@ -583,7 +587,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@ -715,7 +719,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@ -1181,7 +1185,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
hi2c->XferSize--;
hi2c->XferCount--;
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
@ -1231,7 +1235,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -1308,7 +1312,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -1390,7 +1394,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
@ -1462,7 +1466,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* Generate Start */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED
else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED patch
{
/* Generate ReStart */
hi2c->Instance->CR1 |= I2C_CR1_START;
@ -1493,7 +1497,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
@ -1564,7 +1568,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
/* Generate Start */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) // MBED
else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) // MBED patch
{
/* Enable Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
@ -1955,7 +1959,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -2073,7 +2077,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@ -2192,7 +2196,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
@ -2429,7 +2433,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2562,7 +2567,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2827,7 +2833,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -2912,7 +2919,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -3002,7 +3010,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -3122,7 +3131,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@ -3283,7 +3293,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
* @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
@ -4003,22 +4014,35 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
}
else if((tmp == 2U) || (tmp == 3U))
{
// MBED patch if(hi2c->XferOptions != I2C_NEXT_FRAME)
// MBED patch {
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Enable Pos */
hi2c->Instance->CR1 |= I2C_CR1_POS;
// MBED patch }
// MBED patch else
// MBED patch {
// MBED patch /* Enable Acknowledge */
// MBED patch hi2c->Instance->CR1 |= I2C_CR1_ACK;
// MBED patch }
/* Disable BUF interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
}
else
{
// MBED patch if(hi2c->XferOptions != I2C_NEXT_FRAME)
// MBED patch {
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
if(hi2c->XferOptions == I2C_NEXT_FRAME)
// MBED patch }
// MBED patch else
if(hi2c->XferOptions == I2C_NEXT_FRAME) // MBED patch
{
// MBED patch /* Enable Acknowledge */
// MBED patch hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Enable Pos */
hi2c->Instance->CR1 |= I2C_CR1_POS;
}
@ -4076,17 +4100,28 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Prepare next transfer or stop current transfer */
if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
{
// MBED patch if(CurrentXferOptions != I2C_NEXT_FRAME)
// MBED patch {
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
// MBED patch }
// MBED patch else
if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) // MBED patch
{
/* Generate ReStart */
hi2c->Instance->CR1 |= I2C_CR1_START;
// MBED patch /* Enable Acknowledge */
// MBED patch hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Generate ReStart */ // MBED patch
hi2c->Instance->CR1 |= I2C_CR1_START; // MBED patch
}
/* Disable EVT and ERR interrupt */
// MBED patch __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
}
else
{
/* Disable EVT and ERR interrupt */
// MBED patch __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
}
@ -4099,8 +4134,8 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
/* Disable EVT and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
/* Disable EVT and ERR interrupt */ // MBED patch
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); // MBED patch
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
@ -4751,7 +4786,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
@ -4827,7 +4862,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* in datasheet must be shifted to the left before calling the interface
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
@ -4933,7 +4968,8 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@ -5023,7 +5059,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@ -5558,4 +5595,3 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

10
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_i2c.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@ -564,6 +562,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
* @{
*/
#define I2C_FLAG_MASK 0x0000FFFFU
#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
/**
* @}
*/
@ -573,10 +573,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
* @{
*/
#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_i2s.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_i2s.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_irda.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_irda.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention

8
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@ -166,7 +164,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
uint32_t tickstart;
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
if (hiwdg == NULL)
{
return HAL_ERROR;
}
@ -190,9 +188,9 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while(hiwdg->Instance->SR != RESET)
while (hiwdg->Instance->SR != RESET)
{
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}

6
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
@ -40,7 +38,7 @@
#define __STM32F1xx_HAL_IWDG_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -81,7 +79,7 @@ typedef struct
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
}IWDG_HandleTypeDef;
} IWDG_HandleTypeDef;
/**
* @}

4
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_mmc.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief MMC card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
@ -1312,7 +1310,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd,
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check if the card command class supports erase command */
if((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE == 0U)
if(((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_mmc.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of MMC HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_nand.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_nand.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_nor.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_nor.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pccard.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pccard.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention

6
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pcd.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -1152,7 +1150,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USB_OTG_EPTypeDef *ep = NULL;
uint32_t len;
uint32_t len; // MBED patch
uint32_t len32b = 0U;
uint32_t fifoemptymsk = 0U;
@ -1185,7 +1183,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
ep->xfer_count += len;
}
if (ep->xfer_count >= ep->xfer_len)
if (ep->xfer_count >= ep->xfer_len) // MBED patch
{
fifoemptymsk = 0x01U << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pcd.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of Extended PCD HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pwr.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_pwr.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

144
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rcc.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -207,42 +205,144 @@ static void RCC_Delay(uint32_t mdelay);
* @brief Resets the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE and PLL OFF
* - HSE, PLL, PLL2 and PLL3 are OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS and MCO1 OFF
* - All interrupts disabled
* - All flags are cleared
* @note This function does not modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval None
* @retval HAL_StatusTypeDef
*/
void HAL_RCC_DeInit(void)
HAL_StatusTypeDef HAL_RCC_DeInit(void)
{
/* Switch SYSCLK to HSI */
CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
uint32_t tickstart;
/* Reset HSEON, CSSON, & PLLON bits */
CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
/* Set HSION bit */
SET_BIT(RCC->CR, RCC_CR_HSION);
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set HSITRIM bits to the reset value */
MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
#if defined(RCC_CFGR2_SUPPORT)
/* Reset CFGR2 register */
CLEAR_REG(RCC->CFGR2);
/* Get Start Tick */
tickstart = HAL_GetTick();
#endif /* RCC_CFGR2_SUPPORT */
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Wait till clock switch is ready */
while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
return HAL_ERROR;
}
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Second step is to clear PLLON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Ensure to reset PLLSRC and PLLMUL bits */
CLEAR_REG(RCC->CFGR);
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Reset HSEON & CSSON bits */
CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
#if defined(RCC_PLL2_SUPPORT)
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Clear PLL2ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
/* Wait till PLL2 is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)
{
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Clear PLL3ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
/* Wait till PLL3 is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)
{
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
#endif /* RCC_PLLI2S_SUPPORT */
#if defined(RCC_CFGR2_PREDIV1)
/* Reset CFGR2 register */
CLEAR_REG(RCC->CFGR2);
#endif /* RCC_CFGR2_PREDIV1 */
/* Reset all CSR flags */
SET_BIT(RCC->CSR, RCC_CSR_RMVF);
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
return HAL_OK;
}
/**
@ -1027,12 +1127,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
}
else
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
}
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
@ -1043,7 +1143,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else

4
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rcc.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@ -1170,7 +1168,7 @@ typedef struct
*/
/* Initialization and de-initialization functions ******************************/
void HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rtc.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rtc.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_sd.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_sd.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of SD HAL module.
******************************************************************************
* @attention

218
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_smartcard.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@ -166,7 +164,7 @@
*/
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
@ -249,7 +247,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
{
/* Check the SMARTCARD handle allocation */
if(hsc == NULL)
if (hsc == NULL)
{
return HAL_ERROR;
}
@ -258,7 +256,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
if (hsc->gState == HAL_SMARTCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsc->Lock = HAL_UNLOCKED;
@ -273,7 +271,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
/* Set the Guard Time */
MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime) << 8U));
/* Set the Smartcard Communication parameters */
SMARTCARD_SetConfig(hsc);
@ -301,8 +299,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
/* Initialize the SMARTCARD state*/
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->gState= HAL_SMARTCARD_STATE_READY;
hsc->RxState= HAL_SMARTCARD_STATE_READY;
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
@ -316,7 +314,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Check the SMARTCARD handle allocation */
if(hsc == NULL)
if (hsc == NULL)
{
return HAL_ERROR;
}
@ -437,12 +435,11 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
uint32_t tickstart = 0U;
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
if (hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -458,19 +455,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0U)
while (hsc->TxXferCount > 0U)
{
hsc->TxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
pData +=1U;
hsc->Instance->DR = *(uint8_t *) pData;
pData += 1U;
}
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@ -502,9 +498,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
{
uint32_t tickstart = 0U;
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
if (hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -522,15 +518,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
hsc->RxXferCount = Size;
/* Check the remain data to be received */
while(hsc->RxXferCount > 0U)
while (hsc->RxXferCount > 0U)
{
hsc->RxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
if (SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
*pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
pData +=1U;
*(uint8_t *) pData = (uint8_t)hsc->Instance->DR;
pData += 1U;
}
/* At end of Rx process, restore hsc->RxState to Ready */
@ -558,9 +554,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
if (hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -605,9 +601,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
if (hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -626,7 +622,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
__HAL_UNLOCK(hsc);
/* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
@ -652,9 +648,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
uint32_t *tmp;
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
if (hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -679,8 +675,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
hsc->hdmatx->XferAbortCallback = NULL;
/* Enable the SMARTCARD transmit DMA Channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
tmp = (uint32_t *)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t *)tmp, (uint32_t)&hsc->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
@ -714,9 +710,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
uint32_t *tmp;
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
if (hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -740,8 +736,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
hsc->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA Channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
tmp = (uint32_t *)&pData;
HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t *)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
@ -786,12 +782,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
if (hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@ -802,12 +798,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
}
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
if (hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@ -849,12 +845,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
if (hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@ -892,12 +888,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
if (hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@ -941,11 +937,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if(hsc->hdmatx != NULL)
if (hsc->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
}
@ -955,11 +951,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
}
}
/* DMA Rx Handle is valid */
if(hsc->hdmarx != NULL)
if (hsc->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
}
@ -970,19 +966,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
}
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at SMARTCARD level */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
if(hsc->hdmatx != NULL)
if (hsc->hdmatx != NULL)
{
/* SMARTCARD Tx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
if (HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
{
hsc->hdmatx->XferAbortCallback = NULL;
}
@ -994,18 +990,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
}
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
if(hsc->hdmarx != NULL)
if (hsc->hdmarx != NULL)
{
/* SMARTCARD Rx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
if (HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
hsc->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
@ -1018,7 +1014,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if(AbortCplt == 0x01U)
if (AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
hsc->TxXferCount = 0x00U;
@ -1057,19 +1053,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
if (hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
if (HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
{
/* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
@ -1123,19 +1119,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
if (hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
if (HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
/* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
@ -1184,10 +1180,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
if(errorflags == RESET)
if (errorflags == RESET)
{
/* SMARTCARD in mode Receiver -------------------------------------------------*/
if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
SMARTCARD_Receive_IT(hsc);
return;
@ -1195,37 +1191,37 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
}
/* If some errors occur */
if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
/* SMARTCARD parity error interrupt occurred ---------------------------*/
if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
if (((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
}
/* SMARTCARD noise error interrupt occurred ----------------------------*/
if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
if (((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
}
/* SMARTCARD frame error interrupt occurred ----------------------------*/
if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
if (((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
}
/* SMARTCARD Over-Run interrupt occurred -------------------------------*/
if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
if (((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
}
/* Call SMARTCARD Error Call back function if need be ------------------*/
if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
if (hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
{
/* SMARTCARD in mode Receiver ----------------------------------------*/
if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
SMARTCARD_Receive_IT(hsc);
}
@ -1233,7 +1229,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
if (((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
{
/* Blocking error : transfer is aborted
Set the SMARTCARD state ready to be able to start again the process,
@ -1241,17 +1237,17 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
SMARTCARD_EndRxTransfer(hsc);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel */
if(hsc->hdmarx != NULL)
if (hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
if (HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
@ -1281,14 +1277,14 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
} /* End if some error occurs */
/* SMARTCARD in mode Transmitter -------------------------------------------*/
if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
if (((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
SMARTCARD_Transmit_IT(hsc);
return;
}
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
if (((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
SMARTCARD_EndTransmit_IT(hsc);
return;
@ -1345,7 +1341,7 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
@ -1360,7 +1356,7 @@ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
@ -1375,7 +1371,7 @@ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hs
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
@ -1412,7 +1408,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t temp1= 0x00U, temp2 = 0x00U;
uint32_t temp1 = 0x00U, temp2 = 0x00U;
temp1 = hsc->gState;
temp2 = hsc->RxState;
@ -1442,7 +1438,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->TxXferCount = 0U;
@ -1462,7 +1458,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->RxXferCount = 0U;
@ -1489,21 +1485,21 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->RxXferCount = 0U;
hsc->TxXferCount = 0U;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
/* Stop SMARTCARD DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
if ((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
{
SMARTCARD_EndTxTransfer(hsc);
}
/* Stop SMARTCARD DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
if ((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
{
SMARTCARD_EndRxTransfer(hsc);
}
@ -1523,19 +1519,19 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
while ((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
hsc->gState= HAL_SMARTCARD_STATE_READY;
hsc->RxState= HAL_SMARTCARD_STATE_READY;
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@ -1587,7 +1583,7 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
*/
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->RxXferCount = 0x00U;
hsc->TxXferCount = 0x00U;
@ -1604,14 +1600,14 @@ static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hsc->hdmarx != NULL)
if (hsc->hdmarx != NULL)
{
if(hsc->hdmarx->XferAbortCallback != NULL)
if (hsc->hdmarx->XferAbortCallback != NULL)
{
return;
}
@ -1642,14 +1638,14 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hsc->hdmatx != NULL)
if (hsc->hdmatx != NULL)
{
if(hsc->hdmatx->XferAbortCallback != NULL)
if (hsc->hdmatx->XferAbortCallback != NULL)
{
return;
}
@ -1680,7 +1676,7 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->TxXferCount = 0x00U;
@ -1701,7 +1697,7 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
SMARTCARD_HandleTypeDef *hsc = (SMARTCARD_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hsc->RxXferCount = 0x00U;
@ -1720,16 +1716,13 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
*/
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint16_t* tmp;
/* Check that a Tx process is ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
if (hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
tmp = (uint16_t*) hsc->pTxBuffPtr;
hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
hsc->Instance->DR = *(uint8_t *) hsc->pTxBuffPtr;
hsc->pTxBuffPtr += 1U;
if(--hsc->TxXferCount == 0U)
if (--hsc->TxXferCount == 0U)
{
/* Disable the SMARTCARD Transmit data register empty Interrupt */
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
@ -1776,16 +1769,13 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar
*/
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint16_t* tmp;
/* Check that a Rx process is ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
if (hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
tmp = (uint16_t*) hsc->pRxBuffPtr;
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
*(uint8_t *) hsc->pRxBuffPtr = (uint8_t)hsc->Instance->DR;
hsc->pRxBuffPtr += 1U;
if(--hsc->RxXferCount == 0U)
if (--hsc->RxXferCount == 0U)
{
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
@ -1847,7 +1837,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
/* Set LBCL bit according to hsc->Init.CLKLastBit value */
/* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
hsc->Init.CLKPhase | hsc->Init.CLKLastBit | hsc->Init.StopBits);
/* Write to USART CR2 */
WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
@ -1884,7 +1874,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
/*-------------------------- USART BRR Configuration -----------------------*/
if(hsc->Instance == USART1)
if (hsc->Instance == USART1)
{
hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
}

10
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_smartcard.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@ -40,7 +38,7 @@
#define __STM32F1xx_HAL_SMARTCARD_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -104,7 +102,7 @@ typedef struct
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state
This parameter can be a value of @ref SMARTCARD_NACK_State */
}SMARTCARD_InitTypeDef;
} SMARTCARD_InitTypeDef;
/**
* @brief HAL SMARTCARD State structures definition
@ -164,7 +162,7 @@ typedef enum
Value is allowed for gState only */
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
}HAL_SMARTCARD_StateTypeDef;
} HAL_SMARTCARD_StateTypeDef;
/**
* @brief SMARTCARD handle Structure definition
@ -201,7 +199,7 @@ typedef struct
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
}SMARTCARD_HandleTypeDef;
} SMARTCARD_HandleTypeDef;
/**
* @}

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_spi.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_spi.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_spi_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Extended SPI HAL module driver.
*
* This file provides firmware functions to manage the following

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_sram.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_sram.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_tim.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief TIM HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_tim.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention

96
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_tim_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
@ -494,7 +492,6 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -524,7 +521,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -554,7 +550,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -585,13 +580,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
}
break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
@ -621,7 +609,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -654,13 +641,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
@ -694,7 +674,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData : The source Buffer address.
* @param Length : The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@ -754,7 +733,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
break;
case TIM_CHANNEL_3:
{
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
@ -769,22 +748,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
}
break;
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
@ -811,7 +774,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -842,13 +804,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
@ -911,7 +866,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -940,7 +894,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -970,7 +923,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -1001,13 +953,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
}
break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
@ -1037,10 +982,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpccer = 0U;
@ -1070,13 +1014,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
@ -1110,7 +1047,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData : The source Buffer address.
* @param Length : The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@ -1185,22 +1121,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
}
break;
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
@ -1227,7 +1147,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -1258,13 +1177,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
@ -1318,7 +1230,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@ -1390,7 +1302,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/* Return function status */
return HAL_OK;
}
}
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_uart.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_uart.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_usart.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_usart.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention

10
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_wwdg.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@ -168,7 +166,7 @@
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
if(hwwdg == NULL)
if (hwwdg == NULL)
{
return HAL_ERROR;
}
@ -264,10 +262,10 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
/* Check if Early Wakeup Interrupt is enable */
if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
/* Check if WWDG Early Wakeup Interrupt occurred */
if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Clear the WWDG Early Wakeup flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
@ -284,7 +282,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
* the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);

10
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_wwdg.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
@ -40,7 +38,7 @@
#define __STM32F1xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -76,7 +74,7 @@ typedef struct
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
}WWDG_InitTypeDef;
} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
@ -87,7 +85,7 @@ typedef struct
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
}WWDG_HandleTypeDef;
} WWDG_HandleTypeDef;
/**
* @}
*/
@ -257,7 +255,7 @@ void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_adc.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief ADC LL module driver
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_adc.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of ADC LL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_bus.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of BUS LL module.
@verbatim

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_cortex.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_crc.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief CRC LL module driver.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_crc.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of CRC LL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_dac.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief DAC LL module driver
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_dac.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of DAC LL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_dma.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief DMA LL module driver.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_dma.h
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief Header file of DMA LL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_exti.c
* @author MCD Application Team
* @version V1.1.0
* @date 14-April-2017
* @brief EXTI LL module driver.
******************************************************************************
* @attention

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