diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_clock.c
index abbadf5c65..5258fcedd3 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_clock.c
@@ -17,9 +17,9 @@
 /**
   * This file configures the system clock as follows:
   *-------------------------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC  / CLOCK_SOURCE_USB=1 | 3- PLL_HSI / CLOCK_SOURCE_USB=1
+  * System clock source                | 1- PLL_HSE_EXTC  / DEVICE_USBDEVICE   | 3- PLL_HSI / DEVICE_USBDEVICE
   *                                    | (external 8 MHz clock)                | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL / CLOCK_SOURCE_USB=1  |
+  *                                    | 2- PLL_HSE_XTAL / DEVICE_USBDEVICE    |
   *                                    | (external 8 MHz xtal)                 |
   *-------------------------------------------------------------------------------------------
   * SYSCLK(MHz)                        | 72 / 72                               | 64 / 48
@@ -30,8 +30,6 @@
   *-------------------------------------------------------------------------------------------
   * APB2CLK (MHz)                      | 72 / 72                               | 64 / 48
   *-------------------------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO / YES                              | NO / YES
-  *-------------------------------------------------------------------------------------------
   */
 
 #include "stm32f1xx.h"
@@ -164,9 +162,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 {
     RCC_ClkInitTypeDef RCC_ClkInitStruct;
     RCC_OscInitTypeDef RCC_OscInitStruct;
-#if (CLOCK_SOURCE_USB)
+#if (DEVICE_USBDEVICE)
     RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;
-#endif /* CLOCK_SOURCE_USB */
+#endif /* DEVICE_USBDEVICE */
 
     /* Enable HSE oscillator and activate PLL with HSE as source */
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
@@ -193,12 +191,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
         return 0; // FAIL
     }
 
-#if (CLOCK_SOURCE_USB)
+#if (DEVICE_USBDEVICE)
     /* USB clock selection */
     RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
     RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
     HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);
-#endif /* CLOCK_SOURCE_USB */
+#endif /* DEVICE_USBDEVICE */
 
     /* Output clock on MCO1 pin(PA8) for debugging purpose */
     //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
@@ -215,9 +213,9 @@ uint8_t SetSysClock_PLL_HSI(void)
 {
     RCC_ClkInitTypeDef RCC_ClkInitStruct;
     RCC_OscInitTypeDef RCC_OscInitStruct;
-#if (CLOCK_SOURCE_USB)
+#if (DEVICE_USBDEVICE)
     RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;
-#endif /* CLOCK_SOURCE_USB */
+#endif /* DEVICE_USBDEVICE */
 
     /* Enable HSI oscillator and activate PLL with HSI as source */
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
@@ -226,21 +224,21 @@ uint8_t SetSysClock_PLL_HSI(void)
     RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
-#if (CLOCK_SOURCE_USB)
+#if (DEVICE_USBDEVICE)
     RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12; // 48 MHz (8 MHz/2 * 12)
-#else /* CLOCK_SOURCE_USB */
+#else /* DEVICE_USBDEVICE */
     RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-#endif /* CLOCK_SOURCE_USB */
+#endif /* DEVICE_USBDEVICE */
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         return 0; // FAIL
     }
 
-#if (CLOCK_SOURCE_USB)
+#if (DEVICE_USBDEVICE)
     /* USB clock selection */
     RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
     RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
     HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);
-#endif /* CLOCK_SOURCE_USB */
+#endif /* DEVICE_USBDEVICE */
 
     /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
     RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
diff --git a/targets/targets.json b/targets/targets.json
index d170d22244..076d19296a 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2173,11 +2173,6 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
-            },
-            "clock_source_usb": {
-                "help": "In case of HSI clock source, to get 48 Mhz USB, SYSCLK has to be reduced from 64 to 48 MHz (set 0 for the max SYSCLK value)",
-                "value": "0",
-                "macro_name": "CLOCK_SOURCE_USB"
             }
         },
         "detect_code": ["0700"],