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Squashed 'features/nanostack/FEATURE_NANOSTACK/coap-service/' changes from e125164..d65b6b0 

d65b6b0 Update unittests for nsdynmemlib API change (#71)
bc69b8b Disable CoAP duplicate message detection (#69)
ccb65f8 Change year 2017 to copyright (#68)
76490a7 Add option to join COAP multicast group (#67)
381d910 Register to multicast groups (#66)
dce323c Add transaction delete to CoAP service (#65)
feea33e Add option to select used socket interface (#63)
5a5c0f9 Merge pull request #62 from ARMmbed/coap_separation
0d26c00 Modifying file headers and Makefile  to adapt from libcoap to mbed-coap
d323c3a Fixing unit tests based on new coap library
d1a3d25 Modifying Makefile and source file based on new coap library

git-subtree-dir: features/nanostack/FEATURE_NANOSTACK/coap-service
git-subtree-split: d65b6b0eb890be93f667debe8da83aa498021ccf
pull/4960/head
Arto Kinnunen 2017-08-23 15:09:48 +03:00
parent 7dc2dc8c66
commit 9d5a9f5a29
10541 changed files with 362 additions and 5034500 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

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*.c text
*.cpp text
*.h text
*.s text
*.sct text
*.ld text
*.txt text
*.xml text
*.py text
*.md text
*.json text
*.tmpl text
*.dia binary
*.elf binary
*.bin binary

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Note: This is just a template, so feel free to use/remove the unnecessary things
### Description
- Type: Bug | Enhancement | Question
- Related issue: `#abc`
- Priority: Blocker | Major | Minor
---------------------------------------------------------------
## Bug
**Target**
K64F|??
**Toolchain:**
GCC_ARM|ARM|IAR
**Toolchain version:**
**mbed-cli version:**
(`mbed --version`)
**meed-os sha:**
(`git log -n1 --oneline`)
**DAPLink version:**
**Expected behavior**
**Actual behavior**
**Steps to reproduce**
----------------------------------------------------------------
## Enhancement
**Reason to enhance or problem with existing solution**
**Suggested enhancement**
**Pros**
**Cons**
-----------------------------------------------------------------
## Question
**How to?**

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Notes:
* Pull requests will not be accepted until the submitter has agreed to the [contributer agreement](https://github.com/ARMmbed/mbed-os/blob/master/CONTRIBUTING.md).
* This is just a template, so feel free to use/remove the unnecessary things
## Description
A few sentences describing the overall goals of the pull request's commits.
## Status
**READY/IN DEVELOPMENT/HOLD**
## Migrations
If this PR changes any APIs or behaviors, give a short description of what *API users* should do when this PR is merged.
YES | NO
## Related PRs
List related PRs against other branches:
branch | PR
------ | ------
other_pr_production | [link]()
other_pr_master | [link]()
## Todos
- [ ] Tests
- [ ] Documentation
## Deploy notes
Notes regarding the deployment of this PR. These should note any
required changes in the build environment, tools, compilers, etc.
## Steps to test or reproduce
Outline the steps to test or reproduce the PR here.

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@ -1,77 +1,10 @@
*.py[cod]
# Distribution dir
dist
# MANIFEST file
MANIFEST
# Private settings
mbed_settings.py
# Default Build Directory
.build/
BUILD/
.mbed
venv/
# Eclipse Project Files
.cproject
.project
.pydevproject
# C extensions
*.so
# Packages
*.egg
*.egg-info
dist
build
eggs
parts
bin
var
sdist
develop-eggs
.installed.cfg
# Installer logs
pip-log.txt
# Unit test / coverage reports
.coverage
.tox
nosetests.xml
# Translations
*.mo
# Mr Developer
.mr.developer.cfg
output.txt
uVision Project/
# Sublime Text Project Files
*.sublime*
*.bak
debug.log
# Ignore OS X Desktop Services Store files
.DS_Store
# Orig diff files
*.orig
# PyCharm
*.idea
# Cscope
cscope.*
# vim swap files
*.swp
*~
*.a
*.lib
output
lcov
coverage
.yotta.json
build/
yotta_modules/
yotta_targets/
upload.tar.gz

0
features/FEATURE_COMMON_PAL/nanostack-libservice/.mbedignore → .mbedignore
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[Format]
max-line-length=80

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.travis.yml
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python:
- "2.7"
script:
- make -C events/equeue test clean
- PYTHONPATH=. python tools/test/config_test/config_test.py
- PYTHONPATH=. python tools/test/build_api/build_api_test.py
- PYTHONPATH=. python tools/test/targets/target_test.py
- python tools/test/pylint.py
- py.test tools/test/toolchains/api.py
- python tools/test/memap/memap_test.py
- python tools/project.py -S
- python tools/build_travis.py
before_install:
- sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded
- sudo apt-get update -qq
- sudo apt-get install -qq gcc-arm-none-eabi --force-yes
# Print versions we use
- arm-none-eabi-gcc --version
- python --version
install:
- sudo pip install -r requirements.txt
- sudo pip install pytest
- sudo pip install pylint
- sudo pip install hypothesis
- sudo pip install mock

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# Description
This document is cheat sheet for everyone who wants to contribute to [ARMmbed/mbed-os](https://github.com/ARMmbed/mbed-os) GitHub repository at GitHub.
All changes in code base should originate from GitHub Issues and take advantage of existing GitHub flows. Goal is to attract contributors and allow them contribute to code and documentation at the same time.
Guidelines from this document are created to help new and existing contributors understand process workflow and align to project rules before pull request is submitted. It explains how a participant should do things like format code, test fixes, and submit patches.
## Where to get more information?
You can for example read more in our ```docs``` section in [ARMmbed/mbed-os/doc](https://github.com/ARMmbed/mbed-os/tree/master/docs) directory.
# How to contribute
We really appreciate your contributions! We are Open Source project and we need your help. We want to keep it as easy as possible to contribute changes that get things working in your environment. There are a few guidelines that we need contributors to follow so that we can have a chance of keeping on top of things.
Before a pull request will be merged, the [mbed Contributor Agreement](http://developer.mbed.org/contributor_agreement/) must be signed.
You can pick up existing [mbed-os GitHub Issue](https://github.com/ARMmbed/mbed-os/issues) and solve it or implement new feature you find important, attractive or just necessary. We will review your proposal via pull request mechanism, give you comments and merge your changes if we decide your contribution satisfy criteria such as quality.
# Enhancements vs Bugs
Enhancements are:
* New features implementation.
* Code refactoring.
* Coding rules, coding styles improvements.
* Code comments improvement.
* Documentation work.
Bugs are:
* Issues rose internally or externally by [ARMmbed/mbed-os](https://github.com/ARMmbed/mbed-os) users.
* Internally (within mbed team) created issues from Continuous Integration pipeline and build servers.
* Issues detected using automation tools such as compilers, sanitizers, static code analysis tools etc.
# Gate Keeper role
Gate Keeper is a person responsible for GitHub process workflow execution and is responsible for repository / project code base. Gate Keeper is also responsible for code (pull request) quality stamp and approves or rejects code changes in project’s code base.
Gate Keepers will review your pull request code, give you comments in pull request comment section and in the end if everything goes well merge your pull request to one of our branches (most probably default ```master``` branch).
Please be patient, digest Gate Keeper's feedback and respond promptly :)
# mbed SDK porting
* For more information regarding mbed SDK porting please refer to [mbed SDK porting](http://developer.mbed.org/handbook/mbed-SDK-porting) handbook.
* Before starting the mbed SDK porting, you might want to familiarize with the [mbed SDK library internals](http://developer.mbed.org/handbook/mbed-library-internals) first.
# Glossary
* Gate Keeper – persons responsible for overall code-base quality of [ARMmbed/mbed-os](https://github.com/ARMmbed/mbed-os) project.
* Enhancement – New feature deployment, code refactoring actions or existing code improvements.
* Bugfix – Issues originated from GitHub Issues pool, raised internally within mbed classic team or issues from automated code validators like linters, static code analysis tools etc.
* Mbed classic – mbed SDK 2.0 located in GitHub at [ARMmbed/mbed-os](https://github.com/ARMmbed/mbed-os).

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# mbed OS code base
This is the code documentation for mbed OS.
For more information, please see:
* [The mbed OS API References](https://docs.mbed.com/docs/mbed-os-api-reference/)
* [The mbed OS Handbook](https://docs.mbed.com/docs/mbed-os-handbook/)

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// List of targets to compile
def targets = [
//"LPC1768",
//"NUCLEO_F401RE",
//"NRF51822",
"K64F"
]
// Map toolchains to compiler labels on Jenkins
def toolchains = [
ARM: "armcc",
//IAR: "iar_arm",
GCC_ARM: "arm-none-eabi-gcc"
]
// mbed.getCurrentBranch returns either local branch name or reference to pull request
def currentBranch = mbed.getCurrentBranch()
// Create a map of predefined build steps
def parallelSteps = mbed.createParalleSteps("mbed-os", targets, toolchains)
// Run build steps parallel, map as paramater
mbed.compile(parallelSteps)
def testApps = [
"mbed-os-cliapp",
"mbed-client-testapp"
]
// buildTestApps accepts array of test application names and a mbed-os branch or PR reference as parameters
mbed.buildTestApps(testApps, "${currentBranch}")

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@ -1,165 +1,2 @@
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8. Limitation of Liability.
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5
features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile → Makefile
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@ -24,8 +24,9 @@ override CFLAGS += -I$(SERVLIB_DIR)/libService/
NANOSTACK_DIR := ../nanostack
override CFLAGS += -I$(NANOSTACK_DIR)/nanostack/
NSDLC_DIR := ../nsdl-c
override CFLAGS += -I$(NSDLC_DIR)/nsdl-c
COAP_DIR := ../mbed-coap
override CFLAGS += -I$(COAP_DIR)/
EVENTLOOP_DIR := ../event-loop
override CFLAGS += -I$(EVENTLOOP_DIR)/nanostack-event-loop/

0
features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile.test → Makefile.test
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README.md
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@ -1,22 +0,0 @@
# ARM mbed OS
mbed OS is an open-source embedded operating system designed specifically for the "things" in the Internet of Things (IoT). It includes all the features you need to develop a connected product based on an ARM Cortex-M microcontroller.
mbed OS accelerates the process of creating a connected product by providing a platform operating system that includes robust security foundations, standards based communication capabilities, built-in cloud management services, and drivers for sensors, I/O devices and connectivity. mbed OS is built as a modular, configurable software stack so that you can readily customize it to the device you're developing for, and reduce memory requirements by excluding unnecessary software components.
## Current release
The current release, along with a selection of previous versions are detailed here:
[Release Notes](https://docs.mbed.com/docs/mbed-os-release-notes/en/latest/)
## Getting Started for Developers
Please note that you will require [mbed CLI](https://github.com/ARMmbed/mbed-cli) to build mbed OS. For more details, please read the getting started guide for developers using mbed OS in applications:
- [Getting Started](https://docs.mbed.com/docs/mbed-os-handbook/en/latest/)
## Getting Started for Contributors
We have a getting started guide for contributors working on mbed OS:
- Have a look in the docs directory

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TESTS/events/queue/main.cpp
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#include "mbed_events.h"
#include "mbed.h"
#include "rtos.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
// flag for called
volatile bool touched = false;
// static functions
void func5(int a0, int a1, int a2, int a3, int a4) {
touched = true;
TEST_ASSERT_EQUAL(a0 | a1 | a2 | a3 | a4, 0x1f);
}
void func4(int a0, int a1, int a2, int a3) {
touched = true;
TEST_ASSERT_EQUAL(a0 | a1 | a2 | a3, 0xf);
}
void func3(int a0, int a1, int a2) {
touched = true;
TEST_ASSERT_EQUAL(a0 | a1 | a2, 0x7);
}
void func2(int a0, int a1) {
touched = true;
TEST_ASSERT_EQUAL(a0 | a1, 0x3);
}
void func1(int a0) {
touched = true;
TEST_ASSERT_EQUAL(a0, 0x1);
}
void func0() {
touched = true;
}
#define SIMPLE_POSTS_TEST(i, ...) \
void simple_posts_test##i() { \
EventQueue queue; \
\
touched = false; \
queue.call(func##i,##__VA_ARGS__); \
queue.dispatch(0); \
TEST_ASSERT(touched); \
\
touched = false; \
queue.call_in(1, func##i,##__VA_ARGS__); \
queue.dispatch(2); \
TEST_ASSERT(touched); \
\
touched = false; \
queue.call_every(1, func##i,##__VA_ARGS__); \
queue.dispatch(2); \
TEST_ASSERT(touched); \
}
SIMPLE_POSTS_TEST(5, 0x01, 0x02, 0x04, 0x08, 0x010)
SIMPLE_POSTS_TEST(4, 0x01, 0x02, 0x04, 0x08)
SIMPLE_POSTS_TEST(3, 0x01, 0x02, 0x04)
SIMPLE_POSTS_TEST(2, 0x01, 0x02)
SIMPLE_POSTS_TEST(1, 0x01)
SIMPLE_POSTS_TEST(0)
void time_func(Timer *t, int ms) {
TEST_ASSERT_INT_WITHIN(2, ms, t->read_ms());
t->reset();
}
template <int N>
void call_in_test() {
Timer tickers[N];
EventQueue queue;
for (int i = 0; i < N; i++) {
tickers[i].start();
queue.call_in((i+1)*100, time_func, &tickers[i], (i+1)*100);
}
queue.dispatch(N*100);
}
template <int N>
void call_every_test() {
Timer tickers[N];
EventQueue queue;
for (int i = 0; i < N; i++) {
tickers[i].start();
queue.call_every((i+1)*100, time_func, &tickers[i], (i+1)*100);
}
queue.dispatch(N*100);
}
void allocate_failure_test() {
EventQueue queue;
int id;
for (int i = 0; i < 100; i++) {
id = queue.call((void (*)())0);
}
TEST_ASSERT(!id);
}
void no() {
TEST_ASSERT(false);
}
template <int N>
void cancel_test1() {
EventQueue queue;
int ids[N];
for (int i = 0; i < N; i++) {
ids[i] = queue.call_in(1000, no);
}
for (int i = N-1; i >= 0; i--) {
queue.cancel(ids[i]);
}
queue.dispatch(0);
}
// Testing the dynamic arguments to the event class
unsigned counter = 0;
void count5(unsigned a0, unsigned a1, unsigned a2, unsigned a3, unsigned a5) {
counter += a0 + a1 + a2 + a3 + a5;
}
void count4(unsigned a0, unsigned a1, unsigned a2, unsigned a3) {
counter += a0 + a1 + a2 + a3;
}
void count3(unsigned a0, unsigned a1, unsigned a2) {
counter += a0 + a1 + a2;
}
void count2(unsigned a0, unsigned a1) {
counter += a0 + a1;
}
void count1(unsigned a0) {
counter += a0;
}
void count0() {
counter += 0;
}
void event_class_test() {
counter = 0;
EventQueue queue(2048);
Event<void(int, int, int, int, int)> e5(&queue, count5);
Event<void(int, int, int, int)> e4(&queue, count5, 1);
Event<void(int, int, int)> e3(&queue, count5, 1, 1);
Event<void(int, int)> e2(&queue, count5, 1, 1, 1);
Event<void(int)> e1(&queue, count5, 1, 1, 1, 1);
Event<void()> e0(&queue, count5, 1, 1, 1, 1, 1);
e5.post(1, 1, 1, 1, 1);
e4.post(1, 1, 1, 1);
e3.post(1, 1, 1);
e2.post(1, 1);
e1.post(1);
e0.post();
queue.dispatch(0);
TEST_ASSERT_EQUAL(counter, 30);
}
void event_class_helper_test() {
counter = 0;
EventQueue queue(2048);
Event<void()> e5 = queue.event(count5, 1, 1, 1, 1, 1);
Event<void()> e4 = queue.event(count4, 1, 1, 1, 1);
Event<void()> e3 = queue.event(count3, 1, 1, 1);
Event<void()> e2 = queue.event(count2, 1, 1);
Event<void()> e1 = queue.event(count1, 1);
Event<void()> e0 = queue.event(count0);
e5.post();
e4.post();
e3.post();
e2.post();
e1.post();
e0.post();
queue.dispatch(0);
TEST_ASSERT_EQUAL(counter, 15);
}
void event_inference_test() {
counter = 0;
EventQueue queue (2048);
queue.event(count5, 1, 1, 1, 1, 1).post();
queue.event(count5, 1, 1, 1, 1).post(1);
queue.event(count5, 1, 1, 1).post(1, 1);
queue.event(count5, 1, 1).post(1, 1, 1);
queue.event(count5, 1).post(1, 1, 1, 1);
queue.event(count5).post(1, 1, 1, 1, 1);
queue.dispatch(0);
TEST_ASSERT_EQUAL(counter, 30);
}
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
const Case cases[] = {
Case("Testing calls with 5 args", simple_posts_test5),
Case("Testing calls with 4 args", simple_posts_test4),
Case("Testing calls with 3 args", simple_posts_test3),
Case("Testing calls with 2 args", simple_posts_test2),
Case("Testing calls with 1 args", simple_posts_test1),
Case("Testing calls with 0 args", simple_posts_test0),
Case("Testing call_in", call_in_test<20>),
Case("Testing call_every", call_every_test<20>),
Case("Testing allocate failure", allocate_failure_test),
Case("Testing event cancel 1", cancel_test1<20>),
Case("Testing the event class", event_class_test),
Case("Testing the event class helpers", event_class_helper_test),
Case("Testing the event inference", event_inference_test),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

106
TESTS/host_tests/timing_drift_auto.py
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@ -1,106 +0,0 @@
"""
mbed SDK
Copyright (c) 2011-2013 ARM Limited
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
"""
from mbed_host_tests import BaseHostTest
class TimingDriftTest(BaseHostTest):
""" This test is reading single characters from stdio
and measures time between their occurrences.
"""
__result = None
# This is calculated later: average_drift_max * number of tick events
total_drift_max = None
average_drift_max = 0.05
ticks = []
start_time = None
finish_time = None
dut_seconds_passed = None
total_time = None
total_drift = None
average_drift = None
def _callback_result(self, key, value, timestamp):
# We should not see result data in this test
self.__result = False
def _callback_end(self, key, value, timestamp):
""" {{end;%s}}} """
self.log("Received end event, timestamp: %f" % timestamp)
self.notify_complete(result=self.result(print_stats=True))
def _callback_tick(self, key, value, timestamp):
""" {{tick;%d}}} """
self.log("tick! %f" % timestamp)
self.ticks.append((key, value, timestamp))
def setup(self):
self.register_callback("end", self._callback_end)
self.register_callback('tick', self._callback_tick)
def result(self, print_stats=True):
self.dut_seconds_passed = len(self.ticks) - 1
if self.dut_seconds_passed < 1:
if print_stats:
self.log("FAIL: failed to receive at least two tick events")
self.__result = False
return self.__result
self.total_drift_max = self.dut_seconds_passed * self.average_drift_max
self.start_time = self.ticks[0][2]
self.finish_time = self.ticks[-1][2]
self.total_time = self.finish_time - self.start_time
self.total_drift = self.total_time - self.dut_seconds_passed
self.average_drift = self.total_drift / self.dut_seconds_passed
if print_stats:
self.log("Start: %f" % self.start_time)
self.log("Finish: %f" % self.finish_time)
self.log("Total time taken: %f" % self.total_time)
total_drift_ratio_string = "Total drift/Max total drift: %f/%f"
self.log(total_drift_ratio_string % (self.total_drift,
self.total_drift_max))
average_drift_ratio_string = "Average drift/Max average drift: %f/%f"
self.log(average_drift_ratio_string % (self.average_drift,
self.average_drift_max))
if abs(self.total_drift) > self.total_drift_max:
if print_stats:
self.log("FAIL: Total drift exceeded max total drift")
self.__result = False
elif self.average_drift > self.average_drift_max:
if print_stats:
self.log("FAIL: Average drift exceeded max average drift")
self.__result = False
else:
self.__result = True
return self.__result
def teardown(self):
pass

6
TESTS/integration/basic/main.cpp
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#include "test_env.h"
int main() {
GREENTEA_SETUP(15, "default_auto");
GREENTEA_TESTSUITE_RESULT(true);
}

122
TESTS/mbed_drivers/c_strings/main.cpp
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@ -1,122 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <string.h>
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
namespace {
static char buffer[256] = {0};
}
#define CLEAN_BUFFER memset(::buffer, 0x00, sizeof(::buffer))
#define NEGATIVE_INTEGERS -32768,-3214,-999,-100,-1,0,-1,-4231,-999,-4123,-32760,-99999
#define POSITIVE_INTEGERS 32768,3214,999,100,1,0,1,4231,999,4123,32760,99999
#define FLOATS 0.002,0.92430,15.91320,791.77368,6208.2,25719.4952,426815.982588,6429271.046,42468024.93,212006462.910
using namespace utest::v1;
void test_case_c_string_i_d() {
CLEAN_BUFFER;
sprintf(buffer, "%i %d %i %d %i %d %i %d %i %d %i %i", NEGATIVE_INTEGERS);
TEST_ASSERT_EQUAL_STRING("-32768 -3214 -999 -100 -1 0 -1 -4231 -999 -4123 -32760 -99999", buffer);
}
void test_case_c_string_u_d() {
CLEAN_BUFFER;
sprintf(buffer, "%u %d %u %d %u %d %u %d %u %d %u %d", POSITIVE_INTEGERS);
TEST_ASSERT_EQUAL_STRING("32768 3214 999 100 1 0 1 4231 999 4123 32760 99999", buffer);
}
void test_case_c_string_x_E() {
CLEAN_BUFFER;
sprintf(buffer, "%x %X %x %X %x %X %x %X %x %X %x %X", POSITIVE_INTEGERS);
TEST_ASSERT_EQUAL_STRING("8000 C8E 3e7 64 1 0 1 1087 3e7 101B 7ff8 1869F", buffer);
}
void test_case_c_string_f_f() {
CLEAN_BUFFER;
sprintf(buffer, "%f %f %f %f %f %f %f %f %f %f", FLOATS);
TEST_ASSERT_EQUAL_STRING("0.002000 0.924300 15.913200 791.773680 6208.200000 25719.495200 426815.982588 6429271.046000 42468024.930000 212006462.910000", buffer);
}
void test_case_c_string_g_g() {
CLEAN_BUFFER;
sprintf(buffer, "%g %g %g %g %g %g %g %g %g %g", FLOATS);
TEST_ASSERT_EQUAL_STRING("0.002 0.9243 15.9132 791.774 6208.2 25719.5 426816 6.42927e+06 4.2468e+07 2.12006e+08", buffer);
}
void test_case_c_string_e_E() {
CLEAN_BUFFER;
sprintf(buffer, "%e %E %e %E %e %E %e %E %e %E", FLOATS);
TEST_ASSERT_EQUAL_STRING("2.000000e-03 9.243000E-01 1.591320e+01 7.917737E+02 6.208200e+03 2.571950E+04 4.268160e+05 6.429271E+06 4.246802e+07 2.120065E+08", buffer);
}
void test_case_c_string_strtok() {
CLEAN_BUFFER;
char str[] ="- This, a sample string.";
char * pch = strtok (str," ,.-");
while (pch != NULL) {
strcat(buffer, pch);
pch = strtok (NULL, " ,.-");
}
TEST_ASSERT_EQUAL_STRING("Thisasamplestring", buffer);
}
void test_case_c_string_strpbrk() {
CLEAN_BUFFER;
char str[] = "This is a sample string";
char key[] = "aeiou";
char *pch = strpbrk(str, key);
while (pch != NULL)
{
char buf[2] = {*pch, '\0'};
strcat(buffer, buf);
pch = strpbrk(pch + 1,key);
}
TEST_ASSERT_EQUAL_STRING("iiaaei", buffer);
}
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
Case cases[] = {
Case("C strings: strtok", test_case_c_string_strtok, greentea_failure_handler),
Case("C strings: strpbrk", test_case_c_string_strpbrk, greentea_failure_handler),
Case("C strings: %i %d integer formatting", test_case_c_string_i_d, greentea_failure_handler),
Case("C strings: %u %d integer formatting", test_case_c_string_u_d, greentea_failure_handler),
Case("C strings: %x %E integer formatting", test_case_c_string_x_E, greentea_failure_handler),
Case("C strings: %f %f float formatting", test_case_c_string_f_f, greentea_failure_handler),
Case("C strings: %e %E float formatting", test_case_c_string_e_E, greentea_failure_handler),
Case("C strings: %g %g float formatting", test_case_c_string_g_g, greentea_failure_handler),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(5, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

51
TESTS/mbed_drivers/dev_null/main.cpp
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@ -1,51 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
class DevNull : public Stream {
public:
DevNull(const char *name = NULL) : Stream(name) {}
protected:
virtual int _getc() {
return 0;
}
virtual int _putc(int c) {
return c;
}
};
DevNull null("null");
int main() {
GREENTEA_SETUP(2, "dev_null_auto");
printf("MBED: before re-routing stdout to /null\n"); // This shouldn't appear
greentea_send_kv("to_stdout", "re-routing stdout to /null");
if (freopen("/null", "w", stdout)) {
// This shouldn't appear on serial
// We should use pure printf here to send KV
printf("{{to_null;printf redirected to /null}}\n");
printf("MBED: this printf is already redirected to /null\n");
}
while(1) {
// Success is determined by the host test at this point, so busy wait
}
}

64
TESTS/mbed_drivers/echo/main.cpp
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@ -1,64 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <string.h>
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
using namespace utest::v1;
// Echo server (echo payload to host)
template<int N>
void test_case_echo_server_x() {
char _key[10] = {};
char _value[128] = {};
const int echo_count = N;
// Handshake with host
greentea_send_kv("echo_count", echo_count);
greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
TEST_ASSERT_EQUAL_INT(echo_count, atoi(_value));
for (int i=0; i < echo_count; ++i) {
greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
greentea_send_kv(_key, _value);
}
}
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
Case cases[] = {
Case("Echo server: x16", test_case_echo_server_x<16>, greentea_failure_handler),
Case("Echo server: x32", test_case_echo_server_x<32>, greentea_failure_handler),
Case("Echo server: x64", test_case_echo_server_x<64>, greentea_failure_handler),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(180, "echo");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

119
TESTS/mbed_drivers/generic_tests/main.cpp
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@ -1,119 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <string.h>
#include <utility> // std::pair
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
using namespace utest::v1;
#define PATTERN_CHECK_VALUE 0xF0F0ADAD
class CppTestCaseHelperClass {
private:
const char* name;
const unsigned pattern;
public:
CppTestCaseHelperClass(const char* _name) : name(_name), pattern(PATTERN_CHECK_VALUE) {
print("init");
}
void print(const char *message) {
printf("%s::%s\n", name, message);
}
bool check_init(void) {
bool result = (pattern == PATTERN_CHECK_VALUE);
print(result ? "check_init: OK" : "check_init: ERROR");
return result;
}
void stack_test(void) {
print("stack_test");
CppTestCaseHelperClass t("Stack");
t.hello();
}
void hello(void) {
print("hello");
}
~CppTestCaseHelperClass() {
print("destroy");
}
};
void test_case_basic() {
TEST_ASSERT_TRUE(true);
TEST_ASSERT_FALSE(false);
TEST_ASSERT_EQUAL_STRING("The quick brown fox jumps over the lazy dog",
"The quick brown fox jumps over the lazy dog");
}
void test_case_blinky() {
static DigitalOut myled(LED1);
const int cnt_max = 1024;
for (int cnt = 0; cnt < cnt_max; ++cnt) {
myled = !myled;
}
}
void test_case_cpp_stack() {
// Check C++ start-up initialisation
CppTestCaseHelperClass s("Static");
// Global stack object simple test
s.stack_test();
TEST_ASSERT_TRUE_MESSAGE(s.check_init(), "s.check_init() failed");
}
void test_case_cpp_heap() {
// Heap test object simple test
CppTestCaseHelperClass *m = new CppTestCaseHelperClass("Heap");
m->hello();
TEST_ASSERT_TRUE_MESSAGE(m->check_init(), "m->check_init() failed");
delete m;
}
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
// Generic test cases
Case cases[] = {
Case("Basic", test_case_basic, greentea_failure_handler),
Case("Blinky", test_case_blinky, greentea_failure_handler),
Case("C++ stack", test_case_cpp_stack, greentea_failure_handler),
Case("C++ heap", test_case_cpp_heap, greentea_failure_handler)
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

146
TESTS/mbed_drivers/lp_timeout/main.cpp
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@ -1,146 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if !DEVICE_LOWPOWERTIMER
#error [NOT_SUPPORTED] Low power timer not supported for this target
#endif
#include "utest/utest.h"
#include "unity/unity.h"
#include "greentea-client/test_env.h"
#include "mbed.h"
#include "us_ticker_api.h"
using namespace utest::v1;
volatile static bool complete;
static LowPowerTimeout lpt;
/* Timeouts are quite arbitrary due to large number of boards with varying level of accuracy */
#define LONG_TIMEOUT (100000)
#define SHORT_TIMEOUT (600)
void cb_done() {
complete = true;
}
#if DEVICE_SLEEP
void lp_timeout_1s_deepsleep(void)
{
complete = false;
/*
* Since deepsleep() may shut down the UART peripheral, we wait for 10ms
* to allow for hardware serial buffers to completely flush.
* This should be replaced with a better function that checks if the
* hardware buffers are empty. However, such an API does not exist now,
* so we'll use the wait_ms() function for now.
*/
wait_ms(10);
/*
* We use here lp_ticker_read() instead of us_ticker_read() for start and
* end because the microseconds timer might be disable during deepsleep.
*/
timestamp_t start = lp_ticker_read();
lpt.attach(&cb_done, 1);
deepsleep();
while (!complete);
timestamp_t end = lp_ticker_read();
/* It takes longer to wake up from deep sleep */
TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
TEST_ASSERT_TRUE(complete);
}
void lp_timeout_1s_sleep(void)
{
complete = false;
timestamp_t start = us_ticker_read();
lpt.attach(&cb_done, 1);
sleep();
while (!complete);
timestamp_t end = us_ticker_read();
TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
TEST_ASSERT_TRUE(complete);
}
#endif /* DEVICE_SLEEP */
void lp_timeout_us(uint32_t delay_us, uint32_t tolerance)
{
complete = false;
timestamp_t start = us_ticker_read();
lpt.attach_us(&cb_done, delay_us);
while (!complete);
timestamp_t end = us_ticker_read();
/* Using RTC which is less accurate */
TEST_ASSERT_UINT32_WITHIN(tolerance, delay_us, end - start);
TEST_ASSERT_TRUE(complete);
}
void lp_timeout_5s(void)
{
lp_timeout_us(5000000, LONG_TIMEOUT);
}
void lp_timeout_1s(void)
{
lp_timeout_us(1000000, LONG_TIMEOUT);
}
void lp_timeout_1ms(void)
{
lp_timeout_us(1000, SHORT_TIMEOUT);
}
void lp_timeout_500us(void)
{
lp_timeout_us(500, SHORT_TIMEOUT);
}
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
Case cases[] = {
Case("500us LowPowerTimeout", lp_timeout_500us, greentea_failure_handler),
Case("1ms LowPowerTimeout", lp_timeout_1ms, greentea_failure_handler),
Case("1sec LowPowerTimeout", lp_timeout_1s, greentea_failure_handler),
Case("5sec LowPowerTimeout", lp_timeout_5s, greentea_failure_handler),
#if DEVICE_SLEEP
Case("1sec LowPowerTimeout from sleep", lp_timeout_1s_sleep, greentea_failure_handler),
Case("1sec LowPowerTimeout from deepsleep", lp_timeout_1s_deepsleep, greentea_failure_handler),
#endif /* DEVICE_SLEEP */
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

289
TESTS/mbed_drivers/mem_trace/main.cpp
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@ -1,289 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
#include "mbed_mem_trace.h"
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#ifndef MBED_MEM_TRACING_ENABLED
#error [NOT_SUPPORTED] test not supported
#endif
using namespace utest::v1;
/******************************************************************************/
/* Helper functions and data structures */
/******************************************************************************/
// This structure keeps data about the various memory allocation operations,
// as traced by 'test_trace_cb' below.
#define TEST_MAX_MEMORY_OPS 10
// Trace results for all possible operations
typedef struct {
uint8_t op;
void *res;
union {
struct {
size_t arg_size;
} malloc_info;
struct {
void *arg_ptr;
size_t arg_size;
} realloc_info;
struct {
size_t arg_nmemb;
size_t arg_size;
} calloc_info;
struct {
void *arg_ptr;
} free_info;
};
} mem_trace_data_t;
// Memory operation statistics
typedef struct {
mem_trace_data_t op_data[TEST_MAX_MEMORY_OPS];
uint32_t total_ops;
bool invalid_op, overflow;
} stats_t;
static stats_t stats;
// Clear all the memory statistics
static void test_clear_stats() {
memset(&stats, 0, sizeof(stats));
}
// Memory tracer callback that records each operation in "stats" (above)
extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) {
va_list va;
mem_trace_data_t *pmem = stats.op_data + stats.total_ops;
if (stats.total_ops >= TEST_MAX_MEMORY_OPS) {
stats.overflow = true;
return;
}
va_start(va, caller);
pmem->op = op;
pmem->res = res;
switch(op) {
case MBED_MEM_TRACE_MALLOC:
pmem->malloc_info.arg_size = va_arg(va, size_t);
break;
case MBED_MEM_TRACE_REALLOC:
pmem->realloc_info.arg_ptr = va_arg(va, void *);
pmem->realloc_info.arg_size = va_arg(va, size_t);
break;
case MBED_MEM_TRACE_CALLOC:
pmem->calloc_info.arg_nmemb = va_arg(va, size_t);
pmem->calloc_info.arg_size = va_arg(va, size_t);
break;
case MBED_MEM_TRACE_FREE:
pmem->free_info.arg_ptr = va_arg(va, void *);
break;
default:
stats.invalid_op = true;
}
stats.total_ops ++;
va_end(va);
}
// Generic sanity checks for the tracer
static void check_sanity(uint32_t expected_ops) {
TEST_ASSERT_FALSE(stats.overflow);
TEST_ASSERT_FALSE(stats.invalid_op);
TEST_ASSERT_EQUAL_UINT32(stats.total_ops, expected_ops);
}
// Check a "malloc" operation
static void check_malloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_size) {
TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_MALLOC);
TEST_ASSERT_EQUAL_PTR(p->res, expected_res);
TEST_ASSERT_EQUAL_UINT32(p->malloc_info.arg_size, expected_arg_size);
}
// Check a "free" operation
static void check_free_op(const mem_trace_data_t *p, void *expected_arg_ptr) {
TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_FREE);
TEST_ASSERT_EQUAL_PTR(p->free_info.arg_ptr, expected_arg_ptr);
}
// Check a "realloc" operation
static void check_realloc_op(const mem_trace_data_t *p, void *expected_res, void *expected_arg_ptr, size_t expected_arg_size) {
TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_REALLOC);
TEST_ASSERT_EQUAL_PTR(p->res, expected_res);
TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_ptr, expected_arg_ptr);
TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_size, expected_arg_size);
}
// Check a "calloc" operation
static void check_calloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_nmemb, size_t expected_arg_size) {
TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_CALLOC);
TEST_ASSERT_EQUAL_PTR(p->res, expected_res);
TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_nmemb, expected_arg_nmemb);
TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_size, expected_arg_size);
}
/******************************************************************************/
/* Tests */
/******************************************************************************/
// Allocate a single buffer, then free it. Check that tracing matches the operations.
static void test_case_single_malloc_free() {
const size_t block_size = 126;
const mem_trace_data_t *pmem = stats.op_data;
test_clear_stats();
mbed_mem_trace_set_callback(test_trace_cb);
// Allocate a single memory block
void *p = malloc(block_size);
TEST_ASSERT_NOT_EQUAL(p, NULL);
// Free the memory block
free(p);
// Stop tracing
mbed_mem_trace_set_callback(NULL);
// Check tracer result
check_sanity(2);
check_malloc_op(pmem ++, p, block_size);
check_free_op(pmem, p);
}
// Test all memory operations (malloc, realloc, free, calloc)
static void test_case_all_memory_ops() {
const size_t malloc_size = 40, realloc_size = 80, nmemb = 25, size = 10;
const mem_trace_data_t *pmem = stats.op_data;
test_clear_stats();
mbed_mem_trace_set_callback(test_trace_cb);
// Allocate a single memory block, the realloc it
void *p_malloc = malloc(malloc_size);
TEST_ASSERT_NOT_EQUAL(p_malloc, NULL);
void *p_realloc = realloc(p_malloc, realloc_size);
TEST_ASSERT_NOT_EQUAL(p_realloc, NULL);
// Use calloc() now
void *p_calloc = calloc(nmemb, size);
//TEST_ASSERT_NOT_EQUAL(p_calloc, NULL);
// Free the realloc() pointer first, then the calloc() one
free(p_realloc);
free(p_calloc);
// Stop tracing
mbed_mem_trace_set_callback(NULL);
// Check tracer result
check_sanity(6);
check_malloc_op(pmem ++, p_malloc, malloc_size);
check_realloc_op(pmem ++, p_realloc, p_malloc, realloc_size);
// calloc() calls malloc() internally
check_malloc_op(pmem ++, p_calloc, nmemb * size);
check_calloc_op(pmem ++, p_calloc, nmemb, size);
check_free_op(pmem ++, p_realloc);
check_free_op(pmem, p_calloc);
}
// Test that tracing is off when using a NULL callback
static void test_case_trace_off() {
const size_t malloc_size = 10;
test_clear_stats();
// We don't want any tracing
mbed_mem_trace_set_callback(NULL);
// Allocate a buffer and free it
void *p_malloc = malloc(malloc_size);
TEST_ASSERT_NOT_EQUAL(p_malloc, NULL);
free(p_malloc);
// Check that we didn't trace anything
check_sanity(0);
}
// Test partial tracing (start tracing, stop tracing, restart later)
static void test_case_partial_trace() {
const size_t malloc_size_1 = 20, malloc_size_2 = 30;
const mem_trace_data_t *pmem = stats.op_data;
test_clear_stats();
// Start tracing
mbed_mem_trace_set_callback(test_trace_cb);
// Allocate a buffer
void *p_malloc_1 = malloc(malloc_size_1);
TEST_ASSERT_NOT_EQUAL(p_malloc_1, NULL);
// Disable tracing before freeing the first buffer
mbed_mem_trace_set_callback(NULL);
free(p_malloc_1);
// Allocate another buffer (still not traced)
void *p_malloc_2 = malloc(malloc_size_2);
TEST_ASSERT_NOT_EQUAL(p_malloc_2, NULL);
// Re-enable tracing
mbed_mem_trace_set_callback(test_trace_cb);
// And free the second buffer (this operation should be tracer)
free(p_malloc_2);
// Stop tracing
mbed_mem_trace_set_callback(NULL);
// Check tracer result
check_sanity(2);
check_malloc_op(pmem ++, p_malloc_1, malloc_size_1);
check_free_op(pmem, p_malloc_2);
}
// Test new/delete tracing
static void test_case_new_delete() {
const mem_trace_data_t *pmem = stats.op_data;
test_clear_stats();
// Start tracing
mbed_mem_trace_set_callback(test_trace_cb);
// Test new, new[], delete and delete[]
int *p_int = new int;
int *p_int_array = new int[10];
delete p_int;
delete[] p_int_array;
// Stop tracing
mbed_mem_trace_set_callback(NULL);
// Check tracer result
check_sanity(4);
check_malloc_op(pmem ++, p_int, sizeof(int));
check_malloc_op(pmem ++, p_int_array, 10 * sizeof(int));
check_free_op(pmem ++, p_int);
check_free_op(pmem ++, p_int_array);
}
static Case cases[] = {
Case("single malloc/free", test_case_single_malloc_free),
Case("all memory operations", test_case_all_memory_ops),
Case("trace off", test_case_trace_off),
Case("partial trace", test_case_partial_trace),
Case("test new/delete", test_case_new_delete)
};
static status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
static Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
// Disable stdout buffering to prevent any unwanted allocations
setvbuf(stdout, NULL, _IONBF, 0);
Harness::run(specification);
}

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TESTS/mbed_drivers/race_test/main.cpp
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/*
* Copyright (c) 2016-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "rtos.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
#include "SingletonPtr.h"
#include <stdio.h>
using namespace utest::v1;
#define TEST_STACK_SIZE 1024
static uint32_t instance_count = 0;
class TestClass {
public:
TestClass() {
printf("TestClass ctor start\r\n");
Thread::wait(500);
instance_count++;
printf("TestClass ctor end\r\n");
}
void do_something() {
printf("Do something called\r\n");
}
~TestClass() {
instance_count--;
}
};
static TestClass* get_test_class()
{
static TestClass tc;
return &tc;
}
static SingletonPtr<TestClass> test_class;
static void main_func_race()
{
get_test_class();
}
static void main_class_race()
{
test_class->do_something();
}
void test_case_func_race()
{
printf("Running function race test\r\n");
Callback<void()> cb(main_func_race);
Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
// Start start first thread
t1->start(cb);
// Start second thread while the first is inside the constructor
Thread::wait(250);
t2->start(cb);
// Wait for the threads to finish
t1->join();
t2->join();
delete t1;
delete t2;
TEST_ASSERT_EQUAL_UINT32(1, instance_count);
// Reset instance count
instance_count = 0;
}
void test_case_class_race()
{
printf("Running class race test\r\n");
Callback<void()> cb(main_class_race);
Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
// Start start first thread
t1->start(cb);
// Start second thread while the first is inside the constructor
Thread::wait(250);
t2->start(cb);
// Wait for the threads to finish
t1->join();
t2->join();
delete t1;
delete t2;
TEST_ASSERT_EQUAL_UINT32(1, instance_count);
// Reset instance count
instance_count = 0;
}
Case cases[] = {
Case("function init race", test_case_func_race),
Case("class init race", test_case_class_race),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(20, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main()
{
Harness::run(specification);
}

56
TESTS/mbed_drivers/rtc/main.cpp
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@ -1,56 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
using namespace utest::v1;
#define CUSTOM_TIME 1256729737
void test_case_rtc_strftime() {
greentea_send_kv("timestamp", CUSTOM_TIME);
char buffer[32] = {0};
char kv_buff[64] = {0};
set_time(CUSTOM_TIME); // Set RTC time to Wed, 28 Oct 2009 11:35:37
for (int i=0; i<10; ++i) {
time_t seconds = time(NULL);
sprintf(kv_buff, "[%ld] ", seconds);
strftime(buffer, sizeof(buffer), "%Y-%m-%d %H:%M:%S %p", localtime(&seconds));
strcat(kv_buff, buffer);
greentea_send_kv("rtc", kv_buff);
wait(1);
}
}
Case cases[] = {
Case("RTC strftime", test_case_rtc_strftime),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "rtc_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

207
TESTS/mbed_drivers/stats/main.cpp
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@ -1,207 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
#include "mbed_stats.h"
#include <stdlib.h>
#include <stdio.h>
#if !defined(MBED_HEAP_STATS_ENABLED) || !MBED_HEAP_STATS_ENABLED || defined(__ICCARM__)
#error [NOT_SUPPORTED] test not supported
#endif
using namespace utest::v1;
#define ALLOCATION_SIZE_DEFAULT 564
#define ALLOCATION_SIZE_SMALL 124
#define ALLOCATION_SIZE_LARGE 790
#define ALLOCATION_SIZE_FAIL (1024 * 1024 *1024)
typedef void* (*malloc_cb_t) (uint32_t size);
static void* thunk_malloc(uint32_t size);
static void* thunk_calloc_1(uint32_t size);
static void* thunk_calloc_4(uint32_t size);
static void* thunk_realloc(uint32_t size);
malloc_cb_t malloc_thunk_array[] = {
thunk_malloc,
thunk_calloc_1,
thunk_calloc_4,
thunk_realloc,
};
void test_case_malloc_free_size()
{
printf("Initial print to setup stdio buffers\n");
mbed_stats_heap_t stats_start;
mbed_stats_heap_t stats_current;
void *data;
mbed_stats_heap_get(&stats_start);
for (uint32_t i = 0; i < sizeof(malloc_thunk_array) / sizeof(malloc_cb_t); i++) {
// Allocate memory and assert size change
data = malloc_thunk_array[i](ALLOCATION_SIZE_DEFAULT);
TEST_ASSERT(data != NULL);
mbed_stats_heap_get(&stats_current);
uint32_t increase = stats_current.current_size - stats_start.current_size;
TEST_ASSERT_EQUAL_UINT32(ALLOCATION_SIZE_DEFAULT, increase);
TEST_ASSERT_EQUAL_UINT32(stats_start.total_size + ALLOCATION_SIZE_DEFAULT * (i + 1), stats_current.total_size);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt + 1, stats_current.alloc_cnt);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt);
// Free memory and assert back to starting size
free(data);
mbed_stats_heap_get(&stats_current);
TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt, stats_current.alloc_cnt);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt);
}
}
void test_case_allocate_zero()
{
mbed_stats_heap_t stats_start;
mbed_stats_heap_t stats_current;
void *data;
mbed_stats_heap_get(&stats_start);
for (uint32_t i = 0; i < sizeof(malloc_thunk_array) / sizeof(malloc_cb_t); i++) {
// Allocate memory and assert size change
data = malloc_thunk_array[i](0);
// Return can be NULL
mbed_stats_heap_get(&stats_current);
TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size);
TEST_ASSERT_EQUAL_UINT32(stats_start.total_size, stats_current.total_size);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt);
// Free memory and assert back to starting size
free(data);
mbed_stats_heap_get(&stats_current);
TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt, stats_current.alloc_cnt);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt);
}
}
void test_case_allocate_fail()
{
mbed_stats_heap_t stats_start;
mbed_stats_heap_t stats_current;
void *data;
mbed_stats_heap_get(&stats_start);
for (uint32_t i = 0; i < sizeof(malloc_thunk_array) / sizeof(malloc_cb_t); i++) {
// Trigger a failure by trying to allocate a buffer that won't fit
data = malloc_thunk_array[i](ALLOCATION_SIZE_FAIL);
TEST_ASSERT(data == NULL);
mbed_stats_heap_get(&stats_current);
TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size);
TEST_ASSERT_EQUAL_UINT32(stats_start.total_size, stats_current.total_size);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt, stats_current.alloc_cnt);
TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt + i + 1, stats_current.alloc_fail_cnt);
}
}
static void* thunk_malloc(uint32_t size)
{
printf("Malloc thunk\n");
return malloc(size);
}
static void* thunk_calloc_1(uint32_t size)
{
printf("Calloc thunk 1 byte\n");
return calloc(size / 1, 1);
}
static void* thunk_calloc_4(uint32_t size)
{
printf("Calloc thunk 4 bytes\n");
return calloc(size / 4, 4);
}
static void* thunk_realloc(uint32_t size)
{
printf("Realloc thunk\n");
return realloc(NULL, size);
}
void test_case_realloc_size()
{
mbed_stats_heap_t stats_start;
mbed_stats_heap_t stats_current;
uint32_t increase;
void *data;
mbed_stats_heap_get(&stats_start);
// Allocate memory and assert size change
data = realloc(NULL, ALLOCATION_SIZE_DEFAULT);
TEST_ASSERT(data != NULL);
mbed_stats_heap_get(&stats_current);
increase = stats_current.current_size - stats_start.current_size;
TEST_ASSERT_EQUAL_UINT32(increase, ALLOCATION_SIZE_DEFAULT);
// Decrease size and assert size change
data = realloc(data, ALLOCATION_SIZE_SMALL);
TEST_ASSERT(data != NULL);
mbed_stats_heap_get(&stats_current);
increase = stats_current.current_size - stats_start.current_size;
TEST_ASSERT_EQUAL_UINT32(increase, ALLOCATION_SIZE_SMALL);
// Increase size and assert size change
data = realloc(data, ALLOCATION_SIZE_LARGE);
TEST_ASSERT(data != NULL);
mbed_stats_heap_get(&stats_current);
increase = stats_current.current_size - stats_start.current_size;
TEST_ASSERT_EQUAL_UINT32(increase, ALLOCATION_SIZE_LARGE);
// Free memory and assert back to starting size
free(data);
mbed_stats_heap_get(&stats_current);
TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size);
}
Case cases[] = {
Case("malloc and free size", test_case_malloc_free_size),
Case("allocate size zero", test_case_allocate_zero),
Case("allocation failure", test_case_allocate_fail),
Case("realloc size", test_case_realloc_size),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(20, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main()
{
Harness::run(specification);
}

139
TESTS/mbed_drivers/stl_features/main.cpp
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@ -1,139 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity/unity.h"
#include "utest/utest.h"
#include <stdio.h>
#include <string.h>
#include <algorithm>
#include <string>
#include <vector>
#include <queue>
#include <map>
#include <math.h>
using namespace utest::v1;
#define TABLE_SIZE(TAB) (sizeof(TAB) / sizeof(TAB[0]))
#define NEGATIVE_INTEGERS -32768,-3214,-999,-100,-1,0,1,4231,999,4123,32760,99999
#define POSITIVE_INTEGERS 32768,3214,999,100,1,0,1,4231,999,4123,32760,99999
#define FLOATS 0.002,0.92430,15.91320,791.77368,6208.2,25719.4952,426815.982588,6429271.046,42468024.93,212006462.910
#define FLOATS_STR "0.002","0.92430","15.91320","791.77368","6208.2","25719.4952","426815.982588","6429271.046","42468024.93","212006462.910"
namespace {
int p_integers[] = {POSITIVE_INTEGERS};
int n_integers[] = {NEGATIVE_INTEGERS};
float floats[] = {FLOATS};
template <class T, class F>
void BubbleSort(T& _array, size_t array_size, F functor) {
bool flag = true;
size_t numLength = array_size;
for(size_t i = 1; (i <= numLength) && flag; i++) {
flag = false;
for (size_t j = 0; j < (numLength - 1); j++) {
if (functor(_array[j+1], _array[j])) {
int temp = _array[j];
_array[j] = _array[j + 1];
_array[j+1] = temp;
flag = true;
}
}
}
}
struct printInt {
void operator()(int i) { printf("%d ", i); }
};
struct printFloat {
void operator()(float f) { printf("%f ", f); }
};
struct printString {
void operator()(const char* s) { printf("%s ", s); }
};
struct greaterAbs {
bool operator()(int a, int b) { return abs(a) > abs(b); }
};
} // namespace
void test_case_stl_equal() {
std::vector<int> v_pints(p_integers, p_integers + TABLE_SIZE(p_integers));
TEST_ASSERT_TRUE(std::equal(v_pints.begin(), v_pints.end(), p_integers));
}
void test_case_stl_transform() {
const char* floats_str[] = {FLOATS_STR};
float floats_transform[TABLE_SIZE(floats_str)] = {0.0};
std::transform(floats_str, floats_str + TABLE_SIZE(floats_str), floats_transform, atof);
//printf("stl_transform::floats_str: ");
//std::for_each(floats_str, floats_str + TABLE_SIZE(floats_str), printString());
//printf("stl_transform::floats_transform: ");
//std::for_each(floats_transform, floats_transform + TABLE_SIZE(floats_transform), printFloat());
//printf("\n");
TEST_ASSERT_TRUE(std::equal(floats_transform, floats_transform + TABLE_SIZE(floats_transform), floats));
}
void test_case_stl_sort_greater() {
std::vector<int> v_nints_1(n_integers, n_integers + TABLE_SIZE(n_integers));
std::vector<int> v_nints_2(n_integers, n_integers + TABLE_SIZE(n_integers));
BubbleSort(v_nints_1, v_nints_1.size(), std::greater<int>());
std::sort(v_nints_2.begin(), v_nints_2.end(), std::greater<int>());
TEST_ASSERT_TRUE(std::equal(v_nints_1.begin(), v_nints_1.end(), v_nints_2.begin()));
}
void test_case_stl_sort_abs() {
std::vector<int> v_nints_1(n_integers, n_integers + TABLE_SIZE(n_integers));
std::vector<int> v_nints_2(n_integers, n_integers + TABLE_SIZE(n_integers));
BubbleSort(v_nints_1, v_nints_1.size(), greaterAbs());
std::sort(v_nints_2.begin(), v_nints_2.end(), greaterAbs());
TEST_ASSERT_TRUE(std::equal(v_nints_1.begin(), v_nints_1.end(), v_nints_2.begin()));
}
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
Case cases[] = {
Case("STL std::equal", test_case_stl_equal, greentea_failure_handler),
Case("STL std::transform", test_case_stl_transform, greentea_failure_handler),
Case("STL std::sort greater", test_case_stl_sort_greater, greentea_failure_handler),
Case("STL std::sort abs", test_case_stl_sort_abs, greentea_failure_handler)
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(5, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

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TESTS/mbed_drivers/ticker/main.cpp
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/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "utest/utest.h"
using namespace utest::v1;
static const int ONE_SECOND_MS = 1000;
static const int total_ticks = 10;
DigitalOut led1(LED1);
DigitalOut led2(LED2);
Ticker *ticker1;
Ticker *ticker2;
volatile int ticker_count = 0;
volatile bool print_tick = false;
void send_kv_tick() {
if (ticker_count <= total_ticks) {
print_tick = true;
}
}
void ticker_callback_0(void) {
static int fast_ticker_count = 0;
if (fast_ticker_count >= ONE_SECOND_MS) {
send_kv_tick();
fast_ticker_count = 0;
led1 = !led1;
}
fast_ticker_count++;
}
void ticker_callback_1(void) {
led1 = !led1;
send_kv_tick();
}
void ticker_callback_2_led(void) {
led2 = !led2;
}
void ticker_callback_2(void) {
ticker_callback_2_led();
send_kv_tick();
}
void ticker_callback_1_switch_to_2(void);
void ticker_callback_2_switch_to_1(void);
void ticker_callback_1_switch_to_2(void) {
ticker1->detach();
ticker1->attach(ticker_callback_2_switch_to_1, 1.0);
ticker_callback_1();
}
void ticker_callback_2_switch_to_1(void) {
ticker2->detach();
ticker2->attach(ticker_callback_1_switch_to_2, 1.0);
ticker_callback_2();
}
void wait_and_print() {
while(ticker_count <= total_ticks) {
if (print_tick) {
print_tick = false;
greentea_send_kv("tick", ticker_count++);
}
}
}
void test_case_1x_ticker() {
led1 = 0;
led2 = 0;
ticker_count = 0;
ticker1->attach_us(ticker_callback_0, ONE_SECOND_MS);
wait_and_print();
}
void test_case_2x_ticker() {
led1 = 0;
led2 = 0;
ticker_count = 0;
ticker1->attach(&ticker_callback_1, 1.0);
ticker2->attach(&ticker_callback_2_led, 2.0);
wait_and_print();
}
void test_case_2x_callbacks() {
led1 = 0;
led2 = 0;
ticker_count = 0;
ticker1->attach(ticker_callback_1_switch_to_2, 1.0);
wait_and_print();
}
utest::v1::status_t one_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case) {
ticker1 = new Ticker();
return greentea_case_setup_handler(source, index_of_case);
}
utest::v1::status_t two_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case) {
ticker1 = new Ticker();
ticker2 = new Ticker();
return greentea_case_setup_handler(source, index_of_case);
}
utest::v1::status_t one_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const failure_t reason) {
delete ticker1;
return greentea_case_teardown_handler(source, passed, failed, reason);
}
utest::v1::status_t two_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const failure_t reason) {
delete ticker1;
delete ticker2;
return greentea_case_teardown_handler(source, passed, failed, reason);
}
// Test cases
Case cases[] = {
Case("Timers: 1x ticker", one_ticker_case_setup_handler_t, test_case_1x_ticker, one_ticker_case_teardown_handler_t),
Case("Timers: 2x tickers", two_ticker_case_setup_handler_t, test_case_2x_ticker, two_ticker_case_teardown_handler_t),
Case("Timers: 2x callbacks", two_ticker_case_setup_handler_t, test_case_2x_callbacks,two_ticker_case_teardown_handler_t),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP((total_ticks + 5) * 3, "timing_drift_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

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TESTS/mbed_drivers/timeout/main.cpp
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/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "utest/utest.h"
using namespace utest::v1;
Timeout timeout;
DigitalOut led(LED1);
volatile int ticker_count = 0;
volatile bool print_tick = false;
static const int total_ticks = 10;
const int ONE_SECOND_US = 1000000;
void send_kv_tick() {
if (ticker_count <= total_ticks) {
timeout.attach_us(send_kv_tick, ONE_SECOND_US);
print_tick = true;
}
}
void wait_and_print() {
while(ticker_count <= total_ticks) {
if (print_tick) {
print_tick = false;
greentea_send_kv("tick", ticker_count++);
led = !led;
}
}
}
void test_case_ticker() {
timeout.attach_us(send_kv_tick, ONE_SECOND_US);
wait_and_print();
}
// Test cases
Case cases[] = {
Case("Timers: toggle on/off", test_case_ticker),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

56
TESTS/mbed_drivers/wait_us/main.cpp
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@ -1,56 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "utest/utest.h"
/**
NOTE: This test will have a bit of inherent drift due to it being
single-threaded, so having a drift that is non-zero should be ok. However,
it should still be well under the limit.
**/
using namespace utest::v1;
DigitalOut led(LED1);
volatile bool print_tick = false;
const int ONE_SECOND_US = 1000000;
const int total_ticks = 10;
void test_case_ticker() {
for (int i = 0; i <= total_ticks; i++) {
wait_us(ONE_SECOND_US);
greentea_send_kv("tick", i);
}
}
// Test cases
Case cases[] = {
Case("Timers: wait_us", test_case_ticker),
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

520
TESTS/mbed_functional/callback/main.cpp
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#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
// static functions
template <typename T>
T static_func0()
{ return 0; }
template <typename T>
T static_func1(T a0)
{ return 0 | a0; }
template <typename T>
T static_func2(T a0, T a1)
{ return 0 | a0 | a1; }
template <typename T>
T static_func3(T a0, T a1, T a2)
{ return 0 | a0 | a1 | a2; }
template <typename T>
T static_func4(T a0, T a1, T a2, T a3)
{ return 0 | a0 | a1 | a2 | a3; }
template <typename T>
T static_func5(T a0, T a1, T a2, T a3, T a4)
{ return 0 | a0 | a1 | a2 | a3 | a4; }
// class functions
template <typename T>
struct Thing {
T t;
Thing() : t(0x80) {}
T member_func0()
{ return t; }
T member_func1(T a0)
{ return t | a0; }
T member_func2(T a0, T a1)
{ return t | a0 | a1; }
T member_func3(T a0, T a1, T a2)
{ return t | a0 | a1 | a2; }
T member_func4(T a0, T a1, T a2, T a3)
{ return t | a0 | a1 | a2 | a3; }
T member_func5(T a0, T a1, T a2, T a3, T a4)
{ return t | a0 | a1 | a2 | a3 | a4; }
T const_member_func0() const
{ return t; }
T const_member_func1(T a0) const
{ return t | a0; }
T const_member_func2(T a0, T a1) const
{ return t | a0 | a1; }
T const_member_func3(T a0, T a1, T a2) const
{ return t | a0 | a1 | a2; }
T const_member_func4(T a0, T a1, T a2, T a3) const
{ return t | a0 | a1 | a2 | a3; }
T const_member_func5(T a0, T a1, T a2, T a3, T a4) const
{ return t | a0 | a1 | a2 | a3 | a4; }
T volatile_member_func0() volatile
{ return t; }
T volatile_member_func1(T a0) volatile
{ return t | a0; }
T volatile_member_func2(T a0, T a1) volatile
{ return t | a0 | a1; }
T volatile_member_func3(T a0, T a1, T a2) volatile
{ return t | a0 | a1 | a2; }
T volatile_member_func4(T a0, T a1, T a2, T a3) volatile
{ return t | a0 | a1 | a2 | a3; }
T volatile_member_func5(T a0, T a1, T a2, T a3, T a4) volatile
{ return t | a0 | a1 | a2 | a3 | a4; }
T const_volatile_member_func0() const volatile
{ return t; }
T const_volatile_member_func1(T a0) const volatile
{ return t | a0; }
T const_volatile_member_func2(T a0, T a1) const volatile
{ return t | a0 | a1; }
T const_volatile_member_func3(T a0, T a1, T a2) const volatile
{ return t | a0 | a1 | a2; }
T const_volatile_member_func4(T a0, T a1, T a2, T a3) const volatile
{ return t | a0 | a1 | a2 | a3; }
T const_volatile_member_func5(T a0, T a1, T a2, T a3, T a4) const volatile
{ return t | a0 | a1 | a2 | a3 | a4; }
};
// bound functions
template <typename T>
T bound_func0(Thing<T> *t)
{ return t->t; }
template <typename T>
T bound_func1(Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T bound_func2(Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T bound_func3(Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T bound_func4(Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T bound_func5(Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_bound_func0(const Thing<T> *t)
{ return t->t; }
template <typename T>
T const_bound_func1(const Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T const_bound_func2(const Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T const_bound_func3(const Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T const_bound_func4(const Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_bound_func5(const Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T volatile_bound_func0(volatile Thing<T> *t)
{ return t->t; }
template <typename T>
T volatile_bound_func1(volatile Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T volatile_bound_func2(volatile Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T volatile_bound_func3(volatile Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T volatile_bound_func4(volatile Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T volatile_bound_func5(volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_volatile_bound_func0(const volatile Thing<T> *t)
{ return t->t; }
template <typename T>
T const_volatile_bound_func1(const volatile Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T const_volatile_bound_func2(const volatile Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T const_volatile_bound_func3(const volatile Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T const_volatile_bound_func4(const volatile Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_volatile_bound_func5(const volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
// void functions
template <typename T>
T void_func0(void *t)
{ return static_cast<Thing<T>*>(t)->t; }
template <typename T>
T void_func1(void *t, T a0)
{ return static_cast<Thing<T>*>(t)->t | a0; }
template <typename T>
T void_func2(void *t, T a0, T a1)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T void_func3(void *t, T a0, T a1, T a2)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T void_func4(void *t, T a0, T a1, T a2, T a3)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T void_func5(void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_void_func0(const void *t)
{ return static_cast<const Thing<T>*>(t)->t; }
template <typename T>
T const_void_func1(const void *t, T a0)
{ return static_cast<const Thing<T>*>(t)->t | a0; }
template <typename T>
T const_void_func2(const void *t, T a0, T a1)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T const_void_func3(const void *t, T a0, T a1, T a2)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T const_void_func4(const void *t, T a0, T a1, T a2, T a3)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_void_func5(const void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T volatile_void_func0(volatile void *t)
{ return static_cast<volatile Thing<T>*>(t)->t; }
template <typename T>
T volatile_void_func1(volatile void *t, T a0)
{ return static_cast<volatile Thing<T>*>(t)->t | a0; }
template <typename T>
T volatile_void_func2(volatile void *t, T a0, T a1)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T volatile_void_func3(volatile void *t, T a0, T a1, T a2)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T volatile_void_func4(volatile void *t, T a0, T a1, T a2, T a3)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T volatile_void_func5(volatile void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_volatile_void_func0(const volatile void *t)
{ return static_cast<const volatile Thing<T>*>(t)->t; }
template <typename T>
T const_volatile_void_func1(const volatile void *t, T a0)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0; }
template <typename T>
T const_volatile_void_func2(const volatile void *t, T a0, T a1)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T const_volatile_void_func3(const volatile void *t, T a0, T a1, T a2)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T const_volatile_void_func4(const volatile void *t, T a0, T a1, T a2, T a3)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_volatile_void_func5(const volatile void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
// Inheriting class
template <typename T>
class Thing2 : public Thing<T> {
};
// function call and result verification
template <typename T>
struct Verifier {
static void verify0(Callback<T()> func) {
T result = func();
TEST_ASSERT_EQUAL(result, 0x00);
}
template <typename O, typename M>
static void verify0(O *obj, M method) {
Callback<T()> func(obj, method);
T result = func();
TEST_ASSERT_EQUAL(result, 0x80);
}
static void verify1(Callback<T(T)> func) {
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0));
}
template <typename O, typename M>
static void verify1(O *obj, M method) {
Callback<T(T)> func(obj, method);
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0));
}
static void verify2(Callback<T(T, T)> func) {
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1));
}
template <typename O, typename M>
static void verify2(O *obj, M method) {
Callback<T(T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1));
}
static void verify3(Callback<T(T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2));
}
template <typename O, typename M>
static void verify3(O *obj, M method) {
Callback<T(T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2));
}
static void verify4(Callback<T(T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
template <typename O, typename M>
static void verify4(O *obj, M method) {
Callback<T(T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
static void verify5(Callback<T(T, T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
template <typename O, typename M>
static void verify5(O *obj, M method) {
Callback<T(T, T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
};
// test dispatch
template <typename T>
void test_dispatch0() {
Thing<T> thing;
Thing2<T> thing2;
Verifier<T>::verify0(static_func0<T>);
Verifier<T>::verify0(&thing, &Thing<T>::member_func0);
Verifier<T>::verify0((const Thing<T>*)&thing, &Thing<T>::const_member_func0);
Verifier<T>::verify0((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func0);
Verifier<T>::verify0((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func0);
Verifier<T>::verify0(&thing2, &Thing2<T>::member_func0);
Verifier<T>::verify0(&bound_func0<T>, &thing);
Verifier<T>::verify0(&const_bound_func0<T>, (const Thing<T>*)&thing);
Verifier<T>::verify0(&volatile_bound_func0<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify0(&const_volatile_bound_func0<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify0(&bound_func0<T>, &thing2);
Verifier<T>::verify0(&void_func0<T>, &thing);
Verifier<T>::verify0(&const_void_func0<T>, (const Thing<T>*)&thing);
Verifier<T>::verify0(&volatile_void_func0<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify0(&const_volatile_void_func0<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify0(callback(static_func0<T>));
Callback<T()> cb(static_func0);
Verifier<T>::verify0(cb);
cb = static_func0;
Verifier<T>::verify0(cb);
cb.attach(&bound_func0<T>, &thing);
Verifier<T>::verify0(&cb, &Callback<T()>::call);
Verifier<T>::verify0(&Callback<T()>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch1() {
Thing<T> thing;
Thing2<T> thing2;
Verifier<T>::verify1(static_func1<T>);
Verifier<T>::verify1(&thing, &Thing<T>::member_func1);
Verifier<T>::verify1((const Thing<T>*)&thing, &Thing<T>::const_member_func1);
Verifier<T>::verify1((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func1);
Verifier<T>::verify1((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func1);
Verifier<T>::verify1(&thing2, &Thing2<T>::member_func1);
Verifier<T>::verify1(&bound_func1<T>, &thing);
Verifier<T>::verify1(&const_bound_func1<T>, (const Thing<T>*)&thing);
Verifier<T>::verify1(&volatile_bound_func1<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify1(&const_volatile_bound_func1<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify1(&bound_func1<T>, &thing2);
Verifier<T>::verify1(&void_func1<T>, &thing);
Verifier<T>::verify1(&const_void_func1<T>, (const Thing<T>*)&thing);
Verifier<T>::verify1(&volatile_void_func1<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify1(&const_volatile_void_func1<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify1(callback(static_func1<T>));
Callback<T(T)> cb(static_func1);
Verifier<T>::verify1(cb);
cb = static_func1;
Verifier<T>::verify1(cb);
cb.attach(&bound_func1<T>, &thing);
Verifier<T>::verify1(&cb, &Callback<T(T)>::call);
Verifier<T>::verify1(&Callback<T(T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch2() {
Thing<T> thing;
Thing2<T> thing2;
Verifier<T>::verify2(static_func2<T>);
Verifier<T>::verify2(&thing, &Thing<T>::member_func2);
Verifier<T>::verify2((const Thing<T>*)&thing, &Thing<T>::const_member_func2);
Verifier<T>::verify2((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func2);
Verifier<T>::verify2((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func2);
Verifier<T>::verify2(&thing2, &Thing2<T>::member_func2);
Verifier<T>::verify2(&bound_func2<T>, &thing);
Verifier<T>::verify2(&const_bound_func2<T>, (const Thing<T>*)&thing);
Verifier<T>::verify2(&volatile_bound_func2<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify2(&const_volatile_bound_func2<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify2(&bound_func2<T>, &thing2);
Verifier<T>::verify2(&void_func2<T>, &thing);
Verifier<T>::verify2(&const_void_func2<T>, (const Thing<T>*)&thing);
Verifier<T>::verify2(&volatile_void_func2<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify2(&const_volatile_void_func2<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify2(callback(static_func2<T>));
Callback<T(T, T)> cb(static_func2);
Verifier<T>::verify2(cb);
cb = static_func2;
Verifier<T>::verify2(cb);
cb.attach(&bound_func2<T>, &thing);
Verifier<T>::verify2(&cb, &Callback<T(T, T)>::call);
Verifier<T>::verify2(&Callback<T(T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch3() {
Thing<T> thing;
Thing2<T> thing2;
Verifier<T>::verify3(static_func3<T>);
Verifier<T>::verify3(&thing, &Thing<T>::member_func3);
Verifier<T>::verify3((const Thing<T>*)&thing, &Thing<T>::const_member_func3);
Verifier<T>::verify3((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func3);
Verifier<T>::verify3((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func3);
Verifier<T>::verify3(&thing2, &Thing2<T>::member_func3);
Verifier<T>::verify3(&bound_func3<T>, &thing);
Verifier<T>::verify3(&const_bound_func3<T>, (const Thing<T>*)&thing);
Verifier<T>::verify3(&volatile_bound_func3<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify3(&const_volatile_bound_func3<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify3(&bound_func3<T>, &thing2);
Verifier<T>::verify3(&void_func3<T>, &thing);
Verifier<T>::verify3(&const_void_func3<T>, (const Thing<T>*)&thing);
Verifier<T>::verify3(&volatile_void_func3<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify3(&const_volatile_void_func3<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify3(callback(static_func3<T>));
Callback<T(T, T, T)> cb(static_func3);
Verifier<T>::verify3(cb);
cb = static_func3;
Verifier<T>::verify3(cb);
cb.attach(&bound_func3<T>, &thing);
Verifier<T>::verify3(&cb, &Callback<T(T, T, T)>::call);
Verifier<T>::verify3(&Callback<T(T, T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch4() {
Thing<T> thing;
Thing2<T> thing2;
Verifier<T>::verify4(static_func4<T>);
Verifier<T>::verify4(&thing, &Thing<T>::member_func4);
Verifier<T>::verify4((const Thing<T>*)&thing, &Thing<T>::const_member_func4);
Verifier<T>::verify4((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func4);
Verifier<T>::verify4((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func4);
Verifier<T>::verify4(&thing2, &Thing2<T>::member_func4);
Verifier<T>::verify4(&bound_func4<T>, &thing);
Verifier<T>::verify4(&const_bound_func4<T>, (const Thing<T>*)&thing);
Verifier<T>::verify4(&volatile_bound_func4<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify4(&const_volatile_bound_func4<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify4(&bound_func4<T>, &thing2);
Verifier<T>::verify4(&void_func4<T>, &thing);
Verifier<T>::verify4(&const_void_func4<T>, (const Thing<T>*)&thing);
Verifier<T>::verify4(&volatile_void_func4<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify4(&const_volatile_void_func4<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify4(callback(static_func4<T>));
Callback<T(T, T, T, T)> cb(static_func4);
Verifier<T>::verify4(cb);
cb = static_func4;
Verifier<T>::verify4(cb);
cb.attach(&bound_func4<T>, &thing);
Verifier<T>::verify4(&cb, &Callback<T(T, T, T, T)>::call);
Verifier<T>::verify4(&Callback<T(T, T, T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch5() {
Thing<T> thing;
Thing2<T> thing2;
Verifier<T>::verify5(static_func5<T>);
Verifier<T>::verify5(&thing, &Thing<T>::member_func5);
Verifier<T>::verify5((const Thing<T>*)&thing, &Thing<T>::const_member_func5);
Verifier<T>::verify5((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func5);
Verifier<T>::verify5((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func5);
Verifier<T>::verify5(&thing2, &Thing2<T>::member_func5);
Verifier<T>::verify5(&bound_func5<T>, &thing);
Verifier<T>::verify5(&const_bound_func5<T>, (const Thing<T>*)&thing);
Verifier<T>::verify5(&volatile_bound_func5<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify5(&const_volatile_bound_func5<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify5(&bound_func5<T>, &thing2);
Verifier<T>::verify5(&void_func5<T>, &thing);
Verifier<T>::verify5(&const_void_func5<T>, (const Thing<T>*)&thing);
Verifier<T>::verify5(&volatile_void_func5<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify5(&const_volatile_void_func5<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify5(callback(static_func5<T>));
Callback<T(T, T, T, T, T)> cb(static_func5);
Verifier<T>::verify5(cb);
cb = static_func5;
Verifier<T>::verify5(cb);
cb.attach(&bound_func5<T>, &thing);
Verifier<T>::verify5(&cb, &Callback<T(T, T, T, T, T)>::call);
Verifier<T>::verify5(&Callback<T(T, T, T, T, T)>::thunk, (void*)&cb);
}
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(10, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Testing callbacks with 0 ints", test_dispatch0<int>),
Case("Testing callbacks with 1 ints", test_dispatch1<int>),
Case("Testing callbacks with 2 ints", test_dispatch2<int>),
Case("Testing callbacks with 3 ints", test_dispatch3<int>),
Case("Testing callbacks with 4 ints", test_dispatch4<int>),
Case("Testing callbacks with 5 ints", test_dispatch5<int>),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

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TESTS/mbed_functional/callback_big/main.cpp
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@ -1,351 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
// static functions
template <typename T>
T static_func0() { return 0; }
template <typename T>
T static_func1(T a0) { return 0 | a0; }
template <typename T>
T static_func2(T a0, T a1) { return 0 | a0 | a1; }
template <typename T>
T static_func3(T a0, T a1, T a2) { return 0 | a0 | a1 | a2; }
template <typename T>
T static_func4(T a0, T a1, T a2, T a3) { return 0 | a0 | a1 | a2 | a3; }
template <typename T>
T static_func5(T a0, T a1, T a2, T a3, T a4) { return 0 | a0 | a1 | a2 | a3 | a4; }
// class functions
template <typename T>
struct Thing {
T t;
Thing() : t(0x80) {}
T member_func0() { return t; }
T member_func1(T a0) { return t | a0; }
T member_func2(T a0, T a1) { return t | a0 | a1; }
T member_func3(T a0, T a1, T a2) { return t | a0 | a1 | a2; }
T member_func4(T a0, T a1, T a2, T a3) { return t | a0 | a1 | a2 | a3; }
T member_func5(T a0, T a1, T a2, T a3, T a4) { return t | a0 | a1 | a2 | a3 | a4; }
T const_member_func0() const { return t; }
T const_member_func1(T a0) const { return t | a0; }
T const_member_func2(T a0, T a1) const { return t | a0 | a1; }
T const_member_func3(T a0, T a1, T a2) const { return t | a0 | a1 | a2; }
T const_member_func4(T a0, T a1, T a2, T a3) const { return t | a0 | a1 | a2 | a3; }
T const_member_func5(T a0, T a1, T a2, T a3, T a4) const { return t | a0 | a1 | a2 | a3 | a4; }
T volatile_member_func0() volatile { return t; }
T volatile_member_func1(T a0) volatile { return t | a0; }
T volatile_member_func2(T a0, T a1) volatile { return t | a0 | a1; }
T volatile_member_func3(T a0, T a1, T a2) volatile { return t | a0 | a1 | a2; }
T volatile_member_func4(T a0, T a1, T a2, T a3) volatile { return t | a0 | a1 | a2 | a3; }
T volatile_member_func5(T a0, T a1, T a2, T a3, T a4) volatile { return t | a0 | a1 | a2 | a3 | a4; }
T const_volatile_member_func0() const volatile { return t; }
T const_volatile_member_func1(T a0) const volatile { return t | a0; }
T const_volatile_member_func2(T a0, T a1) const volatile { return t | a0 | a1; }
T const_volatile_member_func3(T a0, T a1, T a2) const volatile { return t | a0 | a1 | a2; }
T const_volatile_member_func4(T a0, T a1, T a2, T a3) const volatile { return t | a0 | a1 | a2 | a3; }
T const_volatile_member_func5(T a0, T a1, T a2, T a3, T a4) const volatile { return t | a0 | a1 | a2 | a3 | a4; }
};
// bound functions
template <typename T>
T bound_func0(Thing<T> *t) { return t->t; }
template <typename T>
T bound_func1(Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T bound_func2(Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T bound_func3(Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T bound_func4(Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T bound_func5(Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// const bound functions
template <typename T>
T const_func0(const Thing<T> *t) { return t->t; }
template <typename T>
T const_func1(const Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T const_func2(const Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T const_func3(const Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T const_func4(const Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_func5(const Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// volatile bound functions
template <typename T>
T volatile_func0(volatile Thing<T> *t) { return t->t; }
template <typename T>
T volatile_func1(volatile Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T volatile_func2(volatile Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T volatile_func3(volatile Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T volatile_func4(volatile Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T volatile_func5(volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// const volatile bound functions
template <typename T>
T const_volatile_func0(const volatile Thing<T> *t) { return t->t; }
template <typename T>
T const_volatile_func1(const volatile Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T const_volatile_func2(const volatile Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T const_volatile_func3(const volatile Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T const_volatile_func4(const volatile Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_volatile_func5(const volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// function call and result verification
template <typename T>
struct Verifier {
static void verify0(Callback<T()> func) {
T result = func();
TEST_ASSERT_EQUAL(result, 0x00);
}
template <typename O, typename M>
static void verify0(O *obj, M method) {
Callback<T()> func(obj, method);
T result = func();
TEST_ASSERT_EQUAL(result, 0x80);
}
static void verify1(Callback<T(T)> func) {
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0));
}
template <typename O, typename M>
static void verify1(O *obj, M method) {
Callback<T(T)> func(obj, method);
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0));
}
static void verify2(Callback<T(T, T)> func) {
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1));
}
template <typename O, typename M>
static void verify2(O *obj, M method) {
Callback<T(T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1));
}
static void verify3(Callback<T(T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2));
}
template <typename O, typename M>
static void verify3(O *obj, M method) {
Callback<T(T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2));
}
static void verify4(Callback<T(T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
template <typename O, typename M>
static void verify4(O *obj, M method) {
Callback<T(T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
static void verify5(Callback<T(T, T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
template <typename O, typename M>
static void verify5(O *obj, M method) {
Callback<T(T, T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
};
// test dispatch
template <typename T>
void test_dispatch0() {
Thing<T> thing;
Verifier<T>::verify0(static_func0<T>);
Verifier<T>::verify0(&thing, &Thing<T>::member_func0);
Verifier<T>::verify0((const Thing<T>*)&thing, &Thing<T>::const_member_func0);
Verifier<T>::verify0((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func0);
Verifier<T>::verify0((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func0);
Verifier<T>::verify0(&bound_func0<T>, &thing);
Verifier<T>::verify0(&const_func0<T>, (const Thing<T>*)&thing);
Verifier<T>::verify0(&volatile_func0<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify0(&const_volatile_func0<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify0(callback(static_func0<T>));
Callback<T()> cb(static_func0);
Verifier<T>::verify0(cb);
cb = static_func0;
Verifier<T>::verify0(cb);
cb.attach(&bound_func0<T>, &thing);
Verifier<T>::verify0(&cb, &Callback<T()>::call);
Verifier<T>::verify0(&Callback<T()>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch1() {
Thing<T> thing;
Verifier<T>::verify1(static_func1<T>);
Verifier<T>::verify1(&thing, &Thing<T>::member_func1);
Verifier<T>::verify1((const Thing<T>*)&thing, &Thing<T>::const_member_func1);
Verifier<T>::verify1((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func1);
Verifier<T>::verify1((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func1);
Verifier<T>::verify1(&bound_func1<T>, &thing);
Verifier<T>::verify1(&const_func1<T>, (const Thing<T>*)&thing);
Verifier<T>::verify1(&volatile_func1<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify1(&const_volatile_func1<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify1(callback(static_func1<T>));
Callback<T(T)> cb(static_func1);
Verifier<T>::verify1(cb);
cb = static_func1;
Verifier<T>::verify1(cb);
cb.attach(&bound_func1<T>, &thing);
Verifier<T>::verify1(&cb, &Callback<T(T)>::call);
Verifier<T>::verify1(&Callback<T(T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch2() {
Thing<T> thing;
Verifier<T>::verify2(static_func2<T>);
Verifier<T>::verify2(&thing, &Thing<T>::member_func2);
Verifier<T>::verify2((const Thing<T>*)&thing, &Thing<T>::const_member_func2);
Verifier<T>::verify2((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func2);
Verifier<T>::verify2((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func2);
Verifier<T>::verify2(&bound_func2<T>, &thing);
Verifier<T>::verify2(&const_func2<T>, (const Thing<T>*)&thing);
Verifier<T>::verify2(&volatile_func2<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify2(&const_volatile_func2<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify2(callback(static_func2<T>));
Callback<T(T, T)> cb(static_func2);
Verifier<T>::verify2(cb);
cb = static_func2;
Verifier<T>::verify2(cb);
cb.attach(&bound_func2<T>, &thing);
Verifier<T>::verify2(&cb, &Callback<T(T, T)>::call);
Verifier<T>::verify2(&Callback<T(T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch3() {
Thing<T> thing;
Verifier<T>::verify3(static_func3<T>);
Verifier<T>::verify3(&thing, &Thing<T>::member_func3);
Verifier<T>::verify3((const Thing<T>*)&thing, &Thing<T>::const_member_func3);
Verifier<T>::verify3((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func3);
Verifier<T>::verify3((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func3);
Verifier<T>::verify3(&bound_func3<T>, &thing);
Verifier<T>::verify3(&const_func3<T>, (const Thing<T>*)&thing);
Verifier<T>::verify3(&volatile_func3<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify3(&const_volatile_func3<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify3(callback(static_func3<T>));
Callback<T(T, T, T)> cb(static_func3);
Verifier<T>::verify3(cb);
cb = static_func3;
Verifier<T>::verify3(cb);
cb.attach(&bound_func3<T>, &thing);
Verifier<T>::verify3(&cb, &Callback<T(T, T, T)>::call);
Verifier<T>::verify3(&Callback<T(T, T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch4() {
Thing<T> thing;
Verifier<T>::verify4(static_func4<T>);
Verifier<T>::verify4(&thing, &Thing<T>::member_func4);
Verifier<T>::verify4((const Thing<T>*)&thing, &Thing<T>::const_member_func4);
Verifier<T>::verify4((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func4);
Verifier<T>::verify4((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func4);
Verifier<T>::verify4(&bound_func4<T>, &thing);
Verifier<T>::verify4(&const_func4<T>, (const Thing<T>*)&thing);
Verifier<T>::verify4(&volatile_func4<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify4(&const_volatile_func4<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify4(callback(static_func4<T>));
Callback<T(T, T, T, T)> cb(static_func4);
Verifier<T>::verify4(cb);
cb = static_func4;
Verifier<T>::verify4(cb);
cb.attach(&bound_func4<T>, &thing);
Verifier<T>::verify4(&cb, &Callback<T(T, T, T, T)>::call);
Verifier<T>::verify4(&Callback<T(T, T, T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch5() {
Thing<T> thing;
Verifier<T>::verify5(static_func5<T>);
Verifier<T>::verify5(&thing, &Thing<T>::member_func5);
Verifier<T>::verify5((const Thing<T>*)&thing, &Thing<T>::const_member_func5);
Verifier<T>::verify5((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func5);
Verifier<T>::verify5((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func5);
Verifier<T>::verify5(&bound_func5<T>, &thing);
Verifier<T>::verify5(&const_func5<T>, (const Thing<T>*)&thing);
Verifier<T>::verify5(&volatile_func5<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify5(&const_volatile_func5<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify5(callback(static_func5<T>));
Callback<T(T, T, T, T, T)> cb(static_func5);
Verifier<T>::verify5(cb);
cb = static_func5;
Verifier<T>::verify5(cb);
cb.attach(&bound_func5<T>, &thing);
Verifier<T>::verify5(&cb, &Callback<T(T, T, T, T, T)>::call);
Verifier<T>::verify5(&Callback<T(T, T, T, T, T)>::thunk, (void*)&cb);
}
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(10, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Testing callbacks with 0 uint64s", test_dispatch0<uint64_t>),
Case("Testing callbacks with 1 uint64s", test_dispatch1<uint64_t>),
Case("Testing callbacks with 2 uint64s", test_dispatch2<uint64_t>),
Case("Testing callbacks with 3 uint64s", test_dispatch3<uint64_t>),
Case("Testing callbacks with 4 uint64s", test_dispatch4<uint64_t>),
Case("Testing callbacks with 5 uint64s", test_dispatch5<uint64_t>),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

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TESTS/mbed_functional/callback_small/main.cpp
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@ -1,351 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
// static functions
template <typename T>
T static_func0() { return 0; }
template <typename T>
T static_func1(T a0) { return 0 | a0; }
template <typename T>
T static_func2(T a0, T a1) { return 0 | a0 | a1; }
template <typename T>
T static_func3(T a0, T a1, T a2) { return 0 | a0 | a1 | a2; }
template <typename T>
T static_func4(T a0, T a1, T a2, T a3) { return 0 | a0 | a1 | a2 | a3; }
template <typename T>
T static_func5(T a0, T a1, T a2, T a3, T a4) { return 0 | a0 | a1 | a2 | a3 | a4; }
// class functions
template <typename T>
struct Thing {
T t;
Thing() : t(0x80) {}
T member_func0() { return t; }
T member_func1(T a0) { return t | a0; }
T member_func2(T a0, T a1) { return t | a0 | a1; }
T member_func3(T a0, T a1, T a2) { return t | a0 | a1 | a2; }
T member_func4(T a0, T a1, T a2, T a3) { return t | a0 | a1 | a2 | a3; }
T member_func5(T a0, T a1, T a2, T a3, T a4) { return t | a0 | a1 | a2 | a3 | a4; }
T const_member_func0() const { return t; }
T const_member_func1(T a0) const { return t | a0; }
T const_member_func2(T a0, T a1) const { return t | a0 | a1; }
T const_member_func3(T a0, T a1, T a2) const { return t | a0 | a1 | a2; }
T const_member_func4(T a0, T a1, T a2, T a3) const { return t | a0 | a1 | a2 | a3; }
T const_member_func5(T a0, T a1, T a2, T a3, T a4) const { return t | a0 | a1 | a2 | a3 | a4; }
T volatile_member_func0() volatile { return t; }
T volatile_member_func1(T a0) volatile { return t | a0; }
T volatile_member_func2(T a0, T a1) volatile { return t | a0 | a1; }
T volatile_member_func3(T a0, T a1, T a2) volatile { return t | a0 | a1 | a2; }
T volatile_member_func4(T a0, T a1, T a2, T a3) volatile { return t | a0 | a1 | a2 | a3; }
T volatile_member_func5(T a0, T a1, T a2, T a3, T a4) volatile { return t | a0 | a1 | a2 | a3 | a4; }
T const_volatile_member_func0() const volatile { return t; }
T const_volatile_member_func1(T a0) const volatile { return t | a0; }
T const_volatile_member_func2(T a0, T a1) const volatile { return t | a0 | a1; }
T const_volatile_member_func3(T a0, T a1, T a2) const volatile { return t | a0 | a1 | a2; }
T const_volatile_member_func4(T a0, T a1, T a2, T a3) const volatile { return t | a0 | a1 | a2 | a3; }
T const_volatile_member_func5(T a0, T a1, T a2, T a3, T a4) const volatile { return t | a0 | a1 | a2 | a3 | a4; }
};
// bound functions
template <typename T>
T bound_func0(Thing<T> *t) { return t->t; }
template <typename T>
T bound_func1(Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T bound_func2(Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T bound_func3(Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T bound_func4(Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T bound_func5(Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// const bound functions
template <typename T>
T const_func0(const Thing<T> *t) { return t->t; }
template <typename T>
T const_func1(const Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T const_func2(const Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T const_func3(const Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T const_func4(const Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_func5(const Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// volatile bound functions
template <typename T>
T volatile_func0(volatile Thing<T> *t) { return t->t; }
template <typename T>
T volatile_func1(volatile Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T volatile_func2(volatile Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T volatile_func3(volatile Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T volatile_func4(volatile Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T volatile_func5(volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// const volatile bound functions
template <typename T>
T const_volatile_func0(const volatile Thing<T> *t) { return t->t; }
template <typename T>
T const_volatile_func1(const volatile Thing<T> *t, T a0) { return t->t | a0; }
template <typename T>
T const_volatile_func2(const volatile Thing<T> *t, T a0, T a1) { return t->t | a0 | a1; }
template <typename T>
T const_volatile_func3(const volatile Thing<T> *t, T a0, T a1, T a2) { return t->t | a0 | a1 | a2; }
template <typename T>
T const_volatile_func4(const volatile Thing<T> *t, T a0, T a1, T a2, T a3) { return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_volatile_func5(const volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4) { return t->t | a0 | a1 | a2 | a3 | a4; }
// function call and result verification
template <typename T>
struct Verifier {
static void verify0(Callback<T()> func) {
T result = func();
TEST_ASSERT_EQUAL(result, 0x00);
}
template <typename O, typename M>
static void verify0(O *obj, M method) {
Callback<T()> func(obj, method);
T result = func();
TEST_ASSERT_EQUAL(result, 0x80);
}
static void verify1(Callback<T(T)> func) {
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0));
}
template <typename O, typename M>
static void verify1(O *obj, M method) {
Callback<T(T)> func(obj, method);
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0));
}
static void verify2(Callback<T(T, T)> func) {
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1));
}
template <typename O, typename M>
static void verify2(O *obj, M method) {
Callback<T(T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1));
}
static void verify3(Callback<T(T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2));
}
template <typename O, typename M>
static void verify3(O *obj, M method) {
Callback<T(T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2));
}
static void verify4(Callback<T(T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
template <typename O, typename M>
static void verify4(O *obj, M method) {
Callback<T(T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
static void verify5(Callback<T(T, T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
template <typename O, typename M>
static void verify5(O *obj, M method) {
Callback<T(T, T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
};
// test dispatch
template <typename T>
void test_dispatch0() {
Thing<T> thing;
Verifier<T>::verify0(static_func0<T>);
Verifier<T>::verify0(&thing, &Thing<T>::member_func0);
Verifier<T>::verify0((const Thing<T>*)&thing, &Thing<T>::const_member_func0);
Verifier<T>::verify0((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func0);
Verifier<T>::verify0((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func0);
Verifier<T>::verify0(&bound_func0<T>, &thing);
Verifier<T>::verify0(&const_func0<T>, (const Thing<T>*)&thing);
Verifier<T>::verify0(&volatile_func0<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify0(&const_volatile_func0<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify0(callback(static_func0<T>));
Callback<T()> cb(static_func0);
Verifier<T>::verify0(cb);
cb = static_func0;
Verifier<T>::verify0(cb);
cb.attach(&bound_func0<T>, &thing);
Verifier<T>::verify0(&cb, &Callback<T()>::call);
Verifier<T>::verify0(&Callback<T()>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch1() {
Thing<T> thing;
Verifier<T>::verify1(static_func1<T>);
Verifier<T>::verify1(&thing, &Thing<T>::member_func1);
Verifier<T>::verify1((const Thing<T>*)&thing, &Thing<T>::const_member_func1);
Verifier<T>::verify1((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func1);
Verifier<T>::verify1((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func1);
Verifier<T>::verify1(&bound_func1<T>, &thing);
Verifier<T>::verify1(&const_func1<T>, (const Thing<T>*)&thing);
Verifier<T>::verify1(&volatile_func1<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify1(&const_volatile_func1<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify1(callback(static_func1<T>));
Callback<T(T)> cb(static_func1);
Verifier<T>::verify1(cb);
cb = static_func1;
Verifier<T>::verify1(cb);
cb.attach(&bound_func1<T>, &thing);
Verifier<T>::verify1(&cb, &Callback<T(T)>::call);
Verifier<T>::verify1(&Callback<T(T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch2() {
Thing<T> thing;
Verifier<T>::verify2(static_func2<T>);
Verifier<T>::verify2(&thing, &Thing<T>::member_func2);
Verifier<T>::verify2((const Thing<T>*)&thing, &Thing<T>::const_member_func2);
Verifier<T>::verify2((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func2);
Verifier<T>::verify2((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func2);
Verifier<T>::verify2(&bound_func2<T>, &thing);
Verifier<T>::verify2(&const_func2<T>, (const Thing<T>*)&thing);
Verifier<T>::verify2(&volatile_func2<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify2(&const_volatile_func2<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify2(callback(static_func2<T>));
Callback<T(T, T)> cb(static_func2);
Verifier<T>::verify2(cb);
cb = static_func2;
Verifier<T>::verify2(cb);
cb.attach(&bound_func2<T>, &thing);
Verifier<T>::verify2(&cb, &Callback<T(T, T)>::call);
Verifier<T>::verify2(&Callback<T(T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch3() {
Thing<T> thing;
Verifier<T>::verify3(static_func3<T>);
Verifier<T>::verify3(&thing, &Thing<T>::member_func3);
Verifier<T>::verify3((const Thing<T>*)&thing, &Thing<T>::const_member_func3);
Verifier<T>::verify3((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func3);
Verifier<T>::verify3((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func3);
Verifier<T>::verify3(&bound_func3<T>, &thing);
Verifier<T>::verify3(&const_func3<T>, (const Thing<T>*)&thing);
Verifier<T>::verify3(&volatile_func3<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify3(&const_volatile_func3<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify3(callback(static_func3<T>));
Callback<T(T, T, T)> cb(static_func3);
Verifier<T>::verify3(cb);
cb = static_func3;
Verifier<T>::verify3(cb);
cb.attach(&bound_func3<T>, &thing);
Verifier<T>::verify3(&cb, &Callback<T(T, T, T)>::call);
Verifier<T>::verify3(&Callback<T(T, T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch4() {
Thing<T> thing;
Verifier<T>::verify4(static_func4<T>);
Verifier<T>::verify4(&thing, &Thing<T>::member_func4);
Verifier<T>::verify4((const Thing<T>*)&thing, &Thing<T>::const_member_func4);
Verifier<T>::verify4((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func4);
Verifier<T>::verify4((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func4);
Verifier<T>::verify4(&bound_func4<T>, &thing);
Verifier<T>::verify4(&const_func4<T>, (const Thing<T>*)&thing);
Verifier<T>::verify4(&volatile_func4<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify4(&const_volatile_func4<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify4(callback(static_func4<T>));
Callback<T(T, T, T, T)> cb(static_func4);
Verifier<T>::verify4(cb);
cb = static_func4;
Verifier<T>::verify4(cb);
cb.attach(&bound_func4<T>, &thing);
Verifier<T>::verify4(&cb, &Callback<T(T, T, T, T)>::call);
Verifier<T>::verify4(&Callback<T(T, T, T, T)>::thunk, (void*)&cb);
}
template <typename T>
void test_dispatch5() {
Thing<T> thing;
Verifier<T>::verify5(static_func5<T>);
Verifier<T>::verify5(&thing, &Thing<T>::member_func5);
Verifier<T>::verify5((const Thing<T>*)&thing, &Thing<T>::const_member_func5);
Verifier<T>::verify5((volatile Thing<T>*)&thing, &Thing<T>::volatile_member_func5);
Verifier<T>::verify5((const volatile Thing<T>*)&thing, &Thing<T>::const_volatile_member_func5);
Verifier<T>::verify5(&bound_func5<T>, &thing);
Verifier<T>::verify5(&const_func5<T>, (const Thing<T>*)&thing);
Verifier<T>::verify5(&volatile_func5<T>, (volatile Thing<T>*)&thing);
Verifier<T>::verify5(&const_volatile_func5<T>, (const volatile Thing<T>*)&thing);
Verifier<T>::verify5(callback(static_func5<T>));
Callback<T(T, T, T, T, T)> cb(static_func5);
Verifier<T>::verify5(cb);
cb = static_func5;
Verifier<T>::verify5(cb);
cb.attach(&bound_func5<T>, &thing);
Verifier<T>::verify5(&cb, &Callback<T(T, T, T, T, T)>::call);
Verifier<T>::verify5(&Callback<T(T, T, T, T, T)>::thunk, (void*)&cb);
}
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(10, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Testing callbacks with 0 uchars", test_dispatch0<unsigned char>),
Case("Testing callbacks with 1 uchars", test_dispatch1<unsigned char>),
Case("Testing callbacks with 2 uchars", test_dispatch2<unsigned char>),
Case("Testing callbacks with 3 uchars", test_dispatch3<unsigned char>),
Case("Testing callbacks with 4 uchars", test_dispatch4<unsigned char>),
Case("Testing callbacks with 5 uchars", test_dispatch5<unsigned char>),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

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@ -1,347 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
// static functions
template <typename T>
T static_func0()
{ return 0; }
template <typename T>
T static_func1(T a0)
{ return 0 | a0; }
template <typename T>
T static_func2(T a0, T a1)
{ return 0 | a0 | a1; }
template <typename T>
T static_func3(T a0, T a1, T a2)
{ return 0 | a0 | a1 | a2; }
template <typename T>
T static_func4(T a0, T a1, T a2, T a3)
{ return 0 | a0 | a1 | a2 | a3; }
template <typename T>
T static_func5(T a0, T a1, T a2, T a3, T a4)
{ return 0 | a0 | a1 | a2 | a3 | a4; }
// class functions
template <typename T>
struct Thing {
T t;
Thing() : t(0x80) {}
T member_func0()
{ return t; }
T member_func1(T a0)
{ return t | a0; }
T member_func2(T a0, T a1)
{ return t | a0 | a1; }
T member_func3(T a0, T a1, T a2)
{ return t | a0 | a1 | a2; }
T member_func4(T a0, T a1, T a2, T a3)
{ return t | a0 | a1 | a2 | a3; }
T member_func5(T a0, T a1, T a2, T a3, T a4)
{ return t | a0 | a1 | a2 | a3 | a4; }
T const_member_func0() const
{ return t; }
T const_member_func1(T a0) const
{ return t | a0; }
T const_member_func2(T a0, T a1) const
{ return t | a0 | a1; }
T const_member_func3(T a0, T a1, T a2) const
{ return t | a0 | a1 | a2; }
T const_member_func4(T a0, T a1, T a2, T a3) const
{ return t | a0 | a1 | a2 | a3; }
T const_member_func5(T a0, T a1, T a2, T a3, T a4) const
{ return t | a0 | a1 | a2 | a3 | a4; }
T volatile_member_func0() volatile
{ return t; }
T volatile_member_func1(T a0) volatile
{ return t | a0; }
T volatile_member_func2(T a0, T a1) volatile
{ return t | a0 | a1; }
T volatile_member_func3(T a0, T a1, T a2) volatile
{ return t | a0 | a1 | a2; }
T volatile_member_func4(T a0, T a1, T a2, T a3) volatile
{ return t | a0 | a1 | a2 | a3; }
T volatile_member_func5(T a0, T a1, T a2, T a3, T a4) volatile
{ return t | a0 | a1 | a2 | a3 | a4; }
T const_volatile_member_func0() const volatile
{ return t; }
T const_volatile_member_func1(T a0) const volatile
{ return t | a0; }
T const_volatile_member_func2(T a0, T a1) const volatile
{ return t | a0 | a1; }
T const_volatile_member_func3(T a0, T a1, T a2) const volatile
{ return t | a0 | a1 | a2; }
T const_volatile_member_func4(T a0, T a1, T a2, T a3) const volatile
{ return t | a0 | a1 | a2 | a3; }
T const_volatile_member_func5(T a0, T a1, T a2, T a3, T a4) const volatile
{ return t | a0 | a1 | a2 | a3 | a4; }
};
// bound functions
template <typename T>
T bound_func0(Thing<T> *t)
{ return t->t; }
template <typename T>
T bound_func1(Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T bound_func2(Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T bound_func3(Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T bound_func4(Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T bound_func5(Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_bound_func0(const Thing<T> *t)
{ return t->t; }
template <typename T>
T const_bound_func1(const Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T const_bound_func2(const Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T const_bound_func3(const Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T const_bound_func4(const Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_bound_func5(const Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T volatile_bound_func0(volatile Thing<T> *t)
{ return t->t; }
template <typename T>
T volatile_bound_func1(volatile Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T volatile_bound_func2(volatile Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T volatile_bound_func3(volatile Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T volatile_bound_func4(volatile Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T volatile_bound_func5(volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_volatile_bound_func0(const volatile Thing<T> *t)
{ return t->t; }
template <typename T>
T const_volatile_bound_func1(const volatile Thing<T> *t, T a0)
{ return t->t | a0; }
template <typename T>
T const_volatile_bound_func2(const volatile Thing<T> *t, T a0, T a1)
{ return t->t | a0 | a1; }
template <typename T>
T const_volatile_bound_func3(const volatile Thing<T> *t, T a0, T a1, T a2)
{ return t->t | a0 | a1 | a2; }
template <typename T>
T const_volatile_bound_func4(const volatile Thing<T> *t, T a0, T a1, T a2, T a3)
{ return t->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_volatile_bound_func5(const volatile Thing<T> *t, T a0, T a1, T a2, T a3, T a4)
{ return t->t | a0 | a1 | a2 | a3 | a4; }
// void functions
template <typename T>
T void_func0(void *t)
{ return static_cast<Thing<T>*>(t)->t; }
template <typename T>
T void_func1(void *t, T a0)
{ return static_cast<Thing<T>*>(t)->t | a0; }
template <typename T>
T void_func2(void *t, T a0, T a1)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T void_func3(void *t, T a0, T a1, T a2)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T void_func4(void *t, T a0, T a1, T a2, T a3)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T void_func5(void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_void_func0(const void *t)
{ return static_cast<const Thing<T>*>(t)->t; }
template <typename T>
T const_void_func1(const void *t, T a0)
{ return static_cast<const Thing<T>*>(t)->t | a0; }
template <typename T>
T const_void_func2(const void *t, T a0, T a1)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T const_void_func3(const void *t, T a0, T a1, T a2)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T const_void_func4(const void *t, T a0, T a1, T a2, T a3)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_void_func5(const void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<const Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T volatile_void_func0(volatile void *t)
{ return static_cast<volatile Thing<T>*>(t)->t; }
template <typename T>
T volatile_void_func1(volatile void *t, T a0)
{ return static_cast<volatile Thing<T>*>(t)->t | a0; }
template <typename T>
T volatile_void_func2(volatile void *t, T a0, T a1)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T volatile_void_func3(volatile void *t, T a0, T a1, T a2)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T volatile_void_func4(volatile void *t, T a0, T a1, T a2, T a3)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T volatile_void_func5(volatile void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
template <typename T>
T const_volatile_void_func0(const volatile void *t)
{ return static_cast<const volatile Thing<T>*>(t)->t; }
template <typename T>
T const_volatile_void_func1(const volatile void *t, T a0)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0; }
template <typename T>
T const_volatile_void_func2(const volatile void *t, T a0, T a1)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1; }
template <typename T>
T const_volatile_void_func3(const volatile void *t, T a0, T a1, T a2)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1 | a2; }
template <typename T>
T const_volatile_void_func4(const volatile void *t, T a0, T a1, T a2, T a3)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3; }
template <typename T>
T const_volatile_void_func5(const volatile void *t, T a0, T a1, T a2, T a3, T a4)
{ return static_cast<const volatile Thing<T>*>(t)->t | a0 | a1 | a2 | a3 | a4; }
// function call and result verification
template <typename T>
struct Verifier {
static void verify0(Callback<T()> func) {
T result = func();
TEST_ASSERT_EQUAL(result, 0x00);
}
template <typename O, typename M>
static void verify0(O *obj, M method) {
Callback<T()> func(obj, method);
T result = func();
TEST_ASSERT_EQUAL(result, 0x80);
}
static void verify1(Callback<T(T)> func) {
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0));
}
template <typename O, typename M>
static void verify1(O *obj, M method) {
Callback<T(T)> func(obj, method);
T result = func((1 << 0));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0));
}
static void verify2(Callback<T(T, T)> func) {
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1));
}
template <typename O, typename M>
static void verify2(O *obj, M method) {
Callback<T(T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1));
}
static void verify3(Callback<T(T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2));
}
template <typename O, typename M>
static void verify3(O *obj, M method) {
Callback<T(T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2));
}
static void verify4(Callback<T(T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
template <typename O, typename M>
static void verify4(O *obj, M method) {
Callback<T(T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
}
static void verify5(Callback<T(T, T, T, T, T)> func) {
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x00 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
template <typename O, typename M>
static void verify5(O *obj, M method) {
Callback<T(T, T, T, T, T)> func(obj, method);
T result = func((1 << 0), (1 << 1), (1 << 2), (1 << 3), (1 << 4));
TEST_ASSERT_EQUAL(result, 0x80 | (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4));
}
};
// test dispatch
template <typename T>
void test_fparg1() {
Thing<T> thing;
FunctionPointerArg1<T,T> fp(static_func1<T>);
Verifier<T>::verify1(fp);
Verifier<T>::verify1(fp.get_function());
}
template <typename T>
void test_fparg0() {
Thing<T> thing;
FunctionPointerArg1<T,void> fp(static_func0<T>);
Verifier<T>::verify0(fp);
Verifier<T>::verify0(fp.get_function());
}
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(10, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Testing FunctionPointerArg1 compatibility", test_fparg1<int>),
Case("Testing FunctionPointer compatibility", test_fparg0<int>),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

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TESTS/mbed_hal/lp_ticker/main.cpp
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/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if !DEVICE_LOWPOWERTIMER
#error [NOT_SUPPORTED] Low power timer not supported for this target
#endif
#include "utest/utest.h"
#include "unity/unity.h"
#include "greentea-client/test_env.h"
#include "mbed.h"
#include "us_ticker_api.h"
#include "lp_ticker_api.h"
using namespace utest::v1;
volatile static bool complete;
static ticker_event_t delay_event;
static const ticker_data_t *lp_ticker_data = get_lp_ticker_data();
/* Timeouts are quite arbitrary due to large number of boards with varying level of accuracy */
#define LONG_TIMEOUT (100000)
#define SHORT_TIMEOUT (600)
void cb_done(uint32_t id) {
complete = true;
}
void lp_ticker_delay_us(uint32_t delay_us, uint32_t tolerance)
{
complete = false;
uint32_t delay_ts;
ticker_set_handler(lp_ticker_data, cb_done);
ticker_remove_event(lp_ticker_data, &delay_event);
delay_ts = lp_ticker_read() + delay_us;
timestamp_t start = us_ticker_read();
ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event);
while (!complete);
timestamp_t end = us_ticker_read();
TEST_ASSERT_UINT32_WITHIN(tolerance, delay_us, end - start);
TEST_ASSERT_TRUE(complete);
}
#if DEVICE_SLEEP
void lp_ticker_1s_deepsleep()
{
complete = false;
uint32_t delay_ts;
/*
* Since deepsleep() may shut down the UART peripheral, we wait for 10ms
* to allow for hardware serial buffers to completely flush.
* This should be replaced with a better function that checks if the
* hardware buffers are empty. However, such an API does not exist now,
* so we'll use the wait_ms() function for now.
*/
wait_ms(10);
ticker_set_handler(lp_ticker_data, cb_done);
ticker_remove_event(lp_ticker_data, &delay_event);
delay_ts = lp_ticker_read() + 1000000;
/*
* We use here lp_ticker_read() instead of us_ticker_read() for start and
* end because the microseconds timer might be disable during deepsleep.
*/
timestamp_t start = lp_ticker_read();
ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event);
deepsleep();
while (!complete);
timestamp_t end = lp_ticker_read();
TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
TEST_ASSERT_TRUE(complete);
}
void lp_ticker_1s_sleep()
{
complete = false;
uint32_t delay_ts;
ticker_set_handler(lp_ticker_data, cb_done);
ticker_remove_event(lp_ticker_data, &delay_event);
delay_ts = lp_ticker_read() + 1000000;
timestamp_t start = us_ticker_read();
ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event);
sleep();
while (!complete);
timestamp_t end = us_ticker_read();
TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
TEST_ASSERT_TRUE(complete);
}
#endif /* DEVICE_SLEEP */
void lp_ticker_500us(void)
{
lp_ticker_delay_us(500, SHORT_TIMEOUT);
}
void lp_ticker_1ms(void)
{
lp_ticker_delay_us(1000, SHORT_TIMEOUT);
}
void lp_ticker_1s(void)
{
lp_ticker_delay_us(1000000, LONG_TIMEOUT);
}
void lp_ticker_5s(void)
{
lp_ticker_delay_us(5000000, LONG_TIMEOUT);
}
utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
Case cases[] = {
Case("500us lp_ticker", lp_ticker_500us, greentea_failure_handler),
Case("1ms lp_ticker", lp_ticker_1ms, greentea_failure_handler),
Case("1s lp_ticker", lp_ticker_1s, greentea_failure_handler),
Case("5s lp_ticker", lp_ticker_5s, greentea_failure_handler),
#if DEVICE_SLEEP
Case("1s lp_ticker sleep", lp_ticker_1s_sleep, greentea_failure_handler),
Case("1s lp_ticker deepsleep", lp_ticker_1s_deepsleep, greentea_failure_handler),
#endif /* DEVICE_SLEEP */
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(20, "default_auto");
lp_ticker_data->interface->init();
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main() {
Harness::run(specification);
}

153
TESTS/mbedmicro-mbed/attributes/attributes.c
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#include "toolchain.h"
#include <stdio.h>
#include <stdint.h>
MBED_PACKED(struct) TestAttrPackedStruct1 {
char a;
int x;
};
typedef MBED_PACKED(struct) {
char a;
int x;
} TestAttrPackedStruct2;
int testPacked() {
int failed = 0;
if (sizeof(struct TestAttrPackedStruct1) != sizeof(int) + sizeof(char)) {
failed++;
}
if (sizeof(TestAttrPackedStruct2) != sizeof(int) + sizeof(char)) {
failed++;
}
return failed;
}
MBED_ALIGN(8) char a;
MBED_ALIGN(8) char b;
MBED_ALIGN(16) char c;
MBED_ALIGN(8) char d;
MBED_ALIGN(16) char e;
int testAlign() {
int failed = 0;
if(((uintptr_t)&a) & 0x7){
failed++;
}
if(((uintptr_t)&b) & 0x7){
failed++;
}
if(((uintptr_t)&c) & 0xf){
failed++;
}
if(((uintptr_t)&d) & 0x7){
failed++;
}
if(((uintptr_t)&e) & 0xf){
failed++;
}
return failed;
}
int testUnused1(MBED_UNUSED int arg) {
return 0;
}
int testUnused() {
return testUnused1(0);
}
int testWeak1();
int testWeak2();
MBED_WEAK int testWeak1() {
return 1;
}
int testWeak2() {
return 0;
}
int testWeak() {
return testWeak1() | testWeak2();
}
MBED_PURE int testPure1() {
return 0;
}
int testPure() {
return testPure1();
}
MBED_FORCEINLINE int testForceInline1() {
return 0;
}
int testForceInline() {
return testForceInline1();
}
MBED_NORETURN int testNoReturn1() {
while (1) {}
}
int testNoReturn() {
if (0) {
testNoReturn1();
}
return 0;
}
int testUnreachable1(int i) {
switch (i) {
case 0:
return 0;
}
MBED_UNREACHABLE;
}
int testUnreachable() {
return testUnreachable1(0);
}
MBED_DEPRECATED("this message should not be displayed")
void testDeprecatedUnused();
void testDeprecatedUnused() { }
MBED_DEPRECATED("this message should be displayed")
int testDeprecatedUsed();
int testDeprecatedUsed() {
return 0;
}
MBED_DEPRECATED_SINCE("mbed-os-3.14", "this message should not be displayed")
void testDeprecatedSinceUnused();
void testDeprecatedSinceUnused() { }
MBED_DEPRECATED_SINCE("mbed-os-3.14", "this message should be displayed")
int testDeprecatedSinceUsed();
int testDeprecatedSinceUsed() {
return 0;
}
int testDeprecated() {
return testDeprecatedUsed() + testDeprecatedSinceUsed();
}

53
TESTS/mbedmicro-mbed/attributes/main.cpp
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#include <stdio.h>
#include <stdint.h>
#include "toolchain.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
// Test functions declared as C functions to avoid issues with name mangling
extern "C" {
int testPacked();
int testAlign();
int testUnused();
int testWeak();
int testPure();
int testForceInline();
int testNoReturn();
int testUnreachable();
int testDeprecated();
}
// Test wrapper and test cases for utest
template <int (*F)()>
void test_wrapper() {
TEST_ASSERT_UNLESS(F());
}
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(5, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Testing PACKED attribute", test_wrapper<testPacked>),
Case("Testing ALIGN attribute", test_wrapper<testAlign>),
Case("Testing UNUSED attribute", test_wrapper<testUnused>),
Case("Testing WEAK attribute", test_wrapper<testWeak>),
Case("Testing PURE attribute", test_wrapper<testPure>),
Case("Testing FORCEINLINE attribute", test_wrapper<testForceInline>),
Case("Testing NORETURN attribute", test_wrapper<testNoReturn>),
Case("Testing UNREACHABLE attribute", test_wrapper<testUnreachable>),
Case("Testing DEPRECATED attribute", test_wrapper<testDeprecated>),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

10
TESTS/mbedmicro-mbed/attributes/weak.c
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#include "toolchain.h"
int testWeak1() {
return 0;
}
MBED_WEAK int testWeak2() {
return 1;
}

16
TESTS/mbedmicro-mbed/call_before_main/main.cpp
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#include "greentea-client/test_env.h"
namespace {
bool mbed_main_called = false;
}
extern "C" void mbed_main() {
printf("MBED: mbed_main() call before main()\r\n");
mbed_main_called = true;
}
int main() {
GREENTEA_SETUP(5, "default_auto");
printf("MBED: main() starts now!\r\n");
GREENTEA_TESTSUITE_RESULT(mbed_main_called);
}

86
TESTS/mbedmicro-mbed/cpp/main.cpp
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#include "greentea-client/test_env.h"
#define PATTERN_CHECK_VALUE 0xF0F0ADAD
class Test {
private:
const char* name;
const int pattern;
public:
Test(const char* _name, bool print_message=true) : name(_name), pattern(PATTERN_CHECK_VALUE) {
if (print_message) {
print("init");
}
}
void print(const char *message) {
printf("%s::%s\n", name, message);
}
bool check_init(void) {
bool result = (pattern == PATTERN_CHECK_VALUE);
print(result ? "check_init: OK" : "check_init: ERROR");
return result;
}
void stack_test(void) {
print("stack_test");
Test t("Stack");
t.hello();
}
void hello(void) {
print("hello");
}
~Test() {
print("destroy");
}
};
/* Check C++ startup initialisation */
Test s("Static", false);
/* EXPECTED OUTPUT:
*******************
Static::init
Static::stack_test
Stack::init
Stack::hello
Stack::destroy
Static::check_init: OK
Heap::init
Heap::hello
Heap::destroy
*******************/
int main (void) {
GREENTEA_SETUP(10, "default_auto");
bool result = true;
for (;;)
{
s.print("init");
// Global stack object simple test
s.stack_test();
if (s.check_init() == false)
{
result = false;
break;
}
// Heap test object simple test
Test *m = new Test("Heap");
m->hello();
if (m->check_init() == false)
{
result = false;
}
delete m;
break;
}
GREENTEA_TESTSUITE_RESULT(result);
}

41
TESTS/mbedmicro-mbed/div/main.cpp
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@ -1,41 +0,0 @@
#include <utility> // std::pair
#include "mbed.h"
#include "greentea-client/test_env.h"
uint32_t test_64(uint64_t ticks) {
ticks >>= 3; // divide by 8
if (ticks > 0xFFFFFFFF) {
ticks /= 3;
} else {
ticks = (ticks * 0x55555556) >> 32; // divide by 3
}
return (uint32_t)(0xFFFFFFFF & ticks);
}
const char *result_str(bool result) {
return result ? "[OK]" : "[FAIL]";
}
int main() {
GREENTEA_SETUP(5, "default_auto");
bool result = true;
{ // 0xFFFFFFFF * 8 = 0x7fffffff8
std::pair<uint32_t, uint64_t> values = std::make_pair(0x55555555, 0x7FFFFFFF8);
uint32_t test_ret = test_64(values.second);
bool test_res = values.first == test_ret;
result = result && test_res;
printf("64bit: 0x7FFFFFFF8: expected 0x%lX got 0x%lX ... %s\r\n", values.first, test_ret, result_str(test_res));
}
{ // 0xFFFFFFFF * 24 = 0x17ffffffe8
std::pair<uint32_t, uint64_t> values = std::make_pair(0xFFFFFFFF, 0x17FFFFFFE8);
uint32_t test_ret = test_64(values.second);
bool test_res = values.first == test_ret;
result = result && test_res;
printf("64bit: 0x17FFFFFFE8: expected 0x%lX got 0x%lX ... %s\r\n", values.first, test_ret, result_str(test_res));
}
GREENTEA_TESTSUITE_RESULT(result);
}

26
TESTS/mbedmicro-mbed/static_assert/main.cpp
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@ -1,26 +0,0 @@
#include <stdio.h>
#include <stdint.h>
#include "toolchain.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
void no_test() {}
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(5, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Compilation test", no_test),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

39
TESTS/mbedmicro-mbed/static_assert/test_c.c
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@ -1,39 +0,0 @@
#include "mbed_assert.h"
#define THE_ANSWER 42
// Tests for static asserts in different contexts
// multiple asserts are used to garuntee no conflicts occur in generated labels
// Test for static asserts in global context
MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
"An int must be larger than char");
MBED_STATIC_ASSERT(2 + 2 == 4,
"Hopefully the universe is mathematically consistent");
MBED_STATIC_ASSERT(THE_ANSWER == 42,
"Said Deep Thought, with infinite majesty and calm");
struct test {
int dummy;
// Test for static asserts in struct context
MBED_STRUCT_STATIC_ASSERT(sizeof(int) >= sizeof(char),
"An int must be larger than char");
MBED_STRUCT_STATIC_ASSERT(2 + 2 == 4,
"Hopefully the universe is mathematically consistent");
MBED_STRUCT_STATIC_ASSERT(THE_ANSWER == 42,
"Said Deep Thought, with infinite majesty and calm");
};
MBED_STATIC_ASSERT(sizeof(struct test) == sizeof(int),
"Static assertions should not change the size of a struct");
void doit_c(void) {
// Test for static asserts in function context
MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
"An int must be larger than char");
MBED_STATIC_ASSERT(2 + 2 == 4,
"Hopefully the universe is mathematically consistent");
MBED_STATIC_ASSERT(THE_ANSWER == 42,
"Said Deep Thought, with infinite majesty and calm");
}

46
TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp
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@ -1,46 +0,0 @@
#include "mbed_assert.h"
#define THE_ANSWER 42
// Tests for static asserts in different contexts
// multiple asserts are used to garuntee no conflicts occur in generated labels
// Test for static asserts in global context
MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
"An int must be larger than char");
MBED_STATIC_ASSERT(2 + 2 == 4,
"Hopefully the universe is mathematically consistent");
MBED_STATIC_ASSERT(THE_ANSWER == 42,
"Said Deep Thought, with infinite majesty and calm");
struct test {
int dummy;
// Test for static asserts in struct context
MBED_STRUCT_STATIC_ASSERT(sizeof(int) >= sizeof(char),
"An int must be larger than char");
MBED_STRUCT_STATIC_ASSERT(2 + 2 == 4,
"Hopefully the universe is mathematically consistent");
MBED_STRUCT_STATIC_ASSERT(THE_ANSWER == 42,
"Said Deep Thought, with infinite majesty and calm");
MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
"An int must be larger than char");
MBED_STATIC_ASSERT(2 + 2 == 4,
"Hopefully the universe is mathematically consistent");
MBED_STATIC_ASSERT(THE_ANSWER == 42,
"Said Deep Thought, with infinite majesty and calm");
};
MBED_STATIC_ASSERT(sizeof(struct test) == sizeof(int),
"Static assertions should not change the size of a struct");
void doit_c(void) {
// Test for static asserts in function context
MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
"An int must be larger than char");
MBED_STATIC_ASSERT(2 + 2 == 4,
"Hopefully the universe is mathematically consistent");
MBED_STATIC_ASSERT(THE_ANSWER == 42,
"Said Deep Thought, with infinite majesty and calm");
}

57
TESTS/mbedmicro-rtos-mbed/basic/main.cpp
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@ -1,57 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#if defined(TARGET_STM32F070RB) && defined(TOOLCHAIN_GCC)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif (defined(TARGET_EFM32HG_STK3400)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 512
#elif (defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32PG_STK3401)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif (defined(TARGET_EFM32GG_STK3700)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 1536
#elif defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832)
#define STACK_SIZE 768
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif
#define SIGNAL_PRINT_TICK 0x01
DigitalOut led1(LED1);
const int total_ticks = 10;
void print_tick_thread() {
for (int i = 0; i <= total_ticks; i++) {
Thread::signal_wait(SIGNAL_PRINT_TICK);
greentea_send_kv("tick", i);
led1 = !led1;
}
}
int main() {
GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto");
Thread tick_thread(osPriorityNormal, STACK_SIZE);
tick_thread.start(print_tick_thread);
for (int i = 0; i <= total_ticks; i++) {
Thread::wait(1000);
tick_thread.signal_set(SIGNAL_PRINT_TICK);
}
tick_thread.join();
GREENTEA_TESTSUITE_RESULT(1);
}

79
TESTS/mbedmicro-rtos-mbed/isr/main.cpp
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@ -1,79 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
#define QUEUE_SIZE 5
#define THREAD_DELAY 250
#define QUEUE_PUT_ISR_VALUE 128
#define QUEUE_PUT_THREAD_VALUE 127
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#if (defined(TARGET_EFM32HG_STK3400)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 512
#elif (defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32PG_STK3401)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif (defined(TARGET_EFM32GG_STK3700)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 1536
#elif defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832)
#define STACK_SIZE 768
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif
Queue<uint32_t, QUEUE_SIZE> queue;
DigitalOut myled(LED1);
void queue_isr() {
queue.put((uint32_t*)QUEUE_PUT_ISR_VALUE);
myled = !myled;
}
void queue_thread() {
while (true) {
queue.put((uint32_t*)QUEUE_PUT_THREAD_VALUE);
Thread::wait(THREAD_DELAY);
}
}
int main (void) {
GREENTEA_SETUP(20, "default_auto");
Thread thread(osPriorityNormal, STACK_SIZE);
thread.start(queue_thread);
Ticker ticker;
ticker.attach(queue_isr, 1.0);
int isr_puts_counter = 0;
bool result = true;
while (true) {
osEvent evt = queue.get();
if (evt.status != osEventMessage) {
printf("QUEUE_GET: Status(0x%02X) ... [FAIL]\r\n", evt.status);
result = false;
break;
} else {
printf("QUEUE_GET: Value(%u) ... [OK]\r\n", evt.value.v);
if (evt.value.v == QUEUE_PUT_ISR_VALUE) {
isr_puts_counter++;
}
if (isr_puts_counter >= QUEUE_SIZE) {
break;
}
}
}
GREENTEA_TESTSUITE_RESULT(result);
return 0;
}

85
TESTS/mbedmicro-rtos-mbed/mail/main.cpp
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@ -1,85 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
typedef struct {
float voltage; /* AD result of measured voltage */
float current; /* AD result of measured current */
uint32_t counter; /* A counter value */
} mail_t;
#define CREATE_VOLTAGE(COUNTER) (COUNTER * 0.1) * 33
#define CREATE_CURRENT(COUNTER) (COUNTER * 0.1) * 11
#define QUEUE_SIZE 16
#define QUEUE_PUT_DELAY 100
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#if (defined(TARGET_EFM32HG_STK3400)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 512
#elif (defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32PG_STK3401)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif (defined(TARGET_EFM32GG_STK3700)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 1536
#elif defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832)
#define STACK_SIZE 768
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif
Mail<mail_t, QUEUE_SIZE> mail_box;
void send_thread () {
static uint32_t i = 10;
while (true) {
i++; // fake data update
mail_t *mail = mail_box.alloc();
mail->voltage = CREATE_VOLTAGE(i);
mail->current = CREATE_CURRENT(i);
mail->counter = i;
mail_box.put(mail);
Thread::wait(QUEUE_PUT_DELAY);
}
}
int main (void) {
GREENTEA_SETUP(20, "default_auto");
Thread thread(osPriorityNormal, STACK_SIZE);
thread.start(send_thread);
bool result = true;
int result_counter = 0;
while (true) {
osEvent evt = mail_box.get();
if (evt.status == osEventMail) {
mail_t *mail = (mail_t*)evt.value.p;
const float expected_voltage = CREATE_VOLTAGE(mail->counter);
const float expected_current = CREATE_CURRENT(mail->counter);
// Check using macros if received values correspond to values sent via queue
bool expected_values = (expected_voltage == mail->voltage) &&
(expected_current == mail->current);
result = result && expected_values;
const char *result_msg = expected_values ? "OK" : "FAIL";
printf("%3d %.2fV %.2fA ... [%s]\r\n", mail->counter,
mail->voltage,
mail->current,
result_msg);
mail_box.free(mail);
if (result == false || ++result_counter == QUEUE_SIZE) {
break;
}
}
}
GREENTEA_TESTSUITE_RESULT(result);
return 0;
}

72
TESTS/mbedmicro-rtos-mbed/malloc/main.cpp
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@ -1,72 +0,0 @@
#include "mbed.h"
#include "test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
#define NUM_THREADS 5
#if defined(__CORTEX_A9)
#define THREAD_STACK_SIZE DEFAULT_STACK_SIZE
#else
#define THREAD_STACK_SIZE 256
#endif
DigitalOut led1(LED1);
volatile bool should_exit = false;
volatile bool allocation_failure = false;
void task_using_malloc(void)
{
void* data;
while (1) {
// Repeatedly allocate and free memory
data = malloc(100);
if (data != NULL) {
memset(data, 0, 100);
} else {
allocation_failure = true;
}
free(data);
if (should_exit) {
return;
}
}
}
int main()
{
Thread *thread_list[NUM_THREADS];
int test_time = 15;
GREENTEA_SETUP(20, "default_auto");
// Allocate threads for the test
for (int i = 0; i < NUM_THREADS; i++) {
thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE);
if (NULL == thread_list[i]) {
allocation_failure = true;
}
thread_list[i]->start(task_using_malloc);
}
// Give the test time to run
while (test_time) {
led1 = !led1;
Thread::wait(1000);
test_time--;
}
// Join and delete all threads
should_exit = 1;
for (int i = 0; i < NUM_THREADS; i++) {
if (NULL == thread_list[i]) {
continue;
}
thread_list[i]->join();
delete thread_list[i];
}
GREENTEA_TESTSUITE_RESULT(!allocation_failure);
}

112
TESTS/mbedmicro-rtos-mbed/mutex/main.cpp
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@ -1,112 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
#define THREAD_DELAY 50
#define SIGNALS_TO_EMIT 100
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#if defined(TARGET_STM32F334R8) && defined(TOOLCHAIN_IAR)
#define STACK_SIZE DEFAULT_STACK_SIZE/4
#elif defined(TARGET_STM32F070RB)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32F072RB)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32F302R8) && defined(TOOLCHAIN_IAR)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32F303K8) && defined(TOOLCHAIN_IAR)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32L073RZ)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif (defined(TARGET_EFM32HG_STK3400)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 512
#elif (defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32PG_STK3401)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif (defined(TARGET_EFM32GG_STK3700)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 1536
#elif (defined(TARGET_EFR32)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832)
#define STACK_SIZE 1024
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif
void print_char(char c = '*') {
printf("%c", c);
fflush(stdout);
}
Mutex stdio_mutex;
DigitalOut led(LED1);
volatile int change_counter = 0;
volatile bool changing_counter = false;
volatile bool mutex_defect = false;
bool manipulate_protected_zone(const int thread_delay) {
bool result = true;
stdio_mutex.lock(); // LOCK
if (changing_counter == true) {
// 'e' stands for error. If changing_counter is true access is not exclusively
print_char('e');
result = false;
mutex_defect = true;
}
changing_counter = true;
// Some action on protected
led = !led;
change_counter++;
print_char('.');
Thread::wait(thread_delay);
changing_counter = false;
stdio_mutex.unlock(); // UNLOCK
return result;
}
void test_thread(int const *thread_delay) {
while (true) {
manipulate_protected_zone(*thread_delay);
}
}
int main() {
GREENTEA_SETUP(20, "default_auto");
const int t1_delay = THREAD_DELAY * 1;
const int t2_delay = THREAD_DELAY * 2;
const int t3_delay = THREAD_DELAY * 3;
Thread t2(osPriorityNormal, STACK_SIZE);
Thread t3(osPriorityNormal, STACK_SIZE);
t2.start(callback(test_thread, &t2_delay));
t3.start(callback(test_thread, &t3_delay));
while (true) {
// Thread 1 action
Thread::wait(t1_delay);
manipulate_protected_zone(t1_delay);
if (change_counter >= SIGNALS_TO_EMIT or mutex_defect == true) {
t2.terminate();
t3.terminate();
break;
}
}
fflush(stdout);
GREENTEA_TESTSUITE_RESULT(!mutex_defect);
return 0;
}

87
TESTS/mbedmicro-rtos-mbed/queue/main.cpp
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@ -1,87 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
typedef struct {
float voltage; /* AD result of measured voltage */
float current; /* AD result of measured current */
uint32_t counter; /* A counter value */
} message_t;
#define CREATE_VOLTAGE(COUNTER) (COUNTER * 0.1) * 33
#define CREATE_CURRENT(COUNTER) (COUNTER * 0.1) * 11
#define QUEUE_SIZE 16
#define QUEUE_PUT_DELAY 100
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#if (defined(TARGET_EFM32HG_STK3400)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 512
#elif (defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32PG_STK3401)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif (defined(TARGET_EFM32GG_STK3700)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 1536
#elif defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832)
#define STACK_SIZE 768
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif
MemoryPool<message_t, QUEUE_SIZE> mpool;
Queue<message_t, QUEUE_SIZE> queue;
/* Send Thread */
void send_thread () {
static uint32_t i = 10;
while (true) {
i++; // Fake data update
message_t *message = mpool.alloc();
message->voltage = CREATE_VOLTAGE(i);
message->current = CREATE_CURRENT(i);
message->counter = i;
queue.put(message);
Thread::wait(QUEUE_PUT_DELAY);
}
}
int main (void) {
GREENTEA_SETUP(20, "default_auto");
Thread thread(osPriorityNormal, STACK_SIZE);
thread.start(send_thread);
bool result = true;
int result_counter = 0;
while (true) {
osEvent evt = queue.get();
if (evt.status == osEventMessage) {
message_t *message = (message_t*)evt.value.p;
const float expected_voltage = CREATE_VOLTAGE(message->counter);
const float expected_current = CREATE_CURRENT(message->counter);
// Check using macros if received values correspond to values sent via queue
bool expected_values = (expected_voltage == message->voltage) &&
(expected_current == message->current);
result = result && expected_values;
const char *result_msg = expected_values ? "OK" : "FAIL";
printf("%3d %.2fV %.2fA ... [%s]\r\n", message->counter,
message->voltage,
message->current,
result_msg);
mpool.free(message);
if (result == false || ++result_counter == QUEUE_SIZE) {
break;
}
}
}
GREENTEA_TESTSUITE_RESULT(result);
return 0;
}

104
TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp
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@ -1,104 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
#define THREAD_DELAY 75
#define SEMAPHORE_SLOTS 2
#define SEM_CHANGES 100
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#if defined(TARGET_STM32F334R8) && (defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_IAR))
#define STACK_SIZE DEFAULT_STACK_SIZE/4
#elif defined(TARGET_STM32F103RB)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32F070RB)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32F072RB)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32F302R8) && defined(TOOLCHAIN_IAR)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32L073RZ)
#define STACK_SIZE DEFAULT_STACK_SIZE/2
#elif defined(TARGET_STM32F303K8) && defined(TOOLCHAIN_IAR)
#define STACK_SIZE DEFAULT_STACK_SIZE/4
#elif (defined(TARGET_EFM32HG_STK3400)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 512
#elif (defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32PG_STK3401)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif (defined(TARGET_EFM32GG_STK3700)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 1536
#elif (defined(TARGET_EFR32)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832)
#define STACK_SIZE 768
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif
void print_char(char c = '*') {
printf("%c", c);
fflush(stdout);
}
Semaphore two_slots(SEMAPHORE_SLOTS);
volatile int change_counter = 0;
volatile int sem_counter = 0;
volatile bool sem_defect = false;
void test_thread(int const *delay) {
const int thread_delay = *delay;
while (true) {
two_slots.wait();
sem_counter++;
const bool sem_lock_failed = sem_counter > SEMAPHORE_SLOTS;
const char msg = sem_lock_failed ? 'e' : sem_counter + '0';
print_char(msg);
if (sem_lock_failed) {
sem_defect = true;
}
Thread::wait(thread_delay);
print_char('.');
sem_counter--;
change_counter++;
two_slots.release();
}
}
int main (void) {
GREENTEA_SETUP(20, "default_auto");
const int t1_delay = THREAD_DELAY * 1;
const int t2_delay = THREAD_DELAY * 2;
const int t3_delay = THREAD_DELAY * 3;
Thread t1(osPriorityNormal, STACK_SIZE);
Thread t2(osPriorityNormal, STACK_SIZE);
Thread t3(osPriorityNormal, STACK_SIZE);
t1.start(callback(test_thread, &t1_delay));
t2.start(callback(test_thread, &t2_delay));
t3.start(callback(test_thread, &t3_delay));
while (true) {
if (change_counter >= SEM_CHANGES or sem_defect == true) {
t1.terminate();
t2.terminate();
t3.terminate();
break;
}
}
fflush(stdout);
GREENTEA_TESTSUITE_RESULT(!sem_defect);
return 0;
}

64
TESTS/mbedmicro-rtos-mbed/signals/main.cpp
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#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
#define SIGNAL_SET_VALUE 0x01
const int SIGNALS_TO_EMIT = 100;
const int SIGNAL_HANDLE_DELEY = 25;
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#if (defined(TARGET_EFM32HG_STK3400)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 512
#elif (defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32PG_STK3401)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 768
#elif (defined(TARGET_EFM32GG_STK3700)) && !defined(TOOLCHAIN_ARM_MICRO)
#define STACK_SIZE 1536
#elif defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832)
#define STACK_SIZE 768
#elif defined(TARGET_XDOT_L151CC)
#define STACK_SIZE 1024
#else
#define STACK_SIZE DEFAULT_STACK_SIZE
#endif
DigitalOut led(LED1);
int signal_counter = 0;
void led_thread() {
while (true) {
// Signal flags that are reported as event are automatically cleared.
Thread::signal_wait(SIGNAL_SET_VALUE);
led = !led;
signal_counter++;
}
}
int main (void) {
GREENTEA_SETUP(20, "default_auto");
Thread thread(osPriorityNormal, STACK_SIZE);
thread.start(led_thread);
bool result = false;
printf("Handling %d signals...\r\n", SIGNALS_TO_EMIT);
while (true) {
Thread::wait(2 * SIGNAL_HANDLE_DELEY);
thread.signal_set(SIGNAL_SET_VALUE);
if (signal_counter == SIGNALS_TO_EMIT) {
printf("Handled %d signals\r\n", signal_counter);
result = true;
break;
}
}
GREENTEA_TESTSUITE_RESULT(result);
return 0;
}

51
TESTS/mbedmicro-rtos-mbed/threads/LockGuard.h
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@ -1,51 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBEDMICRO_RTOS_MBED_THREADS_LOCK_GUARD
#define MBEDMICRO_RTOS_MBED_THREADS_LOCK_GUARD
#include <rtos.h>
/**
* RAII mutex locker.
* The mutex pass in the constructor will be locked for the lifetime of
* the LockGuard instance.
*/
class LockGuard {
public:
/**
* Construct a LockGuard instance and ackire ownership of mutex in input.
* @param mutex The mutex to ackire ownership of.
*/
LockGuard(rtos::Mutex& mutex) : _mutex(mutex) {
_mutex.lock();
}
/**
* Destruct the lock and release the inner mutex.
*/
~LockGuard() {
_mutex.unlock();
}
private:
LockGuard(const LockGuard&);
LockGuard& operator=(const LockGuard&);
rtos::Mutex& _mutex;
};
#endif /* MBEDMICRO_RTOS_MBED_THREADS_LOCK_GUARD */

73
TESTS/mbedmicro-rtos-mbed/threads/SynchronizedIntegral.h
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@ -1,73 +0,0 @@
/*
* Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBEDMICRO_RTOS_MBED_THREADS_SYNCHRONIZED_INTEGRAL
#define MBEDMICRO_RTOS_MBED_THREADS_SYNCHRONIZED_INTEGRAL
#include <rtos.h>
#include "LockGuard.h"
/**
* Thread safe wrapper for integral types.
* @tparam T type of the integral
*/
template<typename T>
class SynchronizedIntegral {
public:
SynchronizedIntegral(T value) : _mutex(), _value(value) { }
// preincrement operator
T operator++() {
LockGuard lock(_mutex);
return ++_value;
}
// predecrement operator
T operator--() {
LockGuard lock(_mutex);
return --_value;
}
// post increment operator
T operator++(int) {
LockGuard lock(_mutex);
return _value++;
}
// post decrement operator
T operator--(int) {
LockGuard lock(_mutex);
return _value--;
}
// conversion operator, used also for <,>,<=,>=,== and !=
operator T() const {
LockGuard lock(_mutex);
return _value;
}
// access to the internal mutex
rtos::Mutex& internal_mutex() {
return _mutex;
}
private:
mutable rtos::Mutex _mutex;
T _value;
};
#endif /* MBEDMICRO_RTOS_MBED_THREADS_SYNCHRONIZED_INTEGRAL */

148
TESTS/mbedmicro-rtos-mbed/threads/main.cpp
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@ -1,148 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
#include "rtos.h"
#include "SynchronizedIntegral.h"
#include "LockGuard.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
/*
* The stack size is defined in cmsis_os.h mainly dependent on the underlying toolchain and
* the C standard library. For GCC, ARM_STD and IAR it is defined with a size of 2048 bytes
* and for ARM_MICRO 512. Because of reduce RAM size some targets need a reduced stacksize.
*/
#define PARALLEL_STACK_SIZE 512
using namespace utest::v1;
// The counter type used accross all the tests
// It is internall ysynchronized so read
typedef SynchronizedIntegral<int> counter_t;
// Tasks with different functions to test on threads
void increment(counter_t* counter) {
(*counter)++;
}
void increment_with_yield(counter_t* counter) {
Thread::yield();
(*counter)++;
}
void increment_with_wait(counter_t* counter) {
Thread::wait(100);
(*counter)++;
}
void increment_with_child(counter_t* counter) {
Thread child;
child.start(callback(increment, counter));
child.join();
}
void increment_with_murder(counter_t* counter) {
{
// take ownership of the counter mutex so it prevent the child to
// modify counter.
LockGuard lock(counter->internal_mutex());
Thread child;
child.start(callback(increment, counter));
child.terminate();
}
(*counter)++;
}
void self_terminate(Thread *self) {
self->terminate();
// Code should not get here
TEST_ASSERT(0);
}
// Tests that spawn tasks in different configurations
template <void (*F)(counter_t *)>
void test_single_thread() {
counter_t counter(0);
Thread thread;
thread.start(callback(F, &counter));
thread.join();
TEST_ASSERT_EQUAL(counter, 1);
}
template <int N, void (*F)(counter_t *)>
void test_parallel_threads() {
counter_t counter(0);
Thread *threads[N];
for (int i = 0; i < N; i++) {
threads[i] = new Thread(osPriorityNormal, PARALLEL_STACK_SIZE);
threads[i]->start(callback(F, &counter));
}
for (int i = 0; i < N; i++) {
threads[i]->join();
delete threads[i];
}
TEST_ASSERT_EQUAL(counter, N);
}
template <int N, void (*F)(counter_t *)>
void test_serial_threads() {
counter_t counter(0);
for (int i = 0; i < N; i++) {
Thread thread;
thread.start(callback(F, &counter));
thread.join();
}
TEST_ASSERT_EQUAL(counter, N);
}
void test_self_terminate() {
Thread *thread = new Thread();
thread->start(callback(self_terminate, thread));
thread->join();
delete thread;
}
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(40, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
// Test cases
Case cases[] = {
Case("Testing single thread", test_single_thread<increment>),
Case("Testing parallel threads", test_parallel_threads<3, increment>),
Case("Testing serial threads", test_serial_threads<10, increment>),
Case("Testing single thread with yield", test_single_thread<increment_with_yield>),
Case("Testing parallel threads with yield", test_parallel_threads<3, increment_with_yield>),
Case("Testing serial threads with yield", test_serial_threads<10, increment_with_yield>),
Case("Testing single thread with wait", test_single_thread<increment_with_wait>),
Case("Testing parallel threads with wait", test_parallel_threads<3, increment_with_wait>),
Case("Testing serial threads with wait", test_serial_threads<10, increment_with_wait>),
Case("Testing single thread with child", test_single_thread<increment_with_child>),
Case("Testing parallel threads with child", test_parallel_threads<2, increment_with_child>),
Case("Testing serial threads with child", test_serial_threads<10, increment_with_child>),
Case("Testing single thread with murder", test_single_thread<increment_with_murder>),
Case("Testing parallel threads with murder", test_parallel_threads<3, increment_with_murder>),
Case("Testing serial threads with murder", test_serial_threads<10, increment_with_murder>),
Case("Testing thread self terminate", test_self_terminate),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

51
TESTS/mbedmicro-rtos-mbed/timer/main.cpp
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@ -1,51 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "rtos.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
int total_ticks = 10;
volatile int current_tick = 0;
DigitalOut LEDs[4] = {
DigitalOut(LED1), DigitalOut(LED2), DigitalOut(LED3), DigitalOut(LED4)
};
void blink(void const *n) {
static int blink_counter = 0;
const int led_id = int(n);
LEDs[led_id] = !LEDs[led_id];
if (++blink_counter == 75 && current_tick <= total_ticks) {
greentea_send_kv("tick", current_tick++);
blink_counter = 0;
}
}
int main(void) {
GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto");
RtosTimer led_1_timer(blink, osTimerPeriodic, (void *)0);
RtosTimer led_2_timer(blink, osTimerPeriodic, (void *)1);
RtosTimer led_3_timer(blink, osTimerPeriodic, (void *)2);
RtosTimer led_4_timer(blink, osTimerPeriodic, (void *)3);
led_1_timer.start(200);
led_2_timer.start(100);
led_3_timer.start(50);
led_4_timer.start(25);
while(current_tick <= total_ticks) {
Thread::wait(10);
}
led_4_timer.stop();
led_3_timer.stop();
led_2_timer.stop();
led_1_timer.stop();
GREENTEA_TESTSUITE_RESULT(1);
Thread::wait(osWaitForever);
}

102
TESTS/mbedtls/selftest/main.cpp
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@ -1,102 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
#include "rtos.h"
using namespace utest::v1;
#if !defined(MBEDTLS_CONFIG_FILE)
#include "mbedtls/config.h"
#else
#include MBEDTLS_CONFIG_FILE
#endif
#include "mbedtls/sha256.h"
#include "mbedtls/sha512.h"
#include "mbedtls/entropy.h"
#include "mbedtls/entropy_poll.h"
#include <string.h>
#if defined(MBEDTLS_PLATFORM_C)
#include "mbedtls/platform.h"
#else
#include <stdio.h>
#include <stdlib.h>
#define mbedtls_printf printf
#define mbedtls_snprintf snprintf
#define mbedtls_exit exit
#define MBEDTLS_EXIT_SUCCESS EXIT_SUCCESS
#define MBEDTLS_EXIT_FAILURE EXIT_FAILURE
#endif
#define MBEDTLS_SELF_TEST_TEST_CASE(self_test_function) \
void self_test_function ## _test_case() { \
int ret = self_test_function(0); \
TEST_ASSERT_EQUAL(ret, 0); \
}
#if defined(MBEDTLS_SELF_TEST)
#if defined(MBEDTLS_SHA256_C)
MBEDTLS_SELF_TEST_TEST_CASE(mbedtls_sha256_self_test)
#endif
#if defined(MBEDTLS_SHA512_C)
MBEDTLS_SELF_TEST_TEST_CASE(mbedtls_sha512_self_test)
#endif
#if defined(MBEDTLS_ENTROPY_C)
MBEDTLS_SELF_TEST_TEST_CASE(mbedtls_entropy_self_test)
#endif
#else
#warning "MBEDTLS_SELF_TEST not enabled"
#endif /* MBEDTLS_SELF_TEST */
Case cases[] = {
#if defined(MBEDTLS_SELF_TEST)
#if defined(MBEDTLS_SHA256_C)
Case("mbedtls_sha256_self_test", mbedtls_sha256_self_test_test_case),
#endif
#if defined(MBEDTLS_SHA512_C)
Case("mbedtls_sha512_self_test", mbedtls_sha512_self_test_test_case),
#endif
#if defined(MBEDTLS_ENTROPY_C)
Case("mbedtls_entropy_self_test", mbedtls_entropy_self_test_test_case),
#endif
#endif /* MBEDTLS_SELF_TEST */
};
utest::v1::status_t test_setup(const size_t num_cases) {
GREENTEA_SETUP(120, "default_auto");
return verbose_test_setup_handler(num_cases);
}
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

94
TESTS/netsocket/ip_parsing/main.cpp
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@ -1,94 +0,0 @@
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
using namespace utest::v1;
// IP parsing verification
void test_ip_accept(const char *string, nsapi_addr_t addr) {
SocketAddress address;
TEST_ASSERT(address.set_ip_address(string));
TEST_ASSERT(address == SocketAddress(addr));
}
template <const char *string>
void test_ip_reject() {
SocketAddress address;
TEST_ASSERT(!address.set_ip_address(string));
TEST_ASSERT(!address);
}
#define TEST_IP_ACCEPT(name, string, ...) \
void name() { \
nsapi_addr_t addr = __VA_ARGS__; \
test_ip_accept(string, addr); \
}
#define TEST_IP_REJECT(name, string) \
void name() { \
test_ip_reject(string); \
}
// Test cases
TEST_IP_ACCEPT(test_simple_ipv4_address,
"12.34.56.78",
{NSAPI_IPv4,{12,34,56,78}})
TEST_IP_ACCEPT(test_left_weighted_ipv4_address,
"255.0.0.0",
{NSAPI_IPv4,{255,0,0,0}})
TEST_IP_ACCEPT(test_right_weighted_ipv4_address,
"0.0.0.255",
{NSAPI_IPv4,{0,0,0,255}})
TEST_IP_ACCEPT(test_null_ipv4_address,
"0.0.0.0",
{NSAPI_IPv4,{0,0,0,0}})
TEST_IP_ACCEPT(test_simple_ipv6_address,
"1234:5678:9abc:def0:1234:5678:9abc:def0",
{NSAPI_IPv6,{0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,
0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0}})
TEST_IP_ACCEPT(test_left_weighted_ipv6_address,
"1234:5678::",
{NSAPI_IPv6,{0x12,0x34,0x56,0x78,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}})
TEST_IP_ACCEPT(test_right_weighted_ipv6_address,
"::1234:5678",
{NSAPI_IPv6,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x12,0x34,0x56,0x78}})
TEST_IP_ACCEPT(test_hollowed_ipv6_address,
"1234:5678::9abc:def8",
{NSAPI_IPv6,{0x12,0x34,0x56,0x78,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x9a,0xbc,0xde,0xf8}})
TEST_IP_ACCEPT(test_null_ipv6_address,
"::",
{NSAPI_IPv6,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}})
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(10, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Simple IPv4 address", test_simple_ipv4_address),
Case("Left-weighted IPv4 address", test_left_weighted_ipv4_address),
Case("Right-weighted IPv4 address", test_right_weighted_ipv4_address),
Case("Null IPv4 address", test_null_ipv4_address),
Case("Simple IPv6 address", test_simple_ipv6_address),
Case("Left-weighted IPv6 address", test_left_weighted_ipv6_address),
Case("Right-weighted IPv6 address", test_right_weighted_ipv6_address),
Case("Hollowed IPv6 address", test_hollowed_ipv6_address),
Case("Null IPv6 address", test_null_ipv6_address),
};
Specification specification(test_setup, cases);
int main() {
return !Harness::run(specification);
}

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TESTS/network/wifi/main.cpp
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/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "utest/utest.h"
#include "unity/unity.h"
#include "greentea-client/test_env.h"
#include "mbed.h"
#if TARGET_UBLOX_EVK_ODIN_W2
#include "OdinWiFiInterface.h"
#else
#error [NOT_SUPPORTED] Only built in WiFi modules are supported at this time.
#endif
using namespace utest::v1;
/**
* WiFi tests require following macros to be defined:
* - MBED_CONF_APP_WIFI_SSID - SSID of a network the test will try connecting to
* - MBED_CONF_APP_WIFI_PASSWORD - Passphrase that will be used to connecting to the network
* - WIFI_TEST_NETWORKS - List of network that presence will be asserted e.g. "net1", "net2", "net3"
*/
#if !defined(MBED_CONF_APP_WIFI_SSID) || !defined(MBED_CONF_APP_WIFI_PASSWORD) || !defined(MBED_CONF_APP_WIFI_NETWORKS)
#error [NOT_SUPPORTED] MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD and MBED_CONF_APP_WIFI_NETWORKS have to be defined for this test.
#endif
const char *networks[] = {MBED_CONF_APP_WIFI_NETWORKS, NULL};
WiFiInterface *wifi;
/* In normal circumstances the WiFi object could be global, but the delay introduced by WiFi initialization is an issue
for the tests. It causes Greentea to timeout on syncing with the board. To solve it we defer the actual object
creation till we actually need it.
*/
WiFiInterface *get_wifi()
{
if (wifi == NULL) {
/* We don't really care about freeing this, as its lifetime is through the full test suit run. */
#if TARGET_UBLOX_EVK_ODIN_W2
wifi = new OdinWiFiInterface;
#endif
}
return wifi;
}
void check_wifi(const char *ssid, bool *net_stat)
{
int i = 0;
while(networks[i]) {
if (strcmp(networks[i], ssid) == 0) {
net_stat[i] = true;
break;
}
i++;
}
}
void wifi_scan()
{
int count;
WiFiAccessPoint *aps;
const int net_len = sizeof(networks)/sizeof(networks[0]);
bool net_stat[net_len - 1];
memset(net_stat, 0, sizeof(net_stat));
count = get_wifi()->scan(NULL, 0);
TEST_ASSERT_MESSAGE(count >= 0, "WiFi interface returned error");
TEST_ASSERT_MESSAGE(count > 0, "Scan result empty");
aps = new WiFiAccessPoint[count];
count = get_wifi()->scan(aps, count);
for(int i = 0; i < count; i++) {
check_wifi(aps[i].get_ssid(), net_stat);
}
delete[] aps;
for (unsigned i = 0; i < sizeof(net_stat); i++) {
TEST_ASSERT_MESSAGE(net_stat[i] == true, "Not all required WiFi network detected");
}
}
void wifi_connect()
{
int ret;
ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2);
TEST_ASSERT_MESSAGE(ret == 0, "Connect failed");
ret = get_wifi()->disconnect();
TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed");
}
void wifi_connect_scan()
{
int ret;
int count;
WiFiAccessPoint *aps;
const int net_len = sizeof(networks)/sizeof(networks[0]);
bool net_stat[net_len - 1];
memset(net_stat, 0, sizeof(net_stat));
ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2);
TEST_ASSERT_MESSAGE(ret == 0, "Connect failed");
count = get_wifi()->scan(NULL, 0);
TEST_ASSERT_MESSAGE(count >= 0, "WiFi interface returned error");
TEST_ASSERT_MESSAGE(count > 0, "Scan result empty");
aps = new WiFiAccessPoint[count];
count = get_wifi()->scan(aps, count);
for(int i = 0; i < count; i++) {
check_wifi(aps[i].get_ssid(), net_stat);
}
delete[] aps;
ret = get_wifi()->disconnect();
TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed");
for (unsigned i = 0; i < sizeof(net_stat); i++) {
TEST_ASSERT_MESSAGE(net_stat[i] == true, "Not all required WiFi network detected");
}
}
void wifi_http()
{
TCPSocket socket;
int ret;
ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2);
TEST_ASSERT_MESSAGE(ret == 0, "Connect failed");
// Open a socket on the network interface, and create a TCP connection to www.arm.com
ret = socket.open(get_wifi());
TEST_ASSERT_MESSAGE(ret == 0, "Socket open failed");
ret = socket.connect("www.arm.com", 80);
TEST_ASSERT_MESSAGE(ret == 0, "Socket connect failed");
// Send a simple http request
char sbuffer[] = "GET / HTTP/1.1\r\nHost: www.arm.com\r\n\r\n";
int scount = socket.send(sbuffer, sizeof sbuffer);
TEST_ASSERT_MESSAGE(scount >= 0, "Socket send failed");
// Recieve a simple http response and check if it's not empty
char rbuffer[64];
int rcount = socket.recv(rbuffer, sizeof rbuffer);
TEST_ASSERT_MESSAGE(rcount >= 0, "Socket recv error");
TEST_ASSERT_MESSAGE(rcount > 0, "No data received");
ret = socket.close();
TEST_ASSERT_MESSAGE(ret == 0, "Socket close failed");
ret = get_wifi()->disconnect();
TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed");
}
status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
greentea_case_failure_abort_handler(source, reason);
return STATUS_CONTINUE;
}
Case cases[] = {
Case("Scan test", wifi_scan, greentea_failure_handler),
Case("Connect test", wifi_connect, greentea_failure_handler),
Case("Scan while connected test", wifi_connect_scan, greentea_failure_handler),
Case("HTTP test", wifi_http, greentea_failure_handler),
};
status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(90, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
int main() {
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
Harness::run(specification);
}

21
TESTS/network/wifi/template_mbed_app.txt
View File

@ -1,21 +0,0 @@
{
"config": {
"wifi-ssid": {
"help": "WiFi SSID",
"value": "\"SSID\""
},
"wifi-password": {
"help": "WiFi Password",
"value": "\"PASS\""
},
"wifi-networks": {
"help": "WiFi SSIDs which presence will be asserted in the test",
"value": "\"SSID1\",\"SSID2\",\"SSID3\""
}
},
"target_overrides": {
"UBLOX_EVK_ODIN_W2": {
"target.device_has": ["EMAC"]
}
}
}

993
TESTS/storage_abstraction/basicAPI/basicAPI.cpp
View File

@ -1,993 +0,0 @@
/*
* Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if !DEVICE_STORAGE
#error [NOT_SUPPORTED] Storage not supported for this target
#endif
#ifndef AVOID_GREENTEA
#include "greentea-client/test_env.h"
#endif
#include "utest/utest.h"
#include "unity/unity.h"
#include "storage_abstraction/Driver_Storage.h"
#include <string.h>
#include <inttypes.h>
using namespace utest::v1;
extern ARM_DRIVER_STORAGE ARM_Driver_Storage_MTD_K64F;
ARM_DRIVER_STORAGE *drv = &ARM_Driver_Storage_MTD_K64F;
/* temporary buffer to hold data for testing. */
static const unsigned BUFFER_SIZE = 16384;
static uint8_t buffer[BUFFER_SIZE];
/* forward declaration */
void initializationCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation);
/*
* Most tests need some basic initialization of the driver before proceeding
* with their operations.
*/
static control_t preambleForBasicInitialization(void)
{
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
int32_t rc = drv->Initialize(initializationCompleteCallback);
TEST_ASSERT(rc >= ARM_DRIVER_OK);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return CaseTimeout(200) + CaseRepeatAll;
} else {
TEST_ASSERT(rc == 1);
return CaseRepeatAll;
}
}
template<typename T>
static void verifyBytePattern(uint64_t addr, size_t sizeofData, T bytePattern)
{
/* we're limited by BUFFER_SIZE in how much we can verify in a single iteration;
* the variable 'amountBeingVerified' captures the size being verified in each
* iteration. */
size_t amountBeingVerified = sizeofData;
if (amountBeingVerified > BUFFER_SIZE) {
amountBeingVerified = BUFFER_SIZE;
}
TEST_ASSERT((amountBeingVerified % sizeof(T)) == 0);
while (sizeofData) {
int32_t rc = drv->ReadData(addr, buffer, amountBeingVerified);
TEST_ASSERT_EQUAL(amountBeingVerified, rc);
for (size_t index = 0; index < amountBeingVerified / sizeof(T); index++) {
// if (bytePattern != ((const T *)buffer)[index]) {
// printf("%u: expected %x, found %x\n", index, bytePattern, ((const T *)buffer)[index]);
// }
TEST_ASSERT_EQUAL(bytePattern, ((const T *)buffer)[index]);
}
sizeofData -= amountBeingVerified;
addr += amountBeingVerified;
}
}
void test_getVersion()
{
ARM_DRIVER_VERSION version = drv->GetVersion();
TEST_ASSERT_EQUAL(version.api, ARM_STORAGE_API_VERSION);
TEST_ASSERT_EQUAL(version.drv, ARM_DRIVER_VERSION_MAJOR_MINOR(1,00));
}
void test_getCapabilities()
{
TEST_ASSERT(sizeof(ARM_STORAGE_CAPABILITIES) == sizeof(uint32_t));
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
TEST_ASSERT_EQUAL(0, capabilities.reserved);
}
void test_getInfo()
{
ARM_STORAGE_INFO info = {};
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
TEST_ASSERT_EQUAL(0, info.security.reserved1);
TEST_ASSERT_EQUAL(0, info.security.reserved2);
TEST_ASSERT((info.program_cycles == ARM_STORAGE_PROGRAM_CYCLES_INFINITE) || (info.program_cycles > 0));
TEST_ASSERT(info.total_storage > 0);
}
void initializationCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
printf("init complete callback\n");
TEST_ASSERT_EQUAL(1, status);
TEST_ASSERT_EQUAL(operation, ARM_STORAGE_OPERATION_INITIALIZE);
Harness::validate_callback();
}
control_t test_initialize(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 3;
printf("in test_initialize with call_count %u\n", call_count);
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
int32_t rc = drv->Initialize(initializationCompleteCallback);
TEST_ASSERT(rc >= ARM_DRIVER_OK);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? (CaseTimeout(200) + CaseRepeatAll) : (control_t) CaseNext;
}
TEST_ASSERT(rc == 1);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
void uninitializationCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
printf("uninit complete callback\n");
TEST_ASSERT_EQUAL(status, ARM_DRIVER_OK);
TEST_ASSERT_EQUAL(operation, ARM_STORAGE_OPERATION_UNINITIALIZE);
Harness::validate_callback();
}
control_t test_uninitialize(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 3;
printf("in test_uninitialize with call_count %u\n", call_count);
/* update the completion callback. */
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
int32_t rc = drv->Uninitialize();
if (call_count > 2) {
/* the driver should return some error for repeated un-initialization. */
TEST_ASSERT(rc < ARM_DRIVER_OK);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
TEST_ASSERT(rc >= ARM_DRIVER_OK);
if (rc == ARM_DRIVER_OK) {
/* asynchronous operation */
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return CaseTimeout(200) + CaseRepeatAll;
}
/* synchronous operation */
TEST_ASSERT(rc == 1);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
void powerControlCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
printf("power control complete callback\n");
TEST_ASSERT_EQUAL(status, ARM_DRIVER_OK);
TEST_ASSERT_EQUAL(operation, ARM_STORAGE_OPERATION_POWER_CONTROL);
Harness::validate_callback();
}
control_t test_powerControl(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 2;
printf("in test_powerControl with call_count %u\n", call_count);
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
/* Update the completion callback to 'powerControlCompleteCallback'. */
if (call_count == 2) {
int32_t rc = drv->Initialize(powerControlCompleteCallback);
TEST_ASSERT(rc == 1); /* Expect synchronous completion of initialization; the system must have been
* initialized by the previous iteration. */
}
int32_t rc = drv->PowerControl(ARM_POWER_FULL);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT(rc == 1);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
}
void readDataCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
printf("ReadData complete callback\n");
TEST_ASSERT_EQUAL(status, ARM_DRIVER_OK);
TEST_ASSERT_EQUAL(operation, ARM_STORAGE_OPERATION_READ_DATA);
Harness::validate_callback();
}
control_t test_readData(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 5;
printf("in test_readData with call_count %u\n", call_count);
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
/* Update the completion callback to 'readDataCompleteCallback'. */
int32_t rc;
if (call_count == 2) {
rc = drv->Initialize(readDataCompleteCallback);
TEST_ASSERT(rc == 1); /* Expect synchronous completion of initialization; the system must have been
* initialized by the previous iteration. */
}
/* Get the first block. */
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT(firstBlock.size > 0);
ARM_STORAGE_INFO info;
rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
TEST_ASSERT(info.program_unit <= BUFFER_SIZE);
TEST_ASSERT(firstBlock.size >= (REPEAT_INSTANCES - 1) * info.program_unit);
/* choose an increasing address for each iteration. */
uint64_t addr = firstBlock.addr + (call_count - 1) * info.program_unit;
size_t sizeofData = info.program_unit;
rc = drv->ReadData(addr, buffer, sizeofData);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT(rc > 0);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
}
void programDataCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
TEST_ASSERT(status >= 0);
static unsigned programIteration = 0;
static const uint32_t BYTE_PATTERN = 0xAA551122;
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
ARM_STORAGE_INFO info;
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
const uint64_t addr = firstBlock.addr + programIteration * firstBlock.attributes.erase_unit;
size_t sizeofData = info.program_unit;
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
TEST_ASSERT((operation == ARM_STORAGE_OPERATION_ERASE) || (operation == ARM_STORAGE_OPERATION_PROGRAM_DATA));
if (operation == ARM_STORAGE_OPERATION_ERASE) {
// printf("programming %u bytes at address %lu with pattern 0x%" PRIx32 "\n", sizeofData, (uint32_t)addr, BYTE_PATTERN);
size_t sizeofData = info.program_unit;
TEST_ASSERT(BUFFER_SIZE >= sizeofData);
TEST_ASSERT((sizeofData % sizeof(uint32_t)) == 0);
for (size_t index = 0; index < sizeofData / sizeof(uint32_t); index++) {
((uint32_t *)buffer)[index] = BYTE_PATTERN;
}
status = drv->ProgramData(addr, buffer, sizeofData);
if (status < ARM_DRIVER_OK) {
return; /* failure. this will trigger a timeout and cause test failure. */
}
if (status == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return; /* We've successfully pended a programData operation; we'll have another
* invocation of this callback when programming completes. */
}
}
/* We come here either because of completion for program-data or as a very
* unlikely fall through from synchronous completion of program-data (above). */
#ifndef __CC_ARM
printf("verifying programmed sector at addr %lu\n", (uint32_t)addr);
#endif
verifyBytePattern(addr, sizeofData, BYTE_PATTERN);
++programIteration;
Harness::validate_callback();
}
control_t test_programDataUsingProgramUnit(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 5;
printf("in test_programDataUsingProgramUnit with call_count %u\n", call_count);
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
/* Get the first block. */
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT(firstBlock.size > 0);
ARM_STORAGE_INFO info;
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
TEST_ASSERT(info.program_unit <= firstBlock.attributes.erase_unit);
TEST_ASSERT(firstBlock.size >= (REPEAT_INSTANCES - 1) * firstBlock.attributes.erase_unit);
/* initialize the buffer to hold the pattern. */
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
/* Update the completion callback to 'programDataCompleteCallback'. */
if (call_count == 2) {
int32_t rc = drv->Initialize(programDataCompleteCallback);
TEST_ASSERT(rc == 1); /* Expect synchronous completion of initialization; the system must have been
* initialized by the previous iteration. */
}
/* choose an increasing address for each iteration. */
uint64_t addr = firstBlock.addr + (call_count - 2) * firstBlock.attributes.erase_unit;
/* erase the sector at 'addr' */
printf("erasing sector at addr %lu\n", (uint32_t)addr);
rc = drv->Erase(addr, firstBlock.attributes.erase_unit);
TEST_ASSERT(rc >= 0);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT_EQUAL(firstBlock.attributes.erase_unit, rc);
verifyBytePattern(addr, firstBlock.attributes.erase_unit, info.erased_value ? (uint8_t)0xFF : (uint8_t)0);
static const uint32_t BYTE_PATTERN = 0xAA551122;
size_t sizeofData = info.program_unit;
TEST_ASSERT(BUFFER_SIZE >= sizeofData);
TEST_ASSERT((sizeofData % sizeof(uint32_t)) == 0);
for (size_t index = 0; index < sizeofData / sizeof(uint32_t); index++) {
((uint32_t *)buffer)[index] = BYTE_PATTERN;
}
/* program the sector at addr */
// printf("programming %u bytes at address %lu with pattern 0x%" PRIx32 "\n", sizeofData, (uint32_t)addr, BYTE_PATTERN);
rc = drv->ProgramData((uint32_t)addr, buffer, sizeofData);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT(rc > 0);
printf("verifying programmed sector at addr %lu\n", (uint32_t)addr);
verifyBytePattern(addr, sizeofData, BYTE_PATTERN);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
}
}
void programDataOptimalCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
TEST_ASSERT(status >= 0);
static unsigned programIteration = 0;
static const uint8_t BYTE_PATTERN = 0xAA;
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
const uint64_t addr = firstBlock.addr + programIteration * firstBlock.attributes.erase_unit;
ARM_STORAGE_INFO info;
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
size_t sizeofData = info.optimal_program_unit;
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
TEST_ASSERT((operation == ARM_STORAGE_OPERATION_ERASE) || (operation == ARM_STORAGE_OPERATION_PROGRAM_DATA));
if (operation == ARM_STORAGE_OPERATION_ERASE) {
#ifndef __CC_ARM
printf("programming %u bytes at address %lu with pattern 0x%x\n", sizeofData, (uint32_t)addr, BYTE_PATTERN);
#endif
size_t sizeofData = info.optimal_program_unit;
TEST_ASSERT(BUFFER_SIZE >= sizeofData);
memset(buffer, BYTE_PATTERN, sizeofData);
status = drv->ProgramData(addr, buffer, sizeofData);
if (status < ARM_DRIVER_OK) {
return; /* failure. this will trigger a timeout and cause test failure. */
}
if (status == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return; /* We've successfully pended a programData operation; we'll have another
* invocation of this callback when programming completes. */
}
}
/* We come here either because of completion for program-data or as a very
* unlikely fall through from synchronous completion of program-data (above). */
#ifndef __CC_ARM
printf("verifying programmed sector at addr %lu\n", (uint32_t)addr);
#endif
verifyBytePattern(addr, sizeofData, BYTE_PATTERN);
++programIteration;
Harness::validate_callback();
}
control_t test_programDataUsingOptimalProgramUnit(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 5;
printf("in test_programDataUsingOptimalProgramUnit with call_count %u\n", call_count);
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
/* Get the first block. */
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT(firstBlock.size > 0);
ARM_STORAGE_INFO info;
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
TEST_ASSERT(info.optimal_program_unit <= firstBlock.attributes.erase_unit);
TEST_ASSERT(firstBlock.size >= (REPEAT_INSTANCES - 1) * firstBlock.attributes.erase_unit);
/* initialize the buffer to hold the pattern. */
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
/* Update the completion callback to 'programDataCompleteCallback'. */
if (call_count == 2) {
int32_t rc = drv->Initialize(programDataOptimalCompleteCallback);
TEST_ASSERT(rc == 1); /* Expect synchronous completion of initialization; the system must have been
* initialized by the previous iteration. */
}
/* choose an increasing address for each iteration. */
uint64_t addr = firstBlock.addr + (call_count - 2) * firstBlock.attributes.erase_unit;
/* erase the sector at 'addr' */
printf("erasing sector at addr %lu\n", (uint32_t)addr);
rc = drv->Erase(addr, firstBlock.attributes.erase_unit);
TEST_ASSERT(rc >= 0);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT_EQUAL(firstBlock.attributes.erase_unit, rc);
verifyBytePattern(addr, firstBlock.attributes.erase_unit, info.erased_value ? (uint8_t)0xFF : (uint8_t)0);
static const uint8_t BYTE_PATTERN = 0xAA;
size_t sizeofData = info.optimal_program_unit;
TEST_ASSERT(BUFFER_SIZE >= sizeofData);
memset(buffer, BYTE_PATTERN, sizeofData);
/* program the sector at addr */
printf("programming %u bytes at address %lu with pattern 0x%x\n", sizeofData, (uint32_t)addr, BYTE_PATTERN);
rc = drv->ProgramData((uint32_t)addr, buffer, sizeofData);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT_EQUAL(sizeofData, rc);
printf("verifying programmed sector at addr %lu\n", (uint32_t)addr);
verifyBytePattern(addr, sizeofData, BYTE_PATTERN);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
}
}
void test_eraseWithInvalidParameters(void)
{
int32_t rc;
rc = drv->Erase(0, 0);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
/* operate before the start of the first block. */
ARM_STORAGE_BLOCK block;
rc = drv->GetNextBlock(NULL, &block); /* get the first block */
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&block));
TEST_ASSERT(block.size > 0);
rc = drv->Erase(block.addr - 1, BUFFER_SIZE);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
/* operate at an address past the end of the last block */
uint64_t endAddr = block.addr + block.size;
for (; ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
endAddr = block.addr + block.size;
}
rc = drv->Erase(endAddr + 1, BUFFER_SIZE);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
ARM_STORAGE_INFO info;
rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
drv->GetNextBlock(NULL, &block); /* get the first block */
TEST_ASSERT(block.size >= block.attributes.erase_unit);
TEST_ASSERT((block.size % block.attributes.erase_unit) == 0);
rc = drv->Erase(block.addr + 1, block.attributes.erase_unit);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->Erase(block.addr, block.attributes.erase_unit - 1);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->Erase(block.addr, block.attributes.erase_unit + 1);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->Erase(block.addr, block.attributes.erase_unit / 2);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
}
template<size_t ERASE_UNITS_PER_ITERATION>
void eraseCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
static unsigned eraseIteration = 0;
#ifndef __CC_ARM
printf("erase<%u> complete callback: iteration %u\n", ERASE_UNITS_PER_ITERATION, eraseIteration);
#endif
TEST_ASSERT_EQUAL(operation, ARM_STORAGE_OPERATION_ERASE);
/* test that the actual sector has been erased */
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT_EQUAL(ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit, status);
const uint64_t addr = firstBlock.addr + eraseIteration * ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit;
++eraseIteration;
ARM_STORAGE_INFO info;
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
//printf("testing erased sector at addr %lu", (uint32_t)addr);
verifyBytePattern(addr, ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit, info.erased_value ? (uint8_t)0xFF : (uint8_t)0);
Harness::validate_callback();
}
template <size_t ERASE_UNITS_PER_ITERATION>
control_t test_erase(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 5;
printf("in test_erase<%u> with call_count %u\n", ERASE_UNITS_PER_ITERATION, call_count);
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
/* Get the first block. */
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT(firstBlock.size > 0);
if (firstBlock.size < ((call_count - 1) * ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit)) {
printf("firstBlock isn't large enough to support instance %u of test_erase<%u>\n", call_count, ERASE_UNITS_PER_ITERATION);
return CaseNext;
}
/* Update the completion callback to 'eraseCompleteCallback'. */
if (call_count == 2) {
int32_t rc = drv->Initialize(eraseCompleteCallback<ERASE_UNITS_PER_ITERATION>);
TEST_ASSERT(rc == 1); /* Expect synchronous completion of initialization; the system must have been
* initialized by the previous iteration. */
}
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
/* choose an increasing address for each iteration. */
uint64_t addr = firstBlock.addr + (call_count - 2) * ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit;
printf("erasing %lu bytes at addr %lu\n", (ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit), (uint32_t)addr);
int32_t rc = drv->Erase(addr, ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT_EQUAL(ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit, rc);
ARM_STORAGE_INFO info;
rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
/* test that the actual sector has been erased */
printf("testing erased sector at addr %lu\n", (uint32_t)addr);
verifyBytePattern(addr, ERASE_UNITS_PER_ITERATION * firstBlock.attributes.erase_unit, (uint8_t)0xFF);
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
}
void eraseChipCompleteCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
#ifndef __CC_ARM
printf("eraseChip complete callback\n");
#endif
TEST_ASSERT_EQUAL(status, ARM_DRIVER_OK);
TEST_ASSERT_EQUAL(operation, ARM_STORAGE_OPERATION_ERASE_ALL);
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
uint64_t addr = firstBlock.addr;
/* test that the flash has been erased */
#ifndef __CC_ARM
printf("testing erased chip\n");
#endif
unsigned index = 0;
static const unsigned MAX_VERIFY_ITERATIONS = 5;
while ((index < MAX_VERIFY_ITERATIONS) && (addr < (firstBlock.addr + firstBlock.size))) {
// printf("testing erased chip at addr %lu\n", (uint32_t)addr);
verifyBytePattern(addr, firstBlock.attributes.erase_unit, (uint8_t)0xFF);
index++;
addr += firstBlock.attributes.erase_unit;
}
Harness::validate_callback();
}
control_t test_eraseAll(const size_t call_count)
{
static const unsigned REPEAT_INSTANCES = 5;
printf("in test_eraseAll with call_count %u\n", call_count);
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
if (!capabilities.erase_all) {
printf("chip erase not supported on this flash\n");
return CaseNext;
}
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
/* Update the completion callback to 'eraseChipCompleteCallback'. */
if (call_count == 2) {
int32_t rc = drv->Initialize(eraseChipCompleteCallback);
TEST_ASSERT(rc == 1); /* Expect synchronous completion of initialization; the system must have been
* initialized by the previous iteration. */
}
/* Get the first block. */
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT(firstBlock.size > 0);
uint64_t addr = firstBlock.addr;
printf("erasing chip\n");
int32_t rc = drv->EraseAll();
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return (call_count < REPEAT_INSTANCES) ? CaseTimeout(200) + CaseRepeatAll: CaseTimeout(200);
} else {
TEST_ASSERT(rc == 1);
/* test that the flash has been erased */
unsigned index = 0;
static const unsigned MAX_VERIFY_ITERATIONS = 5;
while ((index < MAX_VERIFY_ITERATIONS) && (addr < (firstBlock.addr + firstBlock.size))) {
//printf("testing erased chip at addr %lu", (uint32_t)addr);
ARM_STORAGE_INFO info;
rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
verifyBytePattern(addr, firstBlock.attributes.erase_unit, info.erased_value ? (uint8_t)0xFF : (uint8_t)0);
index++;
addr += firstBlock.attributes.erase_unit;
}
return (call_count < REPEAT_INSTANCES) ? CaseRepeatAll : CaseNext;
}
}
void test_programDataWithInvalidParameters(void)
{
int32_t rc;
rc = drv->ProgramData(0, NULL, 0);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->ProgramData(0, buffer, 0);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->ProgramData(0, NULL, BUFFER_SIZE);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
/* operate before the start of the first block. */
ARM_STORAGE_BLOCK block;
rc = drv->GetNextBlock(NULL, &block); /* get the first block */
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&block));
TEST_ASSERT(block.size > 0);
rc = drv->ProgramData(block.addr - 1, buffer, BUFFER_SIZE);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
/* operate at an address past the end of the last block */
uint64_t endAddr = block.addr + block.size;
for (; ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
endAddr = block.addr + block.size;
}
rc = drv->ProgramData(endAddr + 1, buffer, BUFFER_SIZE);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
ARM_STORAGE_INFO info;
rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
if (info.program_unit <= 1) {
return; /* if program_unit is 1 (or 0), we can't proceed with any alignment tests */
}
drv->GetNextBlock(NULL, &block); /* get the first block */
TEST_ASSERT(block.size >= info.program_unit);
rc = drv->ProgramData(block.addr + 1, buffer, info.program_unit);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->ProgramData(block.addr, buffer, info.program_unit - 1);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->ProgramData(block.addr, buffer, info.program_unit + 1);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
rc = drv->ProgramData(block.addr, buffer, info.program_unit / 2);
TEST_ASSERT_EQUAL(ARM_DRIVER_ERROR_PARAMETER, rc);
}
template <size_t N_UNITS>
void programDataWithMultipleProgramUnitsCallback(int32_t status, ARM_STORAGE_OPERATION operation)
{
TEST_ASSERT(status >= ARM_DRIVER_OK);
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT(firstBlock.size > 0);
ARM_STORAGE_INFO info;
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
size_t rangeNeededForTest = (N_UNITS * info.program_unit);
/* round-up range to the nearest erase_unit */
rangeNeededForTest = ((rangeNeededForTest + firstBlock.attributes.erase_unit - 1) / firstBlock.attributes.erase_unit) * firstBlock.attributes.erase_unit;
static const uint32_t BYTE_PATTERN = 0xABCDEF00;
if (operation == ARM_STORAGE_OPERATION_ERASE) {
TEST_ASSERT_EQUAL(rangeNeededForTest, status);
TEST_ASSERT((N_UNITS * info.program_unit) <= BUFFER_SIZE);
/* setup byte pattern in buffer */
if (info.program_unit >= sizeof(BYTE_PATTERN)) {
for (size_t index = 0; index < ((N_UNITS * info.program_unit) / sizeof(BYTE_PATTERN)); index++) {
((uint32_t *)buffer)[index] = BYTE_PATTERN;
}
} else {
for (size_t index = 0; index < ((N_UNITS * info.program_unit)); index++) {
buffer[index] = ((const uint8_t *)&BYTE_PATTERN)[0];
}
}
#ifndef __CC_ARM
printf("Callback: programming %lu bytes at address %lu with pattern 0x%lx\n", (N_UNITS * info.program_unit), (uint32_t)firstBlock.addr, BYTE_PATTERN);
#endif
rc = drv->ProgramData(firstBlock.addr, buffer, (N_UNITS * info.program_unit));
TEST_ASSERT(rc >= ARM_DRIVER_OK);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return; /* We've successfully pended a programData operation; we'll have another
* invocation of this callback when programming completes. */
}
status = rc;
}
TEST_ASSERT_EQUAL((N_UNITS * info.program_unit), status);
#ifndef __CC_ARM
printf("Callback: verifying programmed sector at addr %lu\n", (uint32_t)firstBlock.addr);
#endif
if (info.program_unit >= sizeof(BYTE_PATTERN)) {
verifyBytePattern(firstBlock.addr, (N_UNITS * info.program_unit), BYTE_PATTERN);
} else {
verifyBytePattern(firstBlock.addr, (N_UNITS * info.program_unit), ((const uint8_t *)&BYTE_PATTERN)[0]);
}
Harness::validate_callback();
}
template<size_t N_UNITS>
control_t test_programDataWithMultipleProgramUnits(const size_t call_count)
{
int32_t rc;
printf("in test_programDataWithMultipleProgramUnits<%u> with call_count %u\n", N_UNITS, call_count);
if (call_count == 1) {
/* Achieve basic initialization for the driver before anything else. */
return preambleForBasicInitialization();
}
/* Update the completion callback to 'programDataWithMultipleProgramUnitsCallback'. */
if (call_count == 2) {
rc = drv->Initialize(programDataWithMultipleProgramUnitsCallback<N_UNITS>);
TEST_ASSERT(rc == 1); /* Expect synchronous completion of initialization; the system must have been
* initialized by the previous iteration. */
ARM_STORAGE_BLOCK firstBlock;
drv->GetNextBlock(NULL, &firstBlock); /* get first block */
TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));
TEST_ASSERT(firstBlock.size > 0);
ARM_STORAGE_INFO info;
int32_t rc = drv->GetInfo(&info);
TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);
ARM_STORAGE_CAPABILITIES capabilities = drv->GetCapabilities();
size_t rangeNeededForTest = (N_UNITS * info.program_unit);
/* round-up range to the nearest erase_unit */
rangeNeededForTest = ((rangeNeededForTest + firstBlock.attributes.erase_unit - 1) / firstBlock.attributes.erase_unit) * firstBlock.attributes.erase_unit;
if (firstBlock.size < rangeNeededForTest) {
printf("first block not large enough; rangeNeededForTest: %u\n", rangeNeededForTest);
return CaseNext; /* first block isn't large enough for the intended operation */
}
if (rangeNeededForTest > BUFFER_SIZE) {
printf("buffer (%u) not large enough; rangeNeededForTest: %u\n", BUFFER_SIZE, rangeNeededForTest);
return CaseNext;
}
// printf("erasing %u bytes at addr %lu\n", rangeNeededForTest, (uint32_t)firstBlock.addr);
rc = drv->Erase(firstBlock.addr, rangeNeededForTest);
TEST_ASSERT(rc >= 0);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return CaseTimeout(500);
} else {
TEST_ASSERT_EQUAL(rangeNeededForTest, rc);
/* setup byte pattern in buffer */
static const uint32_t BYTE_PATTERN = 0xABCDEF00;
if (info.program_unit >= sizeof(BYTE_PATTERN)) {
for (size_t index = 0; index < ((N_UNITS * info.program_unit) / sizeof(BYTE_PATTERN)); index++) {
((uint32_t *)buffer)[index] = BYTE_PATTERN;
}
} else {
for (size_t index = 0; index < ((N_UNITS * info.program_unit)); index++) {
buffer[index] = ((const uint8_t *)&BYTE_PATTERN)[0];
}
}
printf("programming %lu bytes at address %lu with pattern 0x%lx\n", (N_UNITS * info.program_unit), (uint32_t)firstBlock.addr, BYTE_PATTERN);
rc = drv->ProgramData(firstBlock.addr, buffer, (N_UNITS * info.program_unit));
TEST_ASSERT(rc >= 0);
if (rc == ARM_DRIVER_OK) {
TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops);
return CaseTimeout(500);
} else {
TEST_ASSERT_EQUAL((N_UNITS * info.program_unit), rc);
printf("verifying programmed sector at addr %lu\n", (uint32_t)firstBlock.addr);
if (info.program_unit >= sizeof(BYTE_PATTERN)) {
verifyBytePattern(firstBlock.addr, (N_UNITS * info.program_unit), BYTE_PATTERN);
} else {
verifyBytePattern(firstBlock.addr, (N_UNITS * info.program_unit), ((const uint8_t *)&BYTE_PATTERN)[0]);
}
return CaseNext;
}
}
}
return CaseNext;
}
#ifndef AVOID_GREENTEA
// Custom setup handler required for proper Greentea support
utest::v1::status_t greentea_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(60, "default_auto");
// Call the default reporting function
return greentea_test_setup_handler(number_of_cases);
}
#else
status_t default_setup(const size_t)
{
return STATUS_CONTINUE;
}
#endif
// Specify all your test cases here
Case cases[] = {
Case("get version", test_getVersion),
Case("get capabilities", test_getCapabilities),
Case("get info", test_getInfo),
Case("initialize", test_initialize),
Case("uninitialize", test_uninitialize),
Case("power control", test_powerControl),
Case("erase all", test_eraseAll),
Case("read data", test_readData),
Case("erase with invalid parameters", test_eraseWithInvalidParameters),
Case("erase single unit", test_erase<1>),
Case("erase two units", test_erase<2>),
Case("erase four units", test_erase<4>),
Case("erase eight units", test_erase<8>),
Case("program data with invalid parameters", test_programDataWithInvalidParameters),
Case("program data using program_unit", test_programDataUsingProgramUnit),
Case("program data using optimal_program_unit", test_programDataUsingOptimalProgramUnit),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<1>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<2>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<7>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<8>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<9>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<31>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<32>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<33>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<127>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<128>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<129>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<1023>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<1024>),
Case("program data with multiple program units", test_programDataWithMultipleProgramUnits<1025>),
};
// Declare your test specification with a custom setup handler
#ifndef AVOID_GREENTEA
Specification specification(greentea_setup, cases);
#else
Specification specification(default_setup, cases);
#endif
int main(int argc, char** argv)
{
// Run the test specification
Harness::run(specification);
}

0
features/nanostack/FEATURE_NANOSTACK/coap-service/apache-2.0.txt → apache-2.0.txt
View File

94
cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S
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@ -1,94 +0,0 @@
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Functions
*---------------------------------------------------------------------------*/
.text
.global __v7_all_cache
/*
* __STATIC_ASM void __v7_all_cache(uint32_t op) {
*/
__v7_all_cache:
.arm
PUSH {R4-R11}
MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
ANDS R3, R6, #0x07000000 /* Extract coherency level */
MOV R3, R3, LSR #23 /* Total cache levels << 1 */
BEQ Finished /* If 0, no need to clean */
MOV R10, #0 /* R10 holds current cache level << 1 */
Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
AND R1, R1, #7 /* Isolate those lower 3 bits */
CMP R1, #2
BLT Skip /* No cache or only instruction cache at this level */
MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
ISB /* ISB to sync the change to the CacheSizeID reg */
MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
AND R2, R1, #7 /* Extract the line length field */
ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
LDR R4, =0x3FF
ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
CLZ R5, R4 /* R5 is the bit position of the way size increment */
LDR R7, =0x7FFF
ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
CMP R0, #0
BNE Dccsw
MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
B cont
Dccsw: CMP R0, #1
BNE Dccisw
MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
B cont
Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
cont: SUBS R9, R9, #1 /* Decrement the Way number */
BGE Loop3
SUBS R7, R7, #1 /* Decrement the Set number */
BGE Loop2
Skip: ADD R10, R10, #2 /* increment the cache number */
CMP R3, R10
BGT Loop1
Finished:
DSB
POP {R4-R11}
BX lr
.END
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

97
cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s
View File

@ -1,97 +0,0 @@
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Functions
*---------------------------------------------------------------------------*/
SECTION `.text`:CODE:NOROOT(2)
arm
PUBLIC __v7_all_cache
/*
* __STATIC_ASM void __v7_all_cache(uint32_t op) {
*/
__v7_all_cache:
PUSH {R4-R11}
MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
ANDS R3, R6, #0x07000000 /* Extract coherency level */
MOV R3, R3, LSR #23 /* Total cache levels << 1 */
BEQ Finished /* If 0, no need to clean */
MOV R10, #0 /* R10 holds current cache level << 1 */
Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
AND R1, R1, #7 /* Isolate those lower 3 bits */
CMP R1, #2
BLT Skip /* No cache or only instruction cache at this level */
MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
ISB /* ISB to sync the change to the CacheSizeID reg */
MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
AND R2, R1, #7 /* Extract the line length field */
ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
LDR R4, =0x3FF
ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
CLZ R5, R4 /* R5 is the bit position of the way size increment */
LDR R7, =0x7FFF
ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
CMP R0, #0
BNE Dccsw
MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
B cont
Dccsw: CMP R0, #1
BNE Dccisw
MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
B cont
Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
cont: SUBS R9, R9, #1 /* Decrement the Way number */
BGE Loop3
SUBS R7, R7, #1 /* Decrement the Set number */
BGE Loop2
Skip: ADD R10, R10, #2 /* increment the cache number */
CMP R3, R10
BGT Loop1
Finished:
DSB
POP {R4-R11}
BX lr
END
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

81
cmsis/TOOLCHAIN_IAR/cmain.S
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@ -1,81 +0,0 @@
/**************************************************
*
* Part two of the system initialization code, contains C-level
* initialization, thumb-2 only variant.
*
* Copyright 2006 IAR Systems. All rights reserved.
*
* $Revision: 59783 $
*
**************************************************/
; --------------------------------------------------
; Module ?cmain, C-level initialization.
;
SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
SECTION .text:CODE:NOROOT(2)
PUBLIC __cmain
;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
PUBLIC ?main
EXTWEAK __iar_data_init3
EXTWEAK __iar_argc_argv
EXTERN __low_level_init
EXTERN __call_ctors
EXTERN main
EXTERN exit
EXTERN __iar_dynamic_initialization
EXTERN mbed_sdk_init
EXTERN SystemInit
THUMB
__cmain:
?main:
; Initialize segments.
; __segment_init and __low_level_init are assumed to use the same
; instruction set and to be reachable by BL from the ICODE segment
; (it is safest to link them in segment ICODE).
FUNCALL __cmain, __low_level_init
bl __low_level_init
cmp r0,#0
beq ?l1
FUNCALL __cmain, __iar_data_init3
bl __iar_data_init3
MOVS r0,#0 ; No parameters
FUNCALL __cmain, mbed_sdk_init
BL mbed_sdk_init
MOVS r0,#0 ; No parameters
FUNCALL __cmain, __iar_dynamic_initialization
BL __iar_dynamic_initialization ; C++ dynamic initialization
?l1:
REQUIRE ?l3
SECTION .text:CODE:NOROOT(2)
PUBLIC _main
PUBLIC _call_main
THUMB
__iar_init$$done: ; Copy initialization is done
?l3:
_call_main:
MOVS r0,#0 ; No parameters
FUNCALL __cmain, __iar_argc_argv
BL __iar_argc_argv ; Maybe setup command line
FUNCALL __cmain, main
BL main
_main:
FUNCALL __cmain, exit
BL exit
END

136
cmsis/arm_common_tables.h
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@ -1,136 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
//extern const q31_t realCoefAQ31[1024];
//extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

79
cmsis/arm_const_structs.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

7556
cmsis/arm_math.h
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cmsis/core_ca9.h
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/**************************************************************************//**
* @file core_ca9.h
* @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 25 March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CA9_H_GENERIC
#define __CORE_CA9_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_A9
@{
*/
/* CMSIS CA9 definitions */
#define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
#define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
__CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_A (0x09) /*!< Cortex-A Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#define __STATIC_ASM static __asm
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#include <stdint.h>
inline uint32_t __get_PSR(void) {
__ASM("mrs r0, cpsr");
}
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#define __STATIC_ASM static __asm
#endif
/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
#endif
#include <stdint.h> /*!< standard types definitions */
#include "core_caInstr.h" /*!< Core Instruction Access */
#include "core_caFunc.h" /*!< Core Function Access */
#include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
#endif /* __CORE_CA9_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CA9_H_DEPENDANT
#define __CORE_CA9_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CA9_REV
#define __CA9_REV 0x0000
#warning "__CA9_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 1
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1
#endif
#if __Vendor_SysTickConfig == 0
#error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_A9 */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-A processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/*@} end of group CMSIS_CORE */
/*@} end of CMSIS_Core_FPUFunctions */
#endif /* __CORE_CA9_H_GENERIC */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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cmsis/core_caFunc.h
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cmsis/core_caInstr.h
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/**************************************************************************//**
* @file core_caInstr.h
* @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 04. December 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CAINSTR_H__
#define __CORE_CAINSTR_H__
#define __CORTEX_M 0x3
#include "core_cmInstr.h"
#undef __CORTEX_M
#endif

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cmsis/core_ca_mmu.h
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;/**************************************************************************//**
; * @file core_ca_mmu.h
; * @brief MMU Startup File for A9_MP Device Series
; * @version V1.01
; * @date 10 Sept 2014
; *
; * @note
; *
; ******************************************************************************/
;/* Copyright (c) 2012-2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _MMU_FUNC_H
#define _MMU_FUNC_H
#define SECTION_DESCRIPTOR (0x2)
#define SECTION_MASK (0xFFFFFFFC)
#define SECTION_TEXCB_MASK (0xFFFF8FF3)
#define SECTION_B_SHIFT (2)
#define SECTION_C_SHIFT (3)
#define SECTION_TEX0_SHIFT (12)
#define SECTION_TEX1_SHIFT (13)
#define SECTION_TEX2_SHIFT (14)
#define SECTION_XN_MASK (0xFFFFFFEF)
#define SECTION_XN_SHIFT (4)
#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
#define SECTION_DOMAIN_SHIFT (5)
#define SECTION_P_MASK (0xFFFFFDFF)
#define SECTION_P_SHIFT (9)
#define SECTION_AP_MASK (0xFFFF73FF)
#define SECTION_AP_SHIFT (10)
#define SECTION_AP2_SHIFT (15)
#define SECTION_S_MASK (0xFFFEFFFF)
#define SECTION_S_SHIFT (16)
#define SECTION_NG_MASK (0xFFFDFFFF)
#define SECTION_NG_SHIFT (17)
#define SECTION_NS_MASK (0xFFF7FFFF)
#define SECTION_NS_SHIFT (19)
#define PAGE_L1_DESCRIPTOR (0x1)
#define PAGE_L1_MASK (0xFFFFFFFC)
#define PAGE_L2_4K_DESC (0x2)
#define PAGE_L2_4K_MASK (0xFFFFFFFD)
#define PAGE_L2_64K_DESC (0x1)
#define PAGE_L2_64K_MASK (0xFFFFFFFC)
#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
#define PAGE_4K_B_SHIFT (2)
#define PAGE_4K_C_SHIFT (3)
#define PAGE_4K_TEX0_SHIFT (6)
#define PAGE_4K_TEX1_SHIFT (7)
#define PAGE_4K_TEX2_SHIFT (8)
#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
#define PAGE_64K_B_SHIFT (2)
#define PAGE_64K_C_SHIFT (3)
#define PAGE_64K_TEX0_SHIFT (12)
#define PAGE_64K_TEX1_SHIFT (13)
#define PAGE_64K_TEX2_SHIFT (14)
#define PAGE_TEXCB_MASK (0xFFFF8FF3)
#define PAGE_B_SHIFT (2)
#define PAGE_C_SHIFT (3)
#define PAGE_TEX_SHIFT (12)
#define PAGE_XN_4K_MASK (0xFFFFFFFE)
#define PAGE_XN_4K_SHIFT (0)
#define PAGE_XN_64K_MASK (0xFFFF7FFF)
#define PAGE_XN_64K_SHIFT (15)
#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
#define PAGE_DOMAIN_SHIFT (5)
#define PAGE_P_MASK (0xFFFFFDFF)
#define PAGE_P_SHIFT (9)
#define PAGE_AP_MASK (0xFFFFFDCF)
#define PAGE_AP_SHIFT (4)
#define PAGE_AP2_SHIFT (9)
#define PAGE_S_MASK (0xFFFFFBFF)
#define PAGE_S_SHIFT (10)
#define PAGE_NG_MASK (0xFFFFF7FF)
#define PAGE_NG_SHIFT (11)
#define PAGE_NS_MASK (0xFFFFFFF7)
#define PAGE_NS_SHIFT (3)
#define OFFSET_1M (0x00100000)
#define OFFSET_64K (0x00010000)
#define OFFSET_4K (0x00001000)
#define DESCRIPTOR_FAULT (0x00000000)
/* ########################### MMU Function Access ########################### */
/** \ingroup MMU_FunctionInterface
\defgroup MMU_Functions MMU Functions Interface
@{
*/
/* Attributes enumerations */
/* Region size attributes */
typedef enum
{
SECTION,
PAGE_4k,
PAGE_64k,
} mmu_region_size_Type;
/* Region type attributes */
typedef enum
{
NORMAL,
DEVICE,
SHARED_DEVICE,
NON_SHARED_DEVICE,
STRONGLY_ORDERED
} mmu_memory_Type;
/* Region cacheability attributes */
typedef enum
{
NON_CACHEABLE,
WB_WA,
WT,
WB_NO_WA,
} mmu_cacheability_Type;
/* Region parity check attributes */
typedef enum
{
ECC_DISABLED,
ECC_ENABLED,
} mmu_ecc_check_Type;
/* Region execution attributes */
typedef enum
{
EXECUTE,
NON_EXECUTE,
} mmu_execute_Type;
/* Region global attributes */
typedef enum
{
GLOBAL,
NON_GLOBAL,
} mmu_global_Type;
/* Region shareability attributes */
typedef enum
{
NON_SHARED,
SHARED,
} mmu_shared_Type;
/* Region security attributes */
typedef enum
{
SECURE,
NON_SECURE,
} mmu_secure_Type;
/* Region access attributes */
typedef enum
{
NO_ACCESS,
RW,
READ,
} mmu_access_Type;
/* Memory Region definition */
typedef struct RegionStruct {
mmu_region_size_Type rg_t;
mmu_memory_Type mem_t;
uint8_t domain;
mmu_cacheability_Type inner_norm_t;
mmu_cacheability_Type outer_norm_t;
mmu_ecc_check_Type e_t;
mmu_execute_Type xn_t;
mmu_global_Type g_t;
mmu_secure_Type sec_t;
mmu_access_Type priv_t;
mmu_access_Type user_t;
mmu_shared_Type sh_t;
} mmu_region_attributes_Type;
/** \brief Set section execution-never attribute
The function sets section execution-never attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
\return 0
*/
__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
{
*descriptor_l1 &= SECTION_XN_MASK;
*descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
return 0;
}
/** \brief Set section domain
The function sets section domain
\param [out] descriptor_l1 L1 descriptor.
\param [in] domain Section domain
\return 0
*/
__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
{
*descriptor_l1 &= SECTION_DOMAIN_MASK;
*descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
return 0;
}
/** \brief Set section parity check
The function sets section parity check
\param [out] descriptor_l1 L1 descriptor.
\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
\return 0
*/
__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
{
*descriptor_l1 &= SECTION_P_MASK;
*descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
return 0;
}
/** \brief Set section access privileges
The function sets section access privileges
\param [out] descriptor_l1 L1 descriptor.
\param [in] user User Level Access: NO_ACCESS, RW, READ
\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
\param [in] afe Access flag enable
\return 0
*/
__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
{
uint32_t ap = 0;
if (afe == 0) { //full access
if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == READ)) { ap = 0x2; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x7; }
}
else { //Simplified access
if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x7; }
}
*descriptor_l1 &= SECTION_AP_MASK;
*descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
*descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
return 0;
}
/** \brief Set section shareability
The function sets section shareability
\param [out] descriptor_l1 L1 descriptor.
\param [in] s_bit Section shareability: NON_SHARED, SHARED
\return 0
*/
__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
{
*descriptor_l1 &= SECTION_S_MASK;
*descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
return 0;
}
/** \brief Set section Global attribute
The function sets section Global attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
\return 0
*/
__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
{
*descriptor_l1 &= SECTION_NG_MASK;
*descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
return 0;
}
/** \brief Set section Security attribute
The function sets section Global attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] s_bit Section Security attribute: SECURE, NON_SECURE
\return 0
*/
__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
{
*descriptor_l1 &= SECTION_NS_MASK;
*descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
return 0;
}
/* Page 4k or 64k */
/** \brief Set 4k/64k page execution-never attribute
The function sets 4k/64k page execution-never attribute
\param [out] descriptor_l2 L2 descriptor.
\param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
\param [in] page Page size: PAGE_4k, PAGE_64k,
\return 0
*/
__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
{
if (page == PAGE_4k)
{
*descriptor_l2 &= PAGE_XN_4K_MASK;
*descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
}
else
{
*descriptor_l2 &= PAGE_XN_64K_MASK;
*descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
}
return 0;
}
/** \brief Set 4k/64k page domain
The function sets 4k/64k page domain
\param [out] descriptor_l1 L1 descriptor.
\param [in] domain Page domain
\return 0
*/
__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
{
*descriptor_l1 &= PAGE_DOMAIN_MASK;
*descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
return 0;
}
/** \brief Set 4k/64k page parity check
The function sets 4k/64k page parity check
\param [out] descriptor_l1 L1 descriptor.
\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
\return 0
*/
__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
{
*descriptor_l1 &= SECTION_P_MASK;
*descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
return 0;
}
/** \brief Set 4k/64k page access privileges
The function sets 4k/64k page access privileges
\param [out] descriptor_l2 L2 descriptor.
\param [in] user User Level Access: NO_ACCESS, RW, READ
\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
\param [in] afe Access flag enable
\return 0
*/
__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
{
uint32_t ap = 0;
if (afe == 0) { //full access
if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == READ)) { ap = 0x2; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x6; }
}
else { //Simplified access
if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
else if ((priv == READ) && (user == READ)) { ap = 0x7; }
}
*descriptor_l2 &= PAGE_AP_MASK;
*descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
*descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
return 0;
}
/** \brief Set 4k/64k page shareability
The function sets 4k/64k page shareability
\param [out] descriptor_l2 L2 descriptor.
\param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
\return 0
*/
__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
{
*descriptor_l2 &= PAGE_S_MASK;
*descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
return 0;
}
/** \brief Set 4k/64k page Global attribute
The function sets 4k/64k page Global attribute
\param [out] descriptor_l2 L2 descriptor.
\param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
\return 0
*/
__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
{
*descriptor_l2 &= PAGE_NG_MASK;
*descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
return 0;
}
/** \brief Set 4k/64k page Security attribute
The function sets 4k/64k page Global attribute
\param [out] descriptor_l1 L1 descriptor.
\param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
\return 0
*/
__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
{
*descriptor_l1 &= PAGE_NS_MASK;
*descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
return 0;
}
/** \brief Set Section memory attributes
The function sets section memory attributes
\param [out] descriptor_l1 L1 descriptor.
\param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\return 0
*/
__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
{
*descriptor_l1 &= SECTION_TEXCB_MASK;
if (STRONGLY_ORDERED == mem)
{
return 0;
}
else if (SHARED_DEVICE == mem)
{
*descriptor_l1 |= (1 << SECTION_B_SHIFT);
}
else if (NON_SHARED_DEVICE == mem)
{
*descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
}
else if (NORMAL == mem)
{
*descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
switch(inner)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l1 |= (1 << SECTION_B_SHIFT);
break;
case WT:
*descriptor_l1 |= 1 << SECTION_C_SHIFT;
break;
case WB_NO_WA:
*descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
break;
}
switch(outer)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
break;
case WT:
*descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
break;
case WB_NO_WA:
*descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
break;
}
}
return 0;
}
/** \brief Set 4k/64k page memory attributes
The function sets 4k/64k page memory attributes
\param [out] descriptor_l2 L2 descriptor.
\param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
\return 0
*/
__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
{
*descriptor_l2 &= PAGE_4K_TEXCB_MASK;
if (page == PAGE_64k)
{
//same as section
__memory_section(descriptor_l2, mem, outer, inner);
}
else
{
if (STRONGLY_ORDERED == mem)
{
return 0;
}
else if (SHARED_DEVICE == mem)
{
*descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
}
else if (NON_SHARED_DEVICE == mem)
{
*descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
}
else if (NORMAL == mem)
{
*descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
switch(inner)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
break;
case WT:
*descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
break;
case WB_NO_WA:
*descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
break;
}
switch(outer)
{
case NON_CACHEABLE:
break;
case WB_WA:
*descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
break;
case WT:
*descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
break;
case WB_NO_WA:
*descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
break;
}
}
}
return 0;
}
/** \brief Create a L1 section descriptor
The function creates a section descriptor.
Assumptions:
- 16MB super sections not supported
- TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- Functions always return 0
\param [out] descriptor L1 descriptor
\param [out] descriptor2 L2 descriptor
\param [in] reg Section attributes
\return 0
*/
__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
{
*descriptor = 0;
__memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
__xn_section(descriptor,reg.xn_t);
__domain_section(descriptor, reg.domain);
__p_section(descriptor, reg.e_t);
__ap_section(descriptor, reg.priv_t, reg.user_t, 1);
__shared_section(descriptor,reg.sh_t);
__global_section(descriptor,reg.g_t);
__secure_section(descriptor,reg.sec_t);
*descriptor &= SECTION_MASK;
*descriptor |= SECTION_DESCRIPTOR;
return 0;
}
/** \brief Create a L1 and L2 4k/64k page descriptor
The function creates a 4k/64k page descriptor.
Assumptions:
- TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- Functions always return 0
\param [out] descriptor L1 descriptor
\param [out] descriptor2 L2 descriptor
\param [in] reg 4k/64k page attributes
\return 0
*/
__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
{
*descriptor = 0;
*descriptor2 = 0;
switch (reg.rg_t)
{
case PAGE_4k:
__memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
__xn_page(descriptor2, reg.xn_t, PAGE_4k);
__domain_page(descriptor, reg.domain);
__p_page(descriptor, reg.e_t);
__ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
__shared_page(descriptor2,reg.sh_t);
__global_page(descriptor2,reg.g_t);
__secure_page(descriptor,reg.sec_t);
*descriptor &= PAGE_L1_MASK;
*descriptor |= PAGE_L1_DESCRIPTOR;
*descriptor2 &= PAGE_L2_4K_MASK;
*descriptor2 |= PAGE_L2_4K_DESC;
break;
case PAGE_64k:
__memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
__xn_page(descriptor2, reg.xn_t, PAGE_64k);
__domain_page(descriptor, reg.domain);
__p_page(descriptor, reg.e_t);
__ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
__shared_page(descriptor2,reg.sh_t);
__global_page(descriptor2,reg.g_t);
__secure_page(descriptor,reg.sec_t);
*descriptor &= PAGE_L1_MASK;
*descriptor |= PAGE_L1_DESCRIPTOR;
*descriptor2 &= PAGE_L2_64K_MASK;
*descriptor2 |= PAGE_L2_64K_DESC;
break;
case SECTION:
//error
break;
}
return 0;
}
/** \brief Create a 1MB Section
\param [in] ttb Translation table base address
\param [in] base_address Section base address
\param [in] count Number of sections to create
\param [in] descriptor_l1 L1 descriptor (region attributes)
*/
__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
{
uint32_t offset;
uint32_t entry;
uint32_t i;
offset = base_address >> 20;
entry = (base_address & 0xFFF00000) | descriptor_l1;
//4 bytes aligned
ttb = ttb + offset;
for (i = 0; i < count; i++ )
{
//4 bytes aligned
*ttb++ = entry;
entry += OFFSET_1M;
}
}
/** \brief Create a 4k page entry
\param [in] ttb L1 table base address
\param [in] base_address 4k base address
\param [in] count Number of 4k pages to create
\param [in] descriptor_l1 L1 descriptor (region attributes)
\param [in] ttb_l2 L2 table base address
\param [in] descriptor_l2 L2 descriptor (region attributes)
*/
__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
{
uint32_t offset, offset2;
uint32_t entry, entry2;
uint32_t i;
offset = base_address >> 20;
entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
//4 bytes aligned
ttb += offset;
//create l1_entry
*ttb = entry;
offset2 = (base_address & 0xff000) >> 12;
ttb_l2 += offset2;
entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
for (i = 0; i < count; i++ )
{
//4 bytes aligned
*ttb_l2++ = entry2;
entry2 += OFFSET_4K;
}
}
/** \brief Create a 64k page entry
\param [in] ttb L1 table base address
\param [in] base_address 64k base address
\param [in] count Number of 64k pages to create
\param [in] descriptor_l1 L1 descriptor (region attributes)
\param [in] ttb_l2 L2 table base address
\param [in] descriptor_l2 L2 descriptor (region attributes)
*/
__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
{
uint32_t offset, offset2;
uint32_t entry, entry2;
uint32_t i,j;
offset = base_address >> 20;
entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
//4 bytes aligned
ttb += offset;
//create l1_entry
*ttb = entry;
offset2 = (base_address & 0xff000) >> 12;
ttb_l2 += offset2;
entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
for (i = 0; i < count; i++ )
{
//create 16 entries
for (j = 0; j < 16; j++)
//4 bytes aligned
*ttb_l2++ = entry2;
entry2 += OFFSET_64K;
}
}
/*@} end of MMU_Functions */
#endif
#ifdef __cplusplus
}
#endif

750
cmsis/core_cm0.h
View File

@ -1,750 +0,0 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.10
* @date 18. March 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#ifdef __cplusplus
#define __IM volatile /*!< Defines 'read only' permissions */
#else
#define __IM volatile const /*!< Defines 'read only' permissions */
#endif
#define __OM volatile /*!< Defines 'write only' permissions */
#define __IOM volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if((int32_t)(IRQn) < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else {
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if((int32_t)(IRQn) < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
}
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
}
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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cmsis/core_cm0plus.h
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@ -1,864 +0,0 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.10
* @date 18. March 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#ifdef __cplusplus
#define __IM volatile /*!< Defines 'read only' permissions */
#else
#define __IM volatile const /*!< Defines 'read only' permissions */
#endif
#define __OM volatile /*!< Defines 'write only' permissions */
#define __IOM volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if((int32_t)(IRQn) < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else {
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if((int32_t)(IRQn) < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
}
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
}
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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cmsis/core_cm4.h
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cmsis/core_cm4_simd.h
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/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_ccs.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLALD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLALDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLSLD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLSLDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* not yet supported */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CORE_CM4_SIMD_H */
#ifdef __cplusplus
}
#endif

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cmsis/core_cm7.h
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cmsis/core_cmFunc.h
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@ -1,664 +0,0 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.10
* @date 18. March 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Set Base Priority with condition
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Set Base Priority with condition
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

916
cmsis/core_cmInstr.h
View File

@ -1,916 +0,0 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.10
* @date 18. March 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
result = value; // r will be reversed bits of v; first get LSB of v
for (value >>= 1; value; value >>= 1)
{
result <<= 1;
result |= value & 1;
s--;
}
result <<= s; // shift when v's highest bits are zero
return(result);
}
#endif
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb 0xF":::"memory");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
#else
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
result = value; // r will be reversed bits of v; first get LSB of v
for (value >>= 1; value; value >>= 1)
{
result <<= 1;
result |= value & 1;
s--;
}
result <<= s; // shift when v's highest bits are zero
#endif
return(result);
}
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

201
cmsis/core_cmSecureAccess.h
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@ -1,201 +0,0 @@
/**************************************************************************//**
* @file core_cmSecureAccess.h
* @brief CMSIS Cortex-M Core Secure Access Header File
* @version XXX
* @date 10. June 2016
*
* @note
*
******************************************************************************/
/* Copyright (c) 2016 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CM_SECURE_ACCESS_H
#define __CORE_CM_SECURE_ACCESS_H
/* ########################### Core Secure Access ########################### */
#ifdef FEATURE_UVISOR
#include "uvisor-lib/uvisor-lib.h"
/* Secure uVisor implementation. */
/** Set the value at the target address.
*
* Equivalent to: `*address = value`.
* @param address[in] Target address
* @param value[in] Value to write at the address location.
*/
#define SECURE_WRITE(address, value) \
uvisor_write(main, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
/** Get the value at the target address.
*
* @param address[in] Target address
* @returns The value `*address`.
*/
#define SECURE_READ(address) \
uvisor_read(main, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
/** Get the selected bits at the target address.
*
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @returns The value `*address & mask`.
*/
#define SECURE_BITS_GET(address, mask) \
UVISOR_BITS_GET(main, UVISOR_RGW_SHARED, address, mask)
/** Check the selected bits at the target address.
*
* @param address[in] Address at which to check the bits
* @param mask[in] Bits to select out of the target address
* @returns The value `((*address & mask) == mask)`.
*/
#define SECURE_BITS_CHECK(address, mask) \
UVISOR_BITS_CHECK(main, UVISOR_RGW_SHARED, address, mask)
/** Set the selected bits to 1 at the target address.
*
* Equivalent to: `*address |= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_SET(address, mask) \
UVISOR_BITS_SET(main, UVISOR_RGW_SHARED, address, mask)
/** Clear the selected bits at the target address.
*
* Equivalent to: `*address &= ~mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_CLEAR(address, mask) \
UVISOR_BITS_CLEAR(main, UVISOR_RGW_SHARED, address, mask)
/** Set the selected bits at the target address to the given value.
*
* Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @param value[in] Value to write at the address location. Note: The value
* must be already shifted to the correct bit position
*/
#define SECURE_BITS_SET_VALUE(address, mask, value) \
UVISOR_BITS_SET_VALUE(main, UVISOR_RGW_SHARED, address, mask, value)
/** Toggle the selected bits at the target address.
*
* Equivalent to: `*address ^= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_TOGGLE(address, mask) \
UVISOR_BITS_TOGGLE(main, UVISOR_RGW_SHARED, address, mask)
#else
/* Insecure fallback implementation. */
/** Set the value at the target address.
*
* Equivalent to: `*address = value`.
* @param address[in] Target address
* @param value[in] Value to write at the address location.
*/
#define SECURE_WRITE(address, value) \
*(address) = (value)
/** Get the value at the target address.
*
* @param address[in] Target address
* @returns The value `*address`.
*/
#define SECURE_READ(address) \
(*(address))
/** Get the selected bits at the target address.
*
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @returns The value `*address & mask`.
*/
#define SECURE_BITS_GET(address, mask) \
(*(address) & (mask))
/** Check the selected bits at the target address.
*
* @param address[in] Address at which to check the bits
* @param mask[in] Bits to select out of the target address
* @returns The value `((*address & mask) == mask)`.
*/
#define SECURE_BITS_CHECK(address, mask) \
((*(address) & (mask)) == (mask))
/** Set the selected bits to 1 at the target address.
*
* Equivalent to: `*address |= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_SET(address, mask) \
*(address) |= (mask)
/** Clear the selected bits at the target address.
*
* Equivalent to: `*address &= ~mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_CLEAR(address, mask) \
*(address) &= ~(mask)
/** Set the selected bits at the target address to the given value.
*
* Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @param value[in] Value to write at the address location. Note: The value
* must be already shifted to the correct bit position
*/
#define SECURE_BITS_SET_VALUE(address, mask, value) \
*(address) = (*(address) & ~(mask)) | ((value) & (mask))
/** Toggle the selected bits at the target address.
*
* Equivalent to: `*address ^= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_TOGGLE(address, mask) \
*(address) ^= (mask)
#endif
#endif /* __CORE_CM_SECURE_ACCESS_H */

697
cmsis/core_cmSimd.h
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@ -1,697 +0,0 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.10
* @date 18. March 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/* not yet supported */
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

866
cmsis/core_sc000.h
View File

@ -1,866 +0,0 @@
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.10
* @date 18. March 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup SC000
@{
*/
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1];
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154];
__IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/** \brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of SC000 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if((int32_t)(IRQn) < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else {
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if((int32_t)(IRQn) < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
}
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
}
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1677
cmsis/core_sc300.h
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File diff suppressed because it is too large Load Diff

50
features/nanostack/FEATURE_NANOSTACK/coap-service/coap-service/coap_service_api.h → coap-service/coap_service_api.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016 ARM Limited. All Rights Reserved.
* Copyright (c) 2015-2017 ARM Limited. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@ -26,7 +26,7 @@ extern "C" {
#include <string.h>
#include "ns_types.h"
#include "sn_coap_header.h"
#include "mbed-coap/sn_coap_header.h"
#include "ns_address.h"
/**
@ -45,6 +45,10 @@ extern "C" {
#define COAP_SERVICE_OPTIONS_VIRTUAL_SOCKET 0x01
#define COAP_SERVICE_OPTIONS_SECURE 0x02
#define COAP_SERVICE_OPTIONS_EPHEMERAL_PORT 0x04
/** Coap interface selected as socket interface */
#define COAP_SERVICE_OPTIONS_SELECT_SOCKET_IF 0x08
/** Register to COAP multicast groups */
#define COAP_SERVICE_OPTIONS_MULTICAST_JOIN 0x10
/** Link-layer security bypass option is set*/
#define COAP_SERVICE_OPTIONS_SECURE_BYPASS 0x80
@ -56,6 +60,10 @@ extern "C" {
#define COAP_REQUEST_OPTIONS_MULTICAST 0x04 //!< indicates that CoAP library support multicasting
#define COAP_REQUEST_OPTIONS_SECURE_BYPASS 0x08
extern const uint8_t COAP_MULTICAST_ADDR_LINK_LOCAL[16]; //!< ff02::fd, COAP link local multicast address
extern const uint8_t COAP_MULTICAST_ADDR_ADMIN_LOCAL[16]; //!< ff03::fd, COAP admin-local multicast address
extern const uint8_t COAP_MULTICAST_ADDR_SITE_LOCAL[16]; //!> ff05::fd, COAP site-local multicast address
/**
* \brief Service message response receive callback.
*
@ -262,7 +270,45 @@ extern uint16_t coap_service_request_send(int8_t service_id, uint8_t options, co
*/
extern int8_t coap_service_response_send(int8_t service_id, uint8_t options, sn_coap_hdr_s *request_ptr, sn_coap_msg_code_e message_code, sn_coap_content_format_e content_type, const uint8_t *payload_ptr,uint16_t payload_len);
/**
* \brief Delete CoAP request transaction
*
* Removes pending CoAP transaction from service.
*
* \param service_id Id number of the current service.
* \param msg_id Message ID number.
*
* \return -1 For failure
*- 0 For success
*/
extern int8_t coap_service_request_delete(int8_t service_id, uint16_t msg_id);
/**
* \brief Set DTLS handshake timeout values
*
* Configures the DTLS handshake timeout values.
*
* \param service_id Id number of the current service.
* \param min Initial timeout value.
* \param max Maximum value of timeout.
*
* \return -1 For failure
*- 0 For success
*/
extern int8_t coap_service_set_handshake_timeout(int8_t service_id, uint32_t min, uint32_t max);
/**
* \brief Set CoAP duplication message buffer size
*
* Configures the CoAP duplication message buffer size.
*
* \param service_id Id number of the current service.
* \param size Buffer size (messages)
*
* \return -1 For failure
*- 0 For success
*/
extern int8_t coap_service_set_duplicate_message_buffer(int8_t service_id, uint8_t size);
#ifdef __cplusplus
}
#endif

23
docs/build_profiles.md
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@ -1,23 +0,0 @@
# Build Profiles
Mbed 5.0 supports three primary build profiles, *develop*, *debug* and *release*. When using
the online compiler the *develop* profile is used. When building from the command line
the desired profile can be can be selected by adding the ```--profile <profile>```
command line flag, but `develop` will be used by default. Custom user defined profiles can also be specific by giving the path
the the profile.
## Develop profile
* Small and fast code
* Full error information - e.g. asserts have filename and line number
* Hard to follow code flow when using a debugger
## Debug profile
* Easy to step through code with a debugger
* Full error information - e.g. asserts have filename and line number
* Largest and slowest profile
## Release profile
* Smallest profile and still fast
* Minimal error information
* Chip is put to sleep when going idle:
* debugger is likely to drop connection
* breaks the [local file system](https://developer.mbed.org/handbook/LocalFileSystem) on the [mbed interface](https://developer.mbed.org/handbook/mbed-interface) (only for few NXP boards & if used)

65
docs/exporters.md
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@ -1,65 +0,0 @@
# About the exporters
The mbed exporters are used to export your code to various 3rd party tools and IDEs. Each exporter implements a `generate` function that produces an IDE specific project file. Exporters benefit from [mbed build tools](https://github.com/ARMmbed/mbed-os/blob/master/docs/BUILDING.md#build-mbed-sdk-library-from-sources). However, instead of using your source and [config data](https://github.com/ARMmbed/mbed-os/blob/master/docs/config_system.md) to create an executable, we use that information to populate an IDE project file that will be configured to build, flash, and debug your code. You can find exporter implementations [here](https://github.com/ARMmbed/mbed-os/tree/master/tools/export).
## mbed-cli command
`mbed export -m [target] -i [IDE]`
# Adding export support for a target
If you have added new target to the mbed SDK, exporting will allow users to transition from mbed source code to the offline development environment of their choice. This functionality activates the use of your device for larger number of users.
## Eclipse and Make
Eclipse project export utilizes a generated Makefile for building. Other than target configuration within the [config system](https://github.com/ARMmbed/mbed-os/blob/master/docs/mbed_targets.md) for mbed build system support, there is no additional work to provide Make export.
### Available mbed-cli commands
`mbed export -m [target] -i [make_gcc_arm, make_iar, make_armc5, eclipse_gcc_arm, eclipse_iar, eclipse_armc5]`
## UVision and IAR
### CMSIS Packs
UVision and IAR both utilize [CMSIS packs](http://www.keil.com/pack/doc/CMSIS/Pack/html/index.html) to find target information necessary to create a valid project file.
We utilize the tool [ArmPackManager](https://github.com/ARMmbed/mbed-os/tree/master/tools/arm_pack_manager) to scrape [MDK5 Software Packs](https://www.keil.com/dd2/Pack/) for target information. This is achieved by parsing [http://www.keil.com/pack/index.idx](http://sadevicepacksprod.blob.core.windows.net/idxfile/index.idx). The relevant information in the [PDSC (Pack Description)](http://www.keil.com/pack/doc/CMSIS/Pack/html/_pack_format.html) retrieved from each URL in the index is stored in [index.json](https://github.com/ARMmbed/mbed-os/blob/master/tools/arm_pack_manager/index.json). A `.pdsc` file typically describes a family of devices. Each device is uniquely identified by its [device name](https://github.com/ARMmbed/mbed-os/blob/master/docs/mbed_targets.md#device_name). Thus, this name makes a natural key to associate a device with its information in `index.json`.
#### What's in a device name?
There is no reliable way to map an mbed alias like [NUCLEO_F030R8](https://github.com/ARMmbed/mbed-os/blob/master/targets/targets.json#L603) to its unique identifier, [STM32F030R8](https://github.com/ARMmbed/mbed-os/blob/master/targets/targets.json#L615), as it is listed in a CMSIS pack (and subsequently `index.json`). So, we added a [device name](https://github.com/ARMmbed/mbed-os/blob/master/docs/mbed_targets.md#device_name) field in `targets.json`. **This field is required for IAR or UVision exporter support**.
#### Code Usage
http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc is the PDSC that contains TEENSY_31 device (MK20DX256xxx7). It has been parsed by ArmPackManager and stored in `index.json`. The device information begins on line 156:
```xml
<device Dname="MK20DX256xxx7">
<processor Dfpu="0" Dmpu="0" Dendian="Little-endian" Dclock="72000000"/>
<compile header="Device\Include\MK20D7.h" define="MK20DX256xxx7"/>
<debug svd="SVD\MK20D7.svd"/>
<memory id="IROM1" start="0x00000000" size="0x40000" startup="1" default="1"/>
<memory id="IROM2" start="0x10000000" size="0x8000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x8000" init ="0" default="1"/>
<memory id="IRAM2" start="0x1FFF8000" size="0x8000" init ="0" default="0"/>
<algorithm name="Flash\MK_P256.FLM" start="0x00000000" size="0x40000" default="1"/>
<algorithm name="Flash\MK_D32_72MHZ.FLM" start="0x10000000" size="0x8000" default="1"/>
<book name="Documents\K20P100M72SF1RM.pdf" title="MK20DX256xxx7 Reference Manual"/>
<book name="Documents\K20P100M72SF1.pdf" title="MK20DX256xxx7 Data Sheet"/>
</device>
```
##### Uvision
The dname (device name) field on line 156 directly corresponds to that in the Uvision5 IDE target selection window. [`tools/export/uvision/uvision.tmpl`](https://github.com/ARMmbed/mbed-os/blob/master/tools/export/uvision/uvision.tmpl#L15), uses target information from these packs is used to generate valid Uvision5 projects. If the device name is not found, we use a generic ARM CPU target in Uvision5.
##### IAR
[`tools/export/iar/iar_definitions.json`](https://github.com/ARMmbed/mbed-os/blob/master/tools/export/iar/iar_definitions.json) utilizes this device name to store information necessary to set the target in an IAR project.
##### Updating index.json
You can regenerate `index.json` to contain a newly made CMSIS pack with the following command:
`mbed export -i [IDE] --update-packs`
You should include the changes to `index.json` in your PR that adds support for the new target.

27
drivers/AnalogIn.cpp
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@ -1,27 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "drivers/AnalogIn.h"
#if DEVICE_ANALOGIN
namespace mbed {
SingletonPtr<PlatformMutex> AnalogIn::_mutex;
};
#endif

132
drivers/AnalogIn.h
View File

@ -1,132 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ANALOGIN_H
#define MBED_ANALOGIN_H
#include "platform/platform.h"
#if DEVICE_ANALOGIN
#include "hal/analogin_api.h"
#include "platform/SingletonPtr.h"
#include "platform/PlatformMutex.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** An analog input, used for reading the voltage on a pin
*
* @Note Synchronization level: Thread safe
*
* Example:
* @code
* // Print messages when the AnalogIn is greater than 50%
*
* #include "mbed.h"
*
* AnalogIn temperature(p20);
*
* int main() {
* while(1) {
* if(temperature > 0.5) {
* printf("Too hot! (%f)", temperature.read());
* }
* }
* }
* @endcode
*/
class AnalogIn {
public:
/** Create an AnalogIn, connected to the specified pin
*
* @param pin AnalogIn pin to connect to
* @param name (optional) A string to identify the object
*/
AnalogIn(PinName pin) {
lock();
analogin_init(&_adc, pin);
unlock();
}
/** Read the input voltage, represented as a float in the range [0.0, 1.0]
*
* @returns A floating-point value representing the current input voltage, measured as a percentage
*/
float read() {
lock();
float ret = analogin_read(&_adc);
unlock();
return ret;
}
/** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
*
* @returns
* 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
*/
unsigned short read_u16() {
lock();
unsigned short ret = analogin_read_u16(&_adc);
unlock();
return ret;
}
/** An operator shorthand for read()
*
* The float() operator can be used as a shorthand for read() to simplify common code sequences
*
* Example:
* @code
* float x = volume.read();
* float x = volume;
*
* if(volume.read() > 0.25) { ... }
* if(volume > 0.25) { ... }
* @endcode
*/
operator float() {
// Underlying call is thread safe
return read();
}
virtual ~AnalogIn() {
// Do nothing
}
protected:
virtual void lock() {
_mutex->lock();
}
virtual void unlock() {
_mutex->unlock();
}
analogin_t _adc;
static SingletonPtr<PlatformMutex> _mutex;
};
} // namespace mbed
#endif
#endif
/** @}*/

150
drivers/AnalogOut.h
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@ -1,150 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ANALOGOUT_H
#define MBED_ANALOGOUT_H
#include "platform/platform.h"
#if DEVICE_ANALOGOUT
#include "hal/analogout_api.h"
#include "platform/PlatformMutex.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** An analog output, used for setting the voltage on a pin
*
* @Note Synchronization level: Thread safe
*
* Example:
* @code
* // Make a sawtooth output
*
* #include "mbed.h"
*
* AnalogOut tri(p18);
* int main() {
* while(1) {
* tri = tri + 0.01;
* wait_us(1);
* if(tri == 1) {
* tri = 0;
* }
* }
* }
* @endcode
*/
class AnalogOut {
public:
/** Create an AnalogOut connected to the specified pin
*
* @param AnalogOut pin to connect to (18)
*/
AnalogOut(PinName pin) {
analogout_init(&_dac, pin);
}
/** Set the output voltage, specified as a percentage (float)
*
* @param value A floating-point value representing the output voltage,
* specified as a percentage. The value should lie between
* 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
* Values outside this range will be saturated to 0.0f or 1.0f.
*/
void write(float value) {
lock();
analogout_write(&_dac, value);
unlock();
}
/** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
*
* @param value 16-bit unsigned short representing the output voltage,
* normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
*/
void write_u16(unsigned short value) {
lock();
analogout_write_u16(&_dac, value);
unlock();
}
/** Return the current output voltage setting, measured as a percentage (float)
*
* @returns
* A floating-point value representing the current voltage being output on the pin,
* measured as a percentage. The returned value will lie between
* 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
*
* @note
* This value may not match exactly the value set by a previous write().
*/
float read() {
lock();
float ret = analogout_read(&_dac);
unlock();
return ret;
}
/** An operator shorthand for write()
*/
AnalogOut& operator= (float percent) {
// Underlying write call is thread safe
write(percent);
return *this;
}
AnalogOut& operator= (AnalogOut& rhs) {
// Underlying write call is thread safe
write(rhs.read());
return *this;
}
/** An operator shorthand for read()
*/
operator float() {
// Underlying read call is thread safe
return read();
}
virtual ~AnalogOut() {
// Do nothing
}
protected:
virtual void lock() {
_mutex.lock();
}
virtual void unlock() {
_mutex.unlock();
}
dac_t _dac;
PlatformMutex _mutex;
};
} // namespace mbed
#endif
#endif
/** @}*/

96
drivers/BusIn.cpp
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@ -1,96 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "drivers/BusIn.h"
#include "platform/mbed_assert.h"
namespace mbed {
BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
// No lock needed in the constructor
_nc_mask = 0;
for (int i=0; i<16; i++) {
_pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
if (pins[i] != NC) {
_nc_mask |= (1 << i);
}
}
}
BusIn::BusIn(PinName pins[16]) {
// No lock needed in the constructor
_nc_mask = 0;
for (int i=0; i<16; i++) {
_pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
if (pins[i] != NC) {
_nc_mask |= (1 << i);
}
}
}
BusIn::~BusIn() {
// No lock needed in the destructor
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
delete _pin[i];
}
}
}
int BusIn::read() {
int v = 0;
lock();
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
v |= _pin[i]->read() << i;
}
}
unlock();
return v;
}
void BusIn::mode(PinMode pull) {
lock();
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
_pin[i]->mode(pull);
}
}
unlock();
}
void BusIn::lock() {
_mutex.lock();
}
void BusIn::unlock() {
_mutex.unlock();
}
BusIn::operator int() {
// Underlying read is thread safe
return read();
}
DigitalIn& BusIn::operator[] (int index) {
// No lock needed since _pin is not modified outside the constructor
MBED_ASSERT(index >= 0 && index <= 16);
MBED_ASSERT(_pin[index]);
return *_pin[index];
}
} // namespace mbed

108
drivers/BusIn.h
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@ -1,108 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_BUSIN_H
#define MBED_BUSIN_H
#include "platform/platform.h"
#include "drivers/DigitalIn.h"
#include "platform/PlatformMutex.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** A digital input bus, used for reading the state of a collection of pins
*
* @Note Synchronization level: Thread safe
*/
class BusIn {
public:
/* Group: Configuration Methods */
/** Create an BusIn, connected to the specified pins
*
* @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
*
* @note
* It is only required to specify as many pin variables as is required
* for the bus; the rest will default to NC (not connected)
*/
BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
BusIn(PinName pins[16]);
virtual ~BusIn();
/** Read the value of the input bus
*
* @returns
* An integer with each bit corresponding to the value read from the associated DigitalIn pin
*/
int read();
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone
*/
void mode(PinMode pull);
/** Binary mask of bus pins connected to actual pins (not NC pins)
* If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
*
* @returns
* Binary mask of connected pins
*/
int mask() {
// No lock needed since _nc_mask is not modified outside the constructor
return _nc_mask;
}
/** A shorthand for read()
*/
operator int();
/** Access to particular bit in random-iterator fashion
*/
DigitalIn & operator[] (int index);
protected:
DigitalIn* _pin[16];
/** Mask of bus's NC pins
* If bit[n] is set to 1 - pin is connected
* if bit[n] is cleared - pin is not connected (NC)
*/
int _nc_mask;
PlatformMutex _mutex;
/* disallow copy constructor and assignment operators */
private:
virtual void lock();
virtual void unlock();
BusIn(const BusIn&);
BusIn & operator = (const BusIn&);
};
} // namespace mbed
#endif
/** @}*/

138
drivers/BusInOut.cpp
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "drivers/BusInOut.h"
#include "platform/mbed_assert.h"
namespace mbed {
BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
// No lock needed in the constructor
_nc_mask = 0;
for (int i=0; i<16; i++) {
_pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
if (pins[i] != NC) {
_nc_mask |= (1 << i);
}
}
}
BusInOut::BusInOut(PinName pins[16]) {
// No lock needed in the constructor
_nc_mask = 0;
for (int i=0; i<16; i++) {
_pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
if (pins[i] != NC) {
_nc_mask |= (1 << i);
}
}
}
BusInOut::~BusInOut() {
// No lock needed in the destructor
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
delete _pin[i];
}
}
}
void BusInOut::write(int value) {
lock();
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
_pin[i]->write((value >> i) & 1);
}
}
unlock();
}
int BusInOut::read() {
lock();
int v = 0;
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
v |= _pin[i]->read() << i;
}
}
unlock();
return v;
}
void BusInOut::output() {
lock();
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
_pin[i]->output();
}
}
unlock();
}
void BusInOut::input() {
lock();
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
_pin[i]->input();
}
}
unlock();
}
void BusInOut::mode(PinMode pull) {
lock();
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
_pin[i]->mode(pull);
}
}
unlock();
}
BusInOut& BusInOut::operator= (int v) {
// Underlying write is thread safe
write(v);
return *this;
}
BusInOut& BusInOut::operator= (BusInOut& rhs) {
// Underlying read is thread safe
write(rhs.read());
return *this;
}
DigitalInOut& BusInOut::operator[] (int index) {
// No lock needed since _pin is not modified outside the constructor
MBED_ASSERT(index >= 0 && index <= 16);
MBED_ASSERT(_pin[index]);
return *_pin[index];
}
BusInOut::operator int() {
// Underlying read is thread safe
return read();
}
void BusInOut::lock() {
_mutex.lock();
}
void BusInOut::unlock() {
_mutex.unlock();
}
} // namespace mbed

127
drivers/BusInOut.h
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@ -1,127 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_BUSINOUT_H
#define MBED_BUSINOUT_H
#include "drivers/DigitalInOut.h"
#include "platform/PlatformMutex.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** A digital input output bus, used for setting the state of a collection of pins
*
* @Note Synchronization level: Thread safe
*/
class BusInOut {
public:
/** Create an BusInOut, connected to the specified pins
*
* @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
*
* @note
* It is only required to specify as many pin variables as is required
* for the bus; the rest will default to NC (not connected)
*/
BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
BusInOut(PinName pins[16]);
virtual ~BusInOut();
/* Group: Access Methods */
/** Write the value to the output bus
*
* @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
*/
void write(int value);
/** Read the value currently output on the bus
*
* @returns
* An integer with each bit corresponding to associated DigitalInOut pin setting
*/
int read();
/** Set as an output
*/
void output();
/** Set as an input
*/
void input();
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone
*/
void mode(PinMode pull);
/** Binary mask of bus pins connected to actual pins (not NC pins)
* If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
*
* @returns
* Binary mask of connected pins
*/
int mask() {
// No lock needed since _nc_mask is not modified outside the constructor
return _nc_mask;
}
/** A shorthand for write()
*/
BusInOut& operator= (int v);
BusInOut& operator= (BusInOut& rhs);
/** Access to particular bit in random-iterator fashion
*/
DigitalInOut& operator[] (int index);
/** A shorthand for read()
*/
operator int();
protected:
virtual void lock();
virtual void unlock();
DigitalInOut* _pin[16];
/** Mask of bus's NC pins
* If bit[n] is set to 1 - pin is connected
* if bit[n] is cleared - pin is not connected (NC)
*/
int _nc_mask;
PlatformMutex _mutex;
/* disallow copy constructor and assignment operators */
private:
BusInOut(const BusInOut&);
BusInOut & operator = (const BusInOut&);
};
} // namespace mbed
#endif
/** @}*/

108
drivers/BusOut.cpp
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "drivers/BusOut.h"
#include "platform/mbed_assert.h"
namespace mbed {
BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
// No lock needed in the constructor
_nc_mask = 0;
for (int i=0; i<16; i++) {
_pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
if (pins[i] != NC) {
_nc_mask |= (1 << i);
}
}
}
BusOut::BusOut(PinName pins[16]) {
// No lock needed in the constructor
_nc_mask = 0;
for (int i=0; i<16; i++) {
_pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
if (pins[i] != NC) {
_nc_mask |= (1 << i);
}
}
}
BusOut::~BusOut() {
// No lock needed in the destructor
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
delete _pin[i];
}
}
}
void BusOut::write(int value) {
lock();
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
_pin[i]->write((value >> i) & 1);
}
}
unlock();
}
int BusOut::read() {
lock();
int v = 0;
for (int i=0; i<16; i++) {
if (_pin[i] != 0) {
v |= _pin[i]->read() << i;
}
}
unlock();
return v;
}
BusOut& BusOut::operator= (int v) {
// Underlying write is thread safe
write(v);
return *this;
}
BusOut& BusOut::operator= (BusOut& rhs) {
// Underlying write is thread safe
write(rhs.read());
return *this;
}
DigitalOut& BusOut::operator[] (int index) {
// No lock needed since _pin is not modified outside the constructor
MBED_ASSERT(index >= 0 && index <= 16);
MBED_ASSERT(_pin[index]);
return *_pin[index];
}
BusOut::operator int() {
// Underlying read is thread safe
return read();
}
void BusOut::lock() {
_mutex.lock();
}
void BusOut::unlock() {
_mutex.unlock();
}
} // namespace mbed

111
drivers/BusOut.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_BUSOUT_H
#define MBED_BUSOUT_H
#include "drivers/DigitalOut.h"
#include "platform/PlatformMutex.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** A digital output bus, used for setting the state of a collection of pins
*/
class BusOut {
public:
/** Create an BusOut, connected to the specified pins
*
* @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
*
* @Note Synchronization level: Thread safe
*
* @note
* It is only required to specify as many pin variables as is required
* for the bus; the rest will default to NC (not connected)
*/
BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
BusOut(PinName pins[16]);
virtual ~BusOut();
/** Write the value to the output bus
*
* @param value An integer specifying a bit to write for every corresponding DigitalOut pin
*/
void write(int value);
/** Read the value currently output on the bus
*
* @returns
* An integer with each bit corresponding to associated DigitalOut pin setting
*/
int read();
/** Binary mask of bus pins connected to actual pins (not NC pins)
* If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
*
* @returns
* Binary mask of connected pins
*/
int mask() {
// No lock needed since _nc_mask is not modified outside the constructor
return _nc_mask;
}
/** A shorthand for write()
*/
BusOut& operator= (int v);
BusOut& operator= (BusOut& rhs);
/** Access to particular bit in random-iterator fashion
*/
DigitalOut& operator[] (int index);
/** A shorthand for read()
*/
operator int();
protected:
virtual void lock();
virtual void unlock();
DigitalOut* _pin[16];
/** Mask of bus's NC pins
* If bit[n] is set to 1 - pin is connected
* if bit[n] is cleared - pin is not connected (NC)
*/
int _nc_mask;
PlatformMutex _mutex;
/* disallow copy constructor and assignment operators */
private:
BusOut(const BusOut&);
BusOut & operator = (const BusOut&);
};
} // namespace mbed
#endif
/** @}*/

131
drivers/CAN.cpp
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "drivers/CAN.h"
#if DEVICE_CAN
#include "cmsis.h"
namespace mbed {
static void donothing() {}
CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
// No lock needed in constructor
for (int i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
_irq[i].attach(donothing);
}
can_init(&_can, rd, td);
can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
}
CAN::~CAN() {
// No lock needed in destructor
can_irq_free(&_can);
can_free(&_can);
}
int CAN::frequency(int f) {
lock();
int ret = can_frequency(&_can, f);
unlock();
return ret;
}
int CAN::write(CANMessage msg) {
lock();
int ret = can_write(&_can, msg, 0);
unlock();
return ret;
}
int CAN::read(CANMessage &msg, int handle) {
lock();
int ret = can_read(&_can, &msg, handle);
unlock();
return ret;
}
void CAN::reset() {
lock();
can_reset(&_can);
unlock();
}
unsigned char CAN::rderror() {
lock();
int ret = can_rderror(&_can);
unlock();
return ret;
}
unsigned char CAN::tderror() {
lock();
int ret = can_tderror(&_can);
unlock();
return ret;
}
void CAN::monitor(bool silent) {
lock();
can_monitor(&_can, (silent) ? 1 : 0);
unlock();
}
int CAN::mode(Mode mode) {
lock();
int ret = can_mode(&_can, (CanMode)mode);
unlock();
return ret;
}
int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
lock();
int ret = can_filter(&_can, id, mask, format, handle);
unlock();
return ret;
}
void CAN::attach(Callback<void()> func, IrqType type) {
lock();
if (func) {
_irq[(CanIrqType)type].attach(func);
can_irq_set(&_can, (CanIrqType)type, 1);
} else {
_irq[(CanIrqType)type].attach(donothing);
can_irq_set(&_can, (CanIrqType)type, 0);
}
unlock();
}
void CAN::_irq_handler(uint32_t id, CanIrqType type) {
CAN *handler = (CAN*)id;
handler->_irq[type].call();
}
void CAN::lock() {
_mutex.lock();
}
void CAN::unlock() {
_mutex.unlock();
}
} // namespace mbed
#endif

262
drivers/CAN.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CAN_H
#define MBED_CAN_H
#include "platform/platform.h"
#if DEVICE_CAN
#include "hal/can_api.h"
#include "platform/Callback.h"
#include "platform/PlatformMutex.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** CANMessage class
*
* @Note Synchronization level: Thread safe
*/
class CANMessage : public CAN_Message {
public:
/** Creates empty CAN message.
*/
CANMessage() : CAN_Message() {
len = 8;
type = CANData;
format = CANStandard;
id = 0;
memset(data, 0, 8);
}
/** Creates CAN message with specific content.
*/
CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
len = _len & 0xF;
type = _type;
format = _format;
id = _id;
memcpy(data, _data, _len);
}
/** Creates CAN remote message.
*/
CANMessage(int _id, CANFormat _format = CANStandard) {
len = 0;
type = CANRemote;
format = _format;
id = _id;
memset(data, 0, 8);
}
};
/** A can bus client, used for communicating with can devices
*/
class CAN {
public:
/** Creates an CAN interface connected to specific pins.
*
* @param rd read from transmitter
* @param td transmit to transmitter
*
* Example:
* @code
* #include "mbed.h"
*
* Ticker ticker;
* DigitalOut led1(LED1);
* DigitalOut led2(LED2);
* CAN can1(p9, p10);
* CAN can2(p30, p29);
*
* char counter = 0;
*
* void send() {
* if(can1.write(CANMessage(1337, &counter, 1))) {
* printf("Message sent: %d\n", counter);
* counter++;
* }
* led1 = !led1;
* }
*
* int main() {
* ticker.attach(&send, 1);
* CANMessage msg;
* while(1) {
* if(can2.read(msg)) {
* printf("Message received: %d\n\n", msg.data[0]);
* led2 = !led2;
* }
* wait(0.2);
* }
* }
* @endcode
*/
CAN(PinName rd, PinName td);
virtual ~CAN();
/** Set the frequency of the CAN interface
*
* @param hz The bus frequency in hertz
*
* @returns
* 1 if successful,
* 0 otherwise
*/
int frequency(int hz);
/** Write a CANMessage to the bus.
*
* @param msg The CANMessage to write.
*
* @returns
* 0 if write failed,
* 1 if write was successful
*/
int write(CANMessage msg);
/** Read a CANMessage from the bus.
*
* @param msg A CANMessage to read to.
* @param handle message filter handle (0 for any message)
*
* @returns
* 0 if no message arrived,
* 1 if message arrived
*/
int read(CANMessage &msg, int handle = 0);
/** Reset CAN interface.
*
* To use after error overflow.
*/
void reset();
/** Puts or removes the CAN interface into silent monitoring mode
*
* @param silent boolean indicating whether to go into silent mode or not
*/
void monitor(bool silent);
enum Mode {
Reset = 0,
Normal,
Silent,
LocalTest,
GlobalTest,
SilentTest
};
/** Change CAN operation to the specified mode
*
* @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
*
* @returns
* 0 if mode change failed or unsupported,
* 1 if mode change was successful
*/
int mode(Mode mode);
/** Filter out incomming messages
*
* @param id the id to filter on
* @param mask the mask applied to the id
* @param format format to filter on (Default CANAny)
* @param handle message filter handle (Optional)
*
* @returns
* 0 if filter change failed or unsupported,
* new filter handle if successful
*/
int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
/** Returns number of read errors to detect read overflow errors.
*/
unsigned char rderror();
/** Returns number of write errors to detect write overflow errors.
*/
unsigned char tderror();
enum IrqType {
RxIrq = 0,
TxIrq,
EwIrq,
DoIrq,
WuIrq,
EpIrq,
AlIrq,
BeIrq,
IdIrq,
IrqCnt
};
/** Attach a function to call whenever a CAN frame received interrupt is
* generated.
*
* @param func A pointer to a void function, or 0 to set as none
* @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
*/
void attach(Callback<void()> func, IrqType type=RxIrq);
/** Attach a member function to call whenever a CAN frame received interrupt
* is generated.
*
* @param obj pointer to the object to call the member function on
* @param method pointer to the member function to be called
* @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
*/
template<typename T>
void attach(T* obj, void (T::*method)(), IrqType type=RxIrq) {
// Underlying call thread safe
attach(Callback<void()>(obj, method), type);
}
/** Attach a member function to call whenever a CAN frame received interrupt
* is generated.
*
* @param obj pointer to the object to call the member function on
* @param method pointer to the member function to be called
* @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
*/
template<typename T>
void attach(T* obj, void (*method)(T*), IrqType type=RxIrq) {
// Underlying call thread safe
attach(Callback<void()>(obj, method), type);
}
static void _irq_handler(uint32_t id, CanIrqType type);
protected:
virtual void lock();
virtual void unlock();
can_t _can;
Callback<void()> _irq[IrqCnt];
PlatformMutex _mutex;
};
} // namespace mbed
#endif
#endif // MBED_CAN_H
/** @}*/

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drivers/DigitalIn.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DIGITALIN_H
#define MBED_DIGITALIN_H
#include "platform/platform.h"
#include "hal/gpio_api.h"
#include "platform/critical.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** A digital input, used for reading the state of a pin
*
* @Note Synchronization level: Interrupt safe
*
* Example:
* @code
* // Flash an LED while a DigitalIn is true
*
* #include "mbed.h"
*
* DigitalIn enable(p5);
* DigitalOut led(LED1);
*
* int main() {
* while(1) {
* if(enable) {
* led = !led;
* }
* wait(0.25);
* }
* }
* @endcode
*/
class DigitalIn {
public:
/** Create a DigitalIn connected to the specified pin
*
* @param pin DigitalIn pin to connect to
*/
DigitalIn(PinName pin) : gpio() {
// No lock needed in the constructor
gpio_init_in(&gpio, pin);
}
/** Create a DigitalIn connected to the specified pin
*
* @param pin DigitalIn pin to connect to
* @param mode the initial mode of the pin
*/
DigitalIn(PinName pin, PinMode mode) : gpio() {
// No lock needed in the constructor
gpio_init_in_ex(&gpio, pin, mode);
}
/** Read the input, represented as 0 or 1 (int)
*
* @returns
* An integer representing the state of the input pin,
* 0 for logical 0, 1 for logical 1
*/
int read() {
// Thread safe / atomic HAL call
return gpio_read(&gpio);
}
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone, OpenDrain
*/
void mode(PinMode pull) {
core_util_critical_section_enter();
gpio_mode(&gpio, pull);
core_util_critical_section_exit();
}
/** Return the output setting, represented as 0 or 1 (int)
*
* @returns
* Non zero value if pin is connected to uc GPIO
* 0 if gpio object was initialized with NC
*/
int is_connected() {
// Thread safe / atomic HAL call
return gpio_is_connected(&gpio);
}
/** An operator shorthand for read()
*/
operator int() {
// Underlying read is thread safe
return read();
}
protected:
gpio_t gpio;
};
} // namespace mbed
#endif
/** @}*/

144
drivers/DigitalInOut.h
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@ -1,144 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DIGITALINOUT_H
#define MBED_DIGITALINOUT_H
#include "platform/platform.h"
#include "hal/gpio_api.h"
#include "platform/critical.h"
namespace mbed {
/** \addtogroup drivers */
/** @{*/
/** A digital input/output, used for setting or reading a bi-directional pin
*
* @Note Synchronization level: Interrupt safe
*/
class DigitalInOut {
public:
/** Create a DigitalInOut connected to the specified pin
*
* @param pin DigitalInOut pin to connect to
*/
DigitalInOut(PinName pin) : gpio() {
// No lock needed in the constructor
gpio_init_in(&gpio, pin);
}
/** Create a DigitalInOut connected to the specified pin
*
* @param pin DigitalInOut pin to connect to
* @param direction the initial direction of the pin
* @param mode the initial mode of the pin
* @param value the initial value of the pin if is an output
*/
DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
// No lock needed in the constructor
gpio_init_inout(&gpio, pin, direction, mode, value);
}
/** Set the output, specified as 0 or 1 (int)
*
* @param value An integer specifying the pin output value,
* 0 for logical 0, 1 (or any other non-zero value) for logical 1
*/
void write(int value) {
// Thread safe / atomic HAL call
gpio_write(&gpio, value);
}
/** Return the output setting, represented as 0 or 1 (int)
*
* @returns
* an integer representing the output setting of the pin if it is an output,
* or read the input if set as an input
*/
int read() {
// Thread safe / atomic HAL call
return gpio_read(&gpio);
}
/** Set as an output
*/
void output() {
core_util_critical_section_enter();
gpio_dir(&gpio, PIN_OUTPUT);
core_util_critical_section_exit();
}
/** Set as an input
*/
void input() {
core_util_critical_section_enter();
gpio_dir(&gpio, PIN_INPUT);
core_util_critical_section_exit();
}
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone, OpenDrain
*/
void mode(PinMode pull) {
core_util_critical_section_enter();
gpio_mode(&gpio, pull);
core_util_critical_section_exit();
}
/** Return the output setting, represented as 0 or 1 (int)
*
* @returns
* Non zero value if pin is connected to uc GPIO
* 0 if gpio object was initialized with NC
*/
int is_connected() {
// Thread safe / atomic HAL call
return gpio_is_connected(&gpio);
}
/** A shorthand for write()
*/
DigitalInOut& operator= (int value) {
// Underlying write is thread safe
write(value);
return *this;
}
DigitalInOut& operator= (DigitalInOut& rhs) {
core_util_critical_section_enter();
write(rhs.read());
core_util_critical_section_exit();
return *this;
}
/** A shorthand for read()
*/
operator int() {
// Underlying call is thread safe
return read();
}
protected:
gpio_t gpio;
};
} // namespace mbed
#endif
/** @}*/

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