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targets:RT1050: Fix the low speed switch issue 

Fix the low speed switch issue when using QSPI flash

Signed-off-by: Tim Wang <tim.wang@nxp.com>
pull/14323/head
Tim Wang 2020-08-28 10:59:27 +08:00 committed by Arto Kinnunen
parent b14ddf69b7
commit 9c3c3d2dcc
1 changed files with 7 additions and 1 deletions
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8
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c
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@ -75,7 +75,11 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode)
case LPM_PowerModeLowSpeedRun:
case LPM_PowerModeSysIdle:
CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
#ifdef HYPERFLASH_BOOT
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode
#else
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 3); // FLEXSPI in SDR mode
#endif
CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2
/* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */
CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
@ -108,6 +112,7 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode)
/* Enable clock gate of flexspi. */
CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);
#ifdef HYPERFLASH_BOOT
if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode))
{
FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19);
@ -116,7 +121,8 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode)
{
FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15);
}
#endif
FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)