ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add MAX32660EVSYS 

- Add SDK files (updated to match mbed system)
- Implement mbed API files
- Update mbed related configuration (CMakefiles, .json files...)
- Add gcc and arm related files (linker, scatter, startup...)
- Tested with ARM and GCC_ARM toolchain
- GreenTea tests have been executed

Signed-off-by: Sadik.Ozer <Sadik.Ozer@maximintegrated.com>
pull/15109/head
Sadik.Ozer 2021-09-27 11:38:23 +03:00
parent 4cfbea43ca
commit 9c029bfc08
141 changed files with 31581 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
targets/TARGET_Maxim/CMakeLists.txt
View File

@ -5,6 +5,7 @@
add_subdirectory(TARGET_MAX32620C EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MAX32625 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MAX32630 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MAX32660 EXCLUDE_FROM_ALL)
add_library(mbed-maxim INTERFACE)

110
targets/TARGET_Maxim/TARGET_MAX32660/CMakeLists.txt Normal file
View File

@ -0,0 +1,110 @@
# Copyright (c) 2020-2021 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_MAX32660EVSYS EXCLUDE_FROM_ALL)
add_subdirectory(device EXCLUDE_FROM_ALL)
add_library(mbed-max32660 INTERFACE)
set(MXM_PARTNUMBER MAX32660)
set(MXM_SOURCE_DIR ./Libraries/PeriphDrivers/Source)
set(MXM_PERIPH_DRIVER_DIR ./Libraries/PeriphDrivers)
set(MXM_CMSIS_DIR ./Libraries/CMSIS/Device/Maxim)
target_include_directories(mbed-max32660
INTERFACE
.
${MXM_PERIPH_DRIVER_DIR}/Include/${MXM_PARTNUMBER}
${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Include
${MXM_SOURCE_DIR}/DMA
${MXM_SOURCE_DIR}/LP
${MXM_SOURCE_DIR}/FLC
${MXM_SOURCE_DIR}/GPIO
${MXM_SOURCE_DIR}/I2C
${MXM_SOURCE_DIR}/ICC
${MXM_SOURCE_DIR}/RTC
${MXM_SOURCE_DIR}/SPI
${MXM_SOURCE_DIR}/SPIMSS
${MXM_SOURCE_DIR}/TMR
${MXM_SOURCE_DIR}/UART
${MXM_SOURCE_DIR}/WDT
)
target_sources(mbed-max32660
INTERFACE
PeripheralPins.c
gpio_api.c
gpio_irq_api.c
i2c_api.c
pinmap.c
port_api.c
rtc_api.c
serial_api.c
sleep.c
spi_api.c
us_ticker.c
lp_ticker.c
flash_api.c
${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Source/system_max32660.c
${MXM_SOURCE_DIR}/SYS/mxc_assert.c
${MXM_SOURCE_DIR}/SYS/mxc_delay.c
${MXM_SOURCE_DIR}/SYS/mxc_lock.c
${MXM_SOURCE_DIR}/SYS/pins_me11.c
${MXM_SOURCE_DIR}/SYS/sys_me11.c
${MXM_SOURCE_DIR}/SYS/nvic_table.c
${MXM_SOURCE_DIR}/DMA/dma_me11.c
${MXM_SOURCE_DIR}/DMA/dma_reva.c
${MXM_SOURCE_DIR}/LP/lp_me11.c
${MXM_SOURCE_DIR}/FLC/flc_common.c
${MXM_SOURCE_DIR}/FLC/flc_me11.c
${MXM_SOURCE_DIR}/FLC/flc_reva.c
${MXM_SOURCE_DIR}/GPIO/gpio_common.c
${MXM_SOURCE_DIR}/GPIO/gpio_me11.c
${MXM_SOURCE_DIR}/GPIO/gpio_reva.c
${MXM_SOURCE_DIR}/I2C/i2c_me11.c
${MXM_SOURCE_DIR}/I2C/i2c_reva.c
${MXM_SOURCE_DIR}/SPIMSS/spimss_me11.c
${MXM_SOURCE_DIR}/SPIMSS/spimss_reva.c
${MXM_SOURCE_DIR}/SPIMSS/i2s_me11.c
${MXM_SOURCE_DIR}/SPIMSS/i2s_reva.c
${MXM_SOURCE_DIR}/ICC/icc_common.c
${MXM_SOURCE_DIR}/ICC/icc_me11.c
${MXM_SOURCE_DIR}/ICC/icc_reva.c
${MXM_SOURCE_DIR}/RTC/rtc_me11.c
${MXM_SOURCE_DIR}/RTC/rtc_reva.c
${MXM_SOURCE_DIR}/SPI/spi_me11.c
${MXM_SOURCE_DIR}/SPI/spi_reva.c
${MXM_SOURCE_DIR}/TMR/tmr_common.c
${MXM_SOURCE_DIR}/TMR/tmr_me11.c
${MXM_SOURCE_DIR}/TMR/tmr_reva.c
${MXM_SOURCE_DIR}/UART/uart_common.c
${MXM_SOURCE_DIR}/UART/uart_me11.c
${MXM_SOURCE_DIR}/UART/uart_reva.c
${MXM_SOURCE_DIR}/WDT/wdt_common.c
${MXM_SOURCE_DIR}/WDT/wdt_me11.c
${MXM_SOURCE_DIR}/WDT/wdt_reva.c
)
target_link_libraries(mbed-max32660
INTERFACE
mbed-maxim
)

390
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h Normal file
View File

@ -0,0 +1,390 @@
/**
* @file dma_regs.h
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _DMA_REGS_H_
#define _DMA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup dma
* @defgroup dma_registers DMA_Registers
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @details DMA Controller Fully programmable, chaining capable DMA channels.
*/
/**
* @ingroup dma_registers
* Structure type to access the DMA Channel Registers.
*/
typedef struct {
__IO uint32_t cfg; /**< <tt>\b 0x100:</tt> DMA CFG Register */
__IO uint32_t stat; /**< <tt>\b 0x104:</tt> DMA STAT Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t src_rld; /**< <tt>\b 0x114:</tt> DMA SRC_RLD Register */
__IO uint32_t dst_rld; /**< <tt>\b 0x118:</tt> DMA DST_RLD Register */
__IO uint32_t cnt_rld; /**< <tt>\b 0x11C:</tt> DMA CNT_RLD Register */
} mxc_dma_ch_regs_t;
/**
* @ingroup dma_registers
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t int_en; /**< <tt>\b 0x000:</tt> DMA INT_EN Register */
__I uint32_t int_fl; /**< <tt>\b 0x004:</tt> DMA INT_FL Register */
__I uint32_t rsv_0x8_0xff[62];
__IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */
} mxc_dma_regs_t;
/* Register offsets for module DMA */
/**
* @ingroup dma_registers
* @defgroup DMA_Register_Offsets Register Offsets
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_STAT ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_INT_EN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_INT_FL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
/**@} end of group dma_registers */
/**
* @ingroup dma_registers
* @defgroup DMA_INT_EN DMA_INT_EN
* @brief DMA Control Register.
* @{
*/
#define MXC_F_DMA_INT_EN_CHIEN_POS 0 /**< INT_EN_CHIEN Position */
#define MXC_F_DMA_INT_EN_CHIEN ((uint32_t)(0xFUL << MXC_F_DMA_INT_EN_CHIEN_POS)) /**< INT_EN_CHIEN Mask */
#define MXC_V_DMA_INT_EN_CHIEN_DIS ((uint32_t)0x0UL) /**< INT_EN_CHIEN_DIS Value */
#define MXC_S_DMA_INT_EN_CHIEN_DIS (MXC_V_DMA_INT_EN_CHIEN_DIS << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_DIS Setting */
#define MXC_V_DMA_INT_EN_CHIEN_EN ((uint32_t)0x1UL) /**< INT_EN_CHIEN_EN Value */
#define MXC_S_DMA_INT_EN_CHIEN_EN (MXC_V_DMA_INT_EN_CHIEN_EN << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_EN Setting */
/**@} end of group DMA_INT_EN_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_INT_FL DMA_INT_FL
* @brief DMA Interrupt Register.
* @{
*/
#define MXC_F_DMA_INT_FL_IPEND_POS 0 /**< INT_FL_IPEND Position */
#define MXC_F_DMA_INT_FL_IPEND ((uint32_t)(0xFUL << MXC_F_DMA_INT_FL_IPEND_POS)) /**< INT_FL_IPEND Mask */
#define MXC_V_DMA_INT_FL_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IPEND_INACTIVE Value */
#define MXC_S_DMA_INT_FL_IPEND_INACTIVE (MXC_V_DMA_INT_FL_IPEND_INACTIVE << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_INACTIVE Setting */
#define MXC_V_DMA_INT_FL_IPEND_PENDING ((uint32_t)0x1UL) /**< INT_FL_IPEND_PENDING Value */
#define MXC_S_DMA_INT_FL_IPEND_PENDING (MXC_V_DMA_INT_FL_IPEND_PENDING << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_PENDING Setting */
/**@} end of group DMA_INT_FL_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CFG DMA_CFG
* @brief DMA Channel Configuration Register.
* @{
*/
#define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */
#define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */
#define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */
#define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */
#define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */
#define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */
#define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */
#define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */
#define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */
#define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */
#define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */
#define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */
#define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */
#define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */
#define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */
#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */
#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */
#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */
#define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */
#define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */
#define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */
#define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */
#define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */
#define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */
#define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */
#define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */
#define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */
#define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */
#define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */
#define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */
#define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */
#define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */
#define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */
#define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */
#define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */
#define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */
#define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */
#define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */
#define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */
#define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */
#define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */
#define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */
#define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */
#define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */
#define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */
#define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */
#define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */
#define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */
#define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */
#define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */
#define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */
#define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */
#define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */
#define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */
#define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */
#define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */
#define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */
#define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */
#define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */
#define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */
#define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */
#define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */
#define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */
#define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */
/**@} end of group DMA_CFG_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_STAT DMA_STAT
* @brief DMA Channel Status Register.
* @{
*/
#define MXC_F_DMA_STAT_CH_ST_POS 0 /**< STAT_CH_ST Position */
#define MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS)) /**< STAT_CH_ST Mask */
#define MXC_F_DMA_STAT_IPEND_POS 1 /**< STAT_IPEND Position */
#define MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS)) /**< STAT_IPEND Mask */
#define MXC_F_DMA_STAT_CTZ_ST_POS 2 /**< STAT_CTZ_ST Position */
#define MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS)) /**< STAT_CTZ_ST Mask */
#define MXC_F_DMA_STAT_RLD_ST_POS 3 /**< STAT_RLD_ST Position */
#define MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS)) /**< STAT_RLD_ST Mask */
#define MXC_F_DMA_STAT_BUS_ERR_POS 4 /**< STAT_BUS_ERR Position */
#define MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS)) /**< STAT_BUS_ERR Mask */
#define MXC_F_DMA_STAT_TO_ST_POS 6 /**< STAT_TO_ST Position */
#define MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS)) /**< STAT_TO_ST Mask */
/**@} end of group DMA_STAT_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRC DMA_SRC
* @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or
* 4, depending on the data width of each AHB cycle. For peripheral transfers, some
* or all of the actual address bits are fixed. If SRCINC=0, this register remains
* constant. In the case where a count-to-zero condition occurs while RLDEN=1, the
* register is reloaded with the contents of DMA_SRC_RLD.
* @{
*/
#define MXC_F_DMA_SRC_SRC_POS 0 /**< SRC_SRC Position */
#define MXC_F_DMA_SRC_SRC ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_SRC_POS)) /**< SRC_SRC Mask */
/**@} end of group DMA_SRC_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DST DMA_DST
* @brief Destination Device Address. For peripheral transfers, some or all of the actual
* address bits are fixed. If DSTINC=1, this register is incremented on every AHB
* write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the
* data width of each AHB cycle. In the case where a count-to-zero condition occurs
* while RLDEN=1, the register is reloaded with DMA_DST_RLD.
* @{
*/
#define MXC_F_DMA_DST_DST_POS 0 /**< DST_DST Position */
#define MXC_F_DMA_DST_DST ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_DST_POS)) /**< DST_DST Mask */
/**@} end of group DMA_DST_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNT DMA_CNT
* @brief DMA Counter. The user loads this register with the number of bytes to transfer.
* This counter decreases on every AHB cycle into the DMA FIFO. The decrement will
* be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter
* reaches 0, a count-to-zero condition is triggered.
* @{
*/
#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */
#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
/**@} end of group DMA_CNT_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRC_RLD DMA_SRC_RLD
* @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC
* upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */
#define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */
/**@} end of group DMA_SRC_RLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DST_RLD DMA_DST_RLD
* @brief Destination Address Reload Value. The value of this register is loaded into
* DMA0_DST upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */
#define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */
/**@} end of group DMA_DST_RLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNT_RLD DMA_CNT_RLD
* @brief DMA Channel Count Reload Register.
* @{
*/
#define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */
#define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */
#define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */
#define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */
/**@} end of group DMA_CNT_RLD_Register */
#ifdef __cplusplus
}
#endif
#endif /* _DMA_REGS_H_ */

124
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h Normal file
View File

@ -0,0 +1,124 @@
/**
* @file fcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _FCR_REGS_H_
#define _FCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup fcr
* @defgroup fcr_registers FCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
* @details Function Control.
*/
/**
* @ingroup fcr_registers
* Structure type to access the FCR Registers.
*/
typedef struct {
__IO uint32_t reg0; /**< <tt>\b 0x00:</tt> FCR REG0 Register */
} mxc_fcr_regs_t;
/* Register offsets for module FCR */
/**
* @ingroup fcr_registers
* @defgroup FCR_Register_Offsets Register Offsets
* @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
* @{
*/
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
/**@} end of group fcr_registers */
/**
* @ingroup fcr_registers
* @defgroup FCR_REG0 FCR_REG0
* @brief Register 0.
* @{
*/
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */
/**@} end of group FCR_REG0_Register */
#ifdef __cplusplus
}
#endif
#endif /* _FCR_REGS_H_ */

228
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h Normal file
View File

@ -0,0 +1,228 @@
/**
* @file flc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _FLC_REGS_H_
#define _FLC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup flc
* @defgroup flc_registers FLC_Registers
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
* @details Flash Memory Control.
*/
/**
* @ingroup flc_registers
* Structure type to access the FLC Registers.
*/
typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */
__I uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
__I uint32_t rsv_0x28_0x2f[2];
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
} mxc_flc_regs_t;
/* Register offsets for module FLC */
/**
* @ingroup flc_registers
* @defgroup FLC_Register_Offsets Register Offsets
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
* @{
*/
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
/**@} end of group flc_registers */
/**
* @ingroup flc_registers
* @defgroup FLC_ADDR FLC_ADDR
* @brief Flash Write Address.
* @{
*/
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_ADDR_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_CLKDIV FLC_CLKDIV
* @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
* MHz clock for Flash controller.
* @{
*/
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_CLKDIV_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_CTRL FLC_CTRL
* @brief Flash Control Register.
* @{
*/
#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */
#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */
#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */
#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */
#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */
#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */
#define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */
#define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */
#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */
#define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
#define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */
#define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */
#define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */
#define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */
#define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */
#define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */
/**@} end of group FLC_CTRL_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_INTR FLC_INTR
* @brief Flash Interrupt Register.
* @{
*/
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */
#define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */
#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */
#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */
/**@} end of group FLC_INTR_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_DATA FLC_DATA
* @brief Flash Write Data.
* @{
*/
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_DATA_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_ACTRL FLC_ACTRL
* @brief Access Control Register. Writing the ACTRL register with the following values in
* the order shown, allows read and write access to the system and user Information
* block: pflc-actrl = 0x3a7f5ca3; pflc-actrl =
* 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of
* any word will disable access to system and user information block. Readback of
* this register is always zero.
* @{
*/
#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
/**@} end of group FLC_ACTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_REGS_H_ */

436
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h Normal file
View File

@ -0,0 +1,436 @@
/**
* @file gcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GCR_REGS_H_
#define _GCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gcr
* @defgroup gcr_registers GCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
* @details Global Control Registers.
*/
/**
* @ingroup gcr_registers
* Structure type to access the GCR Registers.
*/
typedef struct {
__IO uint32_t scon; /**< <tt>\b 0x00:</tt> GCR SCON Register */
__IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */
__IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */
__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
__I uint32_t rsv_0x10_0x23[5];
__IO uint32_t pclk_dis0; /**< <tt>\b 0x24:</tt> GCR PCLK_DIS0 Register */
__IO uint32_t mem_ctrl; /**< <tt>\b 0x28:</tt> GCR MEM_CTRL Register */
__IO uint32_t mem_zctrl; /**< <tt>\b 0x2C:</tt> GCR MEM_ZCTRL Register */
__I uint32_t rsv_0x30_0x3f[4];
__IO uint32_t sys_stat; /**< <tt>\b 0x40:</tt> GCR SYS_STAT Register */
__IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */
__IO uint32_t pclk_dis1; /**< <tt>\b 0x48:</tt> GCR PCLK_DIS1 Register */
__IO uint32_t evten; /**< <tt>\b 0x4C:</tt> GCR EVTEN Register */
__I uint32_t rev; /**< <tt>\b 0x50:</tt> GCR REV Register */
__IO uint32_t sys_ie; /**< <tt>\b 0x54:</tt> GCR SYS_IE Register */
} mxc_gcr_regs_t;
/* Register offsets for module GCR */
/**
* @ingroup gcr_registers
* @defgroup GCR_Register_Offsets Register Offsets
* @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
* @{
*/
#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */
#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */
#define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */
#define MXC_R_GCR_MEM_CTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */
#define MXC_R_GCR_MEM_ZCTRL ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */
#define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */
#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */
#define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */
#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */
#define MXC_R_GCR_REV ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
#define MXC_R_GCR_SYS_IE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
/**@} end of group gcr_registers */
/**
* @ingroup gcr_registers
* @defgroup GCR_SCON GCR_SCON
* @brief System Control.
* @{
*/
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */
#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
#define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
#define MXC_F_GCR_SCON_ICC0_FLUSH_POS 6 /**< SCON_ICC0_FLUSH Position */
#define MXC_F_GCR_SCON_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_ICC0_FLUSH_POS)) /**< SCON_ICC0_FLUSH Mask */
#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
#define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
/**@} end of group GCR_SCON_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_RST0 GCR_RST0
* @brief Reset.
* @{
*/
#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */
#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */
#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */
#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */
#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */
#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */
#define MXC_F_GCR_RST0_TIMER0_POS 5 /**< RST0_TIMER0 Position */
#define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) /**< RST0_TIMER0 Mask */
#define MXC_F_GCR_RST0_TIMER1_POS 6 /**< RST0_TIMER1 Position */
#define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) /**< RST0_TIMER1 Mask */
#define MXC_F_GCR_RST0_TIMER2_POS 7 /**< RST0_TIMER2 Position */
#define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) /**< RST0_TIMER2 Mask */
#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */
#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */
#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */
#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */
#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */
#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */
#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */
#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */
#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */
#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */
#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */
#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */
#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */
#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */
#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */
#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */
#define MXC_F_GCR_RST0_SYSTEM_POS 31 /**< RST0_SYSTEM Position */
#define MXC_F_GCR_RST0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS)) /**< RST0_SYSTEM Mask */
/**@} end of group GCR_RST0_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_CLK_CTRL GCR_CLK_CTRL
* @brief Clock Control.
* @{
*/
#define MXC_F_GCR_CLK_CTRL_PSC_POS 6 /**< CLK_CTRL_PSC Position */
#define MXC_F_GCR_CLK_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_PSC_POS)) /**< CLK_CTRL_PSC Mask */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CLK_CTRL_PSC_DIV1 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV1 (MXC_V_GCR_CLK_CTRL_PSC_DIV1 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV1 Setting */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CLK_CTRL_PSC_DIV2 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV2 (MXC_V_GCR_CLK_CTRL_PSC_DIV2 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV2 Setting */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CLK_CTRL_PSC_DIV4 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV4 (MXC_V_GCR_CLK_CTRL_PSC_DIV4 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV4 Setting */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CLK_CTRL_PSC_DIV8 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV8 (MXC_V_GCR_CLK_CTRL_PSC_DIV8 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV8 Setting */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CLK_CTRL_PSC_DIV16 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV16 (MXC_V_GCR_CLK_CTRL_PSC_DIV16 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV16 Setting */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CLK_CTRL_PSC_DIV32 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV32 (MXC_V_GCR_CLK_CTRL_PSC_DIV32 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV32 Setting */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CLK_CTRL_PSC_DIV64 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV64 (MXC_V_GCR_CLK_CTRL_PSC_DIV64 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV64 Setting */
#define MXC_V_GCR_CLK_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CLK_CTRL_PSC_DIV128 Value */
#define MXC_S_GCR_CLK_CTRL_PSC_DIV128 (MXC_V_GCR_CLK_CTRL_PSC_DIV128 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV128 Setting */
#define MXC_F_GCR_CLK_CTRL_CLKSEL_POS 9 /**< CLK_CTRL_CLKSEL Position */
#define MXC_F_GCR_CLK_CTRL_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_CLKSEL_POS)) /**< CLK_CTRL_CLKSEL Mask */
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLK_CTRL_CLKSEL_HIRC Value */
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC (MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HIRC Setting */
#define MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLK_CTRL_CLKSEL_NANORING Value */
#define MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING (MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_NANORING Setting */
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLK_CTRL_CLKSEL_HFXIN Value */
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN (MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HFXIN Setting */
#define MXC_F_GCR_CLK_CTRL_CLKRDY_POS 13 /**< CLK_CTRL_CLKRDY Position */
#define MXC_F_GCR_CLK_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CLKRDY_POS)) /**< CLK_CTRL_CLKRDY Mask */
#define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 /**< CLK_CTRL_X32K_EN Position */
#define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) /**< CLK_CTRL_X32K_EN Mask */
#define MXC_F_GCR_CLK_CTRL_HIRC_EN_POS 18 /**< CLK_CTRL_HIRC_EN Position */
#define MXC_F_GCR_CLK_CTRL_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_EN_POS)) /**< CLK_CTRL_HIRC_EN Mask */
#define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 /**< CLK_CTRL_X32K_RDY Position */
#define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) /**< CLK_CTRL_X32K_RDY Mask */
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS 26 /**< CLK_CTRL_HIRC_RDY Position */
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS)) /**< CLK_CTRL_HIRC_RDY Mask */
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29 /**< CLK_CTRL_LIRC8K_RDY Position */
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) /**< CLK_CTRL_LIRC8K_RDY Mask */
/**@} end of group GCR_CLK_CTRL_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PM GCR_PM
* @brief Power Management.
* @{
*/
#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
#define MXC_F_GCR_PM_GPIOWK_EN_POS 4 /**< PM_GPIOWK_EN Position */
#define MXC_F_GCR_PM_GPIOWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWK_EN_POS)) /**< PM_GPIOWK_EN Mask */
#define MXC_F_GCR_PM_RTCWK_EN_POS 5 /**< PM_RTCWK_EN Position */
#define MXC_F_GCR_PM_RTCWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWK_EN_POS)) /**< PM_RTCWK_EN Mask */
#define MXC_F_GCR_PM_HFIOPD_POS 15 /**< PM_HFIOPD Position */
#define MXC_F_GCR_PM_HFIOPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HFIOPD_POS)) /**< PM_HFIOPD Mask */
/**@} end of group GCR_PM_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PCLK_DIS0 GCR_PCLK_DIS0
* @brief Peripheral Clock Disable.
* @{
*/
#define MXC_F_GCR_PCLK_DIS0_GPIO0D_POS 0 /**< PCLK_DIS0_GPIO0D Position */
#define MXC_F_GCR_PCLK_DIS0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0D_POS)) /**< PCLK_DIS0_GPIO0D Mask */
#define MXC_F_GCR_PCLK_DIS0_DMAD_POS 5 /**< PCLK_DIS0_DMAD Position */
#define MXC_F_GCR_PCLK_DIS0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMAD_POS)) /**< PCLK_DIS0_DMAD Mask */
#define MXC_F_GCR_PCLK_DIS0_SPI0D_POS 6 /**< PCLK_DIS0_SPI0D Position */
#define MXC_F_GCR_PCLK_DIS0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0D_POS)) /**< PCLK_DIS0_SPI0D Mask */
#define MXC_F_GCR_PCLK_DIS0_SPI1D_POS 7 /**< PCLK_DIS0_SPI1D Position */
#define MXC_F_GCR_PCLK_DIS0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1D_POS)) /**< PCLK_DIS0_SPI1D Mask */
#define MXC_F_GCR_PCLK_DIS0_UART0D_POS 9 /**< PCLK_DIS0_UART0D Position */
#define MXC_F_GCR_PCLK_DIS0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0D_POS)) /**< PCLK_DIS0_UART0D Mask */
#define MXC_F_GCR_PCLK_DIS0_UART1D_POS 10 /**< PCLK_DIS0_UART1D Position */
#define MXC_F_GCR_PCLK_DIS0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1D_POS)) /**< PCLK_DIS0_UART1D Mask */
#define MXC_F_GCR_PCLK_DIS0_I2C0D_POS 13 /**< PCLK_DIS0_I2C0D Position */
#define MXC_F_GCR_PCLK_DIS0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0D_POS)) /**< PCLK_DIS0_I2C0D Mask */
#define MXC_F_GCR_PCLK_DIS0_TIMER0D_POS 15 /**< PCLK_DIS0_TIMER0D Position */
#define MXC_F_GCR_PCLK_DIS0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0D_POS)) /**< PCLK_DIS0_TIMER0D Mask */
#define MXC_F_GCR_PCLK_DIS0_TIMER1D_POS 16 /**< PCLK_DIS0_TIMER1D Position */
#define MXC_F_GCR_PCLK_DIS0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1D_POS)) /**< PCLK_DIS0_TIMER1D Mask */
#define MXC_F_GCR_PCLK_DIS0_TIMER2D_POS 17 /**< PCLK_DIS0_TIMER2D Position */
#define MXC_F_GCR_PCLK_DIS0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2D_POS)) /**< PCLK_DIS0_TIMER2D Mask */
#define MXC_F_GCR_PCLK_DIS0_I2C1D_POS 28 /**< PCLK_DIS0_I2C1D Position */
#define MXC_F_GCR_PCLK_DIS0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1D_POS)) /**< PCLK_DIS0_I2C1D Mask */
/**@} end of group GCR_PCLK_DIS0_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_MEM_CTRL GCR_MEM_CTRL
* @brief Memory Clock Control Register.
* @{
*/
#define MXC_F_GCR_MEM_CTRL_FWS_POS 0 /**< MEM_CTRL_FWS Position */
#define MXC_F_GCR_MEM_CTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CTRL_FWS_POS)) /**< MEM_CTRL_FWS Mask */
#define MXC_F_GCR_MEM_CTRL_RAM0_LS_POS 8 /**< MEM_CTRL_RAM0_LS Position */
#define MXC_F_GCR_MEM_CTRL_RAM0_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM0_LS_POS)) /**< MEM_CTRL_RAM0_LS Mask */
#define MXC_F_GCR_MEM_CTRL_RAM1_LS_POS 9 /**< MEM_CTRL_RAM1_LS Position */
#define MXC_F_GCR_MEM_CTRL_RAM1_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM1_LS_POS)) /**< MEM_CTRL_RAM1_LS Mask */
#define MXC_F_GCR_MEM_CTRL_RAM2_LS_POS 10 /**< MEM_CTRL_RAM2_LS Position */
#define MXC_F_GCR_MEM_CTRL_RAM2_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM2_LS_POS)) /**< MEM_CTRL_RAM2_LS Mask */
#define MXC_F_GCR_MEM_CTRL_RAM3_LS_POS 11 /**< MEM_CTRL_RAM3_LS Position */
#define MXC_F_GCR_MEM_CTRL_RAM3_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM3_LS_POS)) /**< MEM_CTRL_RAM3_LS Mask */
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS 12 /**< MEM_CTRL_ICACHE_RET Position */
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS)) /**< MEM_CTRL_ICACHE_RET Mask */
/**@} end of group GCR_MEM_CTRL_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_MEM_ZCTRL GCR_MEM_ZCTRL
* @brief Memory Zeroize Control.
* @{
*/
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS 0 /**< MEM_ZCTRL_SRAM_ZERO Position */
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS)) /**< MEM_ZCTRL_SRAM_ZERO Mask */
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS 1 /**< MEM_ZCTRL_ICACHE_ZERO Position */
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS)) /**< MEM_ZCTRL_ICACHE_ZERO Mask */
/**@} end of group GCR_MEM_ZCTRL_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_SYS_STAT GCR_SYS_STAT
* @brief System Status Register.
* @{
*/
#define MXC_F_GCR_SYS_STAT_ICECLOCK_POS 0 /**< SYS_STAT_ICECLOCK Position */
#define MXC_F_GCR_SYS_STAT_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICECLOCK_POS)) /**< SYS_STAT_ICECLOCK Mask */
/**@} end of group GCR_SYS_STAT_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_RST1 GCR_RST1
* @brief Reset 1.
* @{
*/
#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */
#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */
/**@} end of group GCR_RST1_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PCLK_DIS1 GCR_PCLK_DIS1
* @brief Peripheral Clock Disable.
* @{
*/
#define MXC_F_GCR_PCLK_DIS1_FLCD_POS 3 /**< PCLK_DIS1_FLCD Position */
#define MXC_F_GCR_PCLK_DIS1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_FLCD_POS)) /**< PCLK_DIS1_FLCD Mask */
#define MXC_F_GCR_PCLK_DIS1_ICCD_POS 11 /**< PCLK_DIS1_ICCD Position */
#define MXC_F_GCR_PCLK_DIS1_ICCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICCD_POS)) /**< PCLK_DIS1_ICCD Mask */
/**@} end of group GCR_PCLK_DIS1_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_EVTEN GCR_EVTEN
* @brief Event Enable Register.
* @{
*/
#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
#define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
#define MXC_F_GCR_EVTEN_RX_EVT_POS 1 /**< EVTEN_RX_EVT Position */
#define MXC_F_GCR_EVTEN_RX_EVT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RX_EVT_POS)) /**< EVTEN_RX_EVT Mask */
/**@} end of group GCR_EVTEN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_REV GCR_REV
* @brief Revision Register.
* @{
*/
#define MXC_F_GCR_REV_REVISION_POS 0 /**< REV_REVISION Position */
#define MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) /**< REV_REVISION Mask */
/**@} end of group GCR_REV_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_SYS_IE GCR_SYS_IE
* @brief System Status Interrupt Enable
* @{
*/
#define MXC_F_GCR_SYS_IE_ICEULIE_POS 0 /**< SYS_IE_ICEULIE Position */
#define MXC_F_GCR_SYS_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_IE_ICEULIE_POS)) /**< SYS_IE_ICEULIE Mask */
/**@} end of group GCR_SYS_IE_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GCR_REGS_H_ */

677
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h Normal file
View File

@ -0,0 +1,677 @@
/**
* @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gpio
* @defgroup gpio_registers GPIO_Registers
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @details Individual I/O for each GPIO
*/
/**
* @ingroup gpio_registers
* Structure type to access the GPIO Registers.
*/
typedef struct {
__IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */
__IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */
__IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */
__IO uint32_t out_en; /**< <tt>\b 0x0C:</tt> GPIO OUT_EN Register */
__IO uint32_t out_en_set; /**< <tt>\b 0x10:</tt> GPIO OUT_EN_SET Register */
__IO uint32_t out_en_clr; /**< <tt>\b 0x14:</tt> GPIO OUT_EN_CLR Register */
__IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */
__O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
__O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
__I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */
__IO uint32_t int_mod; /**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */
__IO uint32_t int_pol; /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */
__IO uint32_t in_en; /**< <tt>\b 0x30:</tt> GPIO IN_EN Register */
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
__IO uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
__I uint32_t rsv_0x44;
__IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
__IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
__IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
__I uint32_t rsv_0x58;
__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
__I uint32_t rsv_0x80_0xa7[10];
__IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */
__IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
__I uint32_t rsv_0xbc;
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
} mxc_gpio_regs_t;
/* Register offsets for module GPIO */
/**
* @ingroup gpio_registers
* @defgroup GPIO_Register_Offsets Register Offsets
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
* @{
*/
#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
#define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
#define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
#define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
#define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
#define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
#define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
#define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
#define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
#define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
/**@} end of group gpio_registers */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0 GPIO_EN0
* @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
* GPIO pin on the associated port.
* @{
*/
#define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */
#define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
#define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
#define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
#define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
#define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
/**@} end of group GPIO_EN0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0_SET GPIO_EN0_SET
* @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
* register sets the bits in the same positions in GPIO_EN to 1, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */
#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
/**@} end of group GPIO_EN0_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0_CLR GPIO_EN0_CLR
* @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */
#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
/**@} end of group GPIO_EN0_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN GPIO_OUT_EN
* @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
* GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */
/**@} end of group GPIO_OUT_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET
* @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
* in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
#define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
/**@} end of group GPIO_OUT_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR
* @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
* bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
#define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
/**@} end of group GPIO_OUT_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT GPIO_OUT
* @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
* associated port. This register can be written either directly, or by using the
* GPIO_OUT_SET and GPIO_OUT_CLR registers.
* @{
*/
#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
/**@} end of group GPIO_OUT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_SET GPIO_OUT_SET
* @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
* in the same positions in GPIO_OUT to 1, without affecting other bits in that
* register.
* @{
*/
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
/**@} end of group GPIO_OUT_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
* @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_OUT to 0, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
/**@} end of group GPIO_OUT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IN GPIO_IN
* @brief GPIO Input Register. Read-only register to read from the logic states of the
* GPIO pins on this port.
* @{
*/
#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
/**@} end of group GPIO_IN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_MOD GPIO_INT_MOD
* @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
* mode setting for the associated GPIO pin on this port.
* @{
*/
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */
/**@} end of group GPIO_INT_MOD_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_POL GPIO_INT_POL
* @brief GPIO Interrupt Polarity Register. Each bit in this register controls the
* interrupt polarity setting for one GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */
/**@} end of group GPIO_INT_POL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IN_EN GPIO_IN_EN
* @brief GPIO Port Input Enable.
* @{
*/
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */
/**@} end of group GPIO_IN_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN GPIO_INT_EN
* @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
* interrupt enable for the associated pin on the GPIO port.
* @{
*/
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */
/**@} end of group GPIO_INT_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET
* @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
* the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */
/**@} end of group GPIO_INT_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR
* @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */
/**@} end of group GPIO_INT_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_STAT GPIO_INT_STAT
* @brief GPIO Interrupt Status Register. Each bit in this register contains the pending
* interrupt status for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */
/**@} end of group GPIO_INT_STAT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_CLR GPIO_INT_CLR
* @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
#define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
/**@} end of group GPIO_INT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN GPIO_WAKE_EN
* @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
* enable for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */
/**@} end of group GPIO_WAKE_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET
* @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
* bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
#define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */
/**@} end of group GPIO_WAKE_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR
* @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
* the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
#define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */
/**@} end of group GPIO_WAKE_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE
* @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
* edge mode for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */
/**@} end of group GPIO_INT_DUAL_EDGE_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1
* @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */
/**@} end of group GPIO_PAD_CFG1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2
* @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */
/**@} end of group GPIO_PAD_CFG2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1 GPIO_EN1
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
/**@} end of group GPIO_EN1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_SET GPIO_EN1_SET
* @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
/**@} end of group GPIO_EN1_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
* @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
/**@} end of group GPIO_EN1_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2 GPIO_EN2
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
/**@} end of group GPIO_EN2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_SET GPIO_EN2_SET
* @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
/**@} end of group GPIO_EN2_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
* @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN2 to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
/**@} end of group GPIO_EN2_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS0 GPIO_DS0
* @brief GPIO Drive Strength Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */
#define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */
#define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */
#define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */
#define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */
#define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */
/**@} end of group GPIO_DS0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS1 GPIO_DS1
* @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
/**@} end of group GPIO_DS1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PS GPIO_PS
* @brief GPIO Pull Select Mode.
* @{
*/
#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
/**@} end of group GPIO_PS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_VSSEL GPIO_VSSEL
* @brief GPIO Voltage Select.
* @{
*/
#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
/**@} end of group GPIO_VSSEL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_REGS_H_ */

586
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h Normal file
View File

@ -0,0 +1,586 @@
/**
* @file i2c_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _I2C_REGS_H_
#define _I2C_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup i2c
* @defgroup i2c_registers I2C_Registers
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @details Inter-Integrated Circuit.
*/
/**
* @ingroup i2c_registers
* Structure type to access the I2C Registers.
*/
typedef struct {
__IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> I2C CTRL0 Register */
__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
__IO uint32_t intfl0; /**< <tt>\b 0x08:</tt> I2C INTFL0 Register */
__IO uint32_t inten0; /**< <tt>\b 0x0C:</tt> I2C INTEN0 Register */
__IO uint32_t intfl1; /**< <tt>\b 0x10:</tt> I2C INTFL1 Register */
__IO uint32_t inten1; /**< <tt>\b 0x14:</tt> I2C INTEN1 Register */
__IO uint32_t fifolen; /**< <tt>\b 0x18:</tt> I2C FIFOLEN Register */
__IO uint32_t rxctrl0; /**< <tt>\b 0x1C:</tt> I2C RXCTRL0 Register */
__IO uint32_t rxctrl1; /**< <tt>\b 0x20:</tt> I2C RXCTRL1 Register */
__IO uint32_t txctrl0; /**< <tt>\b 0x24:</tt> I2C TXCTRL0 Register */
__IO uint32_t txctrl1; /**< <tt>\b 0x28:</tt> I2C TXCTRL1 Register */
__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
__IO uint32_t mstr_mode; /**< <tt>\b 0x30:</tt> I2C MSTR_MODE Register */
__IO uint32_t clklo; /**< <tt>\b 0x34:</tt> I2C CLKLO Register */
__IO uint32_t clkhi; /**< <tt>\b 0x38:</tt> I2C CLKHI Register */
__IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
__IO uint32_t sladdr; /**< <tt>\b 0x44:</tt> I2C SLADDR Register */
__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
} mxc_i2c_regs_t;
/* Register offsets for module I2C */
/**
* @ingroup i2c_registers
* @defgroup I2C_Register_Offsets Register Offsets
* @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
* @{
*/
#define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */
#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */
#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */
#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */
#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */
#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */
#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */
#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */
#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */
#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */
#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */
#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */
#define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */
#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */
#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */
#define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */
#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */
#define MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */
#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */
/**@} end of group i2c_registers */
/**
* @ingroup i2c_registers
* @defgroup I2C_CTRL0 I2C_CTRL0
* @brief Control Register0.
* @{
*/
#define MXC_F_I2C_CTRL0_I2CEN_POS 0 /**< CTRL0_I2CEN Position */
#define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) /**< CTRL0_I2CEN Mask */
#define MXC_F_I2C_CTRL0_MST_POS 1 /**< CTRL0_MST Position */
#define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) /**< CTRL0_MST Mask */
#define MXC_F_I2C_CTRL0_GCEN_POS 2 /**< CTRL0_GCEN Position */
#define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) /**< CTRL0_GCEN Mask */
#define MXC_F_I2C_CTRL0_IRXM_POS 3 /**< CTRL0_IRXM Position */
#define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) /**< CTRL0_IRXM Mask */
#define MXC_F_I2C_CTRL0_ACK_POS 4 /**< CTRL0_ACK Position */
#define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) /**< CTRL0_ACK Mask */
#define MXC_F_I2C_CTRL0_SCLO_POS 6 /**< CTRL0_SCLO Position */
#define MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS)) /**< CTRL0_SCLO Mask */
#define MXC_F_I2C_CTRL0_SDAO_POS 7 /**< CTRL0_SDAO Position */
#define MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS)) /**< CTRL0_SDAO Mask */
#define MXC_F_I2C_CTRL0_SCL_POS 8 /**< CTRL0_SCL Position */
#define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) /**< CTRL0_SCL Mask */
#define MXC_F_I2C_CTRL0_SDA_POS 9 /**< CTRL0_SDA Position */
#define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) /**< CTRL0_SDA Mask */
#define MXC_F_I2C_CTRL0_SWOE_POS 10 /**< CTRL0_SWOE Position */
#define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) /**< CTRL0_SWOE Mask */
#define MXC_F_I2C_CTRL0_READ_POS 11 /**< CTRL0_READ Position */
#define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) /**< CTRL0_READ Mask */
#define MXC_F_I2C_CTRL0_SCL_STRD_POS 12 /**< CTRL0_SCL_STRD Position */
#define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) /**< CTRL0_SCL_STRD Mask */
#define MXC_F_I2C_CTRL0_SCL_PPM_POS 13 /**< CTRL0_SCL_PPM Position */
#define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) /**< CTRL0_SCL_PPM Mask */
#define MXC_F_I2C_CTRL0_HSMODE_POS 15 /**< CTRL0_HSMODE Position */
#define MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS)) /**< CTRL0_HSMODE Mask */
/**@} end of group I2C_CTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_STATUS I2C_STATUS
* @brief Status Register.
* @{
*/
#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */
#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
#define MXC_F_I2C_STATUS_RXE_POS 1 /**< STATUS_RXE Position */
#define MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS)) /**< STATUS_RXE Mask */
#define MXC_F_I2C_STATUS_RXF_POS 2 /**< STATUS_RXF Position */
#define MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS)) /**< STATUS_RXF Mask */
#define MXC_F_I2C_STATUS_TXE_POS 3 /**< STATUS_TXE Position */
#define MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS)) /**< STATUS_TXE Mask */
#define MXC_F_I2C_STATUS_TXF_POS 4 /**< STATUS_TXF Position */
#define MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS)) /**< STATUS_TXF Mask */
#define MXC_F_I2C_STATUS_CKMD_POS 5 /**< STATUS_CKMD Position */
#define MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS)) /**< STATUS_CKMD Mask */
#define MXC_F_I2C_STATUS_STAT_POS 8 /**< STATUS_STAT Position */
#define MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS)) /**< STATUS_STAT Mask */
#define MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL) /**< STATUS_STAT_IDLE Value */
#define MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_IDLE Setting */
#define MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STAT_MTX_ADDR Value */
#define MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_ADDR Setting */
#define MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STAT_MRX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STAT_MTX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STAT_MRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STAT_SRX_ADDR Value */
#define MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_ADDR Setting */
#define MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STAT_STX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STAT_SRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STAT_STX_EX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_EX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL) /**< STATUS_STAT_TX Value */
#define MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX Setting */
#define MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STAT_RX_ACK Value */
#define MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX_ACK Setting */
#define MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL) /**< STATUS_STAT_RX Value */
#define MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX Setting */
#define MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STAT_TX_ACK Value */
#define MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX_ACK Setting */
#define MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL) /**< STATUS_STAT_NACK Value */
#define MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_NACK Setting */
#define MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL) /**< STATUS_STAT_BY_ST Value */
#define MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_BY_ST Setting */
/**@} end of group I2C_STATUS_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTFL0 I2C_INTFL0
* @brief Interrupt Status Register.
* @{
*/
#define MXC_F_I2C_INTFL0_DONEI_POS 0 /**< INTFL0_DONEI Position */
#define MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS)) /**< INTFL0_DONEI Mask */
#define MXC_F_I2C_INTFL0_IRXMI_POS 1 /**< INTFL0_IRXMI Position */
#define MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS)) /**< INTFL0_IRXMI Mask */
#define MXC_F_I2C_INTFL0_GCI_POS 2 /**< INTFL0_GCI Position */
#define MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS)) /**< INTFL0_GCI Mask */
#define MXC_F_I2C_INTFL0_AMI_POS 3 /**< INTFL0_AMI Position */
#define MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS)) /**< INTFL0_AMI Mask */
#define MXC_F_I2C_INTFL0_RXTHI_POS 4 /**< INTFL0_RXTHI Position */
#define MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS)) /**< INTFL0_RXTHI Mask */
#define MXC_F_I2C_INTFL0_TXTHI_POS 5 /**< INTFL0_TXTHI Position */
#define MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS)) /**< INTFL0_TXTHI Mask */
#define MXC_F_I2C_INTFL0_STOPI_POS 6 /**< INTFL0_STOPI Position */
#define MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS)) /**< INTFL0_STOPI Mask */
#define MXC_F_I2C_INTFL0_ADRACKI_POS 7 /**< INTFL0_ADRACKI Position */
#define MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS)) /**< INTFL0_ADRACKI Mask */
#define MXC_F_I2C_INTFL0_ARBERI_POS 8 /**< INTFL0_ARBERI Position */
#define MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS)) /**< INTFL0_ARBERI Mask */
#define MXC_F_I2C_INTFL0_TOERI_POS 9 /**< INTFL0_TOERI Position */
#define MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS)) /**< INTFL0_TOERI Mask */
#define MXC_F_I2C_INTFL0_ADRERI_POS 10 /**< INTFL0_ADRERI Position */
#define MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS)) /**< INTFL0_ADRERI Mask */
#define MXC_F_I2C_INTFL0_DATERI_POS 11 /**< INTFL0_DATERI Position */
#define MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS)) /**< INTFL0_DATERI Mask */
#define MXC_F_I2C_INTFL0_DNRERI_POS 12 /**< INTFL0_DNRERI Position */
#define MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS)) /**< INTFL0_DNRERI Mask */
#define MXC_F_I2C_INTFL0_STRTERI_POS 13 /**< INTFL0_STRTERI Position */
#define MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS)) /**< INTFL0_STRTERI Mask */
#define MXC_F_I2C_INTFL0_STOPERI_POS 14 /**< INTFL0_STOPERI Position */
#define MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS)) /**< INTFL0_STOPERI Mask */
#define MXC_F_I2C_INTFL0_TXLOI_POS 15 /**< INTFL0_TXLOI Position */
#define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) /**< INTFL0_TXLOI Mask */
/**@} end of group I2C_INTFL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTEN0 I2C_INTEN0
* @brief Interrupt Enable Register.
* @{
*/
#define MXC_F_I2C_INTEN0_DONEIE_POS 0 /**< INTEN0_DONEIE Position */
#define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) /**< INTEN0_DONEIE Mask */
#define MXC_F_I2C_INTEN0_IRXMIE_POS 1 /**< INTEN0_IRXMIE Position */
#define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) /**< INTEN0_IRXMIE Mask */
#define MXC_F_I2C_INTEN0_GCIE_POS 2 /**< INTEN0_GCIE Position */
#define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) /**< INTEN0_GCIE Mask */
#define MXC_F_I2C_INTEN0_AMIE_POS 3 /**< INTEN0_AMIE Position */
#define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) /**< INTEN0_AMIE Mask */
#define MXC_F_I2C_INTEN0_RXTHIE_POS 4 /**< INTEN0_RXTHIE Position */
#define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) /**< INTEN0_RXTHIE Mask */
#define MXC_F_I2C_INTEN0_TXTHIE_POS 5 /**< INTEN0_TXTHIE Position */
#define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) /**< INTEN0_TXTHIE Mask */
#define MXC_F_I2C_INTEN0_STOPIE_POS 6 /**< INTEN0_STOPIE Position */
#define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) /**< INTEN0_STOPIE Mask */
#define MXC_F_I2C_INTEN0_ADRACKIE_POS 7 /**< INTEN0_ADRACKIE Position */
#define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) /**< INTEN0_ADRACKIE Mask */
#define MXC_F_I2C_INTEN0_ARBERIE_POS 8 /**< INTEN0_ARBERIE Position */
#define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) /**< INTEN0_ARBERIE Mask */
#define MXC_F_I2C_INTEN0_TOERIE_POS 9 /**< INTEN0_TOERIE Position */
#define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) /**< INTEN0_TOERIE Mask */
#define MXC_F_I2C_INTEN0_ADRERIE_POS 10 /**< INTEN0_ADRERIE Position */
#define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) /**< INTEN0_ADRERIE Mask */
#define MXC_F_I2C_INTEN0_DATERIE_POS 11 /**< INTEN0_DATERIE Position */
#define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) /**< INTEN0_DATERIE Mask */
#define MXC_F_I2C_INTEN0_DNRERIE_POS 12 /**< INTEN0_DNRERIE Position */
#define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) /**< INTEN0_DNRERIE Mask */
#define MXC_F_I2C_INTEN0_STRTERIE_POS 13 /**< INTEN0_STRTERIE Position */
#define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) /**< INTEN0_STRTERIE Mask */
#define MXC_F_I2C_INTEN0_STOPERIE_POS 14 /**< INTEN0_STOPERIE Position */
#define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) /**< INTEN0_STOPERIE Mask */
#define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */
#define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */
/**@} end of group I2C_INTEN0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTFL1 I2C_INTFL1
* @brief Interrupt Status Register 1.
* @{
*/
#define MXC_F_I2C_INTFL1_RXOFI_POS 0 /**< INTFL1_RXOFI Position */
#define MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS)) /**< INTFL1_RXOFI Mask */
#define MXC_F_I2C_INTFL1_TXUFI_POS 1 /**< INTFL1_TXUFI Position */
#define MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS)) /**< INTFL1_TXUFI Mask */
/**@} end of group I2C_INTFL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTEN1 I2C_INTEN1
* @brief Interrupt Staus Register 1.
* @{
*/
#define MXC_F_I2C_INTEN1_RXOFIE_POS 0 /**< INTEN1_RXOFIE Position */
#define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) /**< INTEN1_RXOFIE Mask */
#define MXC_F_I2C_INTEN1_TXUFIE_POS 1 /**< INTEN1_TXUFIE Position */
#define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) /**< INTEN1_TXUFIE Mask */
/**@} end of group I2C_INTEN1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFOLEN I2C_FIFOLEN
* @brief FIFO Configuration Register.
* @{
*/
#define MXC_F_I2C_FIFOLEN_RXLEN_POS 0 /**< FIFOLEN_RXLEN Position */
#define MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS)) /**< FIFOLEN_RXLEN Mask */
#define MXC_F_I2C_FIFOLEN_TXLEN_POS 8 /**< FIFOLEN_TXLEN Position */
#define MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS)) /**< FIFOLEN_TXLEN Mask */
/**@} end of group I2C_FIFOLEN_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RXCTRL0 I2C_RXCTRL0
* @brief Receive Control Register 0.
* @{
*/
#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */
#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */
#define MXC_F_I2C_RXCTRL0_RXFSH_POS 7 /**< RXCTRL0_RXFSH Position */
#define MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS)) /**< RXCTRL0_RXFSH Mask */
#define MXC_F_I2C_RXCTRL0_RXTH_POS 8 /**< RXCTRL0_RXTH Position */
#define MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS)) /**< RXCTRL0_RXTH Mask */
/**@} end of group I2C_RXCTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RXCTRL1 I2C_RXCTRL1
* @brief Receive Control Register 1.
* @{
*/
#define MXC_F_I2C_RXCTRL1_RXCNT_POS 0 /**< RXCTRL1_RXCNT Position */
#define MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS)) /**< RXCTRL1_RXCNT Mask */
#define MXC_F_I2C_RXCTRL1_RXFIFO_POS 8 /**< RXCTRL1_RXFIFO Position */
#define MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS)) /**< RXCTRL1_RXFIFO Mask */
/**@} end of group I2C_RXCTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TXCTRL0 I2C_TXCTRL0
* @brief Transmit Control Register 0.
* @{
*/
#define MXC_F_I2C_TXCTRL0_TXPRELD_POS 0 /**< TXCTRL0_TXPRELD Position */
#define MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS)) /**< TXCTRL0_TXPRELD Mask */
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */
#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */
#define MXC_F_I2C_TXCTRL0_TXFSH_POS 7 /**< TXCTRL0_TXFSH Position */
#define MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS)) /**< TXCTRL0_TXFSH Mask */
#define MXC_F_I2C_TXCTRL0_TXTH_POS 8 /**< TXCTRL0_TXTH Position */
#define MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS)) /**< TXCTRL0_TXTH Mask */
/**@} end of group I2C_TXCTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TXCTRL1 I2C_TXCTRL1
* @brief Transmit Control Register 1.
* @{
*/
#define MXC_F_I2C_TXCTRL1_TXRDY_POS 0 /**< TXCTRL1_TXRDY Position */
#define MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS)) /**< TXCTRL1_TXRDY Mask */
#define MXC_F_I2C_TXCTRL1_TXLAST_POS 1 /**< TXCTRL1_TXLAST Position */
#define MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS)) /**< TXCTRL1_TXLAST Mask */
#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2 /**< TXCTRL1_FLSH_GCADDR_DIS Position */
#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS)) /**< TXCTRL1_FLSH_GCADDR_DIS Mask */
#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4 /**< TXCTRL1_FLSH_SLADDR_DIS Position */
#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS)) /**< TXCTRL1_FLSH_SLADDR_DIS Mask */
#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5 /**< TXCTRL1_FLSH_NACK_DIS Position */
#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS)) /**< TXCTRL1_FLSH_NACK_DIS Mask */
#define MXC_F_I2C_TXCTRL1_TXFIFO_POS 8 /**< TXCTRL1_TXFIFO Position */
#define MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS)) /**< TXCTRL1_TXFIFO Mask */
/**@} end of group I2C_TXCTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFO I2C_FIFO
* @brief Data Register.
* @{
*/
#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
/**@} end of group I2C_FIFO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_MSTR_MODE I2C_MSTR_MODE
* @brief Master Control Register.
* @{
*/
#define MXC_F_I2C_MSTR_MODE_START_POS 0 /**< MSTR_MODE_START Position */
#define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) /**< MSTR_MODE_START Mask */
#define MXC_F_I2C_MSTR_MODE_RESTART_POS 1 /**< MSTR_MODE_RESTART Position */
#define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) /**< MSTR_MODE_RESTART Mask */
#define MXC_F_I2C_MSTR_MODE_STOP_POS 2 /**< MSTR_MODE_STOP Position */
#define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) /**< MSTR_MODE_STOP Mask */
#define MXC_F_I2C_MSTR_MODE_SEA_POS 7 /**< MSTR_MODE_SEA Position */
#define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) /**< MSTR_MODE_SEA Mask */
/**@} end of group I2C_MSTR_MODE_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLKLO I2C_CLKLO
* @brief Clock Low Register.
* @{
*/
#define MXC_F_I2C_CLKLO_SCL_LO_POS 0 /**< CLKLO_SCL_LO Position */
#define MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS)) /**< CLKLO_SCL_LO Mask */
/**@} end of group I2C_CLKLO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLKHI I2C_CLKHI
* @brief Clock high Register.
* @{
*/
#define MXC_F_I2C_CLKHI_SCL_HI_POS 0 /**< CLKHI_SCL_HI Position */
#define MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS)) /**< CLKHI_SCL_HI Mask */
/**@} end of group I2C_CLKHI_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_HS_CLK I2C_HS_CLK
* @brief HS-Mode Clock Control Register
* @{
*/
#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
#define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */
#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
#define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */
/**@} end of group I2C_HS_CLK_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TIMEOUT I2C_TIMEOUT
* @brief Timeout Register
* @{
*/
#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
#define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
/**@} end of group I2C_TIMEOUT_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_SLADDR I2C_SLADDR
* @brief Slave Address Register.
* @{
*/
#define MXC_F_I2C_SLADDR_SLA_POS 0 /**< SLADDR_SLA Position */
#define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) /**< SLADDR_SLA Mask */
#define MXC_F_I2C_SLADDR_EA_POS 15 /**< SLADDR_EA Position */
#define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) /**< SLADDR_EA Mask */
/**@} end of group I2C_SLADDR_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_DMA I2C_DMA
* @brief DMA Register.
* @{
*/
#define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */
#define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */
#define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */
#define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */
/**@} end of group I2C_DMA_Register */
#ifdef __cplusplus
}
#endif
#endif /* _I2C_REGS_H_ */

157
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h Normal file
View File

@ -0,0 +1,157 @@
/**
* @file icc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _ICC_REGS_H_
#define _ICC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup icc
* @defgroup icc_registers ICC_Registers
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
* @details Instruction Cache Controller Registers
*/
/**
* @ingroup icc_registers
* Structure type to access the ICC Registers.
*/
typedef struct {
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
__I uint32_t mem_size; /**< <tt>\b 0x0004:</tt> ICC MEM_SIZE Register */
__I uint32_t rsv_0x8_0xff[62];
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
__I uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
} mxc_icc_regs_t;
/* Register offsets for module ICC */
/**
* @ingroup icc_registers
* @defgroup ICC_Register_Offsets Register Offsets
* @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address.
* @{
*/
#define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */
#define MXC_R_ICC_MEM_SIZE ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */
#define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */
#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */
/**@} end of group icc_registers */
/**
* @ingroup icc_registers
* @defgroup ICC_CACHE_ID ICC_CACHE_ID
* @brief Cache ID Register.
* @{
*/
#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
#define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
#define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
#define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
/**@} end of group ICC_CACHE_ID_Register */
/**
* @ingroup icc_registers
* @defgroup ICC_MEM_SIZE ICC_MEM_SIZE
* @brief Memory Configuration Register.
* @{
*/
#define MXC_F_ICC_MEM_SIZE_CCHSZ_POS 0 /**< MEM_SIZE_CCHSZ Position */
#define MXC_F_ICC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_CCHSZ_POS)) /**< MEM_SIZE_CCHSZ Mask */
#define MXC_F_ICC_MEM_SIZE_MEMSZ_POS 16 /**< MEM_SIZE_MEMSZ Position */
#define MXC_F_ICC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_MEMSZ_POS)) /**< MEM_SIZE_MEMSZ Mask */
/**@} end of group ICC_MEM_SIZE_Register */
/**
* @ingroup icc_registers
* @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL
* @brief Cache Control and Status Register.
* @{
*/
#define MXC_F_ICC_CACHE_CTRL_ENABLE_POS 0 /**< CACHE_CTRL_ENABLE Position */
#define MXC_F_ICC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS)) /**< CACHE_CTRL_ENABLE Mask */
#define MXC_F_ICC_CACHE_CTRL_READY_POS 16 /**< CACHE_CTRL_READY Position */
#define MXC_F_ICC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS)) /**< CACHE_CTRL_READY Mask */
/**@} end of group ICC_CACHE_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _ICC_REGS_H_ */

408
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h Normal file
View File

@ -0,0 +1,408 @@
/**
* @file max32660.h
* @brief Device-specific perhiperal header file
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
#ifndef _MAX32660_REGS_H_
#define _MAX32660_REGS_H_
#ifndef TARGET_NUM
#define TARGET_NUM 32660
#endif
#include <stdint.h>
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
#if !defined (__GNUC__)
#define CMSIS_VECTAB_VIRTUAL
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
#endif /* !__GNUC__ */
/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
#if defined ( __GNUC__ ) /* GCC */
#define __weak __attribute__((weak))
#elif defined ( __CC_ARM) /* Keil */
#define inline __inline
#pragma anon_unions
#endif
typedef enum {
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
/* Device-specific interrupt sources (external to ARM core) */
/* table entry number */
/* |||| */
/* |||| table offset address */
/* vvvv vvvvvv */
PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */
RTC_IRQn, /* 0x13 0x004C 19: RTC */
RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */
TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */
RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */
RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */
RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */
RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */
I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
SPI0_IRQn, /* 0x20 0x0080 32: SPI17Y */
SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */
RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */
RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */
RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */
RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */
RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */
FLC_IRQn, /* 0x27 0x009C 39: FLC */
GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */
RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */
RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */
DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */
RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */
RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */
RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */
I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */
RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */
RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */
RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */
RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */
RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */
RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */
RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */
RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */
RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */
RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */
RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */
RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */
RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */
RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */
RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */
RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */
GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
MXC_IRQ_EXT_COUNT,
} IRQn_Type;
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present or not */
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_max32660.h" /*!< System Header */
/* ================================================================================ */
/* ================== Device Specific Memory Section ================== */
/* ================================================================================ */
#define MXC_FLASH_MEM_BASE 0x00000000UL
#define MXC_FLASH_PAGE_SIZE 0x00002000UL
#define MXC_FLASH_MEM_SIZE 0x00040000UL
#define MXC_INFO_MEM_BASE 0x00040000UL
#define MXC_INFO_MEM_SIZE 0x00001000UL
#define MXC_SRAM_MEM_BASE 0x20000000UL
#define MXC_SRAM_MEM_SIZE 0x00018000UL
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/*
Base addresses and configuration settings for all MAX32660 peripheral modules.
*/
/******************************************************************************/
/* Global control */
#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
/******************************************************************************/
/* Non-battery backed SI Registers */
#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
/******************************************************************************/
/* Watchdog */
#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
/******************************************************************************/
/* Real Time Clock */
#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
/******************************************************************************/
/* Power Sequencer */
#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
/******************************************************************************/
/* GPIO */
#define MXC_CFG_GPIO_INSTANCES (1)
#define MXC_CFG_GPIO_PINS_PORT (14)
#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1)
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0)
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0)
/******************************************************************************/
/* Timer */
#define MXC_CFG_TMR_INSTANCES (3)
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
(i) == 1 ? TMR1_IRQn : \
(i) == 2 ? TMR2_IRQn : 0)
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
(i) == 1 ? MXC_BASE_TMR1 : \
(i) == 2 ? MXC_BASE_TMR2 : 0)
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
(i) == 1 ? MXC_TMR1 : \
(i) == 2 ? MXC_TMR2 : 0)
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
(p) == MXC_TMR1 ? 1 : \
(p) == MXC_TMR2 ? 2 : -1)
/******************************************************************************/
/* SPIMSS */
#define MXC_SPIMSS_INSTANCES (1)
#define MXC_SPIMSS_FIFO_DEPTH (8)
#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL)
#define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS)
#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1)
#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0)
/******************************************************************************/
/* I2C */
#define MXC_I2C_INSTANCES (2)
#define MXC_I2C_FIFO_DEPTH (8)
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
(i) == 1 ? I2C1_IRQn : 0)
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
(i) == 1 ? MXC_BASE_I2C1 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
(i) == 1 ? MXC_I2C1 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
(p) == MXC_I2C1 ? 1 : -1)
/******************************************************************************/
/* DMA */
#define MXC_DMA_CHANNELS (4)
#define MXC_DMA_INSTANCES (1)
#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA)
#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
/******************************************************************************/
/* FLC */
#define MXC_FLC_INSTANCES (1)
#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC)
#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0)
/******************************************************************************/
/* Instruction Cache */
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC)
/******************************************************************************/
/* UART / Serial Port Interface */
#define MXC_UART_INSTANCES (2)
#define MXC_UART_FIFO_DEPTH (8)
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
(i) == 1 ? UART1_IRQn : 0)
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
(i) == 1 ? MXC_BASE_UART1 : 0)
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
(i) == 1 ? MXC_UART1 : 0)
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
(p) == MXC_UART1 ? 1 : -1)
/******************************************************************************/
/* SPI */
#include "spi_regs.h"
#define MXC_SPI_INSTANCES (1)
#define MXC_SPI_SS_INSTANCES (1)
#define MXC_SPI_FIFO_DEPTH (32)
#define MXC_BASE_SPI ((uint32_t)0x40046000UL)
#define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI)
#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : -1)
#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0)
#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : 0)
/******************************************************************************/
/* Bit Shifting */
#define MXC_F_BIT_0 (1 << 0)
#define MXC_F_BIT_1 (1 << 1)
#define MXC_F_BIT_2 (1 << 2)
#define MXC_F_BIT_3 (1 << 3)
#define MXC_F_BIT_4 (1 << 4)
#define MXC_F_BIT_5 (1 << 5)
#define MXC_F_BIT_6 (1 << 6)
#define MXC_F_BIT_7 (1 << 7)
#define MXC_F_BIT_8 (1 << 8)
#define MXC_F_BIT_9 (1 << 9)
#define MXC_F_BIT_10 (1 << 10)
#define MXC_F_BIT_11 (1 << 11)
#define MXC_F_BIT_12 (1 << 12)
#define MXC_F_BIT_13 (1 << 13)
#define MXC_F_BIT_14 (1 << 14)
#define MXC_F_BIT_15 (1 << 15)
#define MXC_F_BIT_16 (1 << 16)
#define MXC_F_BIT_17 (1 << 17)
#define MXC_F_BIT_18 (1 << 18)
#define MXC_F_BIT_19 (1 << 19)
#define MXC_F_BIT_20 (1 << 20)
#define MXC_F_BIT_21 (1 << 21)
#define MXC_F_BIT_22 (1 << 22)
#define MXC_F_BIT_23 (1 << 23)
#define MXC_F_BIT_24 (1 << 24)
#define MXC_F_BIT_25 (1 << 25)
#define MXC_F_BIT_26 (1 << 26)
#define MXC_F_BIT_27 (1 << 27)
#define MXC_F_BIT_28 (1 << 28)
#define MXC_F_BIT_29 (1 << 29)
#define MXC_F_BIT_30 (1 << 30)
#define MXC_F_BIT_31 (1 << 31)
/******************************************************************************/
/* Bit Banding */
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask))
/******************************************************************************/
/* SCB CPACR */
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
#endif /* _MAX32660_REGS_H_ */

207
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h Normal file
View File

@ -0,0 +1,207 @@
/**
* @file pwrseq_regs.h
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _PWRSEQ_REGS_H_
#define _PWRSEQ_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup pwrseq
* @defgroup pwrseq_registers PWRSEQ_Registers
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
* @details Power Sequencer / Low Power Control Register.
*/
/**
* @ingroup pwrseq_registers
* Structure type to access the PWRSEQ Registers.
*/
typedef struct {
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
__I uint32_t rsv_0xc_0x3f[13];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
} mxc_pwrseq_regs_t;
/* Register offsets for module PWRSEQ */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_Register_Offsets Register Offsets
* @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.
* @{
*/
#define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */
#define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */
#define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
/**@} end of group pwrseq_registers */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL
* @brief Low Power Control Register.
* @{
*/
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */
#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
#define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */
/**@} end of group PWRSEQ_LP_CTRL_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL
* @brief Low Power Mode Wakeup Flags for GPIO0
* @{
*/
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */
/**@} end of group PWRSEQ_LP_WAKEFL_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN
* @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup
* functionality for GPIO0.
* @{
*/
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */
/**@} end of group PWRSEQ_LPWK_EN_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD
* @brief Low Power Memory Shutdown Control.
* @{
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */
/**@} end of group PWRSEQ_LPMEMSD_Register */
#ifdef __cplusplus
}
#endif
#endif /* _PWRSEQ_REGS_H_ */

253
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h Normal file
View File

@ -0,0 +1,253 @@
/**
* @file rtc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _RTC_REGS_H_
#define _RTC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup rtc
* @defgroup rtc_registers RTC_Registers
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @details Real Time Clock and Alarm.
*/
/**
* @ingroup rtc_registers
* Structure type to access the RTC Registers.
*/
typedef struct {
__IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */
__IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */
__IO uint32_t ras; /**< <tt>\b 0x08:</tt> RTC RAS Register */
__IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> RTC RSSA Register */
__IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */
__IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */
__IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
} mxc_rtc_regs_t;
/* Register offsets for module RTC */
/**
* @ingroup rtc_registers
* @defgroup RTC_Register_Offsets Register Offsets
* @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address.
* @{
*/
#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
#define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
#define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
/**@} end of group rtc_registers */
/**
* @ingroup rtc_registers
* @defgroup RTC_SSEC RTC_SSEC
* @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented
* when this register rolls over from 0xFF to 0x00.
* @{
*/
#define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */
#define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */
/**@} end of group RTC_SSEC_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_RAS RTC_RAS
* @brief Time-of-day Alarm.
* @{
*/
#define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */
#define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */
/**@} end of group RTC_RAS_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_RSSA RTC_RSSA
* @brief RTC sub-second alarm. This register contains the reload value for the sub-
* second alarm.
* @{
*/
#define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */
#define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */
/**@} end of group RTC_RSSA_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_CTRL RTC_CTRL
* @brief RTC Control Register.
* @{
*/
#define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */
#define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */
#define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */
#define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */
#define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */
#define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */
#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */
#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
#define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */
#define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */
#define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */
#define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */
#define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */
#define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */
#define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */
#define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */
#define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */
#define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */
#define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */
#define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */
#define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */
#define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */
#define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */
#define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */
#define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */
#define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */
#define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */
#define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */
#define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */
/**@} end of group RTC_CTRL_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_TRIM RTC_TRIM
* @brief RTC Trim Register.
* @{
*/
#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
#define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */
#define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */
/**@} end of group RTC_TRIM_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_OSCCTRL RTC_OSCCTRL
* @brief RTC Oscillator Control Register.
* @{
*/
#define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */
#define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */
#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */
#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */
#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */
#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */
#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
#define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */
#define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */
/**@} end of group RTC_OSCCTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _RTC_REGS_H_ */

135
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h Normal file
View File

@ -0,0 +1,135 @@
/**
* @file sir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SIR_REGS_H_
#define _SIR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup sir
* @defgroup sir_registers SIR_Registers
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
* @details System Initialization Registers.
*/
/**
* @ingroup sir_registers
* Structure type to access the SIR Registers.
*/
typedef struct {
__I uint32_t status; /**< <tt>\b 0x00:</tt> SIR STATUS Register */
__I uint32_t addr; /**< <tt>\b 0x04:</tt> SIR ADDR Register */
} mxc_sir_regs_t;
/* Register offsets for module SIR */
/**
* @ingroup sir_registers
* @defgroup SIR_Register_Offsets Register Offsets
* @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address.
* @{
*/
#define MXC_R_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
/**@} end of group sir_registers */
/**
* @ingroup sir_registers
* @defgroup SIR_STATUS SIR_STATUS
* @brief System Initialization Status Register.
* @{
*/
#define MXC_F_SIR_STATUS_CFG_VALID_POS 0 /**< STATUS_CFG_VALID Position */
#define MXC_F_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_VALID_POS)) /**< STATUS_CFG_VALID Mask */
#define MXC_F_SIR_STATUS_CFG_ERR_POS 1 /**< STATUS_CFG_ERR Position */
#define MXC_F_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_ERR_POS)) /**< STATUS_CFG_ERR Mask */
/**@} end of group SIR_STATUS_Register */
/**
* @ingroup sir_registers
* @defgroup SIR_ADDR SIR_ADDR
* @brief Read-only field set by the SIB block if a CRC error occurs during the read of
* the OTP memory. Contains the failing address in OTP memory (when CRCERR equals
* 1).
* @{
*/
#define MXC_F_SIR_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group SIR_ADDR_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SIR_REGS_H_ */

442
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h Normal file
View File

@ -0,0 +1,442 @@
/**
* @file spi_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spi
* @defgroup spi_registers SPI_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
* @details SPI peripheral.
*/
/**
* @ingroup spi_registers
* Structure type to access the SPI Registers.
*/
typedef struct {
__IO uint32_t data; /**< <tt>\b 0x00:</tt> SPI DATA Register */
__IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */
__IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
__IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */
__IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */
__I uint32_t rsv_0x18;
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */
__IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */
__IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */
__IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPI WAKE_FL Register */
__IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPI WAKE_EN Register */
__I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI STAT Register */
} mxc_spi_regs_t;
/* Register offsets for module SPI */
/**
* @ingroup spi_registers
* @defgroup SPI_Register_Offsets Register Offsets
* @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address.
* @{
*/
#define MXC_R_SPI_DATA ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */
#define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */
#define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */
#define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */
#define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */
#define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */
#define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */
/**@} end of group spi_registers */
/**
* @ingroup spi_registers
* @defgroup SPI_DATA SPI_DATA
* @brief Register for reading and writing the FIFO.
* @{
*/
/**@} end of group SPI_DATA_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CTRL0 SPI_CTRL0
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI_CTRL0_SPI_EN_POS 0 /**< CTRL0_SPI_EN Position */
#define MXC_F_SPI_CTRL0_SPI_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) /**< CTRL0_SPI_EN Mask */
#define MXC_F_SPI_CTRL0_MM_EN_POS 1 /**< CTRL0_MM_EN Position */
#define MXC_F_SPI_CTRL0_MM_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) /**< CTRL0_MM_EN Mask */
#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */
#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */
#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */
#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */
#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
#define MXC_F_SPI_CTRL0_SS_SEL_POS 16 /**< CTRL0_SS_SEL Position */
#define MXC_F_SPI_CTRL0_SS_SEL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) /**< CTRL0_SS_SEL Mask */
#define MXC_V_SPI_CTRL0_SS_SEL_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SEL_SS0 Value */
#define MXC_S_SPI_CTRL0_SS_SEL_SS0 (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS0 Setting */
#define MXC_V_SPI_CTRL0_SS_SEL_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SEL_SS1 Value */
#define MXC_S_SPI_CTRL0_SS_SEL_SS1 (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS1 Setting */
#define MXC_V_SPI_CTRL0_SS_SEL_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SEL_SS2 Value */
#define MXC_S_SPI_CTRL0_SS_SEL_SS2 (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS2 Setting */
#define MXC_V_SPI_CTRL0_SS_SEL_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SEL_SS3 Value */
#define MXC_S_SPI_CTRL0_SS_SEL_SS3 (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS3 Setting */
/**@} end of group SPI_CTRL0_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CTRL1 SPI_CTRL1
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
/**@} end of group SPI_CTRL1_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CTRL2 SPI_CTRL2
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI_CTRL2_CLK_PHA_POS 0 /**< CTRL2_CLK_PHA Position */
#define MXC_F_SPI_CTRL2_CLK_PHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) /**< CTRL2_CLK_PHA Mask */
#define MXC_F_SPI_CTRL2_CLK_POL_POS 1 /**< CTRL2_CLK_POL Position */
#define MXC_F_SPI_CTRL2_CLK_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) /**< CTRL2_CLK_POL Mask */
#define MXC_F_SPI_CTRL2_NUM_BITS_POS 8 /**< CTRL2_NUM_BITS Position */
#define MXC_F_SPI_CTRL2_NUM_BITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) /**< CTRL2_NUM_BITS Mask */
#define MXC_V_SPI_CTRL2_NUM_BITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUM_BITS_0 Value */
#define MXC_S_SPI_CTRL2_NUM_BITS_0 (MXC_V_SPI_CTRL2_NUM_BITS_0 << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_0 Setting */
#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */
#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */
#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
#define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */
#define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
/**@} end of group SPI_CTRL2_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_SS_TIME SPI_SS_TIME
* @brief Register for controlling SPI peripheral/Slave Select Timing.
* @{
*/
#define MXC_F_SPI_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */
#define MXC_F_SPI_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */
#define MXC_V_SPI_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */
#define MXC_S_SPI_SS_TIME_SSACT1_256 (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */
#define MXC_F_SPI_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */
#define MXC_F_SPI_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */
#define MXC_V_SPI_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */
#define MXC_S_SPI_SS_TIME_SSACT2_256 (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */
#define MXC_F_SPI_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */
#define MXC_F_SPI_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */
#define MXC_V_SPI_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */
#define MXC_S_SPI_SS_TIME_SSINACT_256 (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */
/**@} end of group SPI_SS_TIME_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CLK_CFG SPI_CLK_CFG
* @brief Register for controlling SPI clock rate.
* @{
*/
#define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */
#define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */
#define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */
#define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */
#define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */
#define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */
#define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */
#define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */
#define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */
#define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */
/**@} end of group SPI_CLK_CFG_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_DMA SPI_DMA
* @brief Register for controlling DMA.
* @{
*/
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */
#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
#define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
#define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
#define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
#define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */
#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
#define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
#define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
#define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
#define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
/**@} end of group SPI_DMA_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_INT_FL SPI_INT_FL
* @brief Register for reading and clearing interrupt flags. All bits are write 1 to
* clear.
* @{
*/
#define MXC_F_SPI_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */
#define MXC_F_SPI_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */
#define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */
#define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */
#define MXC_F_SPI_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */
#define MXC_F_SPI_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */
#define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */
#define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */
#define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */
#define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */
#define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */
#define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */
#define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */
#define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */
#define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */
#define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */
#define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */
#define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */
#define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */
#define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */
#define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */
#define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
#define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */
#define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */
/**@} end of group SPI_INT_FL_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_INT_EN SPI_INT_EN
* @brief Register for enabling interrupts.
* @{
*/
#define MXC_F_SPI_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */
#define MXC_F_SPI_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */
#define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */
#define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */
#define MXC_F_SPI_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */
#define MXC_F_SPI_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */
#define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */
#define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */
#define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */
#define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */
#define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */
#define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */
#define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */
#define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */
#define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */
#define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */
#define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */
#define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */
#define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */
#define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */
#define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */
#define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */
#define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */
#define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */
#define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */
#define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */
/**@} end of group SPI_INT_EN_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_WAKE_FL SPI_WAKE_FL
* @brief Register for wake up flags. All bits in this register are write 1 to clear.
* @{
*/
#define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */
#define MXC_F_SPI_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */
#define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */
#define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */
#define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */
#define MXC_F_SPI_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */
#define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */
#define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */
/**@} end of group SPI_WAKE_FL_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_WAKE_EN SPI_WAKE_EN
* @brief Register for wake up enable.
* @{
*/
#define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */
#define MXC_F_SPI_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */
#define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */
#define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */
#define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */
#define MXC_F_SPI_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */
#define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */
#define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */
/**@} end of group SPI_WAKE_EN_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_STAT SPI_STAT
* @brief SPI Status register.
* @{
*/
#define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */
#define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
/**@} end of group SPI_STAT_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPI_REGS_H_ */

346
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h Normal file
View File

@ -0,0 +1,346 @@
/**
* @file spimss_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPIMSS_REGS_H_
#define _SPIMSS_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spimss
* @defgroup spimss_registers SPIMSS_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
* @details Serial Peripheral Interface.
*/
/**
* @ingroup spimss_registers
* Structure type to access the SPIMSS Registers.
*/
typedef struct {
__IO uint16_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */
__I uint16_t rsv_0x2;
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
__IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */
__IO uint32_t mode; /**< <tt>\b 0x0C:</tt> SPIMSS MODE Register */
__I uint32_t rsv_0x10;
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
} mxc_spimss_regs_t;
/* Register offsets for module SPIMSS */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_Register_Offsets Register Offsets
* @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address.
* @{
*/
#define MXC_R_SPIMSS_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPIMSS_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPIMSS_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */
#define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */
/**@} end of group spimss_registers */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DATA SPIMSS_DATA
* @brief SPI 16-bit Data Access
* @{
*/
#define MXC_F_SPIMSS_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_SPIMSS_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group SPIMSS_DATA_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_CTRL SPIMSS_CTRL
* @brief SPI Control Register.
* @{
*/
#define MXC_F_SPIMSS_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
#define MXC_F_SPIMSS_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
#define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */
#define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */
#define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */
#define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */
#define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */
#define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */
#define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */
#define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */
#define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */
#define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */
#define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */
#define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */
#define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */
#define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */
/**@} end of group SPIMSS_CTRL_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_INT_FL SPIMSS_INT_FL
* @brief SPI Interrupt Flag Register.
* @{
*/
#define MXC_F_SPIMSS_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */
#define MXC_F_SPIMSS_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */
#define MXC_F_SPIMSS_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */
#define MXC_F_SPIMSS_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */
#define MXC_F_SPIMSS_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */
#define MXC_F_SPIMSS_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */
#define MXC_F_SPIMSS_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */
#define MXC_F_SPIMSS_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */
#define MXC_F_SPIMSS_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */
#define MXC_F_SPIMSS_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */
#define MXC_F_SPIMSS_INT_FL_COL_POS 5 /**< INT_FL_COL Position */
#define MXC_F_SPIMSS_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS)) /**< INT_FL_COL Mask */
#define MXC_F_SPIMSS_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */
#define MXC_F_SPIMSS_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */
#define MXC_F_SPIMSS_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */
#define MXC_F_SPIMSS_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */
/**@} end of group SPIMSS_INT_FL_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_MODE SPIMSS_MODE
* @brief SPI Mode Register.
* @{
*/
#define MXC_F_SPIMSS_MODE_SSV_POS 0 /**< MODE_SSV Position */
#define MXC_F_SPIMSS_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SSV_POS)) /**< MODE_SSV Mask */
#define MXC_F_SPIMSS_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */
#define MXC_F_SPIMSS_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */
#define MXC_F_SPIMSS_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */
#define MXC_F_SPIMSS_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */
#define MXC_F_SPIMSS_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */
#define MXC_F_SPIMSS_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */
/**@} end of group SPIMSS_MODE_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_BRG SPIMSS_BRG
* @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for
* the SPI Baud Rate Generator. The reload value must be greater than or equal to
* 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by
* 4).
* @{
*/
#define MXC_F_SPIMSS_BRG_DIV_POS 0 /**< BRG_DIV Position */
#define MXC_F_SPIMSS_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS)) /**< BRG_DIV Mask */
/**@} end of group SPIMSS_BRG_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DMA SPIMSS_DMA
* @brief SPI DMA Register.
* @{
*/
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
#define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
#define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
/**@} end of group SPIMSS_DMA_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL
* @brief I2S Control Register.
* @{
*/
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
/**@} end of group SPIMSS_I2S_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_REGS_H_ */

91
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h Normal file
View File

@ -0,0 +1,91 @@
/**
* @file system_max32660.h
* @brief System-specific header file
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
#ifndef _SYSTEM_MAX32660_H_
#define _SYSTEM_MAX32660_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifndef HFX_FREQ
#define HFX_FREQ 32768
#endif
#ifndef NANORING_FREQ
#define NANORING_FREQ 8000
#endif
#ifndef HIRC96_FREQ
#define HIRC96_FREQ 96000000
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
#ifndef PeripheralClock
#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */
#endif
/*
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void);
/*
* Update SystemCoreClock variable
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MAX32660_H_ */

239
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h Normal file
View File

@ -0,0 +1,239 @@
/**
* @file tmr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _TMR_REGS_H_
#define _TMR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup tmr
* @defgroup tmr_registers TMR_Registers
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @details Low-Power Configurable Timer
*/
/**
* @ingroup tmr_registers
* Structure type to access the TMR Registers.
*/
typedef struct {
__IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR CNT Register */
__IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR CMP Register */
__IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR PWM Register */
__IO uint32_t intr; /**< <tt>\b 0x0C:</tt> TMR INTR Register */
__IO uint32_t cn; /**< <tt>\b 0x10:</tt> TMR CN Register */
} mxc_tmr_regs_t;
/* Register offsets for module TMR */
/**
* @ingroup tmr_registers
* @defgroup TMR_Register_Offsets Register Offsets
* @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address.
* @{
*/
#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */
#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */
#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */
#define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */
#define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */
/**@} end of group tmr_registers */
/**
* @ingroup tmr_registers
* @defgroup TMR_CNT TMR_CNT
* @brief Timer Counter Register.
* @{
*/
#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */
#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
/**@} end of group TMR_CNT_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_CMP TMR_CMP
* @brief Timer Compare Register.
* @{
*/
#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */
#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */
/**@} end of group TMR_CMP_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_PWM TMR_PWM
* @brief Timer PWM Register.
* @{
*/
#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */
#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */
/**@} end of group TMR_PWM_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_INTR TMR_INTR
* @brief Timer Interrupt Status Register.
* @{
*/
#define MXC_F_TMR_INTR_IRQ_POS 0 /**< INTR_IRQ Position */
#define MXC_F_TMR_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) /**< INTR_IRQ Mask */
/**@} end of group TMR_INTR_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_CN TMR_CN
* @brief Timer Control Register.
* @{
*/
#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
#define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
#define MXC_V_TMR_CN_TMODE_ONE_SHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONE_SHOT Value */
#define MXC_S_TMR_CN_TMODE_ONE_SHOT (MXC_V_TMR_CN_TMODE_ONE_SHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONE_SHOT Setting */
#define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
#define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
#define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
#define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
#define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
#define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
#define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
#define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
#define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
#define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */
#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
#define MXC_V_TMR_CN_TMODE_CAPCOMP ((uint32_t)0x7UL) /**< CN_TMODE_CAPCOMP Value */
#define MXC_S_TMR_CN_TMODE_CAPCOMP (MXC_V_TMR_CN_TMODE_CAPCOMP << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPCOMP Setting */
#define MXC_V_TMR_CN_TMODE_DUAL_EDGE ((uint32_t)0x8UL) /**< CN_TMODE_DUAL_EDGE Value */
#define MXC_S_TMR_CN_TMODE_DUAL_EDGE (MXC_V_TMR_CN_TMODE_DUAL_EDGE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_DUAL_EDGE Setting */
#define MXC_V_TMR_CN_TMODE_IGATED ((uint32_t)0xCUL) /**< CN_TMODE_IGATED Value */
#define MXC_S_TMR_CN_TMODE_IGATED (MXC_V_TMR_CN_TMODE_IGATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_IGATED Setting */
#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
#define MXC_V_TMR_CN_PRES_DIV_BY_1 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_1 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_1 (MXC_V_TMR_CN_PRES_DIV_BY_1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_2 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_2 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_2 (MXC_V_TMR_CN_PRES_DIV_BY_2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_4 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_4 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_4 (MXC_V_TMR_CN_PRES_DIV_BY_4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_8 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_8 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_8 (MXC_V_TMR_CN_PRES_DIV_BY_8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_16 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_16 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_16 (MXC_V_TMR_CN_PRES_DIV_BY_16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_16 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_32 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_32 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_32 (MXC_V_TMR_CN_PRES_DIV_BY_32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_32 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_64 ((uint32_t)0x6UL) /**< CN_PRES_DIV_BY_64 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_64 (MXC_V_TMR_CN_PRES_DIV_BY_64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_64 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_128 ((uint32_t)0x7UL) /**< CN_PRES_DIV_BY_128 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_128 (MXC_V_TMR_CN_PRES_DIV_BY_128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_128 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x8UL) /**< CN_PRES_DIV_BY_256 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_256 (MXC_V_TMR_CN_PRES_DIV_BY_256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_256 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x9UL) /**< CN_PRES_DIV_BY_512 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_512 (MXC_V_TMR_CN_PRES_DIV_BY_512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_512 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0xAUL) /**< CN_PRES_DIV_BY_1024 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_1024 (MXC_V_TMR_CN_PRES_DIV_BY_1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1024 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0xBUL) /**< CN_PRES_DIV_BY_2048 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_2048 (MXC_V_TMR_CN_PRES_DIV_BY_2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2048 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0xCUL) /**< CN_PRES_DIV_BY_4096 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_4096 (MXC_V_TMR_CN_PRES_DIV_BY_4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4096 Setting */
#define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0xDUL) /**< CN_PRES_DIV_BY_8192 Value */
#define MXC_S_TMR_CN_PRES_DIV_BY_8192 (MXC_V_TMR_CN_PRES_DIV_BY_8192 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8192 Setting */
#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
#define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
#define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
#define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
#define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */
#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
#define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */
#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
#define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */
#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
#define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */
/**@} end of group TMR_CN_Register */
#ifdef __cplusplus
}
#endif
#endif /* _TMR_REGS_H_ */

402
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h Normal file
View File

@ -0,0 +1,402 @@
/**
* @file uart_regs.h
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup uart
* @defgroup uart_registers UART_Registers
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
* @details UART
*/
/**
* @ingroup uart_registers
* Structure type to access the UART Registers.
*/
typedef struct {
__IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> UART CTRL0 Register */
__IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> UART CTRL1 Register */
__I uint32_t stat; /**< <tt>\b 0x08:</tt> UART STAT Register */
__IO uint32_t int_en; /**< <tt>\b 0x0C:</tt> UART INT_EN Register */
__IO uint32_t int_fl; /**< <tt>\b 0x10:</tt> UART INT_FL Register */
__IO uint32_t baud0; /**< <tt>\b 0x14:</tt> UART BAUD0 Register */
__IO uint32_t baud1; /**< <tt>\b 0x18:</tt> UART BAUD1 Register */
__IO uint32_t fifo; /**< <tt>\b 0x1C:</tt> UART FIFO Register */
__IO uint32_t dma; /**< <tt>\b 0x20:</tt> UART DMA Register */
__IO uint32_t txfifo; /**< <tt>\b 0x24:</tt> UART TXFIFO Register */
} mxc_uart_regs_t;
/* Register offsets for module UART */
/**
* @ingroup uart_registers
* @defgroup UART_Register_Offsets Register Offsets
* @brief UART Peripheral Register Offsets from the UART Base Peripheral Address.
* @{
*/
#define MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */
#define MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */
#define MXC_R_UART_STAT ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */
#define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */
#define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */
#define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */
#define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */
#define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */
#define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */
#define MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */
/**@} end of group uart_registers */
/**
* @ingroup uart_registers
* @defgroup UART_CTRL0 UART_CTRL0
* @brief Control Register.
* @{
*/
#define MXC_F_UART_CTRL0_ENABLE_POS 0 /**< CTRL0_ENABLE Position */
#define MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) /**< CTRL0_ENABLE Mask */
#define MXC_F_UART_CTRL0_PARITY_EN_POS 1 /**< CTRL0_PARITY_EN Position */
#define MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) /**< CTRL0_PARITY_EN Mask */
#define MXC_F_UART_CTRL0_PARITY_MODE_POS 2 /**< CTRL0_PARITY_MODE Position */
#define MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) /**< CTRL0_PARITY_MODE Mask */
#define MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) /**< CTRL0_PARITY_MODE_EVEN Value */
#define MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_EVEN Setting */
#define MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) /**< CTRL0_PARITY_MODE_ODD Value */
#define MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_ODD Setting */
#define MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) /**< CTRL0_PARITY_MODE_MARK Value */
#define MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_MARK Setting */
#define MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) /**< CTRL0_PARITY_MODE_SPACE Value */
#define MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_SPACE Setting */
#define MXC_F_UART_CTRL0_PARITY_LVL_POS 4 /**< CTRL0_PARITY_LVL Position */
#define MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) /**< CTRL0_PARITY_LVL Mask */
#define MXC_F_UART_CTRL0_TXFLUSH_POS 5 /**< CTRL0_TXFLUSH Position */
#define MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) /**< CTRL0_TXFLUSH Mask */
#define MXC_F_UART_CTRL0_RXFLUSH_POS 6 /**< CTRL0_RXFLUSH Position */
#define MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) /**< CTRL0_RXFLUSH Mask */
#define MXC_F_UART_CTRL0_BITACC_POS 7 /**< CTRL0_BITACC Position */
#define MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) /**< CTRL0_BITACC Mask */
#define MXC_F_UART_CTRL0_SIZE_POS 8 /**< CTRL0_SIZE Position */
#define MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) /**< CTRL0_SIZE Mask */
#define MXC_V_UART_CTRL0_SIZE_5 ((uint32_t)0x0UL) /**< CTRL0_SIZE_5 Value */
#define MXC_S_UART_CTRL0_SIZE_5 (MXC_V_UART_CTRL0_SIZE_5 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_5 Setting */
#define MXC_V_UART_CTRL0_SIZE_6 ((uint32_t)0x1UL) /**< CTRL0_SIZE_6 Value */
#define MXC_S_UART_CTRL0_SIZE_6 (MXC_V_UART_CTRL0_SIZE_6 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_6 Setting */
#define MXC_V_UART_CTRL0_SIZE_7 ((uint32_t)0x2UL) /**< CTRL0_SIZE_7 Value */
#define MXC_S_UART_CTRL0_SIZE_7 (MXC_V_UART_CTRL0_SIZE_7 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_7 Setting */
#define MXC_V_UART_CTRL0_SIZE_8 ((uint32_t)0x3UL) /**< CTRL0_SIZE_8 Value */
#define MXC_S_UART_CTRL0_SIZE_8 (MXC_V_UART_CTRL0_SIZE_8 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_8 Setting */
#define MXC_F_UART_CTRL0_STOP_POS 10 /**< CTRL0_STOP Position */
#define MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) /**< CTRL0_STOP Mask */
#define MXC_F_UART_CTRL0_FLOW_POS 11 /**< CTRL0_FLOW Position */
#define MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) /**< CTRL0_FLOW Mask */
#define MXC_F_UART_CTRL0_FLOWPOL_POS 12 /**< CTRL0_FLOWPOL Position */
#define MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) /**< CTRL0_FLOWPOL Mask */
#define MXC_F_UART_CTRL0_NULLMOD_POS 13 /**< CTRL0_NULLMOD Position */
#define MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) /**< CTRL0_NULLMOD Mask */
#define MXC_F_UART_CTRL0_BREAK_POS 14 /**< CTRL0_BREAK Position */
#define MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) /**< CTRL0_BREAK Mask */
#define MXC_F_UART_CTRL0_CLK_SEL_POS 15 /**< CTRL0_CLK_SEL Position */
#define MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) /**< CTRL0_CLK_SEL Mask */
#define MXC_F_UART_CTRL0_TO_CNT_POS 16 /**< CTRL0_TO_CNT Position */
#define MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) /**< CTRL0_TO_CNT Mask */
/**@} end of group UART_CTRL0_Register */
/**
* @ingroup uart_registers
* @defgroup UART_CTRL1 UART_CTRL1
* @brief Threshold Control register.
* @{
*/
#define MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 /**< CTRL1_RX_FIFO_LVL Position */
#define MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) /**< CTRL1_RX_FIFO_LVL Mask */
#define MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 /**< CTRL1_TX_FIFO_LVL Position */
#define MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) /**< CTRL1_TX_FIFO_LVL Mask */
#define MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 /**< CTRL1_RTS_FIFO_LVL Position */
#define MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) /**< CTRL1_RTS_FIFO_LVL Mask */
/**@} end of group UART_CTRL1_Register */
/**
* @ingroup uart_registers
* @defgroup UART_STAT UART_STAT
* @brief Status Register.
* @{
*/
#define MXC_F_UART_STAT_TX_BUSY_POS 0 /**< STAT_TX_BUSY Position */
#define MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) /**< STAT_TX_BUSY Mask */
#define MXC_F_UART_STAT_RX_BUSY_POS 1 /**< STAT_RX_BUSY Position */
#define MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) /**< STAT_RX_BUSY Mask */
#define MXC_F_UART_STAT_PARITY_POS 2 /**< STAT_PARITY Position */
#define MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) /**< STAT_PARITY Mask */
#define MXC_F_UART_STAT_BREAK_POS 3 /**< STAT_BREAK Position */
#define MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) /**< STAT_BREAK Mask */
#define MXC_F_UART_STAT_RX_EMPTY_POS 4 /**< STAT_RX_EMPTY Position */
#define MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) /**< STAT_RX_EMPTY Mask */
#define MXC_F_UART_STAT_RX_FULL_POS 5 /**< STAT_RX_FULL Position */
#define MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) /**< STAT_RX_FULL Mask */
#define MXC_F_UART_STAT_TX_EMPTY_POS 6 /**< STAT_TX_EMPTY Position */
#define MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) /**< STAT_TX_EMPTY Mask */
#define MXC_F_UART_STAT_TX_FULL_POS 7 /**< STAT_TX_FULL Position */
#define MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) /**< STAT_TX_FULL Mask */
#define MXC_F_UART_STAT_RX_NUM_POS 8 /**< STAT_RX_NUM Position */
#define MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) /**< STAT_RX_NUM Mask */
#define MXC_F_UART_STAT_TX_NUM_POS 16 /**< STAT_TX_NUM Position */
#define MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) /**< STAT_TX_NUM Mask */
#define MXC_F_UART_STAT_RX_TO_POS 24 /**< STAT_RX_TO Position */
#define MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) /**< STAT_RX_TO Mask */
/**@} end of group UART_STAT_Register */
/**
* @ingroup uart_registers
* @defgroup UART_INT_EN UART_INT_EN
* @brief Interrupt Enable Register.
* @{
*/
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */
#define MXC_F_UART_INT_EN_CTS_POS 2 /**< INT_EN_CTS Position */
#define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) /**< INT_EN_CTS Mask */
#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
#define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */
#define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 /**< INT_EN_RX_FIFO_LVL Position */
#define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) /**< INT_EN_RX_FIFO_LVL Mask */
#define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 /**< INT_EN_TX_FIFO_AE Position */
#define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */
#define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 /**< INT_EN_TX_FIFO_LVL Position */
#define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) /**< INT_EN_TX_FIFO_LVL Mask */
#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
#define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
#define MXC_F_UART_INT_EN_RX_TO_POS 8 /**< INT_EN_RX_TO Position */
#define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) /**< INT_EN_RX_TO Mask */
#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
#define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */
/**@} end of group UART_INT_EN_Register */
/**
* @ingroup uart_registers
* @defgroup UART_INT_FL UART_INT_FL
* @brief Interrupt Status Flags.
* @{
*/
#define MXC_F_UART_INT_FL_FRAME_POS 0 /**< INT_FL_FRAME Position */
#define MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) /**< INT_FL_FRAME Mask */
#define MXC_F_UART_INT_FL_PARITY_POS 1 /**< INT_FL_PARITY Position */
#define MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) /**< INT_FL_PARITY Mask */
#define MXC_F_UART_INT_FL_CTS_POS 2 /**< INT_FL_CTS Position */
#define MXC_F_UART_INT_FL_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_POS)) /**< INT_FL_CTS Mask */
#define MXC_F_UART_INT_FL_RX_OVR_POS 3 /**< INT_FL_RX_OVR Position */
#define MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
#define MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 /**< INT_FL_RX_FIFO_LVL Position */
#define MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) /**< INT_FL_RX_FIFO_LVL Mask */
#define MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 /**< INT_FL_TX_FIFO_AE Position */
#define MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */
#define MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 /**< INT_FL_TX_FIFO_LVL Position */
#define MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) /**< INT_FL_TX_FIFO_LVL Mask */
#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
#define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
#define MXC_F_UART_INT_FL_RX_TO_POS 8 /**< INT_FL_RX_TO Position */
#define MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) /**< INT_FL_RX_TO Mask */
#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
#define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */
/**@} end of group UART_INT_FL_Register */
/**
* @ingroup uart_registers
* @defgroup UART_BAUD0 UART_BAUD0
* @brief Baud rate register. Integer portion.
* @{
*/
#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
#define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
#define MXC_F_UART_BAUD0_CLKDIV_POS 16 /**< BAUD0_CLKDIV Position */
#define MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) /**< BAUD0_CLKDIV Mask */
#define MXC_V_UART_BAUD0_CLKDIV_128 ((uint32_t)0x0UL) /**< BAUD0_CLKDIV_128 Value */
#define MXC_S_UART_BAUD0_CLKDIV_128 (MXC_V_UART_BAUD0_CLKDIV_128 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_128 Setting */
#define MXC_V_UART_BAUD0_CLKDIV_64 ((uint32_t)0x1UL) /**< BAUD0_CLKDIV_64 Value */
#define MXC_S_UART_BAUD0_CLKDIV_64 (MXC_V_UART_BAUD0_CLKDIV_64 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_64 Setting */
#define MXC_V_UART_BAUD0_CLKDIV_32 ((uint32_t)0x2UL) /**< BAUD0_CLKDIV_32 Value */
#define MXC_S_UART_BAUD0_CLKDIV_32 (MXC_V_UART_BAUD0_CLKDIV_32 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_32 Setting */
#define MXC_V_UART_BAUD0_CLKDIV_16 ((uint32_t)0x3UL) /**< BAUD0_CLKDIV_16 Value */
#define MXC_S_UART_BAUD0_CLKDIV_16 (MXC_V_UART_BAUD0_CLKDIV_16 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_16 Setting */
#define MXC_V_UART_BAUD0_CLKDIV_8 ((uint32_t)0x4UL) /**< BAUD0_CLKDIV_8 Value */
#define MXC_S_UART_BAUD0_CLKDIV_8 (MXC_V_UART_BAUD0_CLKDIV_8 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_8 Setting */
/**@} end of group UART_BAUD0_Register */
/**
* @ingroup uart_registers
* @defgroup UART_BAUD1 UART_BAUD1
* @brief Baud rate register. Decimal Setting.
* @{
*/
#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
#define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
/**@} end of group UART_BAUD1_Register */
/**
* @ingroup uart_registers
* @defgroup UART_FIFO UART_FIFO
* @brief FIFO Data buffer.
* @{
*/
#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
#define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */
/**@} end of group UART_FIFO_Register */
/**
* @ingroup uart_registers
* @defgroup UART_DMA UART_DMA
* @brief DMA Configuration.
* @{
*/
#define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */
#define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */
#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
#define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
#define MXC_F_UART_DMA_TXDMA_LVL_POS 8 /**< DMA_TXDMA_LVL Position */
#define MXC_F_UART_DMA_TXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LVL_POS)) /**< DMA_TXDMA_LVL Mask */
#define MXC_F_UART_DMA_RXDMA_LVL_POS 16 /**< DMA_RXDMA_LVL Position */
#define MXC_F_UART_DMA_RXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LVL_POS)) /**< DMA_RXDMA_LVL Mask */
/**@} end of group UART_DMA_Register */
/**
* @ingroup uart_registers
* @defgroup UART_TXFIFO UART_TXFIFO
* @brief Transmit FIFO Status register.
* @{
*/
#define MXC_F_UART_TXFIFO_DATA_POS 0 /**< TXFIFO_DATA Position */
#define MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) /**< TXFIFO_DATA Mask */
/**@} end of group UART_TXFIFO_Register */
#ifdef __cplusplus
}
#endif
#endif /* _UART_REGS_H_ */

214
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h Normal file
View File

@ -0,0 +1,214 @@
/**
* @file wdt_regs.h
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _WDT_REGS_H_
#define _WDT_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup wdt
* @defgroup wdt_registers WDT_Registers
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
* @details Watchdog Timer 0
*/
/**
* @ingroup wdt_registers
* Structure type to access the WDT Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> WDT CTRL Register */
__O uint32_t rst; /**< <tt>\b 0x04:</tt> WDT RST Register */
} mxc_wdt_regs_t;
/* Register offsets for module WDT */
/**
* @ingroup wdt_registers
* @defgroup WDT_Register_Offsets Register Offsets
* @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address.
* @{
*/
#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */
#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */
/**@} end of group wdt_registers */
/**
* @ingroup wdt_registers
* @defgroup WDT_CTRL WDT_CTRL
* @brief Watchdog Timer Control Register.
* @{
*/
#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
#define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
#define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
#define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
#define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
#define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
/**@} end of group WDT_CTRL_Register */
/**
* @ingroup wdt_registers
* @defgroup WDT_RST WDT_RST
* @brief Watchdog Timer Reset Register.
* @{
*/
#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
#define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
#define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
#define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
#define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
#define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
/**@} end of group WDT_RST_Register */
#ifdef __cplusplus
}
#endif
#endif /* _WDT_REGS_H_ */

146
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c Normal file
View File

@ -0,0 +1,146 @@
/**
* @file system_max32660.c
* @brief System-level initialization implementation file
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include "max32660.h"
#include "gcr_regs.h"
#include "pwrseq_regs.h"
#include "tmr_regs.h"
#include "wdt_regs.h"
#include "mxc_sys.h"
#include "icc.h"
uint32_t SystemCoreClock = HIRC96_FREQ;
__weak void SystemCoreClockUpdate(void)
{
uint32_t base_freq, div, clk_src,ovr;
// Get the clock source and frequency
clk_src = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL);
if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) {
base_freq = HFX_FREQ;
} else {
if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING) {
base_freq = NANORING_FREQ;
} else {
ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
base_freq = HIRC96_FREQ/4;
} else {
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
base_freq = HIRC96_FREQ/2;
} else {
base_freq = HIRC96_FREQ;
}
}
}
}
// Get the clock divider
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
SystemCoreClock = base_freq >> div;
}
/* This function is called before C runtime initialization and can be
* implemented by the application for early initializations. If a value other
* than '0' is returned, the C runtime initialization will be skipped.
*
* You may over-ride this function in your program by defining a custom
* PreInit(), but care should be taken to reproduce the initilization steps
* or a non-functional system may result.
*/
__weak int PreInit(void)
{
/* Switch system clock to HIRC, 96 MHz*/
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
/* Enable cache here to reduce boot time */
MXC_ICC_Enable();
return 0;
}
/* Override this function for early platform initialization
*/
__weak void low_level_init(void)
{
}
/* This function is called just before control is transferred to main().
*
* You may over-ride this function in your program by defining a custom
* SystemInit(), but care should be taken to reproduce the initialization
* steps or a non-functional system may result.
*/
__weak void SystemInit(void)
{
MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
#if (__FPU_PRESENT == 1)
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
__DSB();
__ISB();
#endif
/* Disable clocks to peripherals by default to reduce power */
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
/* Early platform initialization */
low_level_init();
}

BIN
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Lib/GCC/libarm_cortexM3l_math.a Normal file
View File

Binary file not shown.

BIN
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Lib/GCC/libarm_cortexM4l_math.a Normal file
View File

Binary file not shown.

BIN
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a Normal file
View File

Binary file not shown.

28
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Lib/license.txt Normal file
View File

@ -0,0 +1,28 @@
All pre-build libraries contained in the folders "ARM", "GCC" and "G++"
are guided by the following license:
Copyright (C) 2009-2012 ARM Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

426
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h Normal file
View File

@ -0,0 +1,426 @@
/**
* @file dma.h
* @brief Direct Memory Access (DMA) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _DMA_H_
#define _DMA_H_
/* **** Includes **** */
#include <stdbool.h>
#include "mxc_device.h"
#include "mxc_errors.h"
#include "dma_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup dma Direct Memory Access (DMA)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* @brief Enumeration for the DMA Channel's priority level.
*
*/
typedef enum {
MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */
MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */
MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */
MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */
} mxc_dma_priority_t;
/** @brief DMA request select */
typedef enum {
MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection
MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection
MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection
MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection
MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection
MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection
MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection
} mxc_dma_reqsel_t;
/** @brief Enumeration for the DMA prescaler */
typedef enum {
MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled
MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256
MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536
MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216
} mxc_dma_prescale_t;
/** @brief Enumeration for the DMA timeout value */
typedef enum {
MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks
MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks
MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks
MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks
MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks
MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks
MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks
MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks
} mxc_dma_timeout_t;
/** @brief DMA transfer data width */
typedef enum {
/* Using the '_V_' define instead of the '_S_' since these same values will be used to
specify the DSTWD also. The API functions will shift the value the correct amount
prior to writing the cfg register. */
MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes
MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words
MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words
} mxc_dma_width_t;
/**
* @brief The basic configuration information to set up a DMA channel
* and prepare it for transfers.
*
*/
typedef struct {
int ch; ///< The channel to load the configuration data into
mxc_dma_reqsel_t reqsel;///< The request select line to be used (mem2mem, peripheral)
mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width)
mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width)
int srcinc_en; ///< Whether to increment the source address during the transfer
int dstinc_en; ///< Whether to increment the source address during the transfer
} mxc_dma_config_t;
/**
* @brief The information needed to complete a DMA transfer
*
*/
typedef struct {
int ch; ///< The channel to use for the transfer
void* source; ///< Pointer to the source address, if applicable
void* dest; ///< Pointer to the destination address, if applicable
int len; ///< Number of bytes to transfer
} mxc_dma_srcdst_t;
/**
* @brief The advanced configuration options, these are optional but could
* be needed in cases where multiple DMA channels are running concurrently
* or DMA is being used with low bandwidth peripherals.
*
*/
typedef struct {
int ch; ///< The channel to use for the transfer
mxc_dma_priority_t prio; ///< The DMA priority for the channel
unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer
mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout
mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer
unsigned int burst_size; ///< Number of bytes moved in a single burst
} mxc_dma_adv_config_t;
/**
* @brief The callback called on completion of a DMA_MemCpy() transfer
*
* @param dest Pointer to the destination of the copy
*/
typedef void (*mxc_dma_complete_cb_t) (void* dest);
/**
* @brief The callback called on completion of a transfer,
* @note This callback is used with MXC_DMA_DoTransfer()
* to allow the user to chain an unlimited number of
* DMA Transfers.
*
* @param trans Struct of the completed transfer
*
* @return Returns the next transfer to be completed, or NULL
* if no more transfers will be done
*/
typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest);
/* **** Function Prototypes **** */
/*************************/
/* Low Level Functions */
/*************************/
/**
* @brief Initialize DMA resources
* @details This initialization is required before using the DMA driver functions.
* @return #E_NO_ERROR if successful
*/
int MXC_DMA_Init (void);
/**
* @brief Request DMA channel
* @details Returns a handle to the first free DMA channel, which can be used via API calls
* or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function.
* @return Non-negative channel handle (inclusive of zero).
* @return #E_NONE_AVAIL All channels in use.
* @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first.
* @return #E_BUSY DMA is currently busy (locked), try again later.
*/
int MXC_DMA_AcquireChannel (void);
/**
* @brief Release DMA channel
* @details Stops any DMA operation on the channel and returns it to the pool of free channels.
*
* @param ch channel handle to release
*
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_ReleaseChannel (int ch);
/**
* @brief Configure the DMA channel
* @details Configures the channel, which was previously requested by MXC_DMA_Getchannel()
*
* @param config Struct containing DMA configuration parameters
* @param srcdst Struct containing pointers and length of DMA operation
*
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
/**
* @brief Configure the DMA channel with more advanced parameters
*
* @param advConfig Struct containing advanced DMA parameters
*
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig);
/**
* @brief Set channel source, destination, and count for the transfer
* @param srcdst Struct containing the channel, source, destination, and count for the channel
* @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM,
* either src_addr or dst_addr will be ignored by the DMA engine.
* In these cases, the address is a don't-care. See the User's
* Guide for more information.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
/**
* @brief Get channel source, destination, and count for transfer
*
* @param srcdst Pointer to struct with the correct channel number
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst);
/**
* @brief Set channel reload source, destination, and count for the transfer
* @param srcdstReload Struct containing the channel, source, destination, and count for the channel
* @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM,
* either src_addr or dst_addr will be ignored by the DMA engine.
* In these cases, the address is a don't-care. See the User's
* Guide for more information.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
/**
* @brief Get channel reload source, destination, and count for transfer
*
* @param srcdstReload Pointer to struct with the correct channel number
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload);
/**
* @brief Set channel interrupt callback
* @param ch channel handle
* @param callback Pointer to a function to call when the channel
* interrupt flag is set and interrupts are enabled or
* when DMA is shutdown by the driver.
* @details Configures the channel interrupt callback. The @p callback
* function is called for two conditions:
* -# When the channel's interrupt flag is set and DMA interrupts
* are enabled.
* -# If the driver calls the MXC_DMA_Shutdown() function. The
* callback function prototype is:
* @code
* void callback_fn(int ch, int reason);
* @endcode
* @p ch indicates the channel that generated the callback, @p
* reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN
* if the DMA is being shutdown.
*
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR
* otherwise
*/
int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
/**
* @brief Set channel interrupt
* @note Each channel has two interrupts (complete, and count to zero).
* To enable complete, pass true for chdis. To enable count to zero,
* pass true for ctz.
* @param ch Channel Handle
* @param chdis Enable channel complete interrupt
* @param ctz Enable channel count to zero interrupt.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz);
/**
* @brief Enable channel interrupt
* @note Each channel has two interrupts (complete, and count to zero)
which must also be enabled with MXC_DMA_SetChannelInterruptEn()
* @param ch channel handle
* @param flags The flags to enable
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_ChannelEnableInt (int ch, int flags);
/**
* @brief Disable channel interrupt
* @param ch channel handle
* @param flags The flags to disable
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_ChannelDisableInt (int ch, int flags);
/**
* @brief Read channel interrupt flags
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise
*/
int MXC_DMA_ChannelGetFlags (int ch);
/**
* @brief Clear channel interrupt flags
* @param ch channel handle
* @param flags The flags to clear
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_ChannelClearFlags (int ch, int flags);
/**
* @brief Enable channel interrupt
* @note Each channel has two interrupts (complete, and count to zero)
which must also be enabled with MXC_DMA_SetChannelInterruptEn()
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_EnableInt (int ch);
/**
* @brief Disable channel interrupt
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_DisableInt (int ch);
/**
* @brief Start transfer
* @param ch channel handle
* @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand.
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_Start (int ch);
/**
* @brief Stop DMA transfer, irrespective of status (complete or in-progress)
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int MXC_DMA_Stop (int ch);
/**
* @brief Get a pointer to the DMA channel registers
* @param ch channel handle
* @details If direct access to DMA channel registers is required, this
* function can be used on a channel handle returned by MXC_DMA_AcquireChannel().
* @return NULL if an unused or invalid channel handle, or a valid pointer otherwise
*/
mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs (int ch);
/**
* @brief Interrupt handler function
* @details Call this function as the ISR for each DMA channel under driver control.
* Interrupt flags for channel ch will be automatically cleared before return.
*/
void MXC_DMA_Handler();
/*************************/
/* High Level Functions */
/*************************/
/**
* @brief Performs a memcpy, using DMA, optionally asynchronous
* @note The user must have the DMA interrupt enabled and call
* MXC_DMA_Handler() from the ISR.
*
* @param dest pointer to destination memory
* @param src pointer to source memory
* @param len number of bytes to copy
* @param callback function to call when transfer is complete
*
* @return see \ref MXC_Error_Codes
*/
int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
/**
* @brief Performs a memcpy, using DMA, optionally asynchronous
* @note The user must have the DMA interrupt enabled and call
* MXC_DMA_Handler() from the ISR.
*
* @param config The channel config struct
* @param firstSrcDst The source, destination, and count for the first transfer
* @param callback function is called when transfer is complete
*
* @return see \ref MXC_Error_Codes
*/
int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
/**
* For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver
*/
/**@} end of group dma */
#ifdef __cplusplus
}
#endif
#endif /* _DMA_H_ */

189
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h Normal file
View File

@ -0,0 +1,189 @@
/**
* @file flc.h
* @brief Flash Controller driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _FLC_H_
#define _FLC_H_
/* **** Includes **** */
#include "flc_regs.h"
#include "mxc_sys.h"
#include "mxc_errors.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup flc Flash Controller (FLC)
* @ingroup periphlibs
* @{
*/
/***** Definitions *****/
/// Bit mask that can be used to find the starting address of a page in flash
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
/// Calculate the address of a page in flash from the page number
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
/***** Function Prototypes *****/
/**
* @brief Initializes the Flash Controller for erase/write operations
* @return #E_NO_ERROR if successful.
*/
int MXC_FLC_Init();
/**
* @brief Checks if Flash Controller is busy.
* @details Reading or executing from flash is not possible if flash is busy
* with an erase or write operation.
* @return If non-zero, flash operation is in progress
*/
int MXC_FLC_Busy (void);
/**
* @brief Erases the entire flash array.
* @note This function must be executed from RAM.
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_MassErase (void);
/**
* @brief Erases the page of flash at the specified address.
* @note This function must be executed from RAM.
* @param address Any address within the page to erase.
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_PageErase (uint32_t address);
/**
* @brief Read Data out of Flash from an address
*
* @param[in] address The address to read from
* @param buffer The buffer to read the data into
* @param[in] len The length of the buffer
*
*/
void MXC_FLC_Read (int address, void* buffer, int len);
/**
* @brief Writes data to flash.
* @note This function must be executed from RAM.
* @param address Address in flash to start writing from.
* @param length Number of bytes to be written.
* @param buffer Pointer to data to be written to flash.
* @return #E_NO_ERROR If function is successful.
* @note make sure to disable ICC with ICC_Disable(); before Running this function
*/
int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer);
/**
* @brief Writes 32 bits of data to flash.
* @note This function must be executed from RAM.
* @param address Address in flash to start writing from.
* @param data Pointer to data to be written to flash.
* @return #E_NO_ERROR If function is successful.
* @note make sure to disable ICC with ICC_Disable(); before Running this function
*/
int MXC_FLC_Write32 (uint32_t address, uint32_t data);
/**
* @brief Writes 128 bits of data to flash.
* @note This function must be executed from RAM.
* @param address Address in flash to start writing from.
* @param data Pointer to data to be written to flash.
* @return #E_NO_ERROR If function is successful.
* @note make sure to disable ICC with ICC_Disable(); before Running this function
*/
int MXC_FLC_Write128 (uint32_t address, uint32_t *data);
/**
* @brief Enable flash interrupts
* @param flags Interrupts to enable
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_EnableInt (uint32_t flags);
/**
* @brief Disable flash interrupts
* @param flags Interrupts to disable
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_DisableInt (uint32_t flags);
/**
* @brief Retrieve flash interrupt flags
* @return Interrupt flags registers
*/
int MXC_FLC_GetFlags (void);
/**
* @brief Clear flash interrupt flags
* @note Provide the bit position to clear, even if the flag is write-0-to-clear
* @param flags Flag bit(s) to clear
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_ClearFlags (uint32_t flags);
/**
* @brief Unlock info block
*
* @param[in] address The address in the info block needing written to
*
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_UnlockInfoBlock (uint32_t address);
/**
* @brief Lock info block
*
* @param[in] address The address in the info block that was written to
* @return #E_NO_ERROR If function is successful.
*/
int MXC_FLC_LockInfoBlock (uint32_t address);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_H_ */

310
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h Normal file
View File

@ -0,0 +1,310 @@
/**
* @file gpio.h
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _GPIO_H_
#define _GPIO_H_
/* **** Includes **** */
#include "gpio_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup gpio General-Purpose Input/Output (GPIO)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* @defgroup gpio_port_pin Port and Pin Definitions
* @ingroup gpio
* @{
* @defgroup gpio_port Port Definitions
* @ingroup gpio_port_pin
* @{
*/
#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define
/**@} end of gpio_port group*/
/**
* @defgroup gpio_pin Pin Definitions
* @ingroup gpio_port_pin
* @{
*/
#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define
#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define
#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define
#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define
#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define
#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define
#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define
#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define
#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define
#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define
#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define
#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define
#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define
#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define
/**@} end of gpio_pin group */
/**@} end of gpio_port_pin group */
/**
* @brief Type alias for a GPIO callback function with prototype:
* @code
void callback_fn(void *cbdata);
* @endcode
* @param cbdata A void pointer to the data type as registered when
* MXC_GPIO_RegisterCallback() was called.
*/
typedef void (*mxc_gpio_callback_fn) (void *cbdata);
/**
* @brief Enumeration type for the GPIO Function Type
*/
typedef enum {
MXC_GPIO_FUNC_IN, ///< GPIO Input
MXC_GPIO_FUNC_OUT, ///< GPIO Output
MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection
MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection
MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection
MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection
} mxc_gpio_func_t;
/**
* @brief Enumeration type for the voltage level on a given pin.
*/
typedef enum {
MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage
MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage
} mxc_gpio_vssel_t;
/**
* @brief Enumeration type for the type of GPIO pad on a given pin.
*/
typedef enum {
MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down
MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up
MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down
} mxc_gpio_pad_t;
/**
* @brief Structure type for configuring a GPIO port.
*/
typedef struct {
mxc_gpio_regs_t* port; ///< Pointer to GPIO regs
uint32_t mask; ///< Pin mask (multiple pins may be set)
mxc_gpio_func_t func; ///< Function type
mxc_gpio_pad_t pad; ///< Pad type
mxc_gpio_vssel_t vssel; ///< Voltage select
} mxc_gpio_cfg_t;
/**
* @brief Enumeration type for the interrupt modes.
*/
typedef enum {
MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive
MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive
} mxc_gpio_int_mode_t;
/**
* @brief Enumeration type for the interrupt polarity.
*/
typedef enum {
MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge
MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high
MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge
MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low
MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge
} mxc_gpio_int_pol_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize GPIO.
* @param portMask Mask for the port to be initialized
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_GPIO_Init (uint32_t portMask);
/**
* @brief Shutdown GPIO.
* @param portMask Mask for the port to be initialized
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_GPIO_Shutdown (uint32_t portMask);
/**
* @brief Reset GPIO.
* @param portMask Mask for the port to be initialized
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_GPIO_Reset (uint32_t portMask);
/**
* @brief Configure GPIO pin(s).
* @param cfg Pointer to configuration structure describing the pin.
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg);
/**
* @brief Gets the pin(s) input state.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to read
* @return The requested pin state.
*/
uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Sets the pin(s) to a high level output.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to set
*/
void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Clears the pin(s) to a low level output.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to clear
*/
void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Gets the pin(s) output state.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to read the output state of
* @return The state of the requested pin.
*
*/
uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Write the pin(s) to a desired output level.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to set output level of
* @param val Desired output level of the pin(s). This will be masked
* with the configuration mask.
*/
void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val);
/**
* @brief Toggles the the pin(s) output level.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to toggle
*/
void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Configure GPIO interrupt(s)
* @param cfg Pointer to configuration structure describing the pin.
* @param pol Requested interrupt polarity.
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
/**
* @brief Enables the specified GPIO interrupt
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to enable interrupts for
*
*/
void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Disables the specified GPIO interrupt.
* @param port Pointer to the GPIO port registers
* @param mask Mask of the pin(s) to disable interrupts for
*/
void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask);
/**
* @brief Gets the interrupt(s) status on a GPIO port
*
* @param port Pointer to the port requested
*
* @return The requested interrupt status.
*/
uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port);
/**
* @brief Gets the interrupt(s) status on a GPIO port
*
* @param port Pointer to the port requested
* @param flags The flags to clear
*/
void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
/**
* @brief Registers a callback for the interrupt on a given port and pin.
* @param cfg Pointer to configuration structure describing the pin
* @param callback A pointer to a function of type #callback_fn.
* @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs.
*
*/
void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
/**
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
* interrupt, the callback function will be called.
*
* @param port Number of the port that generated the interrupt service routine.
*
*/
void MXC_GPIO_Handler (unsigned int port);
/**
* @brief Set Voltage select for pins to VDDIO or VDDIOH
*
* @param port The GPIO port
* @param[in] vssel VDDIO or VDDIOH to set the voltatge to
* @param[in] mask Pins in the GPIO port that will be set to the voltage.
*
* @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask);
/**@} end of group gpio */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_H_ */

191
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h Normal file
View File

@ -0,0 +1,191 @@
/**
* @file i2s.h
* @brief I2S (Inter-Integrated Sound) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _I2S_H_
#define _I2S_H_
/* **** Includes **** */
#include "mxc_sys.h"
#include "dma.h"
#include "spimss_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup i2s Inter-Integrated Sound (I2S)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
typedef enum {
I2S_MAP_A = 0,
I2S_MAP_B = 1,
} mxc_i2s_sys_map_t;
typedef enum {
LEFT_JUSTIFIED= 0,
RIGHT_JUSTIFIED = 1,
} mxc_i2s_justify_t;
typedef enum {
STEREO_MODE = 0,
MONO_MODE = 1,
} mxc_i2s_audio_mode_t;
/** @brief I2S audio directions */
typedef enum {
AUDIO_OUT = 1,
AUDIO_IN = 2,
} mxc_i2s_direction_t;
/** @brief I2S Configuration Struct */
typedef struct {
mxc_i2s_sys_map_t map;
mxc_i2s_justify_t justify;
mxc_i2s_audio_mode_t audio_mode;
mxc_i2s_direction_t audio_direction;
uint16_t sample_rate;
unsigned int start_immediately;
unsigned int dma_reload_en;
void *src_addr;
void *dst_addr;
uint32_t length;
} mxc_i2s_config_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize I2S resources
*
* @param config see \ref mxc_i2s_config_t I2S Config Struct
* @param dma_ctz_cb Function pointer to Count-to-Zero callback function.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int));
/**
* @brief Release I2S
* @details De-configures the I2S protocol and stops DMA request
* @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise
*/
int MXC_I2S_Shutdown(void);
/**
* @brief Mute I2S Output
* @details Sets I2S data to zero, continues sending clock and accessing DMA
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Mute(void);
/**
* @brief Unmute I2S Output
* @details Restores I2S data
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Unmute(void);
/**
* @brief Pause I2S Output
* @details Similar to mute, but stops FIFO and DMA access, clocks continue
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Pause(void);
/**
* @brief Unpause I2S Output
* @details Similar to mute, but restarts FIFO and DMA access
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Unpause(void);
/**
* @brief Stops I2S Output
* @details Similar to pause, but also halts clock
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Stop(void);
/**
* @brief Starts I2S Output
* @details Starts I2S Output, automatically called by configure if requested
* @return \c #E_NO_ERROR
*/
int MXC_I2S_Start(void);
/**
* @brief Clears DMA Interrupt Flags
* @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb
* @return \c #E_NO_ERROR
*/
int MXC_I2S_DMA_ClearFlags(void);
/**
* @brief Set DMA Addr (Source or Dest) and bytes to transfer
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details Sets the address to read/write data in memory and the length of
* the transfer. The unused addr parameter is ignored.
* @return \c #E_NO_ERROR
*/
int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
/**
* @brief Sets the DMA reload address and count
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details If DMA reload is enabled, when the DMA has transfered $count bytes
* (a CTZ event occurs) the src, dst, and count registers will be
* set to these. The DMA reload flag clears after a reload occurs.
* @return \c #E_NO_ERROR
*/
int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
/**@} end of group i2s */
#ifdef __cplusplus
}
#endif
#endif /* _I2S_H_ */

94
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h Normal file
View File

@ -0,0 +1,94 @@
/**
* @file icc.h
* @brief Instruction Controller Cache(ICC) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _ICC_H_
#define _ICC_H_
/* **** Includes **** */
#include <stdint.h>
#include "icc_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup icc ICC
* @ingroup periphlibs
* @{
*/
/**
* @brief Enumeration type for the Cache ID Register
*/
typedef enum {
ICC_INFO_RELNUM, ///< Identifies the RTL release version
ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number
ICC_INFO_ID ///< Specifies the value of Cache ID
} mxc_icc_info_t;
/**
* @brief Reads the data from the Cache Id Register.
* @param cid Enumeration type for Cache Id Register.
* @retval Returns the contents of Cache Id Register.
*/
int MXC_ICC_ID (mxc_icc_info_t cid);
/**
* @brief Enable the instruction cache controller.
*/
void MXC_ICC_Enable (void);
/**
* @brief Disable the instruction cache controller.
*/
void MXC_ICC_Disable (void);
/**
* @brief Flush the instruction cache controller.
*/
void MXC_ICC_Flush (void);
/**@} end of group icc */
#ifdef __cplusplus
}
#endif
#endif /* _ICC_H_ */

346
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h Normal file
View File

@ -0,0 +1,346 @@
/**
* @file lp.h
* @brief Low power function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
* $Revision: 38105 $
*
*************************************************************************** */
// Define to prevent redundant inclusion
#ifndef _LP_H_
#define _LP_H_
/***** Includes *****/
#include "pwrseq_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup pwrseq Low Power (LP)
* @ingroup periphlibs
* @{
*/
/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
typedef enum {
MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */
MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */
MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */
} mxc_lp_ovr_t;
/**
* @brief Clears the low power wakeup flags
*/
void MXC_LP_ClearWakeStatus(void);
/**
* @brief Enables power to RAM addresses 0x20010000-0x20017FFF.
*/
void MXC_LP_EnableSRAM3(void);
/**
* @brief Enables power to RAM addresses 0x20008000-0x2000FFFF.
*/
void MXC_LP_EnableSRAM2(void);
/**
* @brief Enables power to RAM addresses 0x20004000-0x20007FFF.
*/
void MXC_LP_EnableSRAM1(void);
/**
* @brief Enables power to RAM addresses 0x20000000-0x20003FFF.
*/
void MXC_LP_EnableSRAM0(void);
/**
* @brief Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM3(void);
/**
* @brief Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM2(void);
/**
* @brief Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM1(void);
/**
* @brief Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed.
*/
void MXC_LP_DisableSRAM0(void);
/**
* @brief Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void MXC_LP_EnableSysRAM0LightSleep(void);
/**
* @brief Places the instruction cache in active mode.
*/
void MXC_LP_DisableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode.
*/
void MXC_LP_DisableSysRAM0LightSleep(void);
/**
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
* Call this function multiple times to enable pins on multiple ports. This function does not configure
* the GPIO pins nor does it setup their interrupt functionality.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
*/
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);
/**
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
* Call this function multiple times to disable pins on multiple ports.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
*/
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask);
/**
* @brief Enables the RTC alarm to wake up the device from any low power mode.
*/
void MXC_LP_EnableRTCAlarmWakeup(void);
/**
* @brief Disables the RTC alarm from waking up the device.
*/
void MXC_LP_DisableRTCAlarmWakeup(void);
/**
* @brief Places the device into SLEEP mode. This function returns once any interrupt occurs.
* @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void MXC_LP_EnterSleepMode(void);
/**
* @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur.
* @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void MXC_LP_EnterDeepSleepMode(void);
/**
* @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC or external interrupt occur.
* @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void MXC_LP_EnterBackupMode(void);
/**
* @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur.
*/
void MXC_LP_EnterShutDownMode(void);
/**
* @brief Set operating voltage and change the clock to match the new voltage.
* @param system reset configuration struct
*/
int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr);
/**
* @brief Enables Data Retention to RAM addresses 0x20000000-0x20003FFF.
*/
void MXC_LP_EnableSRamRet0(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20000000-0x20003FFF.
*/
void MXC_LP_DisableSRamRet0(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20004000-0x20007FFF.
*/
void MXC_LP_EnableSRamRet1(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20004000-0x20007FFF.
*/
void MXC_LP_DisableSRamRet1(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
*/
void MXC_LP_EnableSRamRet2(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
*/
void MXC_LP_DisableSRamRet2(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20010000-0x20017FFF.
*/
void MXC_LP_EnableSRamRet3(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20010000-0x20017FFF.
*/
void MXC_LP_DisableSRamRet3(void);
/**
* @brief Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time.
*/
void MXC_LP_EnableBlockDetect(void);
/**
* @brief Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time
*/
void MXC_LP_DisableBlockDetect(void);
/**
* @brief RAM Retention Regulator Enable for BACKUP Mode
*/
void MXC_LP_EnableRamRetReg(void);
/**
* @brief RAM Retention Regulator Disabels for BACKUP Mode
*/
void MXC_LP_DisableRamRetReg(void);
/**
* @brief Enables Fast wake up from deepsleep
*/
void MXC_LP_EnableFastWk(void);
/**
* @brief Disables Fast wake up from deepsleep
*/
void MXC_LP_DisableFastWk(void);
/**
* @brief Turns on band gap during deepsleep and backup mode.
*/
void MXC_LP_EnableBandGap(void);
/**
* @brief Turns off band gap during deepsleep and backup mode.
*/
void MXC_LP_DisableBandGap(void);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void MXC_LP_EnableVCorePORSignal(void);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void MXC_LP_DisableVCorePORSignal(void);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void MXC_LP_EnableLDO(void);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void MXC_LP_DisableLDO(void);
/**
* @brief Enables V CORE Supply Voltage Monitor
*/
void MXC_LP_EnableVCoreSVM(void);
/**
* @brief Disables V CORE Supply Voltage Monitor
*/
void MXC_LP_DisableVCoreSVM(void);
/**
* @brief Enables VDDIO Power-On-Reset Monitor
*/
void MXC_LP_EnableVDDIOPorMonitor(void);
/**
* @brief Disables VDDIO Power-On-Reset Monitor
*/
void MXC_LP_DisableVDDIOPorMonitor(void);
/**@} end of group pwrseq */
#ifdef __cplusplus
}
#endif
#endif /* _LP_H_ */

173
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h Normal file
View File

@ -0,0 +1,173 @@
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
********************************************************************************
*/
/**
* \file
* \brief Magnetic Stripe Reader driver
* \details This driver can be used to configure and operate the Magnetic Stripe
* Reader. It reads and decodes magnetic stripe data that is encoded
* according to the ISO/IEC standard 7811.
* \details This file defines the driver API including data types and function
* prototypes.
*/
#ifndef _MSR_H_
#define _MSR_H_
/***** Definitions *****/
/// Number of tracks on a card
#ifndef MSR_NUM_TRACKS
#define MSR_NUM_TRACKS 3
#endif
#define MSR_MAX_SAMPLES 1536
// Assuming nominal bit density of 210 bpi and 3.375 inch length
#define MSR_MAX_RAW_LEN_BITS (709)
#define MSR_MAX_RAW_LEN_BYTES ((MSR_MAX_RAW_LEN_BITS + 7) / 8)
#define MSR_MAX_RAW_LEN_HALFWORDS ((MSR_MAX_RAW_LEN_BITS + 15) / 16)
/// Maximum size in bytes of decoded track characters (5-bit min to 8-bit max)
#define MSR_MAX_DEC_LEN (MSR_MAX_RAW_LEN_BITS / 5)
/// Swipe direction: the card was swiped in the forward direction
#define MSR_FORWARD 0
/// Swipe direction: the card was swiped in the reverse direction
#define MSR_REVERSE 1
/// Error codes
#define MSR_ERR_OK 0x00
#define MSR_ERR_BAD_LEN 0x01
#define MSR_ERR_START_SEN 0x02
#define MSR_ERR_END_SEN 0x04
#define MSR_ERR_OUTLIER 0x08
#define MSR_ERR_PARAM 0x10
#define MSR_ERR_LRC 0x40
#define MSR_ERR_PARITY 0x80
/// Structure to contain result of a track decode
typedef struct {
uint8_t error_code; /**< Error code value */
uint8_t parity_errs; /**< Number of characters with parity errors */
uint8_t lrc; /**< LRC check value. A value of '0' indicates a
successful LRC check. Any other value should be
considered a failure. */
uint8_t direction; /**< Swipe direction determined from decode */
uint8_t len; /**< Number or decoded characters. This does not include
the sentinels or the LRC. */
uint16_t speed;
uint8_t data[MSR_MAX_DEC_LEN]; /**< The decoded data */
} msr_decoded_track_t;
/// MSR sample fields
typedef union {
struct {
uint16_t time : 9;
uint16_t amp : 7;
};
uint16_t value;
} msr_sample_t;
/// Structure to contain raw MSR samples
typedef struct {
uint16_t len;
msr_sample_t data[MSR_MAX_SAMPLES];
} msr_samples_t;
/***** Function Prototypes *****/
/**
* \brief Initializes magnetic card reader hardware
* \returns #E_NO_ERROR if everything is successful
*/
int msr_init (void);
/**
* \brief Initializes specified track
* \param track track number (1 to 3)
*/
void msr_init_track (unsigned int track);
/**
* \brief Enables magnetic card reader
* \pre The reader should be initialized by calling msr_init() and then
* waiting at least 100 us before calling this function.
*/
void msr_enable (void);
/**
* \brief Disables magnetic card reader
*/
void msr_disable (void);
/**
* \brief Task used to execute driver functionality.
* \details This function executes the internal driver functionality that
* processes MSR events and reads stripe data. This function is used
* when MSR interrupt servicing is disabled.
* \returns 1 if all tracking reading is complete, 0 otherwise
*/
int msr_task (void);
/**
* \brief Decodes the specified track of data
* \param track track number (1 to 3)
* \param decoded_track track decode results
* \returns number of characters decoded
* \note This function has significant stack usage.
*/
unsigned int msr_track_decode (unsigned int track, msr_decoded_track_t * decoded_track);
/**
* \brief Registers an application callback function
* \details The callback function will be called after completion of the read
* of all enabled card tracks
* \details Unregistering of the callback can be performed by calling this
* function function with a NULL parameter.
* \param func application callback function
*/
void msr_set_complete_callback (void (*func) (void));
/**
* \brief Retrieves the raw (undecoded) sample data for the specified track
* of data
* \param track track number (1 to 3)
* \param samples pointer to where the sample data will be copied
* \returns number of samples retrieved
*/
unsigned int mcr_get_track_samples (unsigned int track, msr_samples_t * samples);
#endif /* _MSR_H_ */

109
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h Normal file
View File

@ -0,0 +1,109 @@
/**
* @file mxc_assert.h
* @brief Assertion checks for debugging.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_ASSERT_H_
#define _MXC_ASSERT_H_
/* **** Includes **** */
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup mxc_assertions Assertion Checks for Debugging
* @brief Assertion checks for debugging.
* @{
*/
/* **** Definitions **** */
/**
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
///@cond
#ifdef MXC_ASSERT_ENABLE
/**
* Macro that checks the expression for true and generates an assertion.
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
#define MXC_ASSERT(expr) \
if (!(expr)) \
{ \
mxc_assert(#expr, __FILE__, __LINE__); \
}
/**
* Macro that generates an assertion with the message "FAIL".
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__);
#else
#define MXC_ASSERT(expr)
#define MXC_ASSERT_FAIL()
#endif
///@endcond
/* **** Globals **** */
/* **** Function Prototypes **** */
/**
* @brief Assert an error when the given expression fails during debugging.
* @param expr String with the expression that failed the assertion.
* @param file File containing the failed assertion.
* @param line Line number for the failed assertion.
* @note This is defined as a weak function and can be overridden at the
* application layer to print the debugging information.
* @code
* printf("%s, file: %s, line %d\n", expr, file, line);
* @endcode
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
void mxc_assert (const char *expr, const char *file, int line);
/**@} end of group MXC_Assertions*/
#ifdef __cplusplus
}
#endif
#endif /* _MXC_ASSERT_H_ */

130
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h Normal file
View File

@ -0,0 +1,130 @@
/**
* @file mxc_delay.h
* @brief Asynchronous delay routines based on the SysTick Timer.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _DELAY_H_
#define _DELAY_H_
/**
* @ingroup devicelibs
* @defgroup MXC_delay Delay Utility Functions
* @brief Asynchronous delay routines based on the SysTick Timer
* @{
*/
/***** Definitions *****/
/**
* Macro used to specify a microsecond timing parameter in seconds.
* \code
* x = SEC(3) // 3 seconds -> x = 3,000,000
* \endcode
*/
#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL)
/**
* Macro used to specify a microsecond timing parameter in milliseconds.
* \code
* x = MSEC(3) // 3ms -> x = 3,000
* \endcode
*/
#define MXC_DELAY_MSEC(ms) (ms * 1000UL)
/**
* Macro used to specify a microsecond timing parameter.
* \code
* x = USEC(3) // 3us -> x = 3
* \endcode
*/
#define MXC_DELAY_USEC(us) (us)
/**
* @brief The callback routine used by MXC_DelayAsync() when the delay is complete
* or aborted early.
*
* @param result See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*mxc_delay_complete_t) (int result);
/***** Function Prototypes *****/
/**
* @brief Blocks and delays for the specified number of microseconds.
* @details Uses the SysTick to create the requested delay. If the SysTick is
* running, the current settings will be used. If the SysTick is not
* running, it will be started.
* @param us microseconds to delay
* @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_Delay (unsigned long us);
/**
* @brief Starts a non-blocking delay for the specified number of
* microseconds.
* @details Uses the SysTick to time the requested delay. If the SysTick is
* running, the current settings will be used. If the SysTick is not
* running, it will be started.
* @note MXC_Delay_handler() must be called from the SysTick interrupt service
* routine or at a rate greater than the SysTick overflow rate.
* @param us microseconds to delay
* @param callback Function pointer to the function called once the delay expires.
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
* delay request.
*/
int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback);
/**
* @brief Returns the status of a non-blocking delay request
* @pre Start the asynchronous delay by calling MXC_Delay_start().
* @return #E_BUSY until the requested delay time has expired.
*/
int MXC_DelayCheck (void);
/**
* @brief Stops an asynchronous delay previously started.
* @pre Start the asynchronous delay by calling MXC_Delay_start().
*/
void MXC_DelayAbort (void);
/**
* @brief Processes the delay interrupt.
* @details This function must be called from the SysTick IRQ or polled at a
* rate greater than the SysTick overflow rate.
*/
void MXC_DelayHandler (void);
/**@} end of group MXC_delay */
#endif /* _DELAY_H_ */

74
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h Normal file
View File

@ -0,0 +1,74 @@
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
******************************************************************************/
/**
* @file mxc_device.h
* @brief contains device and revision specific definitions
*/
#ifndef _MXC_DEVICE_H_
#define _MXC_DEVICE_H_
#include "max32660.h"
#include "mxc_errors.h"
#ifndef TARGET
#error TARGET NOT DEFINED
#endif
// Create a string definition for the TARGET
#define STRING_ARG(arg) #arg
#define STRING_NAME(name) STRING_ARG(name)
#if MBED_VERSION && MBED_VERSION < 51200
#define TARGET_NAME STRING_NAME(TARGET)
#endif
// Define which revisions of the IP we are using
#ifndef TARGET_REV
#error TARGET_REV NOT DEFINED
#endif
#if(TARGET_REV == 0x4131)
// A1
#define MXC_PBM_REV 0
#define MXC_TMR_REV 0
#define MXC_UART_REV 1
#else
#error TARGET_REV NOT SUPPORTED
#endif // if(TARGET_REV == ...)
#endif /* _MXC_DEVICE_H_ */

92
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h Normal file
View File

@ -0,0 +1,92 @@
/**
* @file mxc_errors.h
* @brief List of common error return codes for Maxim Integrated libraries.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_ERRORS_H_
#define _MXC_ERRORS_H_
/**
* @ingroup syscfg
* @defgroup MXC_Error_Codes Error Codes
* @brief A list of common error codes used by the API.
* @note A Negative Error Convention is used to avoid conflict with
* positive, Non-Error, returns.
* @{
*/
/** No Error */
#define E_NO_ERROR 0
/** No Error, success */
#define E_SUCCESS 0
/** Pointer is NULL */
#define E_NULL_PTR -1
/** No such device */
#define E_NO_DEVICE -2
/** Parameter not acceptable */
#define E_BAD_PARAM -3
/** Value not valid or allowed */
#define E_INVALID -4
/** Module not initialized */
#define E_UNINITIALIZED -5
/** Busy now, try again later */
#define E_BUSY -6
/** Operation not allowed in current state */
#define E_BAD_STATE -7
/** Generic error */
#define E_UNKNOWN -8
/** General communications error */
#define E_COMM_ERR -9
/** Operation timed out */
#define E_TIME_OUT -10
/** Expected response did not occur */
#define E_NO_RESPONSE -11
/** Operations resulted in unexpected overflow */
#define E_OVERFLOW -12
/** Operations resulted in unexpected underflow */
#define E_UNDERFLOW -13
/** Data or resource not available at this time */
#define E_NONE_AVAIL -14
/** Event was shutdown */
#define E_SHUTDOWN -15
/** Event was aborted */
#define E_ABORT -16
/** The requested operation is not supported */
#define E_NOT_SUPPORTED -17
/**@} end of MXC_Error_Codes group */
#endif /* _MXC_ERRORS_H_ */

869
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h Normal file
View File

@ -0,0 +1,869 @@
/**
* @file i2c.h
* @brief Inter-integrated circuit (I2C) communications interface driver.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_I2C_H_
#define _MXC_I2C_H_
#include <stdint.h>
#include "mxc_sys.h"
#include "i2c_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup i2c I2C
* @ingroup periphlibs
* @{
*/
typedef struct _i2c_req_t mxc_i2c_req_t;
/**
* @brief The callback used by the MXC_I2C_ReadByteInteractive() function.
*
* The callback routine used by the MXC_I2C_ReadByteInteractive() function. This
* function allows the application to determine whether the byte received
* should be acknowledged or not.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param byte The byte received.
*
* @return 0 if the byte should not be acknowledged (NACK), non-zero to
* acknowledge the byte.
*/
typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte);
/**
* @brief The callback routine used by the MXC_I2C_MasterTransactionAsync()
* function to indicate the transaction has completed.
*
* @param req The details of the transaction.
* @param result 0 if all bytes are acknowledged, 1 if any byte
* transmitted is not acknowledged, negative if error.
* See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result);
/**
* @brief The callback routine used by the I2C Read/Write FIFO DMA
* functions to indicate the transaction has completed.
*
* @param len The length of data actually read/written
* @param result See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result);
/**
* @brief The information required to perform a complete I2C transaction as
* the bus master.
*
* The information required to perform a complete I2C transaction as the bus
* master. This structure is used by the MXC_I2C_MasterTransaction() and
* MXC_I2C_MasterTransactionAsync() functions.
*/
struct _i2c_req_t {
mxc_i2c_regs_t* i2c; ///< Pointer to I2C registers (selects the
///< I2C block used.)
unsigned int addr; ///< The 7-bit or 10-bit address of the slave.
unsigned char* tx_buf; ///< The buffer containing the bytes to write.
unsigned int tx_len; ///< The number of bytes to write. On return
///< from the function, this will be set to
///< the number of bytes actually transmitted.
unsigned char* rx_buf; ///< The buffer to read the data into.
unsigned int rx_len; ///< The number of bytes to read. On return
///< from the function, this will be set to
///< the number of bytes actually received.
int restart; ///< Controls whether the transaction is
///< terminated with a stop or repeated start
///< condition. Use 0 for a stop, non-zero
///< for repeated start.
mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the
///< transaction is complete or an error has
///< occurred. This field may be set to NULL
///< if no indication is necessary. This
///< field is only used by the
///< MXC_I2C_MasterTransactionAsync() function.
///< MXC_I2C_MasterTransaction() ignores the
///< callback field.
};
/**
* @brief The list of events reported by the MXC_I2C_SlaveTransaction() and
* MXC_I2C_SlaveTransactionAsync() functions.
*
* The list of events reported by the MXC_I2C_SlaveTransaction() and
* MXC_I2C_SlaveTransactionAsync() functions. It is up to the calling
* application to handle these events.
*/
typedef enum {
MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master
///< requesting a write to the slave.
MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master
///< requesting a read from the slave.
MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its
///< threshold level.
MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its
///< threshold level.
MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended.
MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the
///< transmit FIFO was empty.
MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive
///< FIFO was already full.
} mxc_i2c_slave_event_t;
/**
* @brief The callback routine used by the MXC_I2C_SlaveTransaction() and
* MXC_I2C_SlaveTransactionAsync functions to handle the various I2C
* slave events.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param event The event that occurred to trigger this callback.
* @param data This field is used to pass Success/Fail for the
* MXC_I2C_EVT_TRANS_COMP event.
*
* @return The return value is only used in the case of an MXC_I2C_EVT_RX_THRESH
* event. In this case, the return specifies if the last byte
* received should be acknowledged or not. Return 0 to acknowledge,
* non-zero to not acknowledge. The return value is ignored for all
* other event types.
*/
typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
mxc_i2c_slave_event_t event, void* data);
/***** Function Prototypes *****/
/* ************************************************************************* */
/* Control/Configuration functions */
/* ************************************************************************* */
/**
* @brief Initialize and enable I2C peripheral.
* @note This function sets the I2C Speed to 100kHz, if another speed is
* desired use the MXC_I2C_SetFrequency() function to set it.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param masterMode Whether to put the device in master or slave mode. Use
* non-zero
* for master mode, and zero for slave mode.
* @param slaveAddr 7-bit or 10-bit address to use when in slave mode.
* This parameter is ignored when masterMode is non-zero.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr);
/**
* @brief Set slave address for I2C instances acting as slaves on the bus.
* @note Set idx to zero, multiple I2C instances acting as slaves on the
* bus is not yet supported.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param slaveAddr 7-bit or 10-bit address to use when in slave mode.
* This parameter is ignored when masterMode is non-zero.
* @param idx Index of the I2C slave.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx);
/**
* @brief Disable and shutdown I2C peripheral.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c);
/**
* @brief Set the frequency of the I2C interface.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param hz The desired frequency in Hertz.
*
* @return Negative if error, otherwise actual speed set. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz);
/**
* @brief Get the frequency of the I2C interface.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return The I2C bus frequency in Hertz
*/
unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c);
/**
* @brief Checks if the given I2C bus can be placed in sleep more.
*
* This functions checks to see if there are any on-going I2C transactions in
* progress. If there are transactions in progress, the application should
* wait until the I2C bus is free before entering a low-power state.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c);
/**
* @brief Enables or disables clock stretching by the slave.
*
* Enables or disables clock stretching by the slave. This function has no
* affect when operating as the master.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param enable Enables clock stretching if non-zero, disables if zero.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable);
/**
* @brief Determines if clock stretching has been enabled.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return Zero if clock stretching is disabled, non-zero otherwise
*/
int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c);
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
/**
* @brief Generate a start (or repeated start) condition on the I2C bus.
*
* Generate a start (or repeated start) condition on the I2C bus. This
* function may opt to delay the actual generation of the start condition
* until data is actually transferred.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Start (mxc_i2c_regs_t* i2c);
/**
* @brief Generate a stop condition on the I2C bus.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Stop (mxc_i2c_regs_t* i2c);
/**
* @brief Write a single byte to the I2C bus.
*
* Write a single byte to the I2C bus. This function assumes the I2C bus is
* already in the proper state (i.e. a start condition has already been
* generated and the bus is in the write phase of an I2C transaction). If any
* bytes are pending in the FIFO (i.e. in the case of clock stretching), this
* function will return E_OVERFLOW.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param byte The byte to transmit.
*
* @return 0 if byte is acknowledged, 1 if not acknowledged, negative if
* error. See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte);
/**
* @brief Read a single byte from the I2C bus.
*
* Read a single byte from the I2C bus. This function assumes the I2C bus is
* already in the proper state (i.e. a start condition has already been
* generated and the bus is in the read phase of an I2C transaction). If the FIFO
* is empty, this function will return E_UNDERFLOW.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param byte Pointer to the byte to read into.
* @param ack Whether or not to acknowledge the byte once received.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack);
/**
* @brief Read a single byte from the I2C bus.
*
* Read a single byte from the I2C bus. After the byte is received, the
* provided callback will be used to determine if the byte should be
* acknowledged or not before continuing with the rest of the transaction.
* This function assumes the I2C bus is already in the proper state (i.e. a
* start condition has already been generated and the bus is in the read
* phase of an I2C transaction). This function must be called with clock
* stretching enabled.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param byte Pointer to the byte to read into.
* @param getAck A function to be called to determine whether or not
* to acknowledge the byte once received. A non-zero
* return value will acknowledge the byte. If this
* parameter is set to NULL or its return value is 0,
* the byte received will not be acknowledged (i.e., it
* will be NACKed).
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte,
mxc_i2c_getAck_t getAck);
/**
* @brief Write multiple bytes to the I2C bus.
*
* Write multiple bytes to the I2C bus. This function assumes the I2C bus is
* already in the proper state (i.e. a start condition has already been
* generated and the bus is in the write phase of an I2C transaction).
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param bytes The buffer containing the bytes to transmit.
* @param len The number of bytes to write. On return from the
* function, this will be set to the number of bytes
* actually transmitted.
*
* @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not
* acknowledged, negative if error. See \ref MXC_Error_Codes for the
* list of error return codes.
*/
int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len);
/**
* @brief Read multiple bytes from the I2C bus.
*
* Read multiple byte from the I2C bus. This function assumes the I2C bus is
* already in the proper state (i.e. a start condition has already been
* generated and the bus is in the read phase of an I2C transaction).
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read. On return from the
* function, this will be set to the number of bytes
* actually received.
* @param ack Whether or not to acknowledge the last byte once it is
* received. All previous bytes will be acknowledged.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
int ack);
/**
* @brief Unloads bytes from the receive FIFO.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
*
* @return The number of bytes actually read.
*/
int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
unsigned int len);
/**
* @brief Unloads bytes from the receive FIFO using DMA for longer reads.
*
* @note The operation is not complete until the callback has been called
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
* @param callback The function to call when the read is complete
*
* @return See \ref MXC_Error_Codes for a list of return values.
*/
int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return The number of bytes available.
*/
int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c);
/**
* @brief Loads bytes into the transmit FIFO.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
*
* @return The number of bytes actually written.
*/
int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
unsigned int len);
/**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes.
*
* @note The operation is not complete until the callback has been called
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
* @param callback The function to call when the read is complete
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
unsigned int len, mxc_i2c_dma_complete_cb_t callback);
/**
* @brief Get the amount of free space available in the transmit FIFO.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return The number of bytes available.
*/
int MXC_I2C_GetTXFIFOAvailable (mxc_i2c_regs_t* i2c);
/**
* @brief Removes and discards all bytes currently in the receive FIFO.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_ClearRXFIFO (mxc_i2c_regs_t* i2c);
/**
* @brief Removes and discards all bytes currently in the transmit FIFO.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c);
/**
* @brief Get the presently set interrupt flags.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param flags0 Pointer to the variable to store the current status of the interrupt flags in intfl0.
* @param flags1 Pointer to the variable to store the current status of the interrupt flags in intfl0.
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1);
/**
* @brief Clears the Interrupt Flags.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param flags0 Flags to clear in the intfl0 interrupt register.
* @param flags1 Flags to clear in the intfl1 interrupt register.
*/
void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
/**
* @brief Enable Interrupts.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param flags0 Interrupts to be enabled in int->en0
* @param flags1 Interrupts to be enabled in int->en1
*/
void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
/**
* @brief Disable Interrupts.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param flags0 Interrupts to be disabled in int->en0
* @param flags1 Interrupts to be disabled in int->en1
*/
void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
/**
* @brief Enables the slave preload mode
*
* Use this mode to preload the slave TX FIFO with data that can be sent when
* the slave is addressed for a read operation without software intervention.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c);
/**
* @brief Disable the slave preload mode
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c);
/**
* @brief Enables the slave to respond to the general call address
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c);
/**
* @brief Prevents the slave from responding to the general call address
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c);
/**
* @brief Set the I2C Timeout
*
* The I2C timeout determines the amount of time the master will wait while the
* slave is stretching the clock, and the amount of time the slave will stretch
* the clock while waiting for software to unload the fifo.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param timeout Timeout in uS
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout);
/**
* @brief Get the current I2C timeout
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return The current timeout in uS
*/
unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c);
/**
* @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle.
*
* Attempts to recover and reset an I2C bus by sending I2C clocks. During
* each clock cycle, the SDA line is cycled to determine if the master has
* control of the line. The following steps are performed to create one SCL
* clock cycle:
* 1. Drive SCL low
* 2. Verify SCL is low
* 3. Drive SDA low
* 4. Verify SDA is low
* 5. Release SDA allowing it to return high
* 6. Verify SDA is high
* 7. Release SCL allowing it to return high.
* 8. Verify SCL is high
* If any of the steps fail, the bus is considered to still be busy and the
* sequence is repeated up to the requested number of times. If all steps
* succeed, a final stop condition is generated on the I2C bus.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param retries Number of times to attempt the clock cycle sequence.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries);
/* ************************************************************************* */
/* Transaction level functions */
/* ************************************************************************* */
/**
* @brief Performs a blocking I2C Master transaction.
*
* Performs a blocking I2C transaction. These actions will be performed:
* 1. If necessary, generate a start condition on the bus.
* 2. Send the slave address with the low bit set to 0 (indicating a write).
* 3. Transmit req->tx_len bytes of req->tx_buff.
* 4. Generate a repeated start condition on the bus.
* 5. Send the slave address with the low bit set to 1 (indicating a read).
* 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte.
* 7. Generate a stop (or repeated start) condition on the bus.
* Steps 3-6 will be skipped if req->tx_len and req->rx_len are both 0.
* Steps 2-4 will be skipped if req->tx_len equals 0.
* Steps 4-6 will be skipped if req->rx_len equals 0.
*
* @param req Pointer to details of the transaction
*
* @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not
* acknowledged, negative if error. See \ref MXC_Error_Codes for the
* list of error return codes.
*/
int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req);
/**
* @brief Performs a non-blocking I2C Master transaction.
*
* Performs a non-blocking I2C transaction. These actions will be performed:
* 1. If necessary, generate a start condition on the bus.
* 2. Send the slave address with the low bit set to 0 (indicating a write).
* 3. Transmit req->tx_len bytes of req->tx_buff.
* 4. Generate a repeated start condition on the bus.
* 5. Send the slave address with the low bit set to 1 (indicating a read).
* 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte.
* 7. Generate a stop (or repeated start) condition on the bus.
* 8. Execute req->callback to indicate the transaction is complete.
* Steps 3-6 will be skipped if tx_len and rx_len are both 0.
* Steps 2-4 will be skipped if tx_len equals 0.
* Steps 4-6 will be skipped if rx_len equals 0.
*
* @note MXC_I2C_AsyncHandler() must be called periodically for this function
* to operate properly. Ideally from the I2C ISR.
*
* @param req Pointer to details of the transaction. The memory
* used by this parameter must remain available until
* the callback is executed.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req);
/**
* @brief Performs a non-blocking I2C Master transaction using DMA for reduced time
* in the ISR.
*
* Performs a non-blocking I2C transaction. These actions will be performed:
* 1. If necessary, generate a start condition on the bus.
* 2. Send the slave address with the low bit set to 0 (indicating a write).
* 3. Transmit req->tx_len bytes of req->tx_buff.
* 4. Generate a repeated start condition on the bus.
* 5. Send the slave address with the low bit set to 1 (indicating a read).
* 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte.
* 7. Generate a stop (or repeated start) condition on the bus.
* 8. Execute req->callback to indicate the transaction is complete.
* Steps 3-6 will be skipped if tx_len and rx_len are both 0.
* Steps 2-4 will be skipped if tx_len equals 0.
* Steps 4-6 will be skipped if rx_len equals 0.
*
* @note MXC_I2C_AsyncHandler() must be called periodically for this function
* to operate properly. Ideally from the I2C ISR.
*
* @param req Pointer to details of the transaction. The memory
* used by this parameter must remain available until
* the callback is executed.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req);
/**
* @brief Performs a blocking I2C Slave transaction.
*
* Performs a blocking I2C transaction. This function will block until a
* complete transaction with this slave has been performed. A transaction
* begins with the master addressing the slave and ends with a repeated start
* condition, a stop condition, or a bus error. The provided callback
* function will be called for these events:
* - A slave address match occurs with the master requesting a write to
* the slave.
* - A slave address match occurs with the master requesting a read from
* the slave.
* - The receive FIFO crosses the set threshold (see
* MXC_I2C_SetRXThreshold()). The callback code should unload the receive
* FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data.
* The return value of the callback function will determine if the
* last byte received should be acknowledged or not. Return 0 to
* acknowledge, non-zero to not acknowledge.
* - The transmit FIFO crosses the set threshold (see
* MXC_I2C_SetTXThreshold()). If the master is expected to read more
* data from this slave, the callback code should add data to the
* transmit FIFO (see MXC_I2C_WriteFIFO()).
* - The transaction ends. If the master was writing to the slave, the
* receive FIFO may still contain valid data that needs to be
* retreived (see MXC_I2C_ReadFIFO()).
* - The transmit FIFO underflows because the master requests data when
* the transmit FIFO is empty.
* - The receive FIFO overflows because the master writes data while the
* receive FIFO was full.
*
* If clock stretching is disabled, careful attention must be paid to the timing
* of the callback to avoid losing data on write or unintentionally nacking a read.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param callback The function to be called when an I2C event occurs.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback);
/**
* @brief Performs a non-blocking I2C Slave transaction.
*
* Performs a non-blocking I2C transaction. This request will remain active
* until a complete transaction with this slave has been performed. A
* transaction begins with the masterMXC_I2C_MasterTransactionDMA addressing the
* slave and ends with a repeated start condition, a stop condition, or a bus
* error. The provided callback function will be called for these events:
* - A slave address match occurs with the master requesting a write to
* the slave.
* - A slave address match occurs with the master requesting a read from
* the slave.
* - The receive FIFO crosses the set threshold (see
* MXC_I2C_SetRXThreshold()). The callback code should unload the receive
* FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data.
* The return value of the callback function will determine if the
* last byte received should be acknowledged or not. Return 0 to
* acknowledge, non-zero to not acknowledge.
* - The transmit FIFO crosses the set threshold (see
* MXC_I2C_SetTXThreshold()). If the master is expected to read more
* data from this slave, the callback code should add data to the
* transmit FIFO (see MXC_I2C_WriteFIFO()).
* - The transaction ends. If the master was writing to the slave, the
* receive FIFO may still contain valid data that needs to be
* retreived (see MXC_I2C_ReadFIFO()).
* - The transmit FIFO underflows because the master requests data when
* the transmit FIFO is empty.
* - The receive FIFO overflows because the master writes data while the
* receive FIFO was full.
*
* If clock stretching is disabled, careful attention must be paid to the timing
* of the callback to avoid losing data on write or unintentionally nacking a read.
*
* @note MXC_I2C_AsyncHandler() must be called peridocally for this function
* to operate properly.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param callback The function to be called when an I2C event occurs.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback);
/**
* @brief Set the receive threshold level.
*
* When operating as a master, the function sets the receive threshold level
* for when the master should unload the receive FIFO. Smaller values may
* consume more CPU cycles, but decrease the chances of the master delaying
* the generation of I2C bus clocks because it has no room in the FIFO to
* receive data. Larger values may consume fewer CPU cycles, but risk delays
* of the I2C clock. When operating as a slave, this function sets the number
* of bytes the slave transaction functions should receive before issuing a
* call to their callback function. Smaller values may consume more CPU
* cycles, but reduce the risk of missing data from the master due to the
* recieve FIFO being full. Larger values may reduce the number of CPU
* cycles, but may cause bytes sent from the master to be missed.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
/**
* @brief Get the current receive threshold level.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return The receive threshold value (in bytes).
*/
unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c);
/**
* @brief Set the transmit threshold level.
*
* When operating as a master, the function sets the transmit threshold level
* for when the master should add additional bytes to the transmit FIFO.
* Larger values may consume more CPU cycles, but decrease the chances of the
* master delaying the generation of I2C bus clocks because it has no data in
* the FIFO to transmit. Smaller values may consume fewer CPU cycles, but
* risk delays of the I2C clock. When operating as a slave, this function
* sets the number of bytes the slave transaction functions should transmit
* before issuing a call to their callback function. Larger values may
* consume more CPU cycles, but reduce the risk of not having data ready when
* the master requests it. Smaller values may reduce the number of CPU
* cycles, but may cause the master to read from an empty FIFO. (The master
* will read 0xFF in this case.)
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
/**
* @brief Get the current transmit threshold level.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*
* @return The transmit threshold value (in bytes).
*/
unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c);
/**
* @brief Abort any asynchronous requests in progress.
*
* Abort any asynchronous requests in progress. Any callbacks associated with
* the active transaction will be executed to indicate when the transaction
* has been terminated.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c);
/**
* @brief The processing function for asynchronous transactions.
*
* When using the asynchronous functions, the application must call this
* function periodically. This can be done from within the I2C interrupt
* handler or periodically by the application if I2C interrupts are disabled.
*
* @param i2c Pointer to I2C registers (selects the I2C block used.)
*/
void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c);
/**
* @brief The processing function for DMA transactions.
*
* When using the DMA functions, the application must call this
* function periodically. This can be done from within the DMA Interrupt Handler.
*
* @param ch DMA channel
* @param error Error status
*/
void MXC_I2C_DMACallback (int ch, int error);
/**@} end of group i2c */
#ifdef __cplusplus
}
#endif
#endif /* _MXC_I2C_H_ */

104
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h Normal file
View File

@ -0,0 +1,104 @@
/**
* @file mxc_lock.h
* @brief Exclusive access lock utility functions.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_LOCK_H_
#define _MXC_LOCK_H_
// To enable disable this module
#define USE_LOCK_IN_DRIVERS 0
#if USE_LOCK_IN_DRIVERS
/* **** Includes **** */
#include "mxc_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup mxc_lock_utilities Exclusive Access Locks
* @brief Lock functions to obtain and release a variable for exclusive
* access. These functions are marked interrupt safe if they are
* interrupt safe.
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Function Prototypes **** */
/**
* @brief Attempts to acquire the lock.
* @details This in an interrupt safe function that can be used as a mutex.
* The lock variable must remain in scope until the lock is
* released. Will not block if another thread has already acquired
* the lock.
* @param lock Pointer to variable that is used for the lock.
* @param value Value to be place in the lock. Can not be 0.
*
* @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
*/
int MXC_GetLock (uint32_t *lock, uint32_t value);
/**
* @brief Free the given lock.
* @param[in,out] lock Pointer to the variable used for the lock. When the lock
* is free, the value pointed to by @p lock is set to zero.
*/
void MXC_FreeLock (uint32_t *lock);
/**@} end of group mxc_lock_utilities */
#ifdef __cplusplus
}
#endif
#else // USE_LOCK_IN_DRIVERS
#define MXC_GetLock(x, y) E_NO_ERROR
#define MXC_FreeLock(x)
#endif // USE_LOCK_IN_DRIVERS
#endif /* _MXC_LOCK_H_ */

85
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h Normal file
View File

@ -0,0 +1,85 @@
/**
* @file mxc_pins.h
* @brief This file contains constant pin configurations for the peripherals.
*/
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
#ifndef _MXC_PINS_H_
#define _MXC_PINS_H_
#include "gpio.h"
/***** Global Variables *****/
typedef enum {
MAP_A,
MAP_B,
MAP_C
} sys_map_t;
// Predefined GPIO Configurations
extern const mxc_gpio_cfg_t gpio_cfg_swda;
extern const mxc_gpio_cfg_t gpio_cfg_swdb;
extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
extern const mxc_gpio_cfg_t gpio_cfg_uart0;
extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow;
extern const mxc_gpio_cfg_t gpio_cfg_uart1a;
extern const mxc_gpio_cfg_t gpio_cfg_uart1b;
extern const mxc_gpio_cfg_t gpio_cfg_uart1c;
extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow;
extern const mxc_gpio_cfg_t gpio_cfg_spi0;
extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss;
extern const mxc_gpio_cfg_t gpio_cfg_spi1a;
extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss;
extern const mxc_gpio_cfg_t gpio_cfg_spi1b;
extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss;
// Timers are only defined once, depending on package, each timer could be mapped to other pins
extern const mxc_gpio_cfg_t gpio_cfg_tmr0;
extern const mxc_gpio_cfg_t gpio_cfg_32kcal;
extern const mxc_gpio_cfg_t gpio_cfg_i2s0a;
extern const mxc_gpio_cfg_t gpio_cfg_i2s0b;
#endif /* _MXC_PINS_H_ */

648
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h Normal file
View File

@ -0,0 +1,648 @@
/**
* @file spi.h
* @brief Serial Peripheral Interface (SPI) communications driver.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _SPI_H_
#define _SPI_H_
/***** includes *******/
#include "spi_regs.h"
#include "mxc_sys.h"
#include "mxc_assert.h"
#include "gpio.h"
#include "mxc_pins.h"
#include "mxc_lock.h"
/***** Definitions *****/
/**
* @defgroup spi SPI
* @ingroup periphlibs
* @{
*/
/**
* @brief The list of SPI Widths supported
*
* The SPI Width can be set on a per-transaction basis.
* An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is
* given.
*
* Using a MAX31865 RTD-to-SPI IC, read back the temperature
* The IC requires a SPI Read to be executed as
* 1. Assert SS
* 2. Write an 8bit register address
* 3. Read back the 8 bit register
* 4. Deassert SS
* This can be accomplished with the STANDARD_HALFDUPLEX width
* 1. set txData to the address, txLen=1
* 2. set rxData to a buffer of 1 byte, rxLen=1
* 3. The driver will transmit the txData, and after completion of
* txData begin to recieve data, padding MOSI with DefaultTXData
*
*/
typedef enum {
SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex
SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex
SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex
SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex
} mxc_spi_width_t;
/**
* @brief The list of SPI modes
*
* SPI supports four combinations of clock and phase polarity
*
* Clock polarity is controlled using the bit SPIn_CTRL2.cpol
* and determines if the clock is active high or active low
*
* Clock phase determines when the data must be stable for sampling
*
*/
typedef enum {
SPI_MODE_0, ///< clock phase = 0, clock polarity = 0
SPI_MODE_1, ///< clock phase = 0, clock polarity = 1
SPI_MODE_2, ///< clock phase = 1, clock polarity = 0
SPI_MODE_3, ///< clock phase = 1, clock polarity = 1
} mxc_spi_mode_t;
typedef struct _mxc_spi_req_t mxc_spi_req_t;
/**
* @brief The callback routine used to indicate the transaction has terminated.
*
* @param req The details of the transaction.
* @param result See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*spi_complete_cb_t) (void * req, int result);
/**
* @brief The information required to perform a complete SPI transaction
*
* This structure is used by blocking, async, and DMA based transactions.
* @param "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions.
*/
struct _mxc_spi_req_t {
mxc_spi_regs_t* spi; ///<Point to SPI registers
int ssIdx; ///< Slave select line to use (Master only, ignored in slave mode)
int ssDeassert; ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint8_t *rxData; ///< Buffer to store received data For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
uint32_t rxCnt; ///< Number of bytes stored in rxData
spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete
};
/* ************************************************************************* */
/* Control/Configuration functions */
/* ************************************************************************* */
/**
* @brief Initialize and enable SPI peripheral.
*
* This function initializes everything necessary to call a SPI transaction function.
* Some parameters are set to defaults as follows:
* SPI Mode - 0
* SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set)
*
* These parameters can be modified after initialization using low level functions
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param masterMode Whether to put the device in master or slave mode. Use
* non-zero for master mode, and zero for slave mode.
* @param quadModeUsed Whether to obtain control of the SDIO2/3 pins. Use
* non-zero if the pins are needed (if Quad Mode will
* be used), and zero if they are not needed (quad mode
* will never be used).
* @param numSlaves The number of slaves used, if in master mode. This
* is used to obtain control of the necessary SS pins.
* In slave mode this is ignored and SS1 is used.
* @param ssPolarity This field sets the SS active polarity for each
* slave, each bit position corresponds to each SS line.
* @param hz The requested clock frequency. The actual clock frequency
* will be returned by the function if successful. Used in
* master mode only.
* @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is
* To upper layer firmware drive it.
* 1:Driver will drive SS pin, 0:Driver will NOT drive it
*
* @return If successful, the actual clock frequency is returned. Otherwise, see
* \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
/**
* @brief Disable and shutdown SPI peripheral.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_Shutdown (mxc_spi_regs_t* spi);
/**
* @brief Checks if the given SPI bus can be placed in sleep mode.
*
* This functions checks to see if there are any on-going SPI transactions in
* progress. If there are transactions in progress, the application should
* wait until the SPI bus is free before entering a low-power state.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
/**
* @brief Set the frequency of the SPI interface.
*
* This function is applicable in Master mode only
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param hz The desired frequency in Hertz.
*
* @return Negative if error, otherwise actual speed set. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz);
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
/**
* @brief Get the frequency of the SPI interface.
*
* This function is applicable in Master mode only
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return The SPI bus frequency in Hertz
*/
unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi);
/**
* @brief Sets the number of bits per character
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param dataSize The number of bits per character
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize);
/**
* @brief Gets the number of bits per character
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi);
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
/**
* @brief Sets the slave select (SS) line used for transmissions
*
* This function is applicable in Master mode only
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param ssIdx Slave select index
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx);
/**
* @brief Gets the slave select (SS) line used for transmissions
*
* This function is applicable in Master mode only
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return slave slect
*/
int MXC_SPI_GetSlave (mxc_spi_regs_t* spi);
/**
* @brief Sets the SPI width used for transmissions
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth);
/**
* @brief Gets the SPI width used for transmissions
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Spi Width \ref mxc_spi_width_t
*/
mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi);
/**
* @brief Sets the spi mode using clock polarity and clock phase
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param spiMode \ref mxc_spi_mode_t
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode);
/**
* @brief Gets the spi mode
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return mxc_spi_mode_t \ref mxc_spi_mode_t
*/
mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi);
/**
* @brief Starts a SPI Transmission
*
* This function is applicable in Master mode only
*
* The user must ensure that there are no ongoing transmissions before
* calling this function
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi);
/**
* @brief Checks the SPI Peripheral for an ongoing transmission
*
* This function is applicable in Master mode only
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_GetActive (mxc_spi_regs_t* spi);
/**
* @brief Aborts an ongoing SPI Transmission
*
* This function is applicable in Master mode only
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi);
/**
* @brief Unloads bytes from the receive FIFO.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
*
* @return The number of bytes actually read.
*/
unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return The number of bytes available.
*/
unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi);
/**
* @brief Loads bytes into the transmit FIFO.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
*
* @return The number of bytes actually written.
*/
unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len);
/**
* @brief Get the amount of free space available in the transmit FIFO.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return The number of bytes available.
*/
unsigned int MXC_SPI_GetTXFIFOAvailable (mxc_spi_regs_t* spi);
/**
* @brief Removes and discards all bytes currently in the receive FIFO.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*/
void MXC_SPI_ClearRXFIFO (mxc_spi_regs_t* spi);
/**
* @brief Removes and discards all bytes currently in the transmit FIFO.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*/
void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi);
/**
* @brief Set the receive threshold level.
*
* RX FIFO Receive threshold. Smaller values will cause
* interrupts to occur more often, but reduce the possibility
* of losing data because of a FIFO overflow. Larger values
* will reduce the time required by the ISR, but increase the
* possibility of data loss. Passing an invalid value will
* cause the driver to use the value already set in the
* appropriate register.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
/**
* @brief Get the current receive threshold level.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return The receive threshold value (in bytes).
*/
unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi);
/**
* @brief Set the transmit threshold level.
*
* TX FIFO threshold. Smaller values will cause interrupts
* to occur more often, but reduce the possibility of terminating
* a transaction early in master mode, or transmitting invalid data
* in slave mode. Larger values will reduce the time required by
* the ISR, but increase the possibility errors occurring. Passing
* an invalid value will cause the driver to use the value already
* set in the appropriate register.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
/**
* @brief Get the current transmit threshold level.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return The transmit threshold value (in bytes).
*/
unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi);
/**
* @brief Gets the interrupt flags that are currently set
*
* These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*
* @return The interrupt flags
*/
unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi);
/**
* @brief Clears the interrupt flags that are currently set
*
* These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*/
void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi);
/**
* @brief Enables specific interrupts
*
* These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param mask The interrupts to be enabled
*/
void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask);
/**
* @brief Disables specific interrupts
*
* These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param mask The interrupts to be disabled
*/
void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask);
/* ************************************************************************* */
/* Transaction level functions */
/* ************************************************************************* */
/**
* @brief Performs a blocking SPI transaction.
*
* Performs a blocking SPI transaction.
* These actions will be performed in Master Mode:
* 1. Assert the specified SS
* 2. In Full Duplex Modes, send TX data while receiving RX Data
* if rxLen > txLen, pad txData with DefaultTXData
* if txLen > rxLen, discard rxData where rxCnt > rxLen
* 3. In Half Duplex Modes, send TX Data, then receive RX Data
* 4. Deassert the specified SS
*
* These actions will be performed in Slave Mode:
* 1. Fill FIFO with txData
* 2. Wait for SS Assert
* 3. If needed, pad txData with DefaultTXData
* 4. Unload RX FIFO as needed
* 5. On SS Deassert, return
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_MasterTransaction (mxc_spi_req_t* req);
/**
* @brief Setup an interrupt-driven SPI transaction
*
* The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
* Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req);
/**
* @brief Setup a DMA driven SPI transaction
*
* The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
* Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
*
* The lowest-indexed unused DMA channel will be acquired (using the DMA API) and
* set up to load/unload the FIFOs with as few interrupt-based events as
* possible. The channel will be reset and returned to the system at the end of
* the transaction.
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req);
/**
* @brief Performs a blocking SPI transaction.
*
* Performs a blocking SPI transaction.
* These actions will be performed in Slave Mode:
* 1. Fill FIFO with txData
* 2. Wait for SS Assert
* 3. If needed, pad txData with DefaultTXData
* 4. Unload RX FIFO as needed
* 5. On SS Deassert, return
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req);
/**
* @brief Setup an interrupt-driven SPI transaction
*
* The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
* Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
*
* @param req Pointer to details of the transactionz
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req);
/**
* @brief Setup a DMA driven SPI transaction
*
* The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
* Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
*
* The lowest-indexed unused DMA channel will be acquired (using the DMA API) and
* set up to load/unload the FIFOs with as few interrupt-based events as
* possible. The channel will be reset and returned to the system at the end of
* the transaction.
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req);
/**
* @brief Sets the TX data to transmit as a 'dummy' byte
*
* In single wire master mode, this data is transmitted on MOSI when performing
* an RX (MISO) only transaction. This defaults to 0.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param defaultTXData Data to shift out in RX-only transactions
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData);
/**
* @brief Abort any asynchronous requests in progress.
*
* Abort any asynchronous requests in progress. Any callbacks associated with
* the active transaction will be executed to indicate when the transaction
* has been terminated.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*/
void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi);
/**
* @brief The processing function for asynchronous transactions.
*
* When using the asynchronous functions, the application must call this
* function periodically. This can be done from within the SPI interrupt
* handler or periodically by the application if SPI interrupts are disabled.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
*/
void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi);
/**@} end of group spi */
#ifdef __cplusplus
}
#endif
#endif /* _PT_H_ */

167
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h Normal file
View File

@ -0,0 +1,167 @@
/**
* @file mxc_sys.h
* @brief System level header file.
*/
/*******************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
******************************************************************************/
#ifndef _MXC_MXC_SYS_H_
#define _MXC_MXC_SYS_H_
#include "mxc_device.h"
#include "gcr_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
typedef enum {
MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */
MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */
MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */
MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */
MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, /**< System reset */
/* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
} mxc_sys_reset_t;
/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
typedef enum {
MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
/* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
MXC_SYS_PERIPH_CLOCK_FLCD = (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
} mxc_sys_periph_clock_t;
/** @brief Enumeration to select System Clock source */
typedef enum {
MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */
MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */
} mxc_sys_system_clock_t;
/***** Function Prototypes *****/
/**
* @brief Determines if the selected peripheral clock is enabled.
* @param clock Enumeration for desired clock.
* @returns 0 is the clock is disabled, non 0 if the clock is enabled.
*/
int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock);
/**
* @brief Disables the selected peripheral clock.
* @param clock Enumeration for desired clock.
*/
void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock);
/**
* @brief Enables the selected peripheral clock.
* @param clock Enumeration for desired clock.
*/
void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock);
/**
* @brief Enables the 32kHz oscillator
* @param mxc_sys_cfg Not used, may be NULL.
*/
void MXC_SYS_RTCClockEnable (void);
/**
* @brief Disables the 32kHz oscillator
* @returns E_NO_ERROR if everything is successful
*/
int MXC_SYS_RTCClockDisable();
/**
* @brief Enable System Clock Source without switching to it
* @param clock The clock to enable
* @return E_NO_ERROR if everything is successful
*/
int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock);
/**
* @brief Disable System Clock Source
* @param clock The clock to disable
* @return E_NO_ERROR if everything is successful
*/
int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
/**
* @brief Select the system clock.
* @param clock Enumeration for desired clock.
* @param tmr Optional tmr pointer for timeout. NULL if undesired.
* @returns E_NO_ERROR if everything is successful.
*/
int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock);
/**
* @brief Wait for a clock to enable with timeout
* @param ready The clock to wait for
* @return E_NO_ERROR if ready, E_TIME_OUT if timeout
*/
int MXC_SYS_Clock_Timeout (uint32_t ready);
/**
* @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register.
* @param Enumeration for what to reset. Can reset multiple items at once.
*/
void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
#ifdef __cplusplus
}
#endif
#endif /* _MXC_MXC_SYS_H_*/

199
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h Normal file
View File

@ -0,0 +1,199 @@
/**
* @file rtc.h
* @brief Real Time Clock (RTC) functions and prototypes.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _RTC_H_
#define _RTC_H_
/* **** Includes **** */
#include <stdint.h>
#include "mxc_device.h"
#include "rtc_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup rtc Real Time Clock (RTC)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* @brief Bitmasks for each of the RTC's Frequency.
*/
typedef enum {
MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, ///< 1Hz (Compensated)
MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, ///< 512Hz (Compensated)
MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, ///< 4Khz
MXC_RTC_F_32KHZ = 32, ///< 32Khz
} mxc_rtc_freq_sel_t;
/**
* @brief Bitmasks for each of the RTC's interrupt enables.
*/
typedef enum {
MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_ADE, ///< Long-interval alarm interrupt enable
MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_ASE, ///< Short-interval alarm interrupt enable
MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDYE, ///< Timer ready interrupt enable
} mxc_rtc_int_en_t;
/**
* @brief Bitmasks for each of the RTC's interrupt flags.
*/
typedef enum {
MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_ALDF, ///< Long-interval alarm interrupt flag
MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_ALSF, ///< Short-interval alarm interrupt flag
MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag
} mxc_rtc_int_fl_t;
/**
* @brief Set Time-of-Day alarm value and enable Interrupt
* @param ras 20-bit value 0-0xFFFFF
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SetTimeofdayAlarm (uint32_t ras);
/**
* @brief Set Sub-Second alarm value and enable interrupt,
* @brief this is to be called after the init_rtc() function
* @param rssa 32-bit value 0-0xFFFFFFFF
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SetSubsecondAlarm (uint32_t rssa);
/**
* @brief Start the Real Time Clock
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Start (void);
/**
* @brief Stop the Real Time Clock
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Stop (void);
/**
* @brief Initialize the sec and ssec registers and enable RTC
* @param sec set the RTC Sec counter (32-bit)
* @param ssec set the RTC Sub-second counter (8-bit)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Init (uint32_t sec, uint8_t ssec);
/**
* @brief Allow generation of Square Wave on the SQW pin
* @param fq Frequency output selection
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq);
/**
* @brief Stop the generation of square wave
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_SquareWaveStop (void);
/**
* @brief Set Trim register value
* @param trm set the RTC Trim (8-bit, +/- 127)
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_Trim (int8_t trm);
/**
* @brief Enable Interurpts
* @param mask The bitwise OR of interrupts to enable.
* See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_EnableInt (uint32_t mask);
/**
* @brief Disable Interurpts
* @param mask The mask of interrupts to disable.
* See #mxc_rtc_int_en_t for available choices.
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_DisableInt (uint32_t mask);
/**
* @brief Gets interrupt flags.
* @retval The bitwise OR of any interrupts flags that are
* currently set. See \ref mxc_rtc_int_fl_t for the list
* of possible flags.
*/
int MXC_RTC_GetFlags (void);
/**
* @brief Clear interrupt flags.
* @param flags The bitwise OR of the interrupts flags to cleear.
* See #mxc_rtc_int_fl_t for the list of possible flags.
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_ClearFlags (int flags);
/**
* @brief Get SubSecond
* @retval Returns subsecond value
*/
int MXC_RTC_GetSubSecond (void);
/**
* @brief Get Second
* @retval returns second value
*/
int MXC_RTC_GetSecond (void);
/**
* @brief Get the time using nuclear fusion. Or atomically. Something like that.
* @param sec pointer to store seconds value
* @param subsec pointer to store subseconds value
* @retval returns Success or Fail, see \ref MXC_Error_Codes
*/
int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec);
/**@} end of group rtc */
#ifdef __cplusplus
}
#endif
#endif /* _RTC_H_ */

210
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h Normal file
View File

@ -0,0 +1,210 @@
/**
* @file spimss.h
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPIMSS_H_
#define _SPIMSS_H_
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_sys.h"
#include "mxc_pins.h"
#include "gpio.h"
#include "spimss_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spimss SPIMSS
* @ingroup spimss
* @{
*/
/* **** Definitions **** */
/**
* @brief Enumeration type for setting the number data lines to use for communication.
*/
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
DUMMY_1, /**< NOT USED */
DUMMY_2, /**< NOT USED */
DUMMY_3, /**< NOT USED */
} mxc_spimss_width_t;
/**
* @brief Structure type representing a SPI Master Transaction request.
*/
typedef struct mxc_spimss_req mxc_spimss_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
*/
typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
*/
struct mxc_spimss_req {
uint8_t ssel; /**< Not Used*/
uint8_t deass; /**< Not Used*/
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
mxc_spimss_width_t width; /**< Not Used */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
mxc_spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi Pointer to spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
* @param sys_cfg System configuration object
* @param drv_ssel 1 SSEL will be drive by driver
* 0 SSEL will NOT be drive by driver
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel);
/**
* @brief Shutdown SPI module.
* @param spi Pointer to SPI regs.
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
/**
* @brief Execute a master transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Execute SPI transaction based on interrupt handler
* @param spi The spi
*
*/
void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi);
/**
* @brief Execute a slave transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req);
/**
* @brief Sets the TX data to transmit as a 'dummy' byte
*
* In single wire master mode, this data is transmitted on MOSI when performing
* an RX (MISO) only transaction. This defaults to 0.
*
* @param spi Pointer to SPI registers (selects the SPI block used.)
* @param defaultTXData Data to shift out in RX-only transactions
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData);
/**
* @brief Aborts an Asynchronous request
*
* @param req Pointer to spi request
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req);
/**@} end of group spimss */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_H_ */

343
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h Normal file
View File

@ -0,0 +1,343 @@
/**
* @file tmr.h
* @brief Timer (TMR) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _TMR_H_
#define _TMR_H_
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "tmr_regs.h"
#include "mxc_sys.h"
#include "gcr_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup tmr Timer (TMR)
* @ingroup periphlibs
* @{
*/
/**
* @brief Timer prescaler values
*/
typedef enum {
TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV_BY_1, ///< Divide input clock by 1
TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV_BY_2, ///< Divide input clock by 2
TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV_BY_4, ///< Divide input clock by 4
TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV_BY_8, ///< Divide input clock by 8
TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV_BY_16, ///< Divide input clock by 16
TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32
TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64
TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128
TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256, ///< Divide input clock by 256
TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512, ///< Divide input clock by 512
TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024, ///< Divide input clock by 1024
TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048, ///< Divide input clock by 2048
TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096, ///< Divide input clock by 4096
TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 ///< Divide input clock by 8192
} mxc_tmr_pres_t;
/**
* @brief Timer modes
*/
typedef enum {
TMR_MODE_ONESHOT = MXC_S_TMR_CN_TMODE_ONE_SHOT, ///< Timer Mode ONESHOT
TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, ///< Timer Mode CONTINUOUS
TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, ///< Timer Mode COUNTER
TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, ///< Timer Mode PWM
TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, ///< Timer Mode CAPTURE
TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, ///< Timer Mode COMPARE
TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, ///< Timer Mode GATED
TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CN_TMODE_CAPCOMP ///< Timer Mode CAPTURECOMPARE
} mxc_tmr_mode_t;
/**
* @brief Timer bit mode
*
*/
typedef enum {
TMR_BIT_MODE_32, ///< Timer Mode 32 bit
TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit
TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit
} mxc_tmr_bit_mode_t;
/**
* @brief Timer units of time enumeration
*/
typedef enum {
TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator
TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator
TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator
TMR_UNIT_SEC, ///< Second Unit Indicator
} mxc_tmr_unit_t;
/**
* @brief Clock settings
* @note 8M and 32M clocks can be used for Timers 0,1,2 and 3
* 32K and 80K clocks can only be used for Timers 4 and 5
*/
typedef enum {
MXC_TMR_HFIO_CLK, ///< HFIO Clock
MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock
MXC_TMR_EXT_CLK, ///< External Clock
} mxc_tmr_clock_t;
/**
* @brief Timer Configuration
*/
typedef struct {
mxc_tmr_pres_t pres; ///< Desired timer prescaler
mxc_tmr_mode_t mode; ///< Desired timer mode
mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits
mxc_tmr_clock_t clock; ///< Desired clock source
uint32_t cmp_cnt; ///< Compare register value in timer ticks
unsigned pol; ///< Polarity (0 or 1)
} mxc_tmr_cfg_t;
/* **** Definitions **** */
typedef void (*mxc_tmr_complete_t) (int error);
/* **** Function Prototypes **** */
/**
* @brief Initialize timer module clock.
* @param tmr Pointer to timer module to initialize.
* @param cfg System configuration object
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg);
/**
* @brief Shutdown timer module clock.
* @param tmr Pointer to timer module to initialize.
*/
void MXC_TMR_Shutdown (mxc_tmr_regs_t *tmr);
/**
* @brief Start the timer counting.
* @param tmr Pointer to timer module to initialize.
*/
void MXC_TMR_Start (mxc_tmr_regs_t* tmr);
/**
* @brief Stop the timer.
* @param tmr Pointer to timer module to initialize.
*/
void MXC_TMR_Stop (mxc_tmr_regs_t* tmr);
/**
* @brief Set the value of the first transition in PWM mode
* @param tmr Pointer to timer module to initialize.
* @param pwm New pwm count.
* @note Will block until safe to change the period count.
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TMR_SetPWM (mxc_tmr_regs_t* tmr, uint32_t pwm);
/**
* @brief Get the timer compare count.
* @param tmr Pointer to timer module to initialize.
* @return Returns the current compare count.
*/
uint32_t MXC_TMR_GetCompare (mxc_tmr_regs_t* tmr);
/**
* @brief Get the timer capture count.
* @param tmr Pointer to timer module to initialize.
* @return Returns the most recent capture count.
*/
uint32_t MXC_TMR_GetCapture (mxc_tmr_regs_t* tmr);
/**
* @brief Get the timer count.
* @param tmr Pointer to timer module to initialize.
* @return Returns the current count.
*/
uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr);
/**
* @brief Calculate count for required frequency.
* @param tmr Timer
* @param clock Clock source.
* @param prescalar prescalar
* @param frequency required frequency.
* @return Returns the period count.
*/
uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency);
/**
* @brief Clear the timer interrupt.
* @param tmr Pointer to timer module to initialize.
*/
void MXC_TMR_ClearFlags (mxc_tmr_regs_t* tmr);
/**
* @brief Get the timer interrupt status.
* @param tmr Pointer to timer module to initialize.
* @return Returns the interrupt status. 1 if interrupt has occured.
*/
uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr);
/**
* @brief enable interupt
*
* @param tmr The timer
*/
void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr);
/**
* @brief disable interupt
*
* @param tmr The timer
*/
void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr);
/**
* @brief Set the timer compare count.
* @param tmr Pointer to timer module to initialize.
* @param cmp_cnt New compare count.
* @note In PWM Mode use this to set the value of the second transition.
*/
void MXC_TMR_SetCompare (mxc_tmr_regs_t *tmr, uint32_t cmp_cnt);
/**
* @brief Set the timer count.
* @param tmr Pointer to timer module to initialize.
* @param cnt New count.
*/
void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt);
/**
* @brief Dealay for a set periord of time measured in microseconds
*
* @param tmr The timer
* @param us microseconds to delay for
*/
void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
/**
* @brief Start a timer that will time out after a certain number of microseconds
* @note This uses the 32-it Timer
*
* @param tmr The timer
* @param us microseconds to time out after
*/
void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
/**
* @brief Check on time out timer
*
* @param tmr The timer
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TMR_TO_Check (mxc_tmr_regs_t *tmr);
/**
* @brief Stop the Timeout timer
*
* @param tmr The timer
*/
void MXC_TMR_TO_Stop (mxc_tmr_regs_t *tmr);
/**
* @brief Clear timeout timer back to zero
*
* @param tmr The timer
*/
void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr);
/**
* @brief Get elapsed time of timeout timer
*
* @param tmr The timer
*
* @return Time that has elapsed in timeout timer
*/
unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr);
/**
* @brief Amount of time remaining until timeour
*
* @param tmr The timer
*
* @return Time that is left until timeout
*/
unsigned int MXC_TMR_TO_Remaining (mxc_tmr_regs_t *tmr);
/**
* @brief Start stopwatch
*
* @param tmr The timer
*/
void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr);
/**
* @brief Stopwatch stop
*
* @param tmr The timer
*
* @return the time when the stopwatch is stopped.
*/
unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr);
/**
* @brief Get time from timer
*
* @param tmr The timer
* @param ticks The ticks
* @param time The time
* @param units The units
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);
/**@} end of group tmr */
#ifdef __cplusplus
}
#endif
#endif /* _TMR_H_ */

690
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h Normal file
View File

@ -0,0 +1,690 @@
/**
* @file uart.h
* @brief (UART) communications driver.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_UART_H_
#define _MXC_UART_H_
/***** Definitions *****/
#include "uart_regs.h"
#include "mxc_sys.h"
#include "mxc_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup uart UART
* @ingroup periphlibs
* @{
*/
typedef struct _mxc_uart_req_t mxc_uart_req_t;
/**
* @brief The list of UART stop bit lengths supported
*
*/
typedef enum {
MXC_UART_STOP_1, ///< UART Stop 1 clock cycle
MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters)
} mxc_uart_stop_t;
/**
* @brief The list of UART Parity options supported
*
*/
typedef enum {
MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled
MXC_UART_PARITY_EVEN, ///< UART Parity Even
MXC_UART_PARITY_ODD, ///< UART Parity Odd
MXC_UART_PARITY_MARK, ///< UART Parity Mark
MXC_UART_PARITY_SPACE, ///< UART Parity Space
MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based
MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based
MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based
MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based
MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based
MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based
MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based
MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based
} mxc_uart_parity_t;
/**
* @brief The list of UART flow control options supported
*
*/
typedef enum {
MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled
MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low
MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High
} mxc_uart_flow_t;
/**
* @brief The callback routine used to indicate the transaction has terminated.
*
* @param req The details of the transaction.
* @param result See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*mxc_uart_complete_cb_t) (mxc_uart_req_t* req, int result);
/**
* @brief The callback routine used to indicate the transaction has terminated.
*
* @param req The details of the transaction.
* @param num The number of characters actually copied
* @param result See \ref MXC_Error_Codes for the list of error codes.
*/
typedef void (*mxc_uart_dma_complete_cb_t) (mxc_uart_req_t* req, int num, int result);
/**
* @brief The information required to perform a complete UART transaction
*
* @note This structure is used by blocking, async, and DMA based transactions.
*/
struct _mxc_uart_req_t {
mxc_uart_regs_t* uart; ///<Point to UART registers
uint8_t *txData; ///< Buffer containing transmit data. For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint8_t *rxData; ///< Buffer to store received data For character sizes
///< < 8 bits, pad the MSB of each byte with zeros. For
///< character sizes > 8 bits, use two bytes per character
///< and pad the MSB of the upper byte with zeros
uint32_t txLen; ///< Number of bytes to be sent from txData
uint32_t rxLen; ///< Number of bytes to be stored in rxData
uint32_t txCnt; ///< Number of bytes actually transmitted from txData
uint32_t rxCnt; ///< Number of bytes stored in rxData
mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete
};
/***** Function Prototypes *****/
/* ************************************************************************* */
/* Control/Configuration functions */
/* ************************************************************************* */
/**
* @brief Initialize and enable UART peripheral.
*
* This function initializes everything necessary to call a UART transaction function.
* Some parameters are set to defaults as follows:
* UART Data Size - 8 bits
* UART Stop Bits - 1 bit
* UART Parity - None
* UART Flow Control - None
* UART Clock - 7.37MHz Clock (for baud > 7372800, PCLK is used)
*
* These parameters can be modified after initialization using low level functions
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param baud The requested clock frequency. The actual clock frequency
* will be returned by the function if successful.
* @param map Selects which pin map to use.
*
* @return If successful, the actual clock frequency is returned. Otherwise, see
* \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map);
/**
* @brief Disable and shutdown UART peripheral.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Shutdown (mxc_uart_regs_t* uart);
/**
* @brief Checks if the given UART bus can be placed in sleep more.
*
* @note This functions checks to see if there are any on-going UART transactions in
* progress. If there are transactions in progress, the application should
* wait until the UART bus is free before entering a low-power state.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart);
/**
* @brief Set the frequency of the UART interface.
*
*
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param baud The desired baud rate
*
* @return Negative if error, otherwise actual speed set. See \ref
* MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud);
/**
* @brief Get the frequency of the UART interface.
*
* @note This function is applicable in Master mode only
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The UART baud rate
*/
int MXC_UART_GetFrequency (mxc_uart_regs_t* uart);
/**
* @brief Sets the number of bits per character
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param dataSize The number of bits per character (5-8 bits/character are valid)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize);
/**
* @brief Sets the number of stop bits sent at the end of a character
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param stopBits The number of stop bits used
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits);
/**
* @brief Sets the type of parity generation used
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param parity see \ref mxc_uart_parity_t UART Parity Types for details
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity);
/**
* @brief Sets the flow control used
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param flowCtrl see \ref mxc_uart_flow_t UART Flow Control Types for details
* @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold);
/**
* @brief Sets the clock source for the baud rate generator
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param usePCLK Non-zero values will use the PCLK as the bit clock instead
* of the default 7.37MHz clock source. The baud rate generator
* will automatically be reconfigured to the closest possible
* baud rate.
*
* @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes
* for a list of return codes.
*/
int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK);
/**
* @brief Enables or Disables the built-in null modem
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param nullModem Non-zero values will enable the null modem function,
* which swaps TXD/RXD and also swaps RTS/CTS, if used.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem);
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
/**
* @brief Transmits a Break Frame (all bits 0)
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SendBreak (mxc_uart_regs_t* uart);
/**
* @brief Checks the UART Peripheral for an ongoing transmission
*
* @note This function is applicable in Master mode only
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_GetActive (mxc_uart_regs_t* uart);
/**
* @brief Aborts an ongoing UART Transmission
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart);
/**
* @brief Reads the next available character. This function will block until a character
* is available or a UART error occurs.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart);
/**
* @brief Writes a character on the UART. This function will block until the character
* has been placed in the TX FIFO or a UART error occurs.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param character The character to write
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character);
/**
* @brief Reads the next available character. If no character is available, this function
* will return an error.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart);
/**
* @brief Writes a character on the UART. If the character cannot be written because the
* transmit FIFO is currently full, this function returns an error.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param character The character to write
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character);
/**
* @brief Reads the next available character
* @note This function blocks until len characters are received
* See MXC_UART_TransactionAsync() for a non-blocking version
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param buffer Buffer to store data in
* @param len Number of characters
*
* @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len);
/**
* @brief Writes a byte on the UART
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param byte The buffer of characters to write
* @param len The number of characters to write
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len);
/**
* @brief Unloads bytes from the receive FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
*
* @return The number of bytes actually read.
*/
unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
/**
* @brief Unloads bytes from the receive FIFO user DMA for longer reads.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer to read the data into.
* @param len The number of bytes to read.
* @param callback The function to call when the read is complete
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the number of bytes currently available in the receive FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The number of bytes available.
*/
unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart);
/**
* @brief Loads bytes into the transmit FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
*
* @return The number of bytes actually written.
*/
unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len);
/**
* @brief Loads bytes into the transmit FIFO using DMA for longer writes
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param bytes The buffer containing the bytes to write
* @param len The number of bytes to write.
* @param callback The function to call when the write is complete
*
* @return See \ref MXC_Error_Codes for a list of return values
*/
int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes,
unsigned int len, mxc_uart_dma_complete_cb_t callback);
/**
* @brief Get the amount of free space available in the transmit FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The number of bytes available.
*/
unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart);
/**
* @brief Removes and discards all bytes currently in the receive FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart);
/**
* @brief Removes and discards all bytes currently in the transmit FIFO.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart);
/**
* @brief Set the receive threshold level.
*
* @note RX FIFO Receive threshold. Smaller values will cause
* interrupts to occur more often, but reduce the possibility
* of losing data because of a FIFO overflow. Larger values
* will reduce the time required by the ISR, but increase the
* possibility of data loss. Passing an invalid value will
* cause the driver to use the value already set in the
* appropriate register.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
/**
* @brief Get the current receive threshold level.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The receive threshold value (in bytes).
*/
unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart);
/**
* @brief Set the transmit threshold level.
*
* @note TX FIFO threshold. Smaller values will cause interrupts
* to occur more often, but reduce the possibility of terminating
* a transaction early in master mode, or transmitting invalid data
* in slave mode. Larger values will reduce the time required by
* the ISR, but increase the possibility errors occurring. Passing
* an invalid value will cause the driver to use the value already
* set in the appropriate register.
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param numBytes The threshold level to set. This value must be
* between 0 and 8 inclusive.
*
* @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
*/
int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes);
/**
* @brief Get the current transmit threshold level.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The transmit threshold value (in bytes).
*/
unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart);
/**
* @brief Gets the interrupt flags that are currently set
*
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The interrupt flags
*/
unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart);
/**
* @brief Clears the interrupt flags that are currently set
*
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param flags mask of flags to clear
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags);
/**
* @brief Enables specific interrupts
*
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param mask The interrupts to be enabled
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask);
/**
* @brief Disables specific interrupts
*
* @note These functions should not be used while using non-blocking Transaction Level
* functions (Async or DMA)
*
* @param uart Pointer to UART registers (selects the UART block used.)
* @param mask The interrupts to be disabled
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask);
/**
* @brief Gets the status flags that are currently set
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return The status flags
*/
unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart);
int MXC_UART_Busy(mxc_uart_regs_t* uart);
/* ************************************************************************* */
/* Transaction level functions */
/* ************************************************************************* */
/**
* @brief Performs a blocking UART transaction.
*
* @note Performs a blocking UART transaction as follows.
* If tx_len is non-zero, transmit TX data
* Once tx_len has been sent, if rx_len is non-zero, receive data
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_Transaction (mxc_uart_req_t* req);
/**
* @brief Setup an interrupt-driven UART transaction
*
* @note The TX FIFO will be filled with txData if necessary
* Relevant interrupts will be enabled
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_TransactionAsync (mxc_uart_req_t* req);
/**
* @brief Setup a DMA driven UART transaction
*
* @note The TX FIFO will be filled with txData if necessary
* Relevant interrupts will be enabled.
* The DMA channel indicated by the request will be set up to load/unload the FIFOs
* with as few interrupt-based events as possible. The channel will be reset and
* returned to the system at the end of the transaction.
*
* @param req Pointer to details of the transaction
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_TransactionDMA (mxc_uart_req_t* req);
/**
* @brief The processing function for DMA transactions.
*
* When using the DMA functions, the application must call this
* function periodically. This can be done from within the DMA Interrupt Handler.
*
* @param ch DMA channel
* @param error Error status
*/
void MXC_UART_DMACallback (int ch, int error);
/**
* @brief Async callback
*
* @param uart The uart
* @param[in] retVal The ret value
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal);
/**
* @brief stop any async callbacks
*
* @param uart The uart
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AsyncStop (mxc_uart_regs_t* uart);
/**
* @brief Abort any asynchronous requests in progress.
*
* @note Abort any asynchronous requests in progress. Any callbacks associated with
* the active transaction will be executed to indicate when the transaction
* has been terminated.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AbortAsync (mxc_uart_regs_t* uart);
/**
* @brief The processing function for asynchronous transactions.
*
* @note When using the asynchronous functions, the application must call this
* function periodically. This can be done from within the UART interrupt
* handler or periodically by the application if UART interrupts are disabled.
*
* @param uart Pointer to UART registers (selects the UART block used.)
*
* @return See \ref MXC_Error_Codes for the list of error return codes.
*/
int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart);
/**@} end of group uart */
#ifdef __cplusplus
}
#endif
#endif /* _MXC_UART_H_ */

185
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h Normal file
View File

@ -0,0 +1,185 @@
/**
* @file wdt.h
* @brief Watchdog timer (WDT) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _WDT_H_
#define _WDT_H_
/* **** Includes **** */
#include <stdint.h>
#include "mxc_device.h"
#include "wdt_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup wdt Watchdog Timer (WDT)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/** @brief Watchdog period enumeration.
Used to configure the period of the watchdog interrupt */
typedef enum {
MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, ///< Period 2^31
MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, ///< Period 2^30
MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, ///< Period 2^29
MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, ///< Period 2^28
MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, ///< Period 2^27
MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, ///< Period 2^26
MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, ///< Period 2^25
MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, ///< Period 2^24
MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, ///< Period 2^23
MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, ///< Period 2^22
MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, ///< Period 2^21
MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, ///< Period 2^20
MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, ///< Period 2^19
MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, ///< Period 2^18
MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, ///< Period 2^17
MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, ///< Period 2^16
} mxc_wdt_period_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize the Watchdog Timer
* @param wdt Pointer to the watchdog registers
* @return See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_WDT_Init (mxc_wdt_regs_t* wdt);
/**
* @brief Shutdown the Watchdog Timer
* @param wdt Pointer to the watchdog registers
* @return See \ref MXC_Error_Codes for the list of error codes.
*/
int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt);
/**
* @brief Set the period of the watchdog interrupt.
* @param wdt Pointer to watchdog registers.
* @param period Enumeration of the desired watchdog period.
*/
void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period);
/**
* @brief Set the period of the watchdog reset.
* @param wdt Pointer to watchdog registers.
* @param period Enumeration of the desired watchdog period.
*/
void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period);
/**
* @brief Enable the watchdog timer.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_Enable (mxc_wdt_regs_t* wdt);
/**
* @brief Disable the watchdog timer.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_Disable (mxc_wdt_regs_t* wdt);
/**
* @brief Enable the watchdog interrupt.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt);
/**
* @brief Enable the watchdog reset.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt);
/**
* @brief Enable the watchdog interrupt.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt);
/**
* @brief Enable the watchdog reset.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt);
/**
* @brief Reset the watchdog timer.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt);
/**
* @brief Get the status of the reset flag.
* @param wdt Pointer to watchdog registers.
* @returns 1 if the previous reset was caused by the watchdog, 0 otherwise.
*/
int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt);
/**
* @brief Clears the reset flag.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt);
/**
* @brief Get the status of the interrupt flag.
* @param wdt Pointer to watchdog registers.
* @returns 1 if the interrupt is pending, 0 otherwise.
*/
int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt);
/**
* @brief Clears the interrupt flag.
* @param wdt Pointer to watchdog registers.
*/
void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
/**@} end of group wdt */
#ifdef __cplusplus
}
#endif
#endif /* _WDT_H_ */

171
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c Normal file
View File

@ -0,0 +1,171 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/****** Includes *******/
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "dma.h"
#include "dma_reva.h"
#include "dma_regs.h"
/***** Definitions *****/
/******* Globals *******/
/****** Functions ******/
int MXC_DMA_Init(void)
{
if(!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA);
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA);
}
return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t*) MXC_DMA);
}
int MXC_DMA_AcquireChannel(void)
{
return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t*) MXC_DMA);
}
int MXC_DMA_ReleaseChannel(int ch)
{
return MXC_DMA_RevA_ReleaseChannel(ch);
}
int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
{
return MXC_DMA_RevA_ConfigChannel(config, srcdst);
}
int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
{
return MXC_DMA_RevA_AdvConfigChannel(advConfig);
}
int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst)
{
return MXC_DMA_RevA_SetSrcDst(srcdst);
}
int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst)
{
return MXC_DMA_RevA_GetSrcDst(srcdst);
}
int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdst)
{
return MXC_DMA_RevA_SetSrcReload(srcdst);
}
int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdst)
{
return MXC_DMA_RevA_GetSrcReload(srcdst);
}
int MXC_DMA_SetCallback(int ch, void(*callback)(int, int))
{
return MXC_DMA_RevA_SetCallback(ch, callback);
}
int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
{
return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz);
}
int MXC_DMA_ChannelEnableInt(int ch, int flags)
{
return MXC_DMA_RevA_ChannelEnableInt(ch, flags);
}
int MXC_DMA_ChannelDisableInt(int ch, int flags)
{
return MXC_DMA_RevA_ChannelDisableInt(ch, flags);
}
int MXC_DMA_ChannelGetFlags(int ch)
{
return MXC_DMA_RevA_ChannelGetFlags(ch);
}
int MXC_DMA_ChannelClearFlags(int ch, int flags)
{
return MXC_DMA_RevA_ChannelClearFlags(ch, flags);
}
int MXC_DMA_EnableInt(int ch)
{
return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch);
}
int MXC_DMA_DisableInt(int ch)
{
return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch);
}
int MXC_DMA_Start(int ch)
{
return MXC_DMA_RevA_Start(ch);
}
int MXC_DMA_Stop(int ch)
{
return MXC_DMA_RevA_Stop(ch);
}
mxc_dma_ch_regs_t* MXC_DMA_GetCHRegs(int ch)
{
return MXC_DMA_RevA_GetCHRegs(ch);
}
void MXC_DMA_Handler(void)
{
MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t*) MXC_DMA);
}
int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
{
return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t*) MXC_DMA, dest, src, len, callback);
}
int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
{
return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t*) MXC_DMA, config, firstSrcDst, callback);
}

585
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c Normal file
View File

@ -0,0 +1,585 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifdef __CC_ARM // Keil
#pragma diag_suppress 68 // integer conversion resulted in a change of sign
#endif
/****** Includes *******/
#include <stddef.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "dma.h"
#include "dma_reva.h"
#include "dma_reva_regs.h"
/***** Definitions *****/
#define CHECK_HANDLE(x)((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid))
typedef struct {
void* userCallback; // user given callback
void* dest; // memcpy destination
} mxc_dma_highlevel_t;
typedef struct {
unsigned int valid; // Flag to invalidate this resource
unsigned int instance; // Hardware instance of this DMA controller
unsigned int id; // Channel ID, which matches the index into the underlying hardware
mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel
void(*cb)(int, int); // Pointer to a callback function type
} mxc_dma_channel_t;
/******* Globals *******/
static unsigned int dma_initialized[MXC_DMA_INSTANCES] = {0};
static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS];
static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS];
#if USE_LOCK_IN_DRIVERS
static uint32_t dma_lock;
#endif
/****** Functions ******/
static void memcpy_callback(int ch, int error);
static void transfer_callback(int ch, int error);
int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma)
{
int i, numCh, offset;
#if TARGET_NUM == 32665
numCh = MXC_DMA_CH_OFFSET;
offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
#else
numCh = MXC_DMA_CHANNELS;
offset = 0;
#endif
if(dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) {
return E_BAD_STATE;
}
#ifndef __riscv
/* Initialize mutex */
MXC_FreeLock(&dma_lock);
if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY;
}
#endif
/* Ensure all channels are disabled at start, clear flags, init handles */
dma->inten = 0;
for(i = offset; i < (offset + numCh); i++) {
dma_resource[i].valid = 0;
dma_resource[i].instance = 0;
dma_resource[i].id = i;
dma_resource[i].regs = (mxc_dma_reva_ch_regs_t*) &(dma->ch[(i % numCh)]);
dma_resource[i].regs->ctrl = 0;
dma_resource[i].regs->status = dma_resource[i].regs->status;
dma_resource[i].cb = NULL;
}
dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]++;
#ifndef __riscv
MXC_FreeLock(&dma_lock);
#endif
return E_NO_ERROR;
}
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma)
{
int i, channel, numCh, offset;
/* Check for initialization */
if(!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) {
return E_BAD_STATE;
}
#if TARGET_NUM == 32665
numCh = MXC_DMA_CH_OFFSET;
offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
#else
numCh = MXC_DMA_CHANNELS;
offset = 0;
#endif
#ifndef __riscv
/* If DMA is locked return busy */
if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY;
}
#endif
/* Default is no channel available */
channel = E_NONE_AVAIL;
for(i = offset; i < (offset + numCh); i++) {
if(!dma_resource[i].valid) {
/* Found one */
channel = i;
dma_resource[i].valid = 1;
dma_resource[i].regs->ctrl = 0;
dma_resource[i].regs->cntrld = 0; /* Used by DMA_Start() to conditionally set RLDEN */
break;
}
}
#ifndef __riscv
MXC_FreeLock(&dma_lock);
#endif
return channel;
}
int MXC_DMA_RevA_ReleaseChannel(int ch)
{
if(CHECK_HANDLE(ch)) {
if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY;
}
dma_resource[ch].valid = 0;
dma_resource[ch].regs->ctrl = 0;
dma_resource[ch].regs->status = dma_resource[ch].regs->status;
MXC_FreeLock(&dma_lock);
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
{
if(CHECK_HANDLE(config.ch)) {
/* Designed to be safe, not speedy. Should not be called often */
dma_resource[config.ch].regs->ctrl =
((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) |
(config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) |
config.reqsel |
(config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) |
(config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
}
else {
return E_BAD_PARAM;
}
return MXC_DMA_RevA_SetSrcDst(srcdst);
}
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
{
if(CHECK_HANDLE(advConfig.ch) &&(advConfig.burst_size > 0)) {
dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here
/* Designed to be safe, not speedy. Should not be called often */
dma_resource[advConfig.ch].regs->ctrl |=
((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) |
advConfig.prio | advConfig.tosel | advConfig.pssel |
(((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE));
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst)
{
if(CHECK_HANDLE(srcdst.ch)) {
dma_resource[srcdst.ch].regs->src = (unsigned int) srcdst.source;
dma_resource[srcdst.ch].regs->dst = (unsigned int) srcdst.dest;
dma_resource[srcdst.ch].regs->cnt = srcdst.len;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t* srcdst)
{
if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void*) dma_resource[srcdst->ch].regs->src;
srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dst;
srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
{
if(CHECK_HANDLE(srcdst.ch)) {
dma_resource[srcdst.ch].regs->srcrld = (unsigned int) srcdst.source;
dma_resource[srcdst.ch].regs->dstrld = (unsigned int) srcdst.dest;
if(dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) {
/* If channel is already running, set RLDEN to enable next reload */
dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len;
}
else {
/* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
dma_resource[srcdst.ch].regs->cntrld = srcdst.len;
}
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t* srcdst)
{
if (CHECK_HANDLE(srcdst->ch)) {
srcdst->source = (void*) dma_resource[srcdst->ch].regs->srcrld;
srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dstrld;
srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int))
{
if(CHECK_HANDLE(ch)) {
/* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */
dma_resource[ch].cb = callback;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
{
if(CHECK_HANDLE(ch)) {
if(chdis){
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE);
}
if(ctz){
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE);
}
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
{
return E_NOT_SUPPORTED;
}
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
{
if(CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags)
{
if(CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch)
{
if(CHECK_HANDLE(ch)) {
#if TARGET_NUM == 32665
ch %= MXC_DMA_CH_OFFSET;
#endif
dma->inten |= (1 << ch);
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch)
{
if(CHECK_HANDLE(ch)) {
#if TARGET_NUM == 32665
ch %= MXC_DMA_CH_OFFSET;
#endif
dma->inten &= ~(1 << ch);
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_ChannelGetFlags(int ch)
{
if(CHECK_HANDLE(ch)) {
return dma_resource[ch].regs->status;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags)
{
if(CHECK_HANDLE(ch)) {
dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_Start(int ch)
{
if(CHECK_HANDLE(ch)) {
MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch));
if(dma_resource[ch].regs->cntrld) {
dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN);
}
else {
dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN;
}
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_DMA_RevA_Stop(int ch)
{
if(CHECK_HANDLE(ch)) {
dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch)
{
if(CHECK_HANDLE(ch)) {
return(mxc_dma_ch_regs_t*) dma_resource[ch].regs;
}
else {
return NULL;
}
}
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
{
int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES;
int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
/* Do callback, if enabled */
for(int i = offset; i < (offset + numCh); i++) {
if(CHECK_HANDLE(i)) {
if(dma->intfl &(0x1 << (i % numCh))) {
if(dma_resource[i].cb != NULL) {
dma_resource[i].cb(i, E_NO_ERROR);
}
MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i));
break;
}
}
}
}
void memcpy_callback(int ch, int error)
{
mxc_dma_complete_cb_t callback;
callback = (mxc_dma_complete_cb_t) memcpy_resource[ch].userCallback;
if(error != E_NO_ERROR) {
callback(NULL);
}
callback(memcpy_resource[ch].dest);
callback = NULL;
MXC_DMA_ReleaseChannel(ch);
}
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
{
int retval;
mxc_dma_config_t config;
mxc_dma_srcdst_t transfer;
int channel;
#if TARGET_NUM == 32665
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma);
#else
channel = MXC_DMA_AcquireChannel();
#endif
if(memcpy_resource[channel].userCallback != NULL) {
// We acquired a channel we haven't cleared yet
MXC_DMA_ReleaseChannel(channel);
return E_UNKNOWN;
}
transfer.ch = channel;
transfer.source = src;
transfer.dest = dest;
transfer.len = len;
config.ch = channel;
config.reqsel = MXC_DMA_REQUEST_MEMTOMEM;
config.srcwd = MXC_DMA_WIDTH_WORD;
config.dstwd = MXC_DMA_WIDTH_WORD;
config.srcinc_en = 1;
config.dstinc_en = 1;
retval = MXC_DMA_ConfigChannel(config, transfer);
if(retval != E_NO_ERROR) {
return retval;
}
retval = MXC_DMA_EnableInt(channel);
if(retval != E_NO_ERROR) {
return retval;
}
retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
if(retval != E_NO_ERROR) {
return retval;
}
MXC_DMA_SetCallback(channel, memcpy_callback);
memcpy_resource[channel].userCallback = (void*) callback;
memcpy_resource[channel].dest = dest;
return MXC_DMA_Start(channel);
}
void transfer_callback(int ch, int error)
{
// Unimplemented
// Check for reason
// Call user callback for next transfer
// determine whether to load into the transfer slot or reload slot
// continue on or stop
while(1);
}
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
{
int retval, channel;
#if TARGET_NUM == 32665
channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma);
#else
channel = MXC_DMA_AcquireChannel();
#endif
if(memcpy_resource[channel].userCallback != NULL) {
// We acquired a channel we haven't cleared yet
MXC_DMA_ReleaseChannel(channel);
return E_UNKNOWN;
}
retval = MXC_DMA_ConfigChannel(config, firstSrcDst);
if(retval != E_NO_ERROR) {
return retval;
}
retval = MXC_DMA_EnableInt(channel);
if(retval != E_NO_ERROR) {
return retval;
}
retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
if(retval != E_NO_ERROR) {
return retval;
}
MXC_DMA_SetCallback(channel, transfer_callback);
memcpy_resource[channel].userCallback = (void*) callback;
return MXC_DMA_Start(channel);
}

65
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h Normal file
View File

@ -0,0 +1,65 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/****** Includes *******/
#include "dma_reva_regs.h"
#include <stdbool.h>
/***** Definitions *****/
/******* Globals *******/
/****** Functions ******/
int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma);
int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma);
int MXC_DMA_RevA_ReleaseChannel(int ch);
int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst);
int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst);
int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst);
int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst);
int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int));
int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags);
int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags);
int MXC_DMA_RevA_ChannelGetFlags(int ch);
int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags);
int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch);
int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch);
int MXC_DMA_RevA_Start(int ch);
int MXC_DMA_RevA_Stop(int ch);
mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch);
void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma);
int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);

532
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h Normal file
View File

@ -0,0 +1,532 @@
/**
* @file dma_regs.h
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _DMA_REVA_REGS_H_
#define _DMA_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup dma
* @defgroup dma_registers DMA_Registers
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @details DMA Controller Fully programmable, chaining capable DMA channels.
*/
/**
* @ingroup dma_registers
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x100:</tt> DMA CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x104:</tt> DMA STATUS Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t srcrld; /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
__IO uint32_t dstrld; /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
__IO uint32_t cntrld; /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
} mxc_dma_reva_ch_regs_t;
typedef struct {
__IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */
__I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */
__R uint32_t rsv_0x8_0xff[62];
__IO mxc_dma_reva_ch_regs_t ch[8]; /**< <tt>\b 0x100:</tt> DMA CH Register */
} mxc_dma_reva_regs_t;
/* Register offsets for module DMA */
/**
* @ingroup dma_registers
* @defgroup DMA_Register_Offsets Register Offsets
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
/**@} end of group dma_registers */
/**
* @ingroup dma_registers
* @defgroup DMA_INTEN DMA_INTEN
* @brief DMA Control Register.
* @{
*/
#define MXC_F_DMA_REVA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */
#define MXC_F_DMA_REVA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */
#define MXC_F_DMA_REVA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */
#define MXC_F_DMA_REVA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */
#define MXC_F_DMA_REVA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */
#define MXC_F_DMA_REVA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */
#define MXC_F_DMA_REVA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */
#define MXC_F_DMA_REVA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */
#define MXC_F_DMA_REVA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */
#define MXC_F_DMA_REVA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */
#define MXC_F_DMA_REVA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */
#define MXC_F_DMA_REVA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */
#define MXC_F_DMA_REVA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */
#define MXC_F_DMA_REVA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */
#define MXC_F_DMA_REVA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */
#define MXC_F_DMA_REVA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */
#define MXC_F_DMA_REVA_INTEN_CH8_POS 8 /**< INTEN_CH8 Position */
#define MXC_F_DMA_REVA_INTEN_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH8_POS)) /**< INTEN_CH8 Mask */
#define MXC_F_DMA_REVA_INTEN_CH9_POS 9 /**< INTEN_CH9 Position */
#define MXC_F_DMA_REVA_INTEN_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH9_POS)) /**< INTEN_CH9 Mask */
#define MXC_F_DMA_REVA_INTEN_CH10_POS 10 /**< INTEN_CH10 Position */
#define MXC_F_DMA_REVA_INTEN_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH10_POS)) /**< INTEN_CH10 Mask */
#define MXC_F_DMA_REVA_INTEN_CH11_POS 11 /**< INTEN_CH11 Position */
#define MXC_F_DMA_REVA_INTEN_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH11_POS)) /**< INTEN_CH11 Mask */
#define MXC_F_DMA_REVA_INTEN_CH12_POS 12 /**< INTEN_CH12 Position */
#define MXC_F_DMA_REVA_INTEN_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH12_POS)) /**< INTEN_CH12 Mask */
#define MXC_F_DMA_REVA_INTEN_CH13_POS 13 /**< INTEN_CH13 Position */
#define MXC_F_DMA_REVA_INTEN_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH13_POS)) /**< INTEN_CH13 Mask */
#define MXC_F_DMA_REVA_INTEN_CH14_POS 14 /**< INTEN_CH14 Position */
#define MXC_F_DMA_REVA_INTEN_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH14_POS)) /**< INTEN_CH14 Mask */
#define MXC_F_DMA_REVA_INTEN_CH15_POS 15 /**< INTEN_CH15 Position */
#define MXC_F_DMA_REVA_INTEN_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH15_POS)) /**< INTEN_CH15 Mask */
/**@} end of group DMA_INTEN_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_INTFL DMA_INTFL
* @brief DMA Interrupt Register.
* @{
*/
#define MXC_F_DMA_REVA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */
#define MXC_F_DMA_REVA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */
#define MXC_F_DMA_REVA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */
#define MXC_F_DMA_REVA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */
#define MXC_F_DMA_REVA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */
#define MXC_F_DMA_REVA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */
#define MXC_F_DMA_REVA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */
#define MXC_F_DMA_REVA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */
#define MXC_F_DMA_REVA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */
#define MXC_F_DMA_REVA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */
#define MXC_F_DMA_REVA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */
#define MXC_F_DMA_REVA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */
#define MXC_F_DMA_REVA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */
#define MXC_F_DMA_REVA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */
#define MXC_F_DMA_REVA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */
#define MXC_F_DMA_REVA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */
#define MXC_F_DMA_REVA_INTFL_CH8_POS 8 /**< INTFL_CH8 Position */
#define MXC_F_DMA_REVA_INTFL_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH8_POS)) /**< INTFL_CH8 Mask */
#define MXC_F_DMA_REVA_INTFL_CH9_POS 9 /**< INTFL_CH9 Position */
#define MXC_F_DMA_REVA_INTFL_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH9_POS)) /**< INTFL_CH9 Mask */
#define MXC_F_DMA_REVA_INTFL_CH10_POS 10 /**< INTFL_CH10 Position */
#define MXC_F_DMA_REVA_INTFL_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH10_POS)) /**< INTFL_CH10 Mask */
#define MXC_F_DMA_REVA_INTFL_CH11_POS 11 /**< INTFL_CH11 Position */
#define MXC_F_DMA_REVA_INTFL_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH11_POS)) /**< INTFL_CH11 Mask */
#define MXC_F_DMA_REVA_INTFL_CH12_POS 12 /**< INTFL_CH12 Position */
#define MXC_F_DMA_REVA_INTFL_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH12_POS)) /**< INTFL_CH12 Mask */
#define MXC_F_DMA_REVA_INTFL_CH13_POS 13 /**< INTFL_CH13 Position */
#define MXC_F_DMA_REVA_INTFL_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH13_POS)) /**< INTFL_CH13 Mask */
#define MXC_F_DMA_REVA_INTFL_CH14_POS 14 /**< INTFL_CH14 Position */
#define MXC_F_DMA_REVA_INTFL_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH14_POS)) /**< INTFL_CH14 Mask */
#define MXC_F_DMA_REVA_INTFL_CH15_POS 15 /**< INTFL_CH15 Position */
#define MXC_F_DMA_REVA_INTFL_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH15_POS)) /**< INTFL_CH15 Mask */
/**@} end of group DMA_INTFL_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CTRL DMA_CTRL
* @brief DMA Channel Control Register.
* @{
*/
#define MXC_F_DMA_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_DMA_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_DMA_REVA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */
#define MXC_F_DMA_REVA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */
#define MXC_F_DMA_REVA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */
#define MXC_F_DMA_REVA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */
#define MXC_V_DMA_REVA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */
#define MXC_S_DMA_REVA_CTRL_PRI_HIGH (MXC_V_DMA_REVA_CTRL_PRI_HIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */
#define MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */
#define MXC_S_DMA_REVA_CTRL_PRI_MEDHIGH (MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */
#define MXC_V_DMA_REVA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */
#define MXC_S_DMA_REVA_CTRL_PRI_MEDLOW (MXC_V_DMA_REVA_CTRL_PRI_MEDLOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */
#define MXC_V_DMA_REVA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */
#define MXC_S_DMA_REVA_CTRL_PRI_LOW (MXC_V_DMA_REVA_CTRL_PRI_LOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */
#define MXC_F_DMA_REVA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */
#define MXC_F_DMA_REVA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_REVA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */
#define MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_UART0RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_UART1RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_ADC (MXC_V_DMA_REVA_CTRL_REQUEST_ADC << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_UART2RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX ((uint32_t)0x10UL) /**< CTRL_REQUEST_SPI_MSS0RX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0RX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1 ((uint32_t)0x11UL) /**< CTRL_REQUEST_USBRXEP1 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP1 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP1 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2 ((uint32_t)0x12UL) /**< CTRL_REQUEST_USBRXEP2 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP2 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP2 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3 ((uint32_t)0x13UL) /**< CTRL_REQUEST_USBRXEP3 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP3 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP3 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4 ((uint32_t)0x14UL) /**< CTRL_REQUEST_USBRXEP4 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP4 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP4 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5 ((uint32_t)0x15UL) /**< CTRL_REQUEST_USBRXEP5 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP5 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP5 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6 ((uint32_t)0x16UL) /**< CTRL_REQUEST_USBRXEP6 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP6 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP6 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7 ((uint32_t)0x17UL) /**< CTRL_REQUEST_USBRXEP7 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP7 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP7 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8 ((uint32_t)0x18UL) /**< CTRL_REQUEST_USBRXEP8 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP8 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP8 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9 ((uint32_t)0x19UL) /**< CTRL_REQUEST_USBRXEP9 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP9 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP9 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10 ((uint32_t)0x1AUL) /**< CTRL_REQUEST_USBRXEP10 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP10 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP10 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11 ((uint32_t)0x1BUL) /**< CTRL_REQUEST_USBRXEP11 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP11 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP11 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_UART0TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_UART1TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_UART2TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX ((uint32_t)0x30UL) /**< CTRL_REQUEST_SPI_MSS0TX Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0TX Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1 ((uint32_t)0x31UL) /**< CTRL_REQUEST_USBTXEP1 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP1 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP1 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2 ((uint32_t)0x32UL) /**< CTRL_REQUEST_USBTXEP2 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP2 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP2 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3 ((uint32_t)0x33UL) /**< CTRL_REQUEST_USBTXEP3 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP3 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP3 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4 ((uint32_t)0x34UL) /**< CTRL_REQUEST_USBTXEP4 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP4 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP4 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5 ((uint32_t)0x35UL) /**< CTRL_REQUEST_USBTXEP5 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP5 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP5 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6 ((uint32_t)0x36UL) /**< CTRL_REQUEST_USBTXEP6 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP6 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP6 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7 ((uint32_t)0x37UL) /**< CTRL_REQUEST_USBTXEP7 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP7 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP7 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8 ((uint32_t)0x38UL) /**< CTRL_REQUEST_USBTXEP8 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP8 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP8 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9 ((uint32_t)0x39UL) /**< CTRL_REQUEST_USBTXEP9 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP9 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP9 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10 ((uint32_t)0x3AUL) /**< CTRL_REQUEST_USBTXEP10 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP10 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP10 Setting */
#define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11 ((uint32_t)0x3BUL) /**< CTRL_REQUEST_USBTXEP11 Value */
#define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP11 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP11 Setting */
#define MXC_F_DMA_REVA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */
#define MXC_F_DMA_REVA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */
#define MXC_F_DMA_REVA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */
#define MXC_F_DMA_REVA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_REVA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO4 (MXC_V_DMA_REVA_CTRL_TO_PER_TO4 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO8 (MXC_V_DMA_REVA_CTRL_TO_PER_TO8 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO16 (MXC_V_DMA_REVA_CTRL_TO_PER_TO16 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO32 (MXC_V_DMA_REVA_CTRL_TO_PER_TO32 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO64 (MXC_V_DMA_REVA_CTRL_TO_PER_TO64 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO128 (MXC_V_DMA_REVA_CTRL_TO_PER_TO128 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO256 (MXC_V_DMA_REVA_CTRL_TO_PER_TO256 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */
#define MXC_S_DMA_REVA_CTRL_TO_PER_TO512 (MXC_V_DMA_REVA_CTRL_TO_PER_TO512 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */
#define MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */
#define MXC_F_DMA_REVA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */
#define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */
#define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */
#define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */
#define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */
#define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */
#define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */
#define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */
#define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */
#define MXC_F_DMA_REVA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */
#define MXC_F_DMA_REVA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */
#define MXC_V_DMA_REVA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */
#define MXC_S_DMA_REVA_CTRL_SRCWD_BYTE (MXC_V_DMA_REVA_CTRL_SRCWD_BYTE << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */
#define MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */
#define MXC_S_DMA_REVA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */
#define MXC_V_DMA_REVA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */
#define MXC_S_DMA_REVA_CTRL_SRCWD_WORD (MXC_V_DMA_REVA_CTRL_SRCWD_WORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */
#define MXC_F_DMA_REVA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */
#define MXC_F_DMA_REVA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */
#define MXC_F_DMA_REVA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */
#define MXC_F_DMA_REVA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */
#define MXC_V_DMA_REVA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */
#define MXC_S_DMA_REVA_CTRL_DSTWD_BYTE (MXC_V_DMA_REVA_CTRL_DSTWD_BYTE << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */
#define MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */
#define MXC_S_DMA_REVA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */
#define MXC_V_DMA_REVA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */
#define MXC_S_DMA_REVA_CTRL_DSTWD_WORD (MXC_V_DMA_REVA_CTRL_DSTWD_WORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */
#define MXC_F_DMA_REVA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */
#define MXC_F_DMA_REVA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */
#define MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */
#define MXC_F_DMA_REVA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */
#define MXC_F_DMA_REVA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */
#define MXC_F_DMA_REVA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */
#define MXC_F_DMA_REVA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */
#define MXC_F_DMA_REVA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */
/**@} end of group DMA_CTRL_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_STATUS DMA_STATUS
* @brief DMA Channel Status Register.
* @{
*/
#define MXC_F_DMA_REVA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */
#define MXC_F_DMA_REVA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
#define MXC_F_DMA_REVA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */
#define MXC_F_DMA_REVA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */
#define MXC_F_DMA_REVA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */
#define MXC_F_DMA_REVA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */
#define MXC_F_DMA_REVA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */
#define MXC_F_DMA_REVA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */
#define MXC_F_DMA_REVA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */
#define MXC_F_DMA_REVA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */
#define MXC_F_DMA_REVA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */
#define MXC_F_DMA_REVA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */
/**@} end of group DMA_STATUS_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRC DMA_SRC
* @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or
* 4, depending on the data width of each AHB cycle. For peripheral transfers, some
* or all of the actual address bits are fixed. If SRCINC=0, this register remains
* constant. In the case where a count-to-zero condition occurs while RLDEN=1, the
* register is reloaded with the contents of DMA_SRC_RLD.
* @{
*/
#define MXC_F_DMA_REVA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */
#define MXC_F_DMA_REVA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */
/**@} end of group DMA_SRC_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DST DMA_DST
* @brief Destination Device Address. For peripheral transfers, some or all of the actual
* address bits are fixed. If DSTINC=1, this register is incremented on every AHB
* write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the
* data width of each AHB cycle. In the case where a count-to-zero condition occurs
* while RLDEN=1, the register is reloaded with DMA_DST_RLD.
* @{
*/
#define MXC_F_DMA_REVA_DST_ADDR_POS 0 /**< DST_ADDR Position */
#define MXC_F_DMA_REVA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_DST_ADDR_POS)) /**< DST_ADDR Mask */
/**@} end of group DMA_DST_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNT DMA_CNT
* @brief DMA Counter. The user loads this register with the number of bytes to transfer.
* This counter decreases on every AHB cycle into the DMA FIFO. The decrement will
* be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter
* reaches 0, a count-to-zero condition is triggered.
* @{
*/
#define MXC_F_DMA_REVA_CNT_CNT_POS 0 /**< CNT_CNT Position */
#define MXC_F_DMA_REVA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNT_CNT_POS)) /**< CNT_CNT Mask */
/**@} end of group DMA_CNT_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRCRLD DMA_SRCRLD
* @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC
* upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_REVA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */
#define MXC_F_DMA_REVA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */
/**@} end of group DMA_SRCRLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DSTRLD DMA_DSTRLD
* @brief Destination Address Reload Value. The value of this register is loaded into
* DMA0_DST upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_REVA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */
#define MXC_F_DMA_REVA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */
/**@} end of group DMA_DSTRLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNTRLD DMA_CNTRLD
* @brief DMA Channel Count Reload Register.
* @{
*/
#define MXC_F_DMA_REVA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */
#define MXC_F_DMA_REVA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */
#define MXC_F_DMA_REVA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */
#define MXC_F_DMA_REVA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */
/**@} end of group DMA_CNTRLD_Register */
#ifdef __cplusplus
}
#endif
#endif /* _DMA_REVA_REGS_H_ */

170
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c Normal file
View File

@ -0,0 +1,170 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "stdlib.h"
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// Length is number of 32-bit words
int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data)
{
volatile uint32_t* ptr;
for (ptr = (uint32_t*) address; ptr < (((uint32_t*)(address)) + length); ptr++, data++) {
if (*ptr != *data) {
return E_BAD_STATE;
}
}
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
{
int err;
uint32_t bytes_written;
uint32_t current_data_32;
uint8_t* current_data = (uint8_t*) &current_data_32;
uint8_t* buffer8 = (uint8_t*)buffer;
// Align the address to a word boundary and read/write if we have to
if (address & 0x3) {
// Figure out how many bytes we have to write to round up the address
bytes_written = 4 - (address & 0x3);
// Save the data currently in the flash
memcpy(current_data, (void*)(address & (~0x3)), 4);
// Modify current_data to insert the data from buffer
memcpy(&current_data[4 - bytes_written], buffer8, bytes_written);
// Write the modified data
if ((err = MXC_FLC_Write32(address - (address % 4), current_data_32)) != E_NO_ERROR) {
return err;
}
address += bytes_written;
length -= bytes_written;
buffer8 += bytes_written;
}
// Align the address to a 4-word (128bit) boundary
while ((length >= 4) && ((address & 0xF) != 0)) {
memcpy(current_data, buffer8, 4);
if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
return err;
}
address += 4;
length -= 4;
buffer8 += 4;
}
if (length >= 16) {
uint32_t buff128[4];
while (length >= 16) {
memcpy(buff128, buffer8, 16);
if ((err = MXC_FLC_Write128(address, buff128)) != E_NO_ERROR) {
return err;
}
address += 16;
length -= 16;
buffer8 += 16;
}
}
while (length >= 4) {
memcpy(current_data, buffer8, 4);
if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
return err;
}
address += 4;
length -= 4;
buffer8 += 4;
}
if (length > 0) {
// Save the data currently in the flash
memcpy(current_data, (void*)(address), 4);
// Modify current_data to insert the data from buffer
memcpy(current_data, buffer8, length);
if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
return err;
}
}
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
void MXC_FLC_Com_Read(int address, void* buffer, int len)
{
memcpy(buffer, (void*) address, len);
}

72
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h Normal file
View File

@ -0,0 +1,72 @@
/**
* @file flc.h
* @brief Flash Controller driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup flc Flash Controller (FLC)
* @ingroup periphlibs
* @{
*/
/***** Definitions *****/
/***** Function Prototypes *****/
int MXC_FLC_Com_VerifyData (uint32_t address, uint32_t length, uint32_t * data);
int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer);
void MXC_FLC_Com_Read (int address, void* buffer, int len);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif

305
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c Normal file
View File

@ -0,0 +1,305 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_reva.h"
#include "flc_common.h"
//******************************************************************************
void MXC_FLC_ME11_Flash_Operation(void)
{
/* Flush all instruction caches */
MXC_GCR->scon |= MXC_F_GCR_SCON_ICC0_FLUSH;
/* Wait for flush to complete */
while(MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) {
}
}
//******************************************************************************
int MXC_FLC_ME11_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
{
// flash base start from 0x00000000
if ( addr < MXC_FLASH_MEM_SIZE ) {
*flc = MXC_FLC;
}
else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
*flc = MXC_FLC;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_ME11_GetPhysicalAddress(uint32_t addr, uint32_t *result)
{
// flash base start from 0x00000000
if ( addr < MXC_FLASH_MEM_SIZE ) {
*result = addr & (MXC_FLASH_MEM_SIZE-1);
}
else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
*result = (addr & (MXC_INFO_MEM_SIZE-1)) + MXC_FLASH_MEM_SIZE;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_Init()
{
return E_NO_ERROR;
}
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_Busy(void)
{
return MXC_FLC_RevA_Busy();
}
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_ME11_PageErase(uint32_t address)
{
int err;
uint32_t addr;
mxc_flc_regs_t *flc = NULL;
// Get FLC Instance
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err;
}
if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
return err;
}
err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*) flc, addr);
// Flush the cache
MXC_FLC_ME11_Flash_Operation();
return err;
}
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_ME11_Write128(uint32_t address, uint32_t *data)
{
int err;
mxc_flc_regs_t *flc = NULL;
uint32_t addr;
// Address checked if it is 128-bit aligned
if(address & 0xF) {
return E_BAD_PARAM;
}
// Get FLC Instance
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err;
}
if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
return err;
}
if((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*) flc, addr, data)) != E_NO_ERROR) {
return err;
}
// Flush the cache
MXC_FLC_ME11_Flash_Operation();
if((err= MXC_FLC_Com_VerifyData(address, 4, data)) !=E_NO_ERROR) {
return err;
}
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_ME11_Write32(uint32_t address, uint32_t data)
{
uint32_t addr, aligned;
int err;
mxc_flc_regs_t *flc = NULL;
// Address checked if it is byte addressable
if(address & 0x3) {
return E_BAD_PARAM;
}
// Align address to 128-bit word
aligned = address & 0xfffffff0;
// Get FLC Instance
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err;
}
if((err = MXC_FLC_ME11_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) {
return err;
}
return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*) flc, address, data, addr);
}
int MXC_FLC_ME11_MassErase(void)
{
int err;
mxc_flc_regs_t *flc;
flc = MXC_FLC;
err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*) flc);
if(err != E_NO_ERROR) {
return err;
}
MXC_FLC_ME11_Flash_Operation();
return E_NO_ERROR;
}
int MXC_FLC_ME11_UnlockInfoBlock(uint32_t address)
{
int err;
mxc_flc_regs_t *flc;
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err;
}
return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*) flc, address);
}
int MXC_FLC_ME11_LockInfoBlock(uint32_t address)
{
int err;
mxc_flc_regs_t *flc;
if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err;
}
return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*) flc, address);
}
/* ****************************************************************************** */
int MXC_FLC_MassErase(void)
{
return MXC_FLC_ME11_MassErase();
}
int MXC_FLC_PageErase(uint32_t address)
{
return MXC_FLC_ME11_PageErase(address);
}
int MXC_FLC_Write32(uint32_t address, uint32_t data)
{
return MXC_FLC_ME11_Write32(address, data);
}
int MXC_FLC_Write128(uint32_t address, uint32_t *data)
{
return MXC_FLC_ME11_Write128(address, data);
}
int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer)
{
return MXC_FLC_Com_Write(address, length, buffer);
}
void MXC_FLC_Read(int address, void* buffer, int len)
{
MXC_FLC_Com_Read(address, buffer, len);
}
int MXC_FLC_EnableInt(uint32_t flags)
{
return MXC_FLC_RevA_EnableInt(flags);
}
int MXC_FLC_DisableInt(uint32_t flags)
{
return MXC_FLC_RevA_DisableInt(flags);
}
int MXC_FLC_GetFlags(void)
{
return MXC_FLC_RevA_GetFlags();
}
int MXC_FLC_ClearFlags(uint32_t flags)
{
return MXC_FLC_RevA_ClearFlags(flags);
}
int MXC_FLC_UnlockInfoBlock(uint32_t address)
{
return MXC_FLC_ME11_UnlockInfoBlock(address);
}
int MXC_FLC_LockInfoBlock(uint32_t address)
{
return MXC_FLC_ME11_LockInfoBlock(address);
}

378
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c Normal file
View File

@ -0,0 +1,378 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc_reva.h"
#include "flc.h"
/**
* @ingroup flc
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
static int MXC_busy_flc(mxc_flc_reva_regs_t* flc)
{
return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc)
{
/* Check if the flash controller is busy */
if (MXC_busy_flc(flc)) {
return E_BUSY;
}
// Set flash clock divider to generate a 1MHz clock from the APB clock
flc->clkdiv = SystemCoreClock / 1000000;
/* Clear stale errors */
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
}
/* Unlock flash */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED;
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevA_Busy(void)
{
uint32_t flc_cn = 0;
int i;
mxc_flc_reva_regs_t *flc;
for (i = 0; i < MXC_FLC_INSTANCES; i++) {
flc = (mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC (i);
flc_cn = MXC_busy_flc (flc);
if (flc_cn != 0) {
break;
}
}
return flc_cn;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc)
{
int err;
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
return err;
}
/* Write mass erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
/* Issue mass erase command */
flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME;
/* Wait until flash operation is complete */
while (MXC_busy_flc(flc));
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
/* Check access violations */
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
return E_BAD_STATE;
}
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
{
int err;
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
return err;
}
/* Write page erase code */
flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
/* Issue page erase command */
flc->addr = addr;
flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE;
/* Wait until flash operation is complete */
while (MXC_FLC_Busy());
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
/* Check access violations */
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
return E_BAD_STATE;
}
return E_NO_ERROR;
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
{
int err, i = 0;
uint32_t byte;
volatile uint32_t* ptr;
uint32_t current_data[4] = {0, 0, 0, 0};
// Address checked if it is byte addressable
if (logicAddr & 0x3) {
return E_BAD_PARAM;
}
// Check if the location trying to be written has 1's in to be written to 0's
if ((* (uint32_t*) logicAddr & data) != data) {
return E_BAD_STATE;
}
// Get byte idx within 128-bit word
byte = (logicAddr & 0xf);
// Align address to 128-bit word
logicAddr = logicAddr & 0xfffffff0;
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
return err;
}
// Get current data stored in flash
for (ptr = (uint32_t*) logicAddr; ptr < (uint32_t*)(logicAddr + 16); ptr++, i++) {
current_data[i] = *ptr;
}
// write the data
flc->addr = physicalAddr;
if (byte < 4) {
current_data[0] = data;
}
else if (byte < 8) {
current_data[1] = data;
}
else if (byte < 12) {
current_data[2] = data;
}
else {
current_data[3] = data;
}
return MXC_FLC_Write128(logicAddr, current_data);
}
//******************************************************************************
#if IAR_PRAGMAS
#pragma section=".flashprog"
#else
__attribute__((section(".flashprog")))
#endif
// make sure to disable ICC with ICC_Disable(); before Running this function
int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data)
{
int err;
// Address checked if it is 128-bit aligned
if (addr & 0xF) {
return E_BAD_PARAM;
}
if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
return err;
}
// write 128-bits
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_WDTH;
// write the data
flc->addr = addr;
flc->data[0] = data[0];
flc->data[1] = data[1];
flc->data[2] = data[2];
flc->data[3] = data[3];
flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
/* Wait until flash operation is complete */
while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND)!=0){}
while (MXC_busy_flc (flc)){}
/* Lock flash */
flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
/* Check access violations */
if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
return E_BAD_STATE;
}
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_EnableInt(uint32_t mask)
{
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
if (!mask) {
/* No bits set? Wasn't something we can enable. */
return E_BAD_PARAM;
}
/* Apply enables and write back, preserving the flags */
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr |= mask;
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_DisableInt(uint32_t mask)
{
mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE);
if (!mask) {
/* No bits set? Wasn't something we can disable. */
return E_BAD_PARAM;
}
/* Apply disables and write back, preserving the flags */
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr &= ~mask;
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_GetFlags(void)
{
return (((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF));
}
//******************************************************************************
int MXC_FLC_RevA_ClearFlags(uint32_t mask)
{
mask &= (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF);
if (!mask) {
/* No bits set? Wasn't something we can clear. */
return E_BAD_PARAM;
}
/* Both flags are write zero clear */
((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr ^= mask;
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
{
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM;
}
/* Make sure the info block is locked */
flc->actrl = 0x1234;
/* Write the unlock sequence */
flc->actrl = 0x3a7f5ca3;
flc->actrl = 0xa1e34f20;
flc->actrl = 0x9608b2c1;
return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
{
if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
return E_BAD_PARAM;
}
flc->actrl = 0xDEADBEEF;
return E_NO_ERROR;
}
/**@} end of group flc */

85
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h Normal file
View File

@ -0,0 +1,85 @@
/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_reva_regs.h"
/**
* @ingroup flc
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
int MXC_FLC_RevA_Busy (void);
int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc);
int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc,uint32_t addr);
int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data);
int MXC_FLC_RevA_EnableInt (uint32_t mask);
int MXC_FLC_RevA_DisableInt (uint32_t mask);
int MXC_FLC_RevA_GetFlags (void);
int MXC_FLC_RevA_ClearFlags (uint32_t mask);
int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address);
int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif

246
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h Normal file
View File

@ -0,0 +1,246 @@
/**
* @file flc_reva_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _FLC_REVA_REGS_H_
#define _FLC_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup flc_reva
* @defgroup flc_reva_registers FLC_REVA_Registers
* @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
* @details Flash Memory Control.
*/
/**
* @ingroup flc_reva_registers
* Structure type to access the FLC_REVA Registers.
*/
typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC_REVA ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC_REVA CLKDIV Register */
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC_REVA CTRL Register */
__R uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC_REVA INTR Register */
__IO uint32_t eccdata; /**< <tt>\b 0x028:</tt> FLC_REVA ECCDATA Register */
__R uint32_t rsv_0x2c;
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC_REVA DATA Register */
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC_REVA ACTRL Register */
} mxc_flc_reva_regs_t;
/* Register offsets for module FLC_REVA */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_Register_Offsets Register Offsets
* @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address.
* @{
*/
#define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0028</tt> */
#define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0040</tt> */
/**@} end of group flc_reva_registers */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_ADDR FLC_REVA_ADDR
* @brief Flash Write Address.
* @{
*/
#define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_REVA_ADDR_Register */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_CLKDIV FLC_REVA_CLKDIV
* @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
* MHz clock for Flash controller.
* @{
*/
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_REVA_CLKDIV_Register */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_CTRL FLC_REVA_CTRL
* @brief Flash Control Register.
* @{
*/
#define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */
#define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */
#define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */
#define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */
#define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */
#define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
#define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */
#define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
#define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */
#define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
#define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
#define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
#define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */
#define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
#define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
#define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
#define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
#define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
/**@} end of group FLC_REVA_CTRL_Register */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_INTR FLC_REVA_INTR
* @brief Flash Interrupt Register.
* @{
*/
#define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */
#define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */
#define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
#define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
#define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
#define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
/**@} end of group FLC_REVA_INTR_Register */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_ECCDATA FLC_REVA_ECCDATA
* @brief ECC Data Register.
* @{
*/
#define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */
#define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
#define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */
#define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
/**@} end of group FLC_REVA_ECCDATA_Register */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_DATA FLC_REVA_DATA
* @brief Flash Write Data.
* @{
*/
#define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_REVA_DATA_Register */
/**
* @ingroup flc_reva_registers
* @defgroup FLC_REVA_ACTRL FLC_REVA_ACTRL
* @brief Access Control Register. Writing the ACTRL register with the following values in
* the order shown, allows read and write access to the system and user Information
* block: pflc-actrl = 0x3a7f5ca3; pflc-actrl =
* 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of
* any word will disable access to system and user information block. Readback of
* this register is always zero.
* @{
*/
#define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
#define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
/**@} end of group FLC_REVA_ACTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_REVA_REGS_H_ */

107
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c Normal file
View File

@ -0,0 +1,107 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_assert.h"
#include "gpio.h"
#include <stddef.h>
/* **** Globals **** */
static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void*);
static void* cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT];
static uint8_t initialized = 0;
/* **** Functions **** */
int MXC_GPIO_Common_Init(uint32_t portmask)
{
if (!initialized) {
int i, j;
for (i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) {
// Initialize call back arrays
for (j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) {
callback[i][j] = NULL;
}
}
initialized = 1;
}
return E_NO_ERROR;
}
void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata)
{
uint32_t mask;
unsigned int pin;
mask = cfg->mask;
pin = 0;
while (mask) {
if (mask & 1) {
callback[MXC_GPIO_GET_IDX(cfg->port)][pin] = func;
cbparam[MXC_GPIO_GET_IDX(cfg->port)][pin] = cbdata;
}
pin++;
mask >>= 1;
}
}
void MXC_GPIO_Common_Handler(unsigned int port)
{
uint32_t stat;
unsigned int pin;
MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES);
mxc_gpio_regs_t* gpio = MXC_GPIO_GET_GPIO(port);
stat = MXC_GPIO_GetFlags(gpio);
MXC_GPIO_ClearFlags(gpio, stat);
pin = 0;
while (stat) {
if (stat & 1) {
if (callback[port][pin]) {
callback[port][pin](cbparam[port][pin]);
}
}
pin++;
stat >>= 1;
}
}

52
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h Normal file
View File

@ -0,0 +1,52 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* **** Includes **** */
#include "gpio_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* **** Function Prototypes **** */
int MXC_GPIO_Common_Init (uint32_t portmask);
void MXC_GPIO_Common_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
void MXC_GPIO_Common_Handler (unsigned int port);
/**@} end of group gpio */
#ifdef __cplusplus
}
#endif

211
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c Normal file
View File

@ -0,0 +1,211 @@
/* *****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_errors.h"
#include "gpio.h"
#include "gpio_reva.h"
#include "gpio_common.h"
#include <stddef.h>
#include "mxc_sys.h"
/* **** Functions **** */
int MXC_GPIO_Init(uint32_t portmask)
{
int retval = MXC_GPIO_Common_Init(portmask);
if(portmask & MXC_GPIO_PORT_0) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
}
return MXC_GPIO_Common_Init(portmask) + retval;
}
int MXC_GPIO_Shutdown(uint32_t portmask)
{
if(portmask & MXC_GPIO_PORT_0) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0);
}
return E_NO_ERROR;
}
int MXC_GPIO_Reset(uint32_t portmask)
{
if(portmask & MXC_GPIO_PORT_0) {
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0);
}
return E_NO_ERROR;
}
int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = cfg->port;
// Set the GPIO type
switch(cfg->func) {
case MXC_GPIO_FUNC_IN:
gpio->out_en_clr = cfg->mask;
gpio->en0_set = cfg->mask;
gpio->en1_clr = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case MXC_GPIO_FUNC_OUT:
gpio->out_en_set = cfg->mask;
gpio->en0_set = cfg->mask;
gpio->en1_clr = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case MXC_GPIO_FUNC_ALT1:
gpio->en0_clr = cfg->mask;
gpio->en1_clr = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case MXC_GPIO_FUNC_ALT2:
gpio->en0_clr = cfg->mask;
gpio->en1_set = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case MXC_GPIO_FUNC_ALT3:
gpio->en0_set = cfg->mask;
gpio->en1_set = cfg->mask;
// gpio->en2_set |= cfg->mask;
break;
default:
return E_BAD_PARAM;
}
// Configure the pad
switch(cfg->pad) {
case MXC_GPIO_PAD_NONE:
gpio->pad_cfg1 &= ~cfg->mask;
break;
case MXC_GPIO_PAD_PULL_UP:
gpio->pad_cfg1 |= cfg->mask;
gpio->ps |= cfg->mask;
break;
case MXC_GPIO_PAD_PULL_DOWN:
gpio->pad_cfg1 |= cfg->mask;
gpio->ps &= ~cfg->mask;
break;
default:
return E_BAD_PARAM;
}
// Configure the vssel
MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
return E_NO_ERROR;
}
uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask)
{
return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t*) port, mask);
}
void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask)
{
MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t*) port, mask);
}
void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask)
{
MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t*) port, mask);
}
uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask)
{
return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t*) port, mask);
}
void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val)
{
MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t*) port, mask, val);
}
void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask)
{
MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t*) port, mask);
}
int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
{
return MXC_GPIO_RevA_IntConfig(cfg, pol);
}
void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask)
{
MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t*) port, mask);
}
void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask)
{
MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t*) port, mask);
}
void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata)
{
MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata);
}
void MXC_GPIO_Handler(unsigned int port)
{
MXC_GPIO_Common_Handler(port);
}
void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags)
{
MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t*) port, flags);
}
uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port)
{
return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t*) port);
}
int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask)
{
return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t*) port, vssel, mask);
}

201
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c Normal file
View File

@ -0,0 +1,201 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_errors.h"
#include "gpio.h"
#include "gpio_reva.h"
#include "gpio_common.h"
#include <stddef.h>
/* **** Functions **** */
uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask)
{
return (port->in & mask);
}
void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask)
{
port->out_set = mask;
}
void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask)
{
port->out_clr = mask;
}
uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask)
{
return (port->out & mask);
}
void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val)
{
port->out = (port->out & ~mask) | (val & mask);
}
void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask)
{
port->out ^= mask;
}
int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol)
{
mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t*) cfg->port;
switch (pol) {
case MXC_GPIO_INT_HIGH:
gpio->intpol &= ~cfg->mask;
gpio->dualedge &= ~cfg->mask;
gpio->intmode &= ~cfg->mask;
break;
case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */
gpio->intpol &= ~cfg->mask;
gpio->dualedge &= ~cfg->mask;
gpio->intmode |= cfg->mask;
break;
case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */
gpio->intpol |= cfg->mask;
gpio->dualedge &= ~cfg->mask;
gpio->intmode &= ~cfg->mask;
break;
case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */
gpio->intpol |= cfg->mask;
gpio->dualedge &= ~cfg->mask;
gpio->intmode |= cfg->mask;
break;
case MXC_GPIO_INT_BOTH:
gpio->dualedge |= cfg->mask;
gpio->intmode |= cfg->mask;
break;
default:
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask)
{
port->inten_set = mask;
}
void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask)
{
port->inten_clr = mask;
}
void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags)
{
port->intfl_clr = flags;
}
uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port)
{
return port->intfl;
}
int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask)
{
// Configure the vssel
switch (vssel) {
case MXC_GPIO_VSSEL_VDDIO:
port->vssel &= ~mask;
break;
case MXC_GPIO_VSSEL_VDDIOH:
port->vssel |= mask;
break;
default:
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask)
{
switch (func) {
case MXC_GPIO_FUNC_IN:
port->outen_clr = mask;
port->en0_set = mask;
port->en1_clr = mask;
port->en2_clr = mask;
break;
case MXC_GPIO_FUNC_OUT:
port->outen_set = mask;
port->en0_set = mask;
port->en1_clr = mask;
port->en2_clr = mask;
break;
case MXC_GPIO_FUNC_ALT1:
port->en0_clr = mask;
port->en1_clr = mask;
port->en2_clr = mask;
break;
case MXC_GPIO_FUNC_ALT2:
port->en0_clr = mask;
port->en1_set = mask;
port->en2_clr = mask;
break;
#if TARGET_NUM != 32650
case MXC_GPIO_FUNC_ALT3:
port->en0_clr = mask;
port->en1_clr = mask;
port->en2_set = mask;
break;
case MXC_GPIO_FUNC_ALT4:
port->en0_clr = mask;
port->en1_set = mask;
port->en2_set = mask;
break;
#endif
default:
return E_BAD_PARAM;
}
return E_NO_ERROR;
}

73
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h Normal file
View File

@ -0,0 +1,73 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* **** Includes **** */
#include "gpio_reva_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enumeration type for the pullup strength on a given pin.
*/
typedef enum {
MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/
MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/
} mxc_gpio_ps_t;
/* **** Function Prototypes **** */
uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask);
void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask);
void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask);
uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask);
void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val);
void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask);
int MXC_GPIO_RevA_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask);
void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask);
void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags);
uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port);
#if TARGET_NUM != 32650
int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask);
#endif
int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask);
/**@} end of group gpio */
#ifdef __cplusplus
}
#endif

690
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h Normal file
View File

@ -0,0 +1,690 @@
/**
* @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GPIO_REVA_REGS_H_
#define _GPIO_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gpio
* @defgroup gpio_registers GPIO_Registers
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @details Individual I/O for each GPIO
*/
/**
* @ingroup gpio_registers
* Structure type to access the GPIO Registers.
*/
typedef struct {
__IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */
__IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */
__IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */
__IO uint32_t outen; /**< <tt>\b 0x0C:</tt> GPIO OUTEN Register */
__IO uint32_t outen_set; /**< <tt>\b 0x10:</tt> GPIO OUTEN_SET Register */
__IO uint32_t outen_clr; /**< <tt>\b 0x14:</tt> GPIO OUTEN_CLR Register */
__IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */
__O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
__O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
__I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */
__IO uint32_t intmode; /**< <tt>\b 0x28:</tt> GPIO INTMODE Register */
__IO uint32_t intpol; /**< <tt>\b 0x2C:</tt> GPIO INTPOL Register */
__IO uint32_t inen; /**< <tt>\b 0x30:</tt> GPIO INEN Register */
__IO uint32_t inten; /**< <tt>\b 0x34:</tt> GPIO INTEN Register */
__IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */
__IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */
__I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO INTFL Register */
__R uint32_t rsv_0x44;
__IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */
__IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */
__IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */
__IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */
__R uint32_t rsv_0x58;
__IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */
__IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */
__IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
__R uint32_t rsv_0x80_0xa7[10];
__IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */
__IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
__R uint32_t rsv_0xbc;
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
} mxc_gpio_reva_regs_t;
/* Register offsets for module GPIO */
/**
* @ingroup gpio_registers
* @defgroup GPIO_Register_Offsets Register Offsets
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
* @{
*/
#define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
#define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
#define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
#define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
#define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
#define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
#define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
#define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
#define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
#define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
#define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
#define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
#define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
#define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
#define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
#define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
#define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
#define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
#define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
#define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
#define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
#define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
#define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
#define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
/**@} end of group gpio_registers */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0 GPIO_EN0
* @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
* GPIO pin on the associated port.
* @{
*/
#define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_REVA_EN Position */
#define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
#define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
#define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
#define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
#define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
/**@} end of group GPIO_EN0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0_SET GPIO_EN0_SET
* @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
* register sets the bits in the same positions in GPIO_EN to 1, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */
#define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
/**@} end of group GPIO_EN0_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN0_CLR GPIO_EN0_CLR
* @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */
#define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
/**@} end of group GPIO_EN0_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUTEN GPIO_OUTEN
* @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
* GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_REVA_OUTEN_EN_POS 0 /**< OUTEN_EN Position */
#define MXC_F_GPIO_REVA_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */
#define MXC_V_GPIO_REVA_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */
#define MXC_S_GPIO_REVA_OUTEN_EN_DIS (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */
#define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */
#define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */
/**@} end of group GPIO_OUTEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET
* @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
* in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */
#define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */
/**@} end of group GPIO_OUTEN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR
* @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
* bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */
#define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */
/**@} end of group GPIO_OUTEN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT GPIO_OUT
* @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
* associated port. This register can be written either directly, or by using the
* GPIO_OUT_SET and GPIO_OUT_CLR registers.
* @{
*/
#define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
#define MXC_F_GPIO_REVA_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
#define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
#define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
#define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
#define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
/**@} end of group GPIO_OUT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_SET GPIO_OUT_SET
* @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
* in the same positions in GPIO_OUT to 1, without affecting other bits in that
* register.
* @{
*/
#define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */
#define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
#define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
#define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
#define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
#define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
/**@} end of group GPIO_OUT_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
* @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_OUT to 0, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
#define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
/**@} end of group GPIO_OUT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IN GPIO_IN
* @brief GPIO Input Register. Read-only register to read from the logic states of the
* GPIO pins on this port.
* @{
*/
#define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
#define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
/**@} end of group GPIO_IN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTMODE GPIO_INTMODE
* @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
* mode setting for the associated GPIO pin on this port.
* @{
*/
#define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */
#define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */
#define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */
#define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */
#define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */
#define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */
/**@} end of group GPIO_INTMODE_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTPOL GPIO_INTPOL
* @brief GPIO Interrupt Polarity Register. Each bit in this register controls the
* interrupt polarity setting for one GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */
#define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */
#define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */
#define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */
#define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */
#define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */
/**@} end of group GPIO_INTPOL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTEN GPIO_INTEN
* @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
* interrupt enable for the associated pin on the GPIO port.
* @{
*/
#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_REVA_INTEN Position */
#define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */
#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */
#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */
#define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */
#define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */
/**@} end of group GPIO_INTEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTEN_SET GPIO_INTEN_SET
* @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
* the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */
#define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */
#define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */
#define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */
#define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */
#define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */
/**@} end of group GPIO_INTEN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR
* @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */
#define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */
#define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */
#define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */
#define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */
#define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */
/**@} end of group GPIO_INTEN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTFL GPIO_INTFL
* @brief GPIO Interrupt Status Register. Each bit in this register contains the pending
* interrupt status for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */
#define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */
#define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */
#define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */
#define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */
#define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */
/**@} end of group GPIO_INTFL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR
* @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */
#define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */
/**@} end of group GPIO_INTFL_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WKEN GPIO_WKEN
* @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
* enable for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */
#define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */
#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_REVA_WKEN_DIS Value */
#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_REVA_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */
#define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */
#define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */
/**@} end of group GPIO_WKEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WKEN_SET GPIO_WKEN_SET
* @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
* bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */
#define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */
/**@} end of group GPIO_WKEN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR
* @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
* the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */
#define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */
/**@} end of group GPIO_WKEN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DUALEDGE GPIO_DUALEDGE
* @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
* edge mode for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */
#define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */
#define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */
#define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */
#define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */
#define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */
/**@} end of group GPIO_DUALEDGE_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0
* @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */
#define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */
#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */
#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */
#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */
#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */
#define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */
#define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */
/**@} end of group GPIO_PADCTRL0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1
* @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */
#define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */
#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */
#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */
#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */
#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */
#define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */
#define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */
/**@} end of group GPIO_PADCTRL1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1 GPIO_EN1
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
#define MXC_F_GPIO_REVA_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
#define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
#define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
#define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
#define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
/**@} end of group GPIO_EN1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_SET GPIO_EN1_SET
* @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
#define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
/**@} end of group GPIO_EN1_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
* @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
#define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
/**@} end of group GPIO_EN1_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2 GPIO_EN2
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
#define MXC_F_GPIO_REVA_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
#define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
#define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
#define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
#define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
/**@} end of group GPIO_EN2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_SET GPIO_EN2_SET
* @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
#define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
/**@} end of group GPIO_EN2_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
* @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN2 to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
#define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
/**@} end of group GPIO_EN2_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_HYSEN GPIO_HYSEN
* @brief GPIO Input Hysteresis Enable.
* @{
*/
#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */
#define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */
/**@} end of group GPIO_HYSEN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_SRSEL GPIO_SRSEL
* @brief GPIO Slew Rate Enable Register.
* @{
*/
#define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */
#define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */
#define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */
#define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */
#define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */
#define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */
/**@} end of group GPIO_SRSEL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS0 GPIO_DS0
* @brief GPIO Drive Strength Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */
#define MXC_F_GPIO_REVA_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */
#define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */
#define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */
#define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */
#define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */
/**@} end of group GPIO_DS0_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS1 GPIO_DS1
* @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */
#define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */
/**@} end of group GPIO_DS1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PS GPIO_PS
* @brief GPIO Pull Select Mode.
* @{
*/
#define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */
#define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */
/**@} end of group GPIO_PS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_VSSEL GPIO_VSSEL
* @brief GPIO Voltage Select.
* @{
*/
#define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
#define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
/**@} end of group GPIO_VSSEL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_REVA_REGS_H_ */

394
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c Normal file
View File

@ -0,0 +1,394 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_pins.h"
#include "mxc_delay.h"
#include "i2c_regs.h"
#include "dma_regs.h"
#include "mxc_i2c.h"
#include "i2c_reva.h"
/* **** Definitions **** */
#define MXC_I2C_FASTPLUS_SPEED 1000000
/* **** Variable Declaration **** */
uint32_t interruptCheck = MXC_F_I2C_INTFL0_AMI | MXC_F_I2C_INTFL0_DNRERI;
/* **** Function Prototypes **** */
/* ************************************************************************* */
/* Control/Configuration functions */
/* ************************************************************************* */
int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr)
{
if(i2c == NULL) {
return E_NULL_PTR;
}
MXC_I2C_Shutdown(i2c); // Clear everything out
if(i2c == MXC_I2C0) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0);
MXC_GPIO_Config(&gpio_cfg_i2c0);
}
else if(i2c == MXC_I2C1) {
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1);
MXC_GPIO_Config(&gpio_cfg_i2c1);
}
else {
return E_NO_DEVICE;
}
return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t*) i2c, masterMode, slaveAddr);
}
int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx)
{
if(i2c == NULL) {
return E_NULL_PTR;
}
if(idx != 0) {
// Multiple slaves are not supported yet
return E_NOT_SUPPORTED;
}
if(slaveAddr > MXC_F_I2C_SLADDR_SLA) {
// Only support addresses up to 10 bits
return E_BAD_PARAM;
}
i2c->sladdr = 0;
if(slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) {
// Set for 10bit addressing mode
i2c->sladdr = MXC_F_I2C_SLADDR_EA;
}
i2c->sladdr |= slaveAddr;
return E_NO_ERROR;
}
int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c)
{
// Configure GPIO for I2C
if(i2c == MXC_I2C0) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0);
}
else if(i2c == MXC_I2C1) {
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
}
else {
return E_NO_DEVICE;
}
int i2cNum = MXC_I2C_GET_IDX(i2c);
// Reconcile this with MXC_SYS_I2C_Init when we figure out what to do abotu system level things
switch(i2cNum) {
case 0:
MXC_GCR->rst0 |= MXC_F_GCR_RST0_I2C0;
break;
case 1:
MXC_GCR->rst1 |= MXC_F_GCR_RST1_I2C1;
break;
default:
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_I2C_SetFrequency(mxc_i2c_regs_t* i2c, unsigned int hz)
{
// ME13 doesn't support high speed more
if(hz > MXC_I2C_FASTPLUS_SPEED) {
return E_NOT_SUPPORTED;
}
return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t*) i2c, hz);
}
unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_SetClockStretching(mxc_i2c_regs_t* i2c, int enable)
{
return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t*) i2c, enable);
}
int MXC_I2C_GetClockStretching(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t*) i2c);
}
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
int MXC_I2C_Start(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_Stop(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_WriteByte(mxc_i2c_regs_t* i2c, unsigned char byte)
{
return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t*) i2c, byte);
}
int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack)
{
return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t*) i2c, byte, ack);
}
int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t* i2c, unsigned char* byte, mxc_i2c_getAck_t getAck)
{
return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck);
}
int MXC_I2C_Write(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len)
{
return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t*) i2c, bytes, len);
}
int MXC_I2C_Read(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack)
{
return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t*) i2c, bytes, len, ack);
}
int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len)
{
return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len);
}
int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback)
{
uint8_t i2cNum;
mxc_dma_config_t config;
i2cNum = MXC_I2C_GET_IDX(i2c);
switch(i2cNum) {
case 0:
config.reqsel = MXC_DMA_REQUEST_I2C0RX;
break;
case 1:
config.reqsel = MXC_DMA_REQUEST_I2C1RX;
break;
}
return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA);
}
int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len)
{
return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len);
}
int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback)
{
uint8_t i2cNum;
mxc_dma_config_t config;
i2cNum = MXC_I2C_GET_IDX(i2c);
switch(i2cNum) {
case 0:
config.reqsel = MXC_DMA_REQUEST_I2C0TX;
break;
case 1:
config.reqsel = MXC_DMA_REQUEST_I2C1TX;
break;
}
return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA);
}
int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c);
}
void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t* i2c)
{
MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t*) i2c);
}
void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t* i2c)
{
MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_GetFlags(mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1)
{
return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
}
void MXC_I2C_ClearFlags(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1)
{
MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
}
void MXC_I2C_EnableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1)
{
MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
}
void MXC_I2C_DisableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1)
{
MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
}
void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c)
{
MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t*) i2c);
}
void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c)
{
MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t*) i2c);
}
void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c)
{
MXC_I2C_RevA_EnableGeneralCall ((mxc_i2c_reva_regs_t*) i2c);
}
void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c)
{
MXC_I2C_RevA_DisableGeneralCall ((mxc_i2c_reva_regs_t*) i2c);
}
void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout)
{
MXC_I2C_RevA_SetTimeout ((mxc_i2c_reva_regs_t*) i2c, timeout);
}
unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_GetTimeout ((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_Recover(mxc_i2c_regs_t* i2c, unsigned int retries)
{
return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t*) i2c, retries);
}
/* ************************************************************************* */
/* Transaction level functions */
/* ************************************************************************* */
int MXC_I2C_MasterTransaction(mxc_i2c_req_t* req)
{
return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t*) req);
}
int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t* req)
{
return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t*) req);
}
int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req)
{
return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t*) req, MXC_DMA);
}
int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback)
{
return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck);
}
int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback)
{
return MXC_I2C_RevA_SlaveTransactionAsync((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck);
}
int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes)
{
return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes);
}
unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t*) i2c);
}
int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes)
{
return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes);
}
unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t* i2c)
{
return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t*) i2c);
}
void MXC_I2C_AsyncHandler(mxc_i2c_regs_t* i2c)
{
MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t*) i2c, interruptCheck);
}
void MXC_I2C_DMACallback(int ch, int error)
{
MXC_I2C_RevA_DMACallback(ch, error);
}

1348
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c Normal file
View File

File diff suppressed because it is too large Load Diff

157
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h Normal file
View File

@ -0,0 +1,157 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#ifndef _I2C_REVA_H_
#define _I2C_REVA_H_
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "i2c_regs.h"
#include "i2c_reva_regs.h"
#include "dma.h"
/* **** Definitions **** */
#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F
#define MXC_I2C_REVA_STD_MODE 100000
#define MXC_I2C_REVA_FAST_SPEED 400000
#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000
#define MXC_I2C_REVA_HS_MODE 3400000
#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF
#define MXC_I2C_REVA_INTFL1_MASK 0x00000007
#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256
#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \
MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \
MXC_F_I2C_REVA_INTFL0_STOP_ERR)
typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t;
typedef int (*mxc_i2c_reva_getAck_t) (mxc_i2c_reva_regs_t* i2c, unsigned char byte);
typedef void (*mxc_i2c_reva_complete_cb_t) (mxc_i2c_reva_req_t* req, int result);
typedef void (*mxc_i2c_reva_dma_complete_cb_t) (int len, int result);
struct _i2c_reva_req_t {
mxc_i2c_reva_regs_t* i2c;
unsigned int addr;
unsigned char* tx_buf;
unsigned int tx_len;
unsigned char* rx_buf;
unsigned int rx_len;
int restart;
mxc_i2c_reva_complete_cb_t callback;
};
typedef enum {
MXC_I2C_REVA_EVT_MASTER_WR,
MXC_I2C_REVA_EVT_MASTER_RD,
MXC_I2C_REVA_EVT_RX_THRESH,
MXC_I2C_REVA_EVT_TX_THRESH,
MXC_I2C_REVA_EVT_TRANS_COMP,
MXC_I2C_REVA_EVT_UNDERFLOW,
MXC_I2C_REVA_EVT_OVERFLOW,
} mxc_i2c_reva_slave_event_t;
typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c,
mxc_i2c_reva_slave_event_t event, void* data);
/* **** Variable Declaration **** */
/* **** Function Prototypes **** */
/* ************************************************************************* */
/* Control/Configuration functions */
/* ************************************************************************* */
int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr);
int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx);
int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz);
unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable);
int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c);
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte);
int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack);
int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck);
int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len);
int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack);
int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len);
int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma);
int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len);
int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma);
int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1);
void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1);
void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1);
void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1);
void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout);
unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries);
/* ************************************************************************* */
/* Transaction level functions */
/* ************************************************************************* */
int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req);
int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req);
int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma);
int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck);
int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck);
int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes);
unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c);
int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes);
unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal);
void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c);
void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum);
unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal);
void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck);
void MXC_I2C_RevA_DMACallback (int ch, int error);
#endif /* _I2C_REVA_H_ */

580
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h Normal file
View File

@ -0,0 +1,580 @@
/**
* @file i2c_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _I2C_REVA_REGS_H_
#define _I2C_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup i2c
* @defgroup i2c_registers I2C_Registers
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @details Inter-Integrated Circuit.
*/
/**
* @ingroup i2c_registers
* Structure type to access the I2C Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
__IO uint32_t intfl0; /**< <tt>\b 0x08:</tt> I2C INTFL0 Register */
__IO uint32_t inten0; /**< <tt>\b 0x0C:</tt> I2C INTEN0 Register */
__IO uint32_t intfl1; /**< <tt>\b 0x10:</tt> I2C INTFL1 Register */
__IO uint32_t inten1; /**< <tt>\b 0x14:</tt> I2C INTEN1 Register */
__IO uint32_t fifolen; /**< <tt>\b 0x18:</tt> I2C FIFOLEN Register */
__IO uint32_t rxctrl0; /**< <tt>\b 0x1C:</tt> I2C RXCTRL0 Register */
__IO uint32_t rxctrl1; /**< <tt>\b 0x20:</tt> I2C RXCTRL1 Register */
__IO uint32_t txctrl0; /**< <tt>\b 0x24:</tt> I2C TXCTRL0 Register */
__IO uint32_t txctrl1; /**< <tt>\b 0x28:</tt> I2C TXCTRL1 Register */
__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
__IO uint32_t mstctrl; /**< <tt>\b 0x30:</tt> I2C MSTCTRL Register */
__IO uint32_t clklo; /**< <tt>\b 0x34:</tt> I2C CLKLO Register */
__IO uint32_t clkhi; /**< <tt>\b 0x38:</tt> I2C CLKHI Register */
__IO uint32_t hsclk; /**< <tt>\b 0x3C:</tt> I2C HSCLK Register */
__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
__R uint32_t rsv_0x44;
__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
__IO uint32_t slave; /**< <tt>\b 0x4C:</tt> I2C SLAVE Register */
} mxc_i2c_reva_regs_t;
/* Register offsets for module I2C */
/**
* @ingroup i2c_registers
* @defgroup I2C_Register_Offsets Register Offsets
* @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
* @{
*/
#define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */
#define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */
#define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */
#define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */
#define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */
#define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */
#define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */
#define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */
#define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */
#define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */
#define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */
#define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */
#define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */
#define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */
#define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */
#define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */
#define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */
#define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */
#define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: <tt> 0x004C</tt> */
/**@} end of group i2c_registers */
/**
* @ingroup i2c_registers
* @defgroup I2C_CTRL I2C_CTRL
* @brief Control Register0.
* @{
*/
#define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */
#define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */
#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */
#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */
#define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */
#define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */
#define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */
#define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */
#define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
#define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
#define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
#define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
#define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
#define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
#define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
#define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
#define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */
#define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */
#define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */
#define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */
#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */
#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */
#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */
#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */
#define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */
#define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */
/**@} end of group I2C_CTRL_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_STATUS I2C_STATUS
* @brief Status Register.
* @{
*/
#define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */
#define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
#define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */
#define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
#define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
#define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
#define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */
#define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
#define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
#define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
#define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */
#define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */
/**@} end of group I2C_STATUS_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTFL0 I2C_INTFL0
* @brief Interrupt Status Register.
* @{
*/
#define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */
#define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */
#define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */
#define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */
#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */
#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */
#define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */
#define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */
#define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */
#define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */
#define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */
#define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */
#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */
#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */
#define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */
#define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */
#define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */
#define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */
#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */
#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */
#define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */
#define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */
#define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */
#define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */
#define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */
#define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */
#define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */
#define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */
#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */
#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */
#define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */
#define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */
#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */
#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */
/**@} end of group I2C_INTFL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTEN0 I2C_INTEN0
* @brief Interrupt Enable Register.
* @{
*/
#define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */
#define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */
#define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */
#define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */
#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */
#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */
#define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */
#define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */
#define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */
#define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */
#define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */
#define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */
#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */
#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */
#define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */
#define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */
#define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */
#define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */
#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */
#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */
#define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */
#define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */
#define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */
#define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */
#define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */
#define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */
#define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */
#define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */
#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */
#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */
#define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */
#define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */
#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */
#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */
#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */
/**@} end of group I2C_INTEN0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTFL1 I2C_INTFL1
* @brief Interrupt Status Register 1.
* @{
*/
#define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */
#define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */
#define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */
#define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */
#define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */
#define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */
/**@} end of group I2C_INTFL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INTEN1 I2C_INTEN1
* @brief Interrupt Staus Register 1.
* @{
*/
#define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */
#define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */
#define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */
#define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */
#define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */
#define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */
/**@} end of group I2C_INTEN1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFOLEN I2C_FIFOLEN
* @brief FIFO Configuration Register.
* @{
*/
#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */
#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */
#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */
#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */
/**@} end of group I2C_FIFOLEN_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RXCTRL0 I2C_RXCTRL0
* @brief Receive Control Register 0.
* @{
*/
#define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */
#define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */
#define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */
#define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */
#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */
#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */
/**@} end of group I2C_RXCTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RXCTRL1 I2C_RXCTRL1
* @brief Receive Control Register 1.
* @{
*/
#define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */
#define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */
#define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */
#define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */
/**@} end of group I2C_RXCTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TXCTRL0 I2C_TXCTRL0
* @brief Transmit Control Register 0.
* @{
*/
#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */
#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */
#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */
#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */
#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */
#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */
#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */
#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */
#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */
#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */
#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */
#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */
#define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */
#define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */
#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */
#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */
/**@} end of group I2C_TXCTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TXCTRL1 I2C_TXCTRL1
* @brief Transmit Control Register 1.
* @{
*/
#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */
#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */
#define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */
#define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */
/**@} end of group I2C_TXCTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFO I2C_FIFO
* @brief Data Register.
* @{
*/
#define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
#define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
/**@} end of group I2C_FIFO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_MSTCTRL I2C_MSTCTRL
* @brief Master Control Register.
* @{
*/
#define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */
#define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */
#define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */
#define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */
#define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */
#define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */
#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */
#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */
/**@} end of group I2C_MSTCTRL_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLKLO I2C_CLKLO
* @brief Clock Low Register.
* @{
*/
#define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */
#define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */
/**@} end of group I2C_CLKLO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLKHI I2C_CLKHI
* @brief Clock high Register.
* @{
*/
#define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */
#define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */
/**@} end of group I2C_CLKHI_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_HSCLK I2C_HSCLK
* @brief Clock high Register.
* @{
*/
#define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */
#define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */
#define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */
#define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */
/**@} end of group I2C_HSCLK_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TIMEOUT I2C_TIMEOUT
* @brief Timeout Register
* @{
*/
#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */
#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */
/**@} end of group I2C_TIMEOUT_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_DMA I2C_DMA
* @brief DMA Register.
* @{
*/
#define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
#define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
#define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
#define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
/**@} end of group I2C_DMA_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_SLAVE I2C_SLAVE
* @brief Slave Address Register.
* @{
*/
#define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */
#define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */
#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */
#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */
/**@} end of group I2C_SLAVE_Register */
#ifdef __cplusplus
}
#endif
#endif /* _I2C_REGS_H_ */

46
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c Normal file
View File

@ -0,0 +1,46 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "icc.h"
#include "icc_reva.h"
void MXC_ICC_Com_Flush(void)
{
MXC_ICC_Disable();
MXC_ICC_Enable();
}

50
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h Normal file
View File

@ -0,0 +1,50 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
/* **** Includes **** */
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Flush the instruction cache controller.
*/
void MXC_ICC_Com_Flush(void);
/**@} end of group icc */
#ifdef __cplusplus
}
#endif

63
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c Normal file
View File

@ -0,0 +1,63 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "icc.h"
#include "icc_reva.h"
#include "icc_common.h"
/* **** Functions **** */
int MXC_ICC_ID (mxc_icc_info_t cid)
{
return MXC_ICC_RevA_ID ((mxc_icc_reva_regs_t*) MXC_ICC, cid);
}
void MXC_ICC_Enable (void)
{
MXC_ICC_RevA_Enable ((mxc_icc_reva_regs_t*) MXC_ICC);
}
void MXC_ICC_Disable (void)
{
MXC_ICC_RevA_Disable ((mxc_icc_reva_regs_t*) MXC_ICC);
}
void MXC_ICC_Flush (void)
{
MXC_ICC_Com_Flush();
}

91
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c Normal file
View File

@ -0,0 +1,91 @@
/* *****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include <stddef.h>
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "icc.h"
#include "icc_reva_regs.h"
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
static int MXC_ICC_Ready(mxc_icc_reva_regs_t* icc)
{
return (icc->ctrl & MXC_F_ICC_REVA_CTRL_RDY);
}
int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid)
{
if(icc == NULL) {
return E_NULL_PTR;
}
switch(cid) {
case ICC_INFO_RELNUM:
return ((icc->info & MXC_F_ICC_REVA_INFO_RELNUM) >> MXC_F_ICC_REVA_INFO_RELNUM_POS);
case ICC_INFO_PARTNUM:
return ((icc->info & MXC_F_ICC_REVA_INFO_PARTNUM) >> MXC_F_ICC_REVA_INFO_PARTNUM_POS);
case ICC_INFO_ID:
return ((icc->info & MXC_F_ICC_REVA_INFO_ID) >> MXC_F_ICC_REVA_INFO_ID_POS);
default:
return E_BAD_PARAM;
}
}
void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc)
{
// Invalidate cache and wait until ready
icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN;
icc->invalidate = 1;
while(!(MXC_ICC_Ready(icc)));
// Enable Cache
icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN;
while(!(MXC_ICC_Ready(icc)));
}
void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t* icc)
{
// Disable Cache
icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN;
}

50
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h Normal file
View File

@ -0,0 +1,50 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software");,
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "icc.h"
#include "icc_reva_regs.h"
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
int MXC_ICC_RevA_ID (mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid);
void MXC_ICC_RevA_Enable (mxc_icc_reva_regs_t* icc);
void MXC_ICC_RevA_Disable (mxc_icc_reva_regs_t* icc);

159
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h Normal file
View File

@ -0,0 +1,159 @@
/**
* @file icc_reva_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _ICC_REVA_REGS_H_
#define _ICC_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup icc_reva
* @defgroup icc_reva_registers ICC_REVA_Registers
* @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
* @details Instruction Cache Controller Registers
*/
/**
* @ingroup icc_reva_registers
* Structure type to access the ICC_REVA Registers.
*/
typedef struct {
__I uint32_t info; /**< <tt>\b 0x0000:</tt> ICC_REVA INFO Register */
__I uint32_t sz; /**< <tt>\b 0x0004:</tt> ICC_REVA SZ Register */
__R uint32_t rsv_0x8_0xff[62];
__IO uint32_t ctrl; /**< <tt>\b 0x0100:</tt> ICC_REVA CTRL Register */
__R uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC_REVA INVALIDATE Register */
} mxc_icc_reva_regs_t;
/* Register offsets for module ICC_REVA */
/**
* @ingroup icc_reva_registers
* @defgroup ICC_REVA_Register_Offsets Register Offsets
* @brief ICC_REVA Peripheral Register Offsets from the ICC_REVA Base Peripheral Address.
* @{
*/
#define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0000</tt> */
#define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0004</tt> */
#define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0100</tt> */
#define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0700</tt> */
/**@} end of group icc_reva_registers */
/**
* @ingroup icc_reva_registers
* @defgroup ICC_REVA_INFO ICC_REVA_INFO
* @brief Cache ID Register.
* @{
*/
#define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */
#define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */
#define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */
#define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */
#define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */
#define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */
/**@} end of group ICC_REVA_INFO_Register */
/**
* @ingroup icc_reva_registers
* @defgroup ICC_REVA_SZ ICC_REVA_SZ
* @brief Memory Configuration Register.
* @{
*/
#define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */
#define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */
#define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */
#define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */
/**@} end of group ICC_REVA_SZ_Register */
/**
* @ingroup icc_reva_registers
* @defgroup ICC_REVA_CTRL ICC_REVA_CTRL
* @brief Cache Control and Status Register.
* @{
*/
#define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */
#define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
/**@} end of group ICC_REVA_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _ICC_REVA_REGS_H_ */

395
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c Normal file
View File

@ -0,0 +1,395 @@
/**
* @file lp.c
* @brief Low power functions
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/***** Includes *****/
#include "lp.h"
#include "pwrseq_regs.h"
#include "mxc_errors.h"
#include "gcr_regs.h"
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_pins.h"
#include "mxc_sys.h"
#include "flc.h"
#include "mxc_delay.h"
/***** Functions *****/
void MXC_LP_ClearWakeStatus(void)
{
MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF;
/* These flags are slow to clear, so block until they do */
while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en));
}
void MXC_LP_EnableSRAM3(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
}
void MXC_LP_DisableSRAM3(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
}
void MXC_LP_EnableSRAM2(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
}
void MXC_LP_DisableSRAM2(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
}
void MXC_LP_EnableSRAM1(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
}
void MXC_LP_DisableSRAM1(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
}
void MXC_LP_EnableSRAM0(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
}
void MXC_LP_DisableSRAM0(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
}
void MXC_LP_EnableICacheLightSleep(void)
{
MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_ICACHE_RET);
}
void MXC_LP_DisableICacheLightSleep(void)
{
MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_ICACHE_RET);
}
void MXC_LP_EnableSysRAM3LightSleep(void)
{
MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM3_LS);
}
void MXC_LP_DisableSysRAM3LightSleep(void)
{
MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM3_LS);
}
void MXC_LP_EnableSysRAM2LightSleep(void)
{
MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM2_LS);
}
void MXC_LP_DisableSysRAM2LightSleep(void)
{
MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM2_LS);
}
void MXC_LP_EnableSysRAM1LightSleep(void)
{
MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM1_LS);
}
void MXC_LP_DisableSysRAM1LightSleep(void)
{
MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM1_LS);
}
void MXC_LP_EnableSysRAM0LightSleep(void)
{
MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM0_LS);
}
void MXC_LP_DisableSysRAM0LightSleep(void)
{
MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM0_LS);
}
void MXC_LP_EnableRTCAlarmWakeup(void)
{
MXC_GCR->pm |= MXC_F_GCR_PM_RTCWK_EN;
}
void MXC_LP_DisableRTCAlarmWakeup(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWK_EN;
}
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask)
{
MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWK_EN;
//switch(port)
//{
/*case 0:*/ MXC_PWRSEQ->lpwk_en |= mask; //break;
//}
}
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask)
{
//switch(port)
//{
/* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~mask; //break;
//}
if(MXC_PWRSEQ->lpwk_en == 0)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWK_EN;
}
}
void MXC_LP_EnterSleepMode(void)
{
// Clear SLEEPDEEP bit
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
// Go into Sleep mode and wait for an interrupt to wake the processor
__WFI();
}
void MXC_LP_EnterDeepSleepMode(void)
{
// Set SLEEPDEEP bit
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
// Auto-powerdown 96 MHz oscillator when in deep sleep
MXC_GCR->pm |= MXC_F_GCR_PM_HFIOPD;
// Go into Deepsleep mode and wait for an interrupt to wake the processor
__WFI();
}
void MXC_LP_EnterBackupMode(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
while(1);
}
void MXC_LP_EnterShutdownMode(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN;
while(1);
}
int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr)
{
uint32_t current_clock, div;
int error;
// Ensure part is operating from internal LDO for core power
if(MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_LDO_DIS) {
return E_BAD_STATE;
}
// Select the 8KHz nanoring (no guarantee 32KHz is attached) as system clock source
current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL;
if(current_clock == MXC_SYS_CLOCK_HIRC) {
error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_NANORING);
if(error != E_NO_ERROR) {
return error;
}
}
// Set flash wait state for any clock so its not to low after clock changes.
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
// Set the OVR bits
MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR);
MXC_PWRSEQ->lp_ctrl |= ovr;
// Set LVE bit
if(ovr == MXC_LP_OVR_0_9) {
MXC_FLC->ctrl |= MXC_F_FLC_CTRL_LVE;
} else {
MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_LVE);
}
// Revert the clock to original state if it was HIRC
if(current_clock == MXC_SYS_CLOCK_HIRC) {
error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
if(error != E_NO_ERROR) {
return error;
}
}
// Update SystemCoreClock variable
SystemCoreClockUpdate();
// Get the clock divider
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
// Set Flash Wait States
if(ovr == MXC_LP_OVR_0_9) {
if(div == 0) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
}
} else if(ovr == MXC_LP_OVR_1_0) {
if(div == 0) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
}
} else {
if(div == 0) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else if(div == 1) {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
} else {
MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS);
}
}
// Caller must perform peripheral reset
return E_NO_ERROR;
}
void MXC_LP_EnableSRamRet0(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
}
void MXC_LP_DisableSRamRet0(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
}
void MXC_LP_EnableSRamRet1(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
}
void MXC_LP_DisableSRamRet1(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
}
void MXC_LP_EnableSRamRet2(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
}
void MXC_LP_DisableSRamRet2(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
}
void MXC_LP_EnableSRamRet3(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
}
void MXC_LP_DisableSRamRet3(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
}
void MXC_LP_EnableBlockDetect(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
}
void MXC_LP_DisableBlockDetect(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
}
void MXC_LP_EnableRamRetReg(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
}
void MXC_LP_DisableRamRetReg(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
}
void MXC_LP_EnableFastWk(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
}
void MXC_LP_DisableFastWk(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
}
void MXC_LP_EnableBandGap(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
}
void MXC_LP_DisableBandGap(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
}
void MXC_LP_EnableVCorePORSignal(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
}
void MXC_LP_DisableVCorePORSignal(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
}
void MXC_LP_EnableLDO(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
}
void MXC_LP_DisableLDO(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
}
void MXC_LP_EnableVCoreSVM(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
}
void MXC_LP_DisableVCoreSVM(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
}
void MXC_LP_EnableVDDIOPorMonitoF(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
}
void MXC_LP_DisableVDDIOPorMonitor(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
}

119
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c Normal file
View File

@ -0,0 +1,119 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
#include "mxc_device.h"
#include "rtc_regs.h"
#include "rtc.h"
#include "mxc_sys.h"
#include "mxc_pins.h"
#include "mxc_delay.h"
#include "gpio_regs.h"
#include "mxc_errors.h"
#include "rtc_reva.h"
/* ***** Functions ***** */
int MXC_RTC_EnableInt (uint32_t mask)
{
return MXC_RTC_RevA_EnableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask);
}
int MXC_RTC_DisableInt (uint32_t mask)
{
return MXC_RTC_RevA_DisableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask);
}
int MXC_RTC_SetTimeofdayAlarm (uint32_t ras)
{
return MXC_RTC_RevA_SetTimeofdayAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, ras);
}
int MXC_RTC_SetSubsecondAlarm (uint32_t rssa)
{
return MXC_RTC_RevA_SetSubsecondAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, rssa);
}
int MXC_RTC_Start (void)
{
return MXC_RTC_RevA_Start ((mxc_rtc_reva_regs_t*) MXC_RTC);
}
int MXC_RTC_Stop (void)
{
return MXC_RTC_RevA_Stop ((mxc_rtc_reva_regs_t*) MXC_RTC);
}
int MXC_RTC_Init (uint32_t sec, uint8_t ssec)
{
// Enable clock
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN;
return MXC_RTC_RevA_Init ((mxc_rtc_reva_regs_t*) MXC_RTC, sec, ssec);
}
int MXC_RTC_SquareWave (mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
{
MXC_GPIO_Config (&gpio_cfg_32kcal);
return MXC_RTC_RevA_SquareWave ((mxc_rtc_reva_regs_t*) MXC_RTC, sqe, ft);
}
int MXC_RTC_Trim (int8_t trm)
{
return MXC_RTC_RevA_Trim ((mxc_rtc_reva_regs_t*) MXC_RTC, trm);
}
int MXC_RTC_GetFlags (void)
{
return MXC_RTC_RevA_GetFlags();
}
int MXC_RTC_ClearFlags (int flags)
{
return MXC_RTC_RevA_ClearFlags (flags);
}
int MXC_RTC_GetSubSecond (void)
{
return MXC_RTC_RevA_GetSubSecond();
}
int MXC_RTC_GetSecond (void)
{
return MXC_RTC_RevA_GetSecond();
}
int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec)
{
return MXC_RTC_RevA_GetTime (sec, subsec);
}

374
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c Normal file
View File

@ -0,0 +1,374 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
#include <stddef.h>
#include "mxc_device.h"
#include "rtc.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "gpio_regs.h"
#include "mxc_errors.h"
#include "rtc_reva.h"
#if TARGET_NUM == 32650
#include "pwrseq_regs.h"
#endif
int MXC_RTC_CheckBusy(void)
{
// Time-out transfer if it takes > BUSY_TIMEOUT microseconds
MXC_DelayAsync(MXC_DELAY_USEC(MXC_BUSY_TIMEOUT), NULL);
while (MXC_RTC_REVA_IS_BUSY) {
if (MXC_DelayCheck() != E_BUSY) {
return E_BUSY;
}
}
MXC_DelayAbort();
return E_SUCCESS;
}
int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
{
mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
if (!mask) {
/* No bits set? Wasn't something we can enable. */
return E_BAD_PARAM;
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= mask;
return E_SUCCESS;
}
int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
{
mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
if (!mask) {
/* No bits set? Wasn't something we can enable. */
return E_BAD_PARAM;
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~mask;
return E_SUCCESS;
}
int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras)
{
// ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0);
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->toda = (ras << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS) & MXC_F_RTC_REVA_TODA_TOD_ALARM;
return E_SUCCESS;
}
int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa)
{
// ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0);
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->sseca = (rssa << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS) & MXC_F_RTC_REVA_SSECA_SSEC_ALARM;
return E_SUCCESS;
}
int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc)
{
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
// Can only write if WE=1 and BUSY=0
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
return E_SUCCESS;
}
int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc)
{
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
// Can only write if WE=1 and BUSY=0
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
return E_SUCCESS;
}
int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec)
{
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg.
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ssec = ssec;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->sec = sec;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing...
return E_SUCCESS;
}
int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
{
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
if (sqe == MXC_RTC_REVA_SQUARE_WAVE_ENABLED) {
if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected...
rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin
}
else { // if 1Hz, 512Hz, 4KHz output is selected
rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~ MXC_F_RTC_REVA_CTRL_SQW_SEL;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave,
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock
}
else { // Turn off the square wave output on the pin
rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output
}
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
return E_SUCCESS;
}
int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trim)
{
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_SETFIELD (rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS);
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register
return E_SUCCESS;
}
int MXC_RTC_RevA_GetFlags(void)
{
return MXC_RTC->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY);
}
int MXC_RTC_RevA_ClearFlags(int flags)
{
if (MXC_RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY));
return E_SUCCESS;
}
int MXC_RTC_RevA_GetSubSecond(void)
{
#if TARGET_NUM == 32650
int ssec;
if(ChipRevision > 0xA1){
ssec = ((MXC_PWRSEQ->ctrl >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF);
}else{
ssec = MXC_RTC->ssec;
}
return ssec;
#else
return MXC_RTC->ssec;
#endif
}
int MXC_RTC_RevA_GetSecond(void)
{
return MXC_RTC->sec;
}
int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec)
{
uint32_t temp_sec;
if (sec == NULL || subsec == NULL) {
return E_NULL_PTR;
}
do {
// Check if an update is about to happen.
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
return E_BUSY;
}
// Read the seconds count.
temp_sec = MXC_RTC_RevA_GetSecond();
// Check if an update is about to happen.
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
return E_BUSY;
}
// Read the sub-seconds count.
*subsec = MXC_RTC_RevA_GetSubSecond();
// Check if an update is about to happen.
if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
return E_BUSY;
}
// Read the seconds count.
*sec = MXC_RTC_RevA_GetSecond();
// Repeat until a steady state is reached.
}
while (temp_sec != *sec);
return E_NO_ERROR;
}

66
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h Normal file
View File

@ -0,0 +1,66 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
#include "mxc_device.h"
#include "rtc_reva_regs.h"
#include "rtc.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "gpio.h"
#include "mxc_errors.h"
typedef enum {
MXC_RTC_REVA_SQUARE_WAVE_DISABLED, ///< Sq. wave output disabled
MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled
} mxc_rtc_reva_sqwave_en_t;
#define MXC_RTC_REVA_CTRL_RESET_DEFAULT (0x0000UL)
#define MXC_RTC_REVA_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_BUSY)
#define MXC_RTC_REVA_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RTCE)
#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit
int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec);
int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask);
int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask);
int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras);
int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa);
int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc);
int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft);
int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trm);
int MXC_RTC_RevA_GetFlags (void);
int MXC_RTC_RevA_ClearFlags (int flags);
int MXC_RTC_RevA_GetSubSecond (void);
int MXC_RTC_RevA_GetSecond (void);
int MXC_RTC_RevA_GetTime (uint32_t* sec, uint32_t* subsec);

244
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h Normal file
View File

@ -0,0 +1,244 @@
/**
* @file rtc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _RTC_REVA_REGS_H_
#define _RTC_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup rtc
* @defgroup rtc_registers RTC_Registers
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @details Real Time Clock and Alarm.
*/
/**
* @ingroup rtc_registers
* Structure type to access the RTC Registers.
*/
typedef struct {
__IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */
__IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */
__IO uint32_t toda; /**< <tt>\b 0x08:</tt> RTC TODA Register */
__IO uint32_t sseca; /**< <tt>\b 0x0C:</tt> RTC SSECA Register */
__IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */
__IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */
__IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
} mxc_rtc_reva_regs_t;
/* Register offsets for module RTC */
/**
* @ingroup rtc_registers
* @defgroup RTC_Register_Offsets Register Offsets
* @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address.
* @{
*/
#define MXC_R_RTC_REVA_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
#define MXC_R_RTC_REVA_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
#define MXC_R_RTC_REVA_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
#define MXC_R_RTC_REVA_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
#define MXC_R_RTC_REVA_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
#define MXC_R_RTC_REVA_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
#define MXC_R_RTC_REVA_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
/**@} end of group rtc_registers */
/**
* @ingroup rtc_registers
* @defgroup RTC_SEC RTC_SEC
* @brief RTC Second Counter. This register contains the 32-bit second counter.
* @{
*/
#define MXC_F_RTC_REVA_SEC_SEC_POS 0 /**< SEC_SEC Position */
#define MXC_F_RTC_REVA_SEC_SEC ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SEC_SEC_POS)) /**< SEC_SEC Mask */
/**@} end of group RTC_SEC_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_SSEC RTC_SSEC
* @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented
* when this register rolls over from 0xFF to 0x00.
* @{
*/
#define MXC_F_RTC_REVA_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */
#define MXC_F_RTC_REVA_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */
/**@} end of group RTC_SSEC_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_TODA RTC_TODA
* @brief Time-of-day Alarm.
* @{
*/
#define MXC_F_RTC_REVA_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */
#define MXC_F_RTC_REVA_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */
/**@} end of group RTC_TODA_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_SSECA RTC_SSECA
* @brief RTC sub-second alarm. This register contains the reload value for the sub-
* second alarm.
* @{
*/
#define MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */
#define MXC_F_RTC_REVA_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */
/**@} end of group RTC_SSECA_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_CTRL RTC_CTRL
* @brief RTC Control Register.
* @{
*/
#define MXC_F_RTC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */
#define MXC_F_RTC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
#define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */
#define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */
#define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */
#define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */
#define MXC_F_RTC_REVA_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */
#define MXC_F_RTC_REVA_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
#define MXC_F_RTC_REVA_CTRL_RDY_POS 4 /**< CTRL_RDY Position */
#define MXC_F_RTC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
#define MXC_F_RTC_REVA_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */
#define MXC_F_RTC_REVA_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */
#define MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */
#define MXC_F_RTC_REVA_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */
#define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */
#define MXC_F_RTC_REVA_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */
#define MXC_F_RTC_REVA_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */
#define MXC_F_RTC_REVA_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */
#define MXC_F_RTC_REVA_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */
#define MXC_F_RTC_REVA_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */
#define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */
#define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */
#define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */
#define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */
#define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */
#define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */
#define MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */
#define MXC_S_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */
#define MXC_F_RTC_REVA_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */
#define MXC_F_RTC_REVA_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */
#define MXC_F_RTC_REVA_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */
#define MXC_F_RTC_REVA_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */
/**@} end of group RTC_CTRL_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_TRIM RTC_TRIM
* @brief RTC Trim Register.
* @{
*/
#define MXC_F_RTC_REVA_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
#define MXC_F_RTC_REVA_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
#define MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */
#define MXC_F_RTC_REVA_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */
/**@} end of group RTC_TRIM_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_OSCCTRL RTC_OSCCTRL
* @brief RTC Oscillator Control Register.
* @{
*/
#define MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
#define MXC_F_RTC_REVA_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
#define MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */
#define MXC_F_RTC_REVA_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */
/**@} end of group RTC_OSCCTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _RTC_REVA_REGS_H_ */

358
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c Normal file
View File

@ -0,0 +1,358 @@
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "spi_reva.h"
#include "dma.h"
/* **** Functions **** */
int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel)
{
if(numSlaves > MXC_SPI_SS_INSTANCES) {
return E_BAD_PARAM;
}
// Check if frequency is too high
if(hz > PeripheralClock) {
return E_BAD_PARAM;
}
// Configure GPIO for spi
if(spi == MXC_SPI0) {
MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI0;
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0);
MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI0D);
MXC_GPIO_Config(&gpio_cfg_spi0);
}
else {
return E_NO_DEVICE;
}
return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel);
}
int MXC_SPI_Shutdown(mxc_spi_regs_t* spi)
{
if(spi != MXC_SPI0) {
return E_NO_DEVICE;
}
MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t*) spi);
//
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI0D);
return E_NO_ERROR;
}
int MXC_SPI_ReadyForSleep(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_ReadyForSleep((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi)
{
if(spi == MXC_SPI0) {
return PeripheralClock;
}
else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int MXC_SPI_SetFrequency(mxc_spi_regs_t* spi, unsigned int hz)
{
return MXC_SPI_RevA_SetFrequency((mxc_spi_reva_regs_t*) spi, hz);
}
unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetFrequency((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_SetDataSize(mxc_spi_regs_t* spi, int dataSize)
{
return MXC_SPI_RevA_SetDataSize((mxc_spi_reva_regs_t*) spi, dataSize);
}
int MXC_SPI_GetDataSize(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetDataSize((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_SetSlave(mxc_spi_regs_t* spi, int ssIdx)
{
return MXC_SPI_RevA_SetSlave((mxc_spi_reva_regs_t*) spi, ssIdx);
}
int MXC_SPI_GetSlave(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetSlave((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_SetWidth(mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth)
{
return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_width_t)spiWidth);
}
mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t* spi)
{
return(mxc_spi_width_t) MXC_SPI_RevA_GetWidth((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode)
{
return MXC_SPI_RevA_SetMode ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_mode_t)spiMode);
}
mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi)
{
return (mxc_spi_mode_t) MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_StartTransmission(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_StartTransmission((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_GetActive(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetActive((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_AbortTransmission(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t*) spi);
}
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len)
{
return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len);
}
unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t*) spi);
}
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
unsigned int len)
{
return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len);
}
unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetTXFIFOAvailable((mxc_spi_reva_regs_t*) spi);
}
void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t* spi)
{
MXC_SPI_RevA_ClearRXFIFO((mxc_spi_reva_regs_t*) spi);
}
void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t* spi)
{
MXC_SPI_RevA_ClearTXFIFO((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_SetRXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes)
{
return MXC_SPI_RevA_SetRXThreshold((mxc_spi_reva_regs_t*) spi, numBytes);
}
unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetRXThreshold((mxc_spi_reva_regs_t*) spi);
}
int MXC_SPI_SetTXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes)
{
return MXC_SPI_RevA_SetTXThreshold((mxc_spi_reva_regs_t*) spi, numBytes);
}
unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetTXThreshold((mxc_spi_reva_regs_t*) spi);
}
unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t* spi)
{
return MXC_SPI_RevA_GetFlags((mxc_spi_reva_regs_t*) spi);
}
void MXC_SPI_ClearFlags(mxc_spi_regs_t* spi)
{
MXC_SPI_RevA_ClearFlags((mxc_spi_reva_regs_t*) spi);
}
void MXC_SPI_EnableInt(mxc_spi_regs_t* spi, unsigned int mask)
{
MXC_SPI_RevA_EnableInt((mxc_spi_reva_regs_t*) spi, mask);
}
void MXC_SPI_DisableInt(mxc_spi_regs_t* spi, unsigned int mask)
{
MXC_SPI_RevA_DisableInt((mxc_spi_reva_regs_t*) spi, mask);
}
int MXC_SPI_MasterTransaction(mxc_spi_req_t* req)
{
return MXC_SPI_RevA_MasterTransaction((mxc_spi_reva_req_t*) req);
}
int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t* req)
{
return MXC_SPI_RevA_MasterTransactionAsync((mxc_spi_reva_req_t*) req);
}
int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req)
{
int reqselTx = -1;
int reqselRx = -1;
int spi_num;
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);
if(req->txData != NULL) {
switch(spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;
case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;
default:
return E_BAD_PARAM;
}
}
if(req->rxData != NULL) {
switch(spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;
case 1:
reqselTx = MXC_DMA_REQUEST_SPI1RX;
break;
default:
return E_BAD_PARAM;
}
}
return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA);
}
int MXC_SPI_SlaveTransaction(mxc_spi_req_t* req)
{
return MXC_SPI_RevA_SlaveTransaction((mxc_spi_reva_req_t*) req);
}
int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t* req)
{
return MXC_SPI_RevA_SlaveTransactionAsync((mxc_spi_reva_req_t*) req);
}
int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req)
{
int reqselTx = -1;
int reqselRx = -1;
int spi_num;
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);
if(req->txData != NULL) {
switch(spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;
case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;
default:
return E_BAD_PARAM;
}
}
if(req->rxData != NULL) {
switch(spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;
case 1:
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;
default:
return E_BAD_PARAM;
}
}
return MXC_SPI_RevA_SlaveTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA);
}
int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t* spi, unsigned int defaultTXData)
{
return MXC_SPI_RevA_SetDefaultTXData((mxc_spi_reva_regs_t*) spi, defaultTXData);
}
void MXC_SPI_AbortAsync(mxc_spi_regs_t* spi)
{
MXC_SPI_RevA_AbortAsync((mxc_spi_reva_regs_t*) spi);
}
void MXC_SPI_AsyncHandler(mxc_spi_regs_t* spi)
{
MXC_SPI_RevA_AsyncHandler((mxc_spi_reva_regs_t*) spi);
}

1332
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c Normal file
View File

File diff suppressed because it is too large Load Diff

118
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h Normal file
View File

@ -0,0 +1,118 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "spi_regs.h"
#include "spi_reva_regs.h"
#include "mxc_spi.h"
#include "dma.h"
typedef enum {
SPI_REVA_WIDTH_3WIRE,
SPI_REVA_WIDTH_STANDARD,
SPI_REVA_WIDTH_DUAL,
SPI_REVA_WIDTH_QUAD,
} mxc_spi_reva_width_t;
typedef enum {
SPI_REVA_MODE_0,
SPI_REVA_MODE_1,
SPI_REVA_MODE_2,
SPI_REVA_MODE_3,
} mxc_spi_reva_mode_t;
typedef struct _mxc_spi_reva_req_t mxc_spi_reva_req_t;
struct _mxc_spi_reva_req_t {
mxc_spi_reva_regs_t* spi;
int ssIdx;
int ssDeassert;
uint8_t *txData;
uint8_t *rxData;
uint32_t txLen;
uint32_t rxLen;
uint32_t txCnt;
uint32_t rxCnt;
spi_complete_cb_t completeCB;
};
int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz);
unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize);
int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx);
int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth);
mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode);
mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi);
unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes,
unsigned int len);
unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes,
unsigned int len);
unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi);
unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi);
void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi);
void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes);
unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi);
int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes);
unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi);
unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi);
void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi);
void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int mask);
void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int mask);
int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req);
int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req);
int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req);
int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req);
int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
void MXC_SPI_RevA_DMACallback (int ch, int error);
int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData);
void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi);
void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi);

486
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h Normal file
View File

@ -0,0 +1,486 @@
/**
* @file spi_reva_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPI_REVA_REGS_H_
#define _SPI_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spi
* @defgroup spi_registers SPI_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
* @details SPI peripheral.
*/
/**
* @ingroup spi_registers
* Structure type to access the SPI Registers.
*/
typedef struct {
union{
__IO uint32_t fifo32; /**< <tt>\b 0x00:</tt> SPI FIFO32 Register */
__IO uint16_t fifo16[2]; /**< <tt>\b 0x00:</tt> SPI FIFO16 Register */
__IO uint8_t fifo8[4]; /**< <tt>\b 0x00:</tt> SPI FIFO8 Register */
};
__IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */
__IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
__IO uint32_t sstime; /**< <tt>\b 0x10:</tt> SPI SSTIME Register */
__IO uint32_t clkctrl; /**< <tt>\b 0x14:</tt> SPI CLKCTRL Register */
__R uint32_t rsv_0x18;
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */
__IO uint32_t intfl; /**< <tt>\b 0x20:</tt> SPI INTFL Register */
__IO uint32_t inten; /**< <tt>\b 0x24:</tt> SPI INTEN Register */
__IO uint32_t wkfl; /**< <tt>\b 0x28:</tt> SPI WKFL Register */
__IO uint32_t wken; /**< <tt>\b 0x2C:</tt> SPI WKEN Register */
__I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI STAT Register */
} mxc_spi_reva_regs_t;
/* Register offsets for module SPI */
/**
* @ingroup spi_registers
* @defgroup SPI_Register_Offsets Register Offsets
* @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address.
* @{
*/
#define MXC_R_SPI_REVA_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI_REVA_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI_REVA_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI_REVA_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPI_REVA_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPI_REVA_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPI_REVA_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */
#define MXC_R_SPI_REVA_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPI_REVA_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */
#define MXC_R_SPI_REVA_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */
#define MXC_R_SPI_REVA_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */
#define MXC_R_SPI_REVA_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */
#define MXC_R_SPI_REVA_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */
#define MXC_R_SPI_REVA_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */
/**@} end of group spi_registers */
/**
* @ingroup spi_registers
* @defgroup SPI_FIFO32 SPI_FIFO32
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI_REVA_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */
#define MXC_F_SPI_REVA_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_REVA_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */
/**@} end of group SPI_FIFO32_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_FIFO16 SPI_FIFO16
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI_REVA_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */
#define MXC_F_SPI_REVA_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_REVA_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */
/**@} end of group SPI_FIFO16_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_FIFO8 SPI_FIFO8
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI_REVA_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */
#define MXC_F_SPI_REVA_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_REVA_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */
/**@} end of group SPI_FIFO8_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CTRL0 SPI_CTRL0
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI_REVA_CTRL0_EN_POS 0 /**< CTRL0_EN Position */
#define MXC_F_SPI_REVA_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_EN_POS)) /**< CTRL0_EN Mask */
#define MXC_F_SPI_REVA_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */
#define MXC_F_SPI_REVA_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */
#define MXC_F_SPI_REVA_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */
#define MXC_F_SPI_REVA_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
#define MXC_F_SPI_REVA_CTRL0_START_POS 5 /**< CTRL0_START Position */
#define MXC_F_SPI_REVA_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_START_POS)) /**< CTRL0_START Mask */
#define MXC_F_SPI_REVA_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */
#define MXC_F_SPI_REVA_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
#define MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */
#define MXC_F_SPI_REVA_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */
#define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */
#define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */
#define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */
#define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */
#define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */
#define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */
#define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */
#define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */
/**@} end of group SPI_CTRL0_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CTRL1 SPI_CTRL1
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */
#define MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
#define MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */
#define MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
/**@} end of group SPI_CTRL1_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CTRL2 SPI_CTRL2
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI_REVA_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */
#define MXC_F_SPI_REVA_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */
#define MXC_F_SPI_REVA_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */
#define MXC_F_SPI_REVA_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */
#define MXC_F_SPI_REVA_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */
#define MXC_F_SPI_REVA_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */
#define MXC_V_SPI_REVA_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */
#define MXC_S_SPI_REVA_CTRL2_NUMBITS_0 (MXC_V_SPI_REVA_CTRL2_NUMBITS_0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */
#define MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */
#define MXC_F_SPI_REVA_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
#define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
#define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
#define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
#define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
#define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
#define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
#define MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */
#define MXC_F_SPI_REVA_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
#define MXC_F_SPI_REVA_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */
#define MXC_F_SPI_REVA_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
#define MXC_V_SPI_REVA_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */
#define MXC_S_SPI_REVA_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */
#define MXC_V_SPI_REVA_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */
#define MXC_S_SPI_REVA_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */
#define MXC_V_SPI_REVA_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */
#define MXC_S_SPI_REVA_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */
#define MXC_V_SPI_REVA_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */
#define MXC_S_SPI_REVA_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */
/**@} end of group SPI_CTRL2_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_SSTIME SPI_SSTIME
* @brief Register for controlling SPI peripheral/Slave Select Timing.
* @{
*/
#define MXC_F_SPI_REVA_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */
#define MXC_F_SPI_REVA_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */
#define MXC_V_SPI_REVA_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */
#define MXC_S_SPI_REVA_SSTIME_PRE_256 (MXC_V_SPI_REVA_SSTIME_PRE_256 << MXC_F_SPI_REVA_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */
#define MXC_F_SPI_REVA_SSTIME_POST_POS 8 /**< SSTIME_POST Position */
#define MXC_F_SPI_REVA_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_POST_POS)) /**< SSTIME_POST Mask */
#define MXC_V_SPI_REVA_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */
#define MXC_S_SPI_REVA_SSTIME_POST_256 (MXC_V_SPI_REVA_SSTIME_POST_256 << MXC_F_SPI_REVA_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */
#define MXC_F_SPI_REVA_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */
#define MXC_F_SPI_REVA_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */
#define MXC_V_SPI_REVA_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */
#define MXC_S_SPI_REVA_SSTIME_INACT_256 (MXC_V_SPI_REVA_SSTIME_INACT_256 << MXC_F_SPI_REVA_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */
/**@} end of group SPI_SSTIME_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_CLKCTRL SPI_CLKCTRL
* @brief Register for controlling SPI clock rate.
* @{
*/
#define MXC_F_SPI_REVA_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */
#define MXC_F_SPI_REVA_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */
#define MXC_V_SPI_REVA_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */
#define MXC_S_SPI_REVA_CLKCTRL_LO_DIS (MXC_V_SPI_REVA_CLKCTRL_LO_DIS << MXC_F_SPI_REVA_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */
#define MXC_F_SPI_REVA_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */
#define MXC_F_SPI_REVA_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */
#define MXC_V_SPI_REVA_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */
#define MXC_S_SPI_REVA_CLKCTRL_HI_DIS (MXC_V_SPI_REVA_CLKCTRL_HI_DIS << MXC_F_SPI_REVA_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */
#define MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */
#define MXC_F_SPI_REVA_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */
/**@} end of group SPI_CLKCTRL_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_DMA SPI_DMA
* @brief Register for controlling DMA.
* @{
*/
#define MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */
#define MXC_F_SPI_REVA_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */
#define MXC_F_SPI_REVA_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */
#define MXC_F_SPI_REVA_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
#define MXC_F_SPI_REVA_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */
#define MXC_F_SPI_REVA_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */
#define MXC_F_SPI_REVA_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */
#define MXC_F_SPI_REVA_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_REVA_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */
#define MXC_F_SPI_REVA_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */
#define MXC_F_SPI_REVA_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */
#define MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */
#define MXC_F_SPI_REVA_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */
#define MXC_F_SPI_REVA_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */
#define MXC_F_SPI_REVA_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
#define MXC_F_SPI_REVA_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */
#define MXC_F_SPI_REVA_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */
#define MXC_F_SPI_REVA_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */
#define MXC_F_SPI_REVA_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_REVA_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */
#define MXC_F_SPI_REVA_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */
#define MXC_F_SPI_REVA_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */
/**@} end of group SPI_DMA_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_INTFL SPI_INTFL
* @brief Register for reading and clearing interrupt flags. All bits are write 1 to
* clear.
* @{
*/
#define MXC_F_SPI_REVA_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */
#define MXC_F_SPI_REVA_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */
#define MXC_F_SPI_REVA_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */
#define MXC_F_SPI_REVA_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */
#define MXC_F_SPI_REVA_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */
#define MXC_F_SPI_REVA_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */
#define MXC_F_SPI_REVA_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */
#define MXC_F_SPI_REVA_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */
#define MXC_F_SPI_REVA_INTFL_SSA_POS 4 /**< INTFL_SSA Position */
#define MXC_F_SPI_REVA_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_SSA_POS)) /**< INTFL_SSA Mask */
#define MXC_F_SPI_REVA_INTFL_SSD_POS 5 /**< INTFL_SSD Position */
#define MXC_F_SPI_REVA_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_SSD_POS)) /**< INTFL_SSD Mask */
#define MXC_F_SPI_REVA_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */
#define MXC_F_SPI_REVA_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */
#define MXC_F_SPI_REVA_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */
#define MXC_F_SPI_REVA_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */
#define MXC_F_SPI_REVA_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */
#define MXC_F_SPI_REVA_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */
#define MXC_F_SPI_REVA_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */
#define MXC_F_SPI_REVA_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */
#define MXC_F_SPI_REVA_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */
#define MXC_F_SPI_REVA_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */
#define MXC_F_SPI_REVA_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */
#define MXC_F_SPI_REVA_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */
#define MXC_F_SPI_REVA_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */
#define MXC_F_SPI_REVA_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */
/**@} end of group SPI_INTFL_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_INTEN SPI_INTEN
* @brief Register for enabling interrupts.
* @{
*/
#define MXC_F_SPI_REVA_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */
#define MXC_F_SPI_REVA_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */
#define MXC_F_SPI_REVA_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */
#define MXC_F_SPI_REVA_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */
#define MXC_F_SPI_REVA_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */
#define MXC_F_SPI_REVA_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */
#define MXC_F_SPI_REVA_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */
#define MXC_F_SPI_REVA_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */
#define MXC_F_SPI_REVA_INTEN_SSA_POS 4 /**< INTEN_SSA Position */
#define MXC_F_SPI_REVA_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_SSA_POS)) /**< INTEN_SSA Mask */
#define MXC_F_SPI_REVA_INTEN_SSD_POS 5 /**< INTEN_SSD Position */
#define MXC_F_SPI_REVA_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_SSD_POS)) /**< INTEN_SSD Mask */
#define MXC_F_SPI_REVA_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */
#define MXC_F_SPI_REVA_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */
#define MXC_F_SPI_REVA_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */
#define MXC_F_SPI_REVA_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */
#define MXC_F_SPI_REVA_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */
#define MXC_F_SPI_REVA_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */
#define MXC_F_SPI_REVA_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */
#define MXC_F_SPI_REVA_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */
#define MXC_F_SPI_REVA_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */
#define MXC_F_SPI_REVA_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */
#define MXC_F_SPI_REVA_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */
#define MXC_F_SPI_REVA_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */
#define MXC_F_SPI_REVA_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */
#define MXC_F_SPI_REVA_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */
/**@} end of group SPI_INTEN_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_WKFL SPI_WKFL
* @brief Register for wake up flags. All bits in this register are write 1 to clear.
* @{
*/
#define MXC_F_SPI_REVA_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */
#define MXC_F_SPI_REVA_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */
#define MXC_F_SPI_REVA_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */
#define MXC_F_SPI_REVA_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */
#define MXC_F_SPI_REVA_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */
#define MXC_F_SPI_REVA_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */
#define MXC_F_SPI_REVA_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */
#define MXC_F_SPI_REVA_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */
/**@} end of group SPI_WKFL_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_WKEN SPI_WKEN
* @brief Register for wake up enable.
* @{
*/
#define MXC_F_SPI_REVA_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */
#define MXC_F_SPI_REVA_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */
#define MXC_F_SPI_REVA_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */
#define MXC_F_SPI_REVA_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */
#define MXC_F_SPI_REVA_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */
#define MXC_F_SPI_REVA_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */
#define MXC_F_SPI_REVA_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */
#define MXC_F_SPI_REVA_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */
/**@} end of group SPI_WKEN_Register */
/**
* @ingroup spi_registers
* @defgroup SPI_STAT SPI_STAT
* @brief SPI Status register.
* @{
*/
#define MXC_F_SPI_REVA_STAT_BUSY_POS 0 /**< STAT_BUSY Position */
#define MXC_F_SPI_REVA_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_REVA_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
/**@} end of group SPI_STAT_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPI_REVA_REGS_H_ */

124
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c Normal file
View File

@ -0,0 +1,124 @@
/**
* @file i2s.c
* @brief Inter-Integrated Sound (I2S) driver implementation.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#include <stddef.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_pins.h"
#include "dma.h"
#include "i2s.h"
#include "i2s_reva.h"
#include "spimss.h"
#include "spimss_regs.h"
#define I2S_CHANNELS 2
#define I2S_WIDTH 16
int dma_channel = -1;
int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int))
{
if(config->map == I2S_MAP_A) {
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPIMSS: I2S and SPI share pins
}
else if(config->map == I2S_MAP_B) {
MXC_GPIO_Config(&gpio_cfg_spi1b);
}
else {
return E_BAD_PARAM;
}
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 clock used for SPIMSS
return MXC_I2S_RevA_Init((mxc_spimss_reva_regs_t*) MXC_SPIMSS, config, dma_ctz_cb);
}
int MXC_I2S_Shutdown(void)
{
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 used for SPIMSS
return MXC_I2S_RevA_Shutdown((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
}
int MXC_I2S_Mute(void)
{
return MXC_I2S_RevA_Mute((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
}
int MXC_I2S_Unmute(void)
{
return MXC_I2S_RevA_Unmute((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
}
int MXC_I2S_Pause(void)
{
return MXC_I2S_RevA_Pause((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
}
int MXC_I2S_Unpause(void)
{
return MXC_I2S_RevA_Unpause((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
}
int MXC_I2S_Stop(void)
{
return MXC_I2S_RevA_Stop((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
}
int MXC_I2S_Start(void)
{
return MXC_I2S_RevA_Start((mxc_spimss_reva_regs_t*) MXC_SPIMSS);
}
int MXC_I2S_DMA_ClearFlags(void)
{
return MXC_I2S_RevA_DMA_ClearFlags();
}
int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count)
{
return MXC_I2S_RevA_DMA_SetAddrCnt(src_addr, dst_addr, count);
}
int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count)
{
return MXC_I2S_RevA_DMA_SetReload(src_addr, dst_addr, count);
}

264
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c Normal file
View File

@ -0,0 +1,264 @@
/**
* @file i2s.c
* @brief Inter-Integrated Sound(I2S) driver implementation.
*/
/* ****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#include <stddef.h>
#include <stdint.h>
#include "mxc_errors.h"
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "dma.h"
#include "i2s.h"
#include "i2s_reva.h"
#include "spimss.h"
#include "spimss_reva.h"
#define I2S_CHANNELS 2
#define I2S_WIDTH 16
static int dma_channel = -1;
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int))
{
unsigned int baud;
uint16_t clkdiv;
uint8_t ctz_en;
int err;
mxc_dma_config_t dma_config;
mxc_dma_srcdst_t srcdst;
/* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */
spimss->ctrl = MXC_F_SPIMSS_REVA_CTRL_MMEN;
spimss->mode = MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO;
spimss->dma = MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8;
/* Setup I2S register from i2s_cfg_t */
spimss->i2s_ctrl = config->justify << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS |
config->audio_mode << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS;
/* Determine divisor for baud rate generator */
baud = config->sample_rate * I2S_CHANNELS * I2S_WIDTH;
if((PeripheralClock / 4) < baud) {
return E_BAD_PARAM;
}
clkdiv = PeripheralClock / (2 * baud); // Peripheral clock in system_max*****.h
if(clkdiv < 2) {
return E_BAD_PARAM;
}
spimss->brg = clkdiv;
/* Prepare SPIMSS DMA register for DMA setup */
if(dma_ctz_cb == NULL) {
ctz_en = 0;
} else {
ctz_en = 1;
}
/* Initialize DMA */
if(config->audio_direction % 2) {
spimss->dma |= MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR;
if((err = MXC_DMA_Init()) != E_NO_ERROR) {
if(err != E_BAD_STATE) {
return err;
}
}
if((err = MXC_DMA_AcquireChannel()) < 0) {
return err;
}
dma_channel = err;
dma_config.ch = dma_channel;
dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD;
dma_config.dstwd = MXC_DMA_WIDTH_WORD;
#if TARGET_NUM == 32650
dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSTX;
#endif
dma_config.srcinc_en = 1;
dma_config.dstinc_en = 0;
srcdst.ch = dma_channel;
srcdst.source = config->src_addr;
srcdst.len = config->length;
MXC_DMA_ConfigChannel(dma_config, srcdst);
MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1);
MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS);
if(ctz_en) {
MXC_DMA_SetCallback(dma_channel, dma_ctz_cb);
MXC_DMA_EnableInt(dma_channel);
}
}
if(config->audio_direction / 2) {
spimss->dma = MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR;
if((err = MXC_DMA_Init()) != E_NO_ERROR) {
if(err != E_BAD_STATE) { //DMA already initialized
return err;
}
}
if((err = MXC_DMA_AcquireChannel()) < 0) {
return err;
}
dma_channel = err;
dma_config.ch = dma_channel;
dma_config.srcwd = MXC_DMA_WIDTH_WORD;
dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD;
#if TARGET_NUM == 32650
dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSRX;
#endif
dma_config.srcinc_en = 0;
dma_config.dstinc_en = 1;
srcdst.ch = dma_channel;
srcdst.dest = config->dst_addr;
srcdst.len = config->length;
MXC_DMA_ConfigChannel(dma_config, srcdst);
MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1);
MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST;
MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS);
if(ctz_en) {
MXC_DMA_SetCallback(dma_channel, dma_ctz_cb);
MXC_DMA_EnableInt(dma_channel);
}
}
MXC_I2S_DMA_SetAddrCnt(config->src_addr, config->dst_addr, config->length);
if(config->dma_reload_en) {
MXC_I2S_DMA_SetReload(config->src_addr, config->dst_addr, config->length);
}
if(config->start_immediately) {
return MXC_I2S_Start();
}
return E_NO_ERROR;
}
int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss)
{
spimss->ctrl = 0;
spimss->i2s_ctrl = 0;
spimss->brg = 0;
spimss->mode = 0;
spimss->dma = 0;
return MXC_DMA_ReleaseChannel(dma_channel);
}
int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss)
{
spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE;
return E_NO_ERROR;
}
int MXC_I2S_RevA_Unmute(mxc_spimss_reva_regs_t *spimss)
{
spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE;
return E_NO_ERROR;
}
int MXC_I2S_RevA_Pause(mxc_spimss_reva_regs_t *spimss)
{
spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE;
return E_NO_ERROR;
}
int MXC_I2S_RevA_Unpause(mxc_spimss_reva_regs_t *spimss)
{
spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE;
return E_NO_ERROR;
}
int MXC_I2S_RevA_Stop(mxc_spimss_reva_regs_t *spimss)
{
spimss->ctrl &= ~MXC_F_SPIMSS_REVA_CTRL_ENABLE;
spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN;
return MXC_DMA_Stop(dma_channel);
}
int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss)
{
spimss->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE;
spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN;
return MXC_DMA_Start(dma_channel);
}
int MXC_I2S_RevA_DMA_ClearFlags(void)
{
int flags = MXC_DMA_ChannelGetFlags(dma_channel);
return MXC_DMA_ChannelClearFlags(dma_channel, flags);
}
int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count)
{
mxc_dma_srcdst_t srcdst;
srcdst.ch = dma_channel;
srcdst.source = src_addr;
srcdst.dest = dst_addr;
srcdst.len = count;
return MXC_DMA_SetSrcDst(srcdst);
}
int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count)
{
mxc_dma_srcdst_t srcdst;
srcdst.ch = dma_channel;
srcdst.source = src_addr;
srcdst.dest = dst_addr;
srcdst.len = count;
return MXC_DMA_SetSrcReload(srcdst);
}

52
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h Normal file
View File

@ -0,0 +1,52 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include "i2s.h"
#include "spimss_reva_regs.h"
int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req, void (*dma_ctz_cb)(int, int));
int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Unmute(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Pause(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Unpause(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Stop(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss);
int MXC_I2S_RevA_DMA_ClearFlags(void);
int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);

131
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c Normal file
View File

@ -0,0 +1,131 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "spimss_reva_regs.h"
#include "spimss_reva.h"
/* **** Functions **** */
/* ************************************************************************** */
int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel)
{
if (mode > 3) {
return E_BAD_PARAM;
}
// Check if frequency is too high
if (freq > PeripheralClock) {
return E_BAD_PARAM;
}
// Configure GPIO for spimss
if (spi == MXC_SPIMSS) {
MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI1;
while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1);
MXC_GCR->pclk_dis0 &= ~ (MXC_F_GCR_PCLK_DIS0_SPI1D);
if(sys_cfg == MAP_A){
MXC_GPIO_Config(&gpio_cfg_spi1a); // SPI1A chosen
}else if(sys_cfg == MAP_B){
MXC_GPIO_Config(&gpio_cfg_spi1b); // SPI1B chosen
}else{
return E_BAD_PARAM;
}
} else {
return E_NO_DEVICE;
}
return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t*) spi, mode, freq, drv_ssel);
}
/* ************************************************************************* */
int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
{
if(spi != MXC_SPIMSS) {
return E_NO_DEVICE;
}
MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t*) spi);
//
MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D);
return E_NO_ERROR;
}
/* ************************************************************************** */
void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ
{
MXC_SPIMSS_RevA_Handler((mxc_spimss_reva_regs_t*) spi);
}
/* ************************************************************************** */
int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
{
return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
}
/* ************************************************************************** */
int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
{
return MXC_SPIMSS_RevA_SlaveTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
}
/* ************************************************************************** */
int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
{
return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
}
/* ************************************************************************** */
int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req)
{
return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req);
}
/* ************************************************************************* */
int MXC_SPIMSS_SetDefaultTXData(mxc_spimss_req_t* spi, unsigned int defaultTXData)
{
return MXC_SPIMSS_RevA_SetDefaultTXData((spimss_reva_req_t*) spi, defaultTXData);
}
/* ************************************************************************* */
int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req)
{
return MXC_SPIMSS_RevA_AbortAsync((spimss_reva_req_t*) req);
}

515
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c Normal file
View File

@ -0,0 +1,515 @@
/**
* @file spimss.c
* @brief This file contains the function implementations for the
* Serial Peripheral Interface (SPIMSS) peripheral module.
*/
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
**************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include <stdio.h>
#include <stdint.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "spimss_reva.h"
#include "mxc_lock.h"
/**
* @ingroup spimss
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
typedef struct {
spimss_reva_req_t *req;
unsigned defaultTXData;
unsigned drv_ssel;
} spimss_reva_req_state_t;
static spimss_reva_req_state_t states[MXC_SPIMSS_INSTANCES];
/* **** Functions **** */
static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, int master);
static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
static uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
/* ************************************************************************** */
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel)
{
int spi_num;
unsigned int spimss_clk;
unsigned int pol, pha; // Polarity and phase of the clock (SPI mode)
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
states[spi_num].req = NULL;
states[spi_num].defaultTXData = 0;
states[spi_num].drv_ssel = drv_ssel;
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start)
// Set the bit rate
spimss_clk = PeripheralClock;
spi->brg = (spimss_clk / freq) >> 1;
// Set the mode
pol = mode >> 1; // Get the polarity out of the mode input value
pha = mode & 1; // Get the phase out of the mode input value
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase
spi->int_fl &= ~(MXC_F_SPIMSS_REVA_INT_FL_IRQ);
return E_NO_ERROR;
}
/* ************************************************************************* */
int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi)
{
int spi_num;
spimss_reva_req_t *temp_req;
// Disable and turn off the SPI transaction.
spi->ctrl = 0; // Interrupts, SPI transaction all turned off
spi->int_fl = 0;
spi->mode = 0;
// Reset FIFO counters
spi->dma &= ~(MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT);
// Call all of the pending callbacks for this SPI
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
if (states[spi_num].req != NULL) {
// Save the request
temp_req = states[spi_num].req;
// Unlock this SPI
MXC_FreeLock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (temp_req->callback != NULL) {
temp_req->callback(temp_req, E_SHUTDOWN);
}
}
spi->int_fl = 0;
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, int master)
{
int spi_num;
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Make sure the Initiation
// of SPI Start is disabled.
spi->mode |= MXC_F_SPIMSS_REVA_MODE_TX_LJ; // Making sure data is left
// justified.
if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
return -1;
}
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
MXC_ASSERT(spi_num >= 0);
if (req->len == 0) {
return 0;
}
req->tx_num = 0;
req->rx_num = 0;
if (MXC_GetLock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) {
return E_BUSY;
}
if (master) { // Enable master mode
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master.
if (states[spi_num].drv_ssel) {
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SS_IO; // SSEL pin is an output.
}
} else { // Enable slave mode
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave.
spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SS_IO); // SSEL pin is an input.
}
// Setup the character size
if (req->bits <16) {
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
} else {
MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS);
}
if (req->tx_data == NULL) {
// Must have something to send, so we'll use the rx_data buffer initialized to 0.
memset(req->rx_data, states[spi_num].defaultTXData, (req->bits > 8 ? req->len << 1 : req->len));
req->tx_data = req->rx_data;
}
// Clear the TX and RX FIFO
spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR);
if (states[spi_num].drv_ssel) {
// Setup the slave select
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select,
// to get the line ready for active low later
}
return E_NO_ERROR;
}
/* ************************************************************************** */
void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ
{
int spi_num;
uint32_t flags;
unsigned int int_enable;
flags = spi->int_fl;
spi->int_fl = flags;
spi->int_fl|= 0x80; // clear interrupt
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
int_enable = 0;
if (states[spi_num].req != NULL) {
if ((spi->ctrl & MXC_F_SPIMSS_REVA_CTRL_MMEN) >> MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) {
int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, states[spi_num].req);
} else {
int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, states[spi_num].req);
}
}
if (int_enable==1) {
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE );
}
}
/* ************************************************************************** */
int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
int error;
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) {
return error;
}
req->callback = NULL;
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
if (states[spi_num].drv_ssel) {
spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select.
}
while (MXC_SPIMSS_RevA_MasterTransHandler(spi,req)!=0) {
;
}
if (states[spi_num].drv_ssel) {
spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV;
}
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
// stop the transmission...
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
int error;
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req,0)) != E_NO_ERROR) {
return error;
}
while (MXC_SPIMSS_RevA_SlaveTransHandler(spi,req)!=0) {
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
while ((spi->int_fl & MXC_F_SPIMSS_REVA_INT_FL_TXST) == MXC_F_SPIMSS_REVA_INT_FL_TXST) {}
}
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted...
// stop the transmission...
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
int error;
uint8_t int_enable;
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1) )!= E_NO_ERROR) {
return error;
}
int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi,req);
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
if (states[spi_num].drv_ssel) {
spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select.
}
if (int_enable==1) {
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
int error;
uint8_t int_enable;
if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 0)) != E_NO_ERROR) {
return error;
}
int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi,req);
spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI
if (int_enable==1) { // Trigger a SPI Interrupt
spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE );
}
return E_NO_ERROR;
}
/* ************************************************************************** */
uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
unsigned start_set = 0;
uint32_t retval;
if (!start_set) {
start_set = 1;
retval = MXC_SPIMSS_RevA_TransHandler(spi,req);
}
return retval;
}
/* ************************************************************************** */
uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
return MXC_SPIMSS_RevA_TransHandler(spi,req);
}
/* ************************************************************************** */
uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req)
{
unsigned tx_avail, rx_avail;
int remain, spi_num;
uint32_t int_en =0;
uint32_t length =req->len;
spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
if (spi_num < 0) {
MXC_ASSERT(0);
}
// Note:- spi->dma shows the FIFO TX count and FIFO RX count in
// Words, while the calculation below is in bytes.
if (req->tx_data != NULL) {
if (req->tx_num < length) {
// Calculate how many bytes we can write to the FIFO (tx_avail holds that value)
tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes
if ((length - req->tx_num) < tx_avail) {
tx_avail = (length - req->tx_num); // This is for the last spin
}
if (req->bits > 8) {
tx_avail &= ~(unsigned)0x1;
}
// Write the FIFO
while (tx_avail) {
if (req->bits >8) {
spi->data = ((uint16_t*)req->tx_data)[req->tx_num++];
tx_avail -= 1;
} else {
spi->data = ((uint8_t*)req->tx_data)[req->tx_num++];
tx_avail -=1;
}
}
}
remain = length - req->tx_num;
// If there are values remaining to be transmitted, this portion will get
// executed and int_en set, to indicate that this must spin and come back again...
if (remain) {
if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum,
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
} else { // only one more tx round will be done... Transfer whatever remains,
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS));
}
int_en = 1; // This will act as a trigger for the next round...
}
// Break out if we've transmitted all the bytes and not receiving
if ((req->rx_data == NULL) && (req->tx_num == length)) {
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
int_en = 0;
MXC_FreeLock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
}
}
// Read the RX FIFO
// Wait for there to be data in the RX FIFO
uint16_t rx_data;
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
// Read from the FIFO
while (rx_avail) {
rx_data = spi->data;
rx_avail -= 1;
if (req->rx_data != NULL) {
if (req->bits>8) {
((uint16_t*)req->rx_data)[req->rx_num] = rx_data;
} else {
((uint8_t*)req->rx_data)[req->rx_num] = rx_data;
}
}
req->rx_num++; // assume read one byte
rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
}
remain = length - req->rx_num;
if (remain) {
if (remain > MXC_SPIMSS_FIFO_DEPTH) {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
} else {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS));
}
int_en = 1;
}
// Break out once we've transmitted and received all of the data
if ((req->rx_num == length) && (req->tx_num == length)) {
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
int_en = 0;
MXC_FreeLock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
}
return int_en;
}
/* ************************************************************************* */
int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData)
{
int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi);
MXC_ASSERT (spi_num >= 0);
states[spi_num].defaultTXData = defaultTXData;
return E_NO_ERROR;
}
/* ************************************************************************* */
int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req)
{
int spi_num;
mxc_spimss_reva_regs_t *spi;
// Check the input parameters
if (req == NULL) {
return E_BAD_PARAM;
}
// Find the request, set to NULL
for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) {
if (req == states[spi_num].req) {
spi =(mxc_spimss_reva_regs_t *) MXC_SPIMSS_GET_SPI(spi_num);
// Disable interrupts, clear the flags
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR);
// Disable and turn off the SPI transaction.
spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE);
// Unlock this SPI
MXC_FreeLock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_ABORT);
}
return E_NO_ERROR;
}
}
return E_BAD_PARAM;
}
/**@} end of group spimss */

104
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h Normal file
View File

@ -0,0 +1,104 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include "mxc_errors.h"
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "spimss_regs.h"
#include "spimss_reva_regs.h"
#include "spimss.h"
/**
* @brief Enumeration type for setting the number data lines to use for communication.
*/
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
DUMMY_1_RevA, /**< NOT USED */
DUMMY_2_RevA, /**< NOT USED */
DUMMY_3_RevA, /**< NOT USED */
} spimss_reva_width_t;
/**
* @brief Structure type representing a SPI Master Transaction request.
*/
typedef struct spimss_reva_req spimss_reva_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
* @addtogroup spi_async
*/
typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
* @addtogroup spi_async
*/
struct spimss_reva_req {
uint8_t ssel; /**< Not Used*/
uint8_t deass; /**< Not Used*/
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
spimss_reva_width_t width; /**< Not Used */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel);
int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi);
void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi);
int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req);
int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData);
int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req);

460
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h Normal file
View File

@ -0,0 +1,460 @@
/**
* @file spimss_reva_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPIMSS_REVA_REGS_H_
#define _SPIMSS_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spimss
* @defgroup spimss_registers SPIMSS_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
* @details Serial Peripheral Interface.
*/
/**
* @ingroup spimss_registers
* Structure type to access the SPIMSS Registers.
*/
typedef struct {
__IO uint16_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */
__R uint16_t rsv_0x2;
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
__IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */
__IO uint32_t mode; /**< <tt>\b 0x0C:</tt> SPIMSS MODE Register */
__R uint32_t rsv_0x10;
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
} mxc_spimss_reva_regs_t;
/* Register offsets for module SPIMSS */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_Register_Offsets Register Offsets
* @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address.
* @{
*/
#define MXC_R_SPIMSS_REVA_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPIMSS_REVA_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPIMSS_REVA_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPIMSS_REVA_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPIMSS_REVA_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPIMSS_REVA_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */
#define MXC_R_SPIMSS_REVA_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */
/**@} end of group spimss_registers */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DATA SPIMSS_DATA
* @brief SPI 16-bit Data Access
* @{
*/
#define MXC_F_SPIMSS_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_SPIMSS_REVA_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group SPIMSS_DATA_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_CTRL SPIMSS_CTRL
* @brief SPI Control Register.
* @{
*/
#define MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
#define MXC_F_SPIMSS_REVA_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
#define MXC_V_SPIMSS_REVA_CTRL_ENABLE_DISABLE ((uint32_t)0x0UL) /**< CTRL_ENABLE_DISABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_ENABLE_DISABLE (MXC_V_SPIMSS_REVA_CTRL_ENABLE_DISABLE << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_CTRL_ENABLE_ENABLE ((uint32_t)0x1UL) /**< CTRL_ENABLE_ENABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_ENABLE_ENABLE (MXC_V_SPIMSS_REVA_CTRL_ENABLE_ENABLE << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS) /**< CTRL_ENABLE_ENABLE Setting */
#define MXC_F_SPIMSS_REVA_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */
#define MXC_F_SPIMSS_REVA_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */
#define MXC_V_SPIMSS_REVA_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */
#define MXC_S_SPIMSS_REVA_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_REVA_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */
#define MXC_V_SPIMSS_REVA_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */
#define MXC_S_SPIMSS_REVA_CTRL_MMEN_MASTER (MXC_V_SPIMSS_REVA_CTRL_MMEN_MASTER << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */
#define MXC_F_SPIMSS_REVA_CTRL_WOR_POS 2 /**< CTRL_WOR Position */
#define MXC_F_SPIMSS_REVA_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_WOR_POS)) /**< CTRL_WOR Mask */
#define MXC_V_SPIMSS_REVA_CTRL_WOR_DISABLE ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_WOR_DISABLE (MXC_V_SPIMSS_REVA_CTRL_WOR_DISABLE << MXC_F_SPIMSS_REVA_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_CTRL_WOR_ENABLE ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_WOR_ENABLE (MXC_V_SPIMSS_REVA_CTRL_WOR_ENABLE << MXC_F_SPIMSS_REVA_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */
#define MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */
#define MXC_F_SPIMSS_REVA_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */
#define MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */
#define MXC_S_SPIMSS_REVA_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */
#define MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */
#define MXC_S_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */
#define MXC_F_SPIMSS_REVA_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */
#define MXC_F_SPIMSS_REVA_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */
#define MXC_V_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */
#define MXC_S_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */
#define MXC_V_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */
#define MXC_S_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */
#define MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */
#define MXC_F_SPIMSS_REVA_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */
#define MXC_V_SPIMSS_REVA_CTRL_BIRQ_DISABLE ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_BIRQ_DISABLE (MXC_V_SPIMSS_REVA_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_CTRL_BIRQ_ENABLE ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_BIRQ_ENABLE (MXC_V_SPIMSS_REVA_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */
#define MXC_F_SPIMSS_REVA_CTRL_STR_POS 6 /**< CTRL_STR Position */
#define MXC_F_SPIMSS_REVA_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_STR_POS)) /**< CTRL_STR Mask */
#define MXC_V_SPIMSS_REVA_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */
#define MXC_S_SPIMSS_REVA_CTRL_STR_COMPLETE (MXC_V_SPIMSS_REVA_CTRL_STR_COMPLETE << MXC_F_SPIMSS_REVA_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */
#define MXC_V_SPIMSS_REVA_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */
#define MXC_S_SPIMSS_REVA_CTRL_STR_START (MXC_V_SPIMSS_REVA_CTRL_STR_START << MXC_F_SPIMSS_REVA_CTRL_STR_POS) /**< CTRL_STR_START Setting */
#define MXC_F_SPIMSS_REVA_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */
#define MXC_F_SPIMSS_REVA_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */
#define MXC_V_SPIMSS_REVA_CTRL_IRQE_DISABLE ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_IRQE_DISABLE (MXC_V_SPIMSS_REVA_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_CTRL_IRQE_ENABLE ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */
#define MXC_S_SPIMSS_REVA_CTRL_IRQE_ENABLE (MXC_V_SPIMSS_REVA_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */
/**@} end of group SPIMSS_CTRL_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_INT_FL SPIMSS_INT_FL
* @brief SPI Interrupt Flag Register.
* @{
*/
#define MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */
#define MXC_F_SPIMSS_REVA_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_SLAS_SELECTED ((uint32_t)0x0UL) /**< INT_FL_SLAS_SELECTED Value */
#define MXC_S_SPIMSS_REVA_INT_FL_SLAS_SELECTED (MXC_V_SPIMSS_REVA_INT_FL_SLAS_SELECTED << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS) /**< INT_FL_SLAS_SELECTED Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< INT_FL_SLAS_NOTSELECTED Value */
#define MXC_S_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED (MXC_V_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS) /**< INT_FL_SLAS_NOTSELECTED Setting */
#define MXC_F_SPIMSS_REVA_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */
#define MXC_F_SPIMSS_REVA_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_TXST_IDLE ((uint32_t)0x0UL) /**< INT_FL_TXST_IDLE Value */
#define MXC_S_SPIMSS_REVA_INT_FL_TXST_IDLE (MXC_V_SPIMSS_REVA_INT_FL_TXST_IDLE << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS) /**< INT_FL_TXST_IDLE Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_TXST_BUSY ((uint32_t)0x1UL) /**< INT_FL_TXST_BUSY Value */
#define MXC_S_SPIMSS_REVA_INT_FL_TXST_BUSY (MXC_V_SPIMSS_REVA_INT_FL_TXST_BUSY << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS) /**< INT_FL_TXST_BUSY Setting */
#define MXC_F_SPIMSS_REVA_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */
#define MXC_F_SPIMSS_REVA_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_TUND_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TUND_NOEVENT Value */
#define MXC_S_SPIMSS_REVA_INT_FL_TUND_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_TUND_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS) /**< INT_FL_TUND_NOEVENT Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_TUND_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_TUND_OCCURRED Value */
#define MXC_S_SPIMSS_REVA_INT_FL_TUND_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_TUND_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS) /**< INT_FL_TUND_OCCURRED Setting */
#define MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */
#define MXC_F_SPIMSS_REVA_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_ROVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ROVR_NOEVENT Value */
#define MXC_S_SPIMSS_REVA_INT_FL_ROVR_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_ROVR_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS) /**< INT_FL_ROVR_NOEVENT Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_ROVR_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_ROVR_OCCURRED Value */
#define MXC_S_SPIMSS_REVA_INT_FL_ROVR_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_ROVR_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS) /**< INT_FL_ROVR_OCCURRED Setting */
#define MXC_F_SPIMSS_REVA_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */
#define MXC_F_SPIMSS_REVA_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_ABT_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ABT_NOEVENT Value */
#define MXC_S_SPIMSS_REVA_INT_FL_ABT_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_ABT_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS) /**< INT_FL_ABT_NOEVENT Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_ABT_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_ABT_OCCURRED Value */
#define MXC_S_SPIMSS_REVA_INT_FL_ABT_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_ABT_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS) /**< INT_FL_ABT_OCCURRED Setting */
#define MXC_F_SPIMSS_REVA_INT_FL_COL_POS 5 /**< INT_FL_COL Position */
#define MXC_F_SPIMSS_REVA_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_COL_POS)) /**< INT_FL_COL Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_COL_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_COL_NOEVENT Value */
#define MXC_S_SPIMSS_REVA_INT_FL_COL_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_COL_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_COL_POS) /**< INT_FL_COL_NOEVENT Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_COL_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_COL_OCCURRED Value */
#define MXC_S_SPIMSS_REVA_INT_FL_COL_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_COL_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_COL_POS) /**< INT_FL_COL_OCCURRED Setting */
#define MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */
#define MXC_F_SPIMSS_REVA_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_TOVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TOVR_NOEVENT Value */
#define MXC_S_SPIMSS_REVA_INT_FL_TOVR_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_TOVR_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS) /**< INT_FL_TOVR_NOEVENT Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_TOVR_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_TOVR_OCCURRED Value */
#define MXC_S_SPIMSS_REVA_INT_FL_TOVR_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_TOVR_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS) /**< INT_FL_TOVR_OCCURRED Setting */
#define MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */
#define MXC_F_SPIMSS_REVA_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */
#define MXC_V_SPIMSS_REVA_INT_FL_IRQ_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IRQ_INACTIVE Value */
#define MXC_S_SPIMSS_REVA_INT_FL_IRQ_INACTIVE (MXC_V_SPIMSS_REVA_INT_FL_IRQ_INACTIVE << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS) /**< INT_FL_IRQ_INACTIVE Setting */
#define MXC_V_SPIMSS_REVA_INT_FL_IRQ_PENDING ((uint32_t)0x1UL) /**< INT_FL_IRQ_PENDING Value */
#define MXC_S_SPIMSS_REVA_INT_FL_IRQ_PENDING (MXC_V_SPIMSS_REVA_INT_FL_IRQ_PENDING << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS) /**< INT_FL_IRQ_PENDING Setting */
/**@} end of group SPIMSS_INT_FL_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_MODE SPIMSS_MODE
* @brief SPI Mode Register.
* @{
*/
#define MXC_F_SPIMSS_REVA_MODE_SSV_POS 0 /**< MODE_SSV Position */
#define MXC_F_SPIMSS_REVA_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_SSV_POS)) /**< MODE_SSV Mask */
#define MXC_V_SPIMSS_REVA_MODE_SSV_LO ((uint32_t)0x0UL) /**< MODE_SSV_LO Value */
#define MXC_S_SPIMSS_REVA_MODE_SSV_LO (MXC_V_SPIMSS_REVA_MODE_SSV_LO << MXC_F_SPIMSS_REVA_MODE_SSV_POS) /**< MODE_SSV_LO Setting */
#define MXC_V_SPIMSS_REVA_MODE_SSV_HI ((uint32_t)0x1UL) /**< MODE_SSV_HI Value */
#define MXC_S_SPIMSS_REVA_MODE_SSV_HI (MXC_V_SPIMSS_REVA_MODE_SSV_HI << MXC_F_SPIMSS_REVA_MODE_SSV_POS) /**< MODE_SSV_HI Setting */
#define MXC_F_SPIMSS_REVA_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */
#define MXC_F_SPIMSS_REVA_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */
#define MXC_V_SPIMSS_REVA_MODE_SS_IO_INPUT ((uint32_t)0x0UL) /**< MODE_SS_IO_INPUT Value */
#define MXC_S_SPIMSS_REVA_MODE_SS_IO_INPUT (MXC_V_SPIMSS_REVA_MODE_SS_IO_INPUT << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS) /**< MODE_SS_IO_INPUT Setting */
#define MXC_V_SPIMSS_REVA_MODE_SS_IO_OUTPUT ((uint32_t)0x1UL) /**< MODE_SS_IO_OUTPUT Value */
#define MXC_S_SPIMSS_REVA_MODE_SS_IO_OUTPUT (MXC_V_SPIMSS_REVA_MODE_SS_IO_OUTPUT << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS) /**< MODE_SS_IO_OUTPUT Setting */
#define MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */
#define MXC_F_SPIMSS_REVA_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */
#define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */
#define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */
#define MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */
#define MXC_F_SPIMSS_REVA_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */
#define MXC_V_SPIMSS_REVA_MODE_TX_LJ_DISABLE ((uint32_t)0x0UL) /**< MODE_TX_LJ_DISABLE Value */
#define MXC_S_SPIMSS_REVA_MODE_TX_LJ_DISABLE (MXC_V_SPIMSS_REVA_MODE_TX_LJ_DISABLE << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS) /**< MODE_TX_LJ_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_MODE_TX_LJ_ENABLE ((uint32_t)0x1UL) /**< MODE_TX_LJ_ENABLE Value */
#define MXC_S_SPIMSS_REVA_MODE_TX_LJ_ENABLE (MXC_V_SPIMSS_REVA_MODE_TX_LJ_ENABLE << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS) /**< MODE_TX_LJ_ENABLE Setting */
/**@} end of group SPIMSS_MODE_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_BRG SPIMSS_BRG
* @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for
* the SPI Baud Rate Generator. The reload value must be greater than or equal to
* 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by
* 4).
* @{
*/
#define MXC_F_SPIMSS_REVA_BRG_DIV_POS 0 /**< BRG_DIV Position */
#define MXC_F_SPIMSS_REVA_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_REVA_BRG_DIV_POS)) /**< BRG_DIV Mask */
/**@} end of group SPIMSS_BRG_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DMA SPIMSS_DMA
* @brief SPI DMA Register.
* @{
*/
#define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */
#define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */
#define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLR_COMPLETE Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS) /**< DMA_TX_FIFO_CLR_COMPLETE Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_START ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLR_START Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_CLR_START (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_START << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS) /**< DMA_TX_FIFO_CLR_START Setting */
#define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
#define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
#define MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
#define MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE (MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */
#define MXC_S_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE (MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */
#define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */
#define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */
#define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLR_COMPLETE Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS) /**< DMA_RX_FIFO_CLR_COMPLETE Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_START ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLR_START Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_CLR_START (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_START << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS) /**< DMA_RX_FIFO_CLR_START Setting */
#define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
#define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
#define MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
#define MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE (MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */
#define MXC_S_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE (MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */
/**@} end of group SPIMSS_DMA_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL
* @brief I2S Control Register.
* @{
*/
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */
#define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */
#define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */
#define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */
/**@} end of group SPIMSS_I2S_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_REVA_REGS_H_ */

48
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c Normal file
View File

@ -0,0 +1,48 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include "mxc_device.h"
/* **** Definitions **** */
/* **** Globals *****/
/* **** Functions **** */
/* ************************************************************************** */
__weak void mxc_assert(const char* expr, const char* file, int line)
{
while (1) {}
}

257
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c Normal file
View File

@ -0,0 +1,257 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include <stdint.h>
#include <stddef.h>
#include "mxc_device.h"
#include "mxc_delay.h"
#include "mxc_sys.h"
#ifdef __riscv
int MXC_Delay(unsigned long us)
{
// Check if there is nothing to do
if (us == 0) {
return E_NO_ERROR;
}
// Calculate number of cycles needed.
uint32_t ticks = (MXC_SYS_RiscVClockRate() / 1000000) * us;
CSR_SetPCMR(0); // Turn off counter
CSR_SetPCCR(0); // Clear counter register
CSR_SetPCER(1); // Enable counting of cycles
CSR_SetPCMR(3); // Turn on counter
while(CSR_GetPCCR() < ticks) {
// Wait for counter to reach the tick count.
}
return E_NO_ERROR;
}
int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback)
{
return E_NOT_SUPPORTED;
}
int MXC_DelayCheck(void)
{
return E_NOT_SUPPORTED;
}
void MXC_DelayAbort(void)
{
}
#else
/* **** File Scope Variables **** */
static volatile int overflows = -1;
static uint32_t endtick;
static uint32_t ctrl_save;
static mxc_delay_complete_t cbFunc;
static void MXC_DelayInit(unsigned long us);
extern void SysTick_Handler(void);
/* ************************************************************************** */
__weak void SysTick_Handler(void)
{
MXC_DelayHandler();
}
/* ************************************************************************** */
void MXC_DelayHandler(void)
{
// Check and clear overflow flag
if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) {
// Decrement overflow flag if delay is still ongoing
if (overflows > 0) {
overflows--;
}
else {
MXC_DelayAbort();
if (cbFunc != NULL) {
cbFunc(E_NO_ERROR);
cbFunc = NULL;
}
}
}
}
/* ************************************************************************** */
static void MXC_DelayInit(unsigned long us)
{
uint32_t starttick, reload, ticks, lastticks;
// Record the current tick value and clear the overflow flag
starttick = SysTick->VAL;
// Save the state of control register (and clear the overflow flag)
ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk;
// If the SysTick is not running, configure and start it
if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
SysTick->VAL = SysTick_VAL_CURRENT_Msk;
SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
starttick = SysTick_VAL_CURRENT_Msk;
reload = SysTick_LOAD_RELOAD_Msk + 1;
}
else {
reload = SysTick->LOAD + 1; // get the current reload value
}
// Calculate the total number of ticks to delay
ticks = (uint32_t)(((uint64_t) us * (uint64_t) SystemCoreClock) / 1000000);
// How many overflows of the SysTick will occur
overflows = ticks / reload;
// How many remaining ticks after the last overflow
lastticks = ticks % reload;
// Check if there will be another overflow due to the current value of the SysTick
if (lastticks >= starttick) {
overflows++;
endtick = reload - (lastticks - starttick);
}
else {
endtick = starttick - lastticks;
}
}
/* ************************************************************************** */
int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback)
{
cbFunc = callback;
// Check if timeout currently ongoing
if (overflows > 0) {
return E_BUSY;
}
// Check if there is nothing to do
if (us == 0) {
return E_NO_ERROR;
}
// Calculate the necessary delay and start the timer
MXC_DelayInit(us);
// Enable SysTick interrupt if necessary
if (overflows > 0) {
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_DelayCheck(void)
{
// Check if timeout currently ongoing
if (overflows < 0) {
if (cbFunc != NULL) {
cbFunc(E_NO_ERROR);
cbFunc = NULL;
}
return E_NO_ERROR;
}
// Check the global values
if ((overflows == 0) && (SysTick->VAL <= endtick)) {
MXC_DelayAbort();
if (cbFunc != NULL) {
cbFunc(E_NO_ERROR);
cbFunc = NULL;
}
return E_NO_ERROR;
}
return E_BUSY;
}
/* ************************************************************************** */
void MXC_DelayAbort(void)
{
if (cbFunc != NULL) {
cbFunc(E_ABORT);
cbFunc = NULL;
}
SysTick->CTRL = ctrl_save;
overflows = -1;
}
/* ************************************************************************** */
int MXC_Delay(unsigned long us)
{
// Check if timeout currently ongoing
if (overflows > 0) {
return E_BUSY;
}
// Check if there is nothing to do
if (us == 0) {
return E_NO_ERROR;
}
// Calculate the necessary delay and start the timer
MXC_DelayInit(us);
// Wait for the number of overflows
while (overflows > 0) {
// If SysTick interrupts are enabled, COUNTFLAG will never be set here and
// overflows will be decremented in the ISR. If SysTick interrupts are
// disabled, overflows is decremented here.
if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) {
overflows--;
}
}
// Wait for the counter value
while (SysTick->VAL > endtick);
MXC_DelayAbort();
return E_NO_ERROR;
}
#endif // __riscv

83
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c Normal file
View File

@ -0,0 +1,83 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/* **** Includes **** */
#include "mxc_lock.h"
#if USE_LOCK_IN_DRIVERS
#ifndef __riscv
/* ************************************************************************** */
int MXC_GetLock(uint32_t* lock, uint32_t value)
{
do {
// Return if the lock is taken by a different thread
if (__LDREXW((volatile unsigned long*) lock) != 0) {
return E_BUSY;
}
// Attempt to take the lock
}
while (__STREXW(value, (volatile unsigned long*) lock) != 0);
// Do not start any other memory access until memory barrier is complete
__DMB();
return E_NO_ERROR;
}
/* ************************************************************************** */
void MXC_FreeLock(uint32_t* lock)
{
// Ensure memory operations complete before releasing lock
__DMB();
*lock = 0;
}
#else // __riscv
/* ************************************************************************** */
int MXC_GetLock(uint32_t* lock, uint32_t value)
{
#warning "Unimplemented for RISCV"
return E_NO_ERROR;
}
/* ************************************************************************** */
void MXC_FreeLock(uint32_t* lock)
{
#warning "Unimplemented for RISCV"
}
#endif
#endif // USE_LOCK_IN_DRIVERS

76
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c Normal file
View File

@ -0,0 +1,76 @@
/**
* @file mxc_pins.c
* @brief This file contains constant pin configurations for the peripherals.
*/
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
**************************************************************************** */
#include "gpio.h"
#include "mxc_device.h"
/***** Definitions *****/
/***** Global Variables *****/
const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10|MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
//SPI0
const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
// SPI1A
const mxc_gpio_cfg_t gpio_cfg_spi1a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi1a_ss = { MXC_GPIO0, MXC_GPIO_PIN_13, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
//SPI1B
const mxc_gpio_cfg_t gpio_cfg_spi1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_spi1b_ss = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
// Timers are only defined once, depending on package, each timer could be mapped to other pins
const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};
const mxc_gpio_cfg_t gpio_cfg_i2s0a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
const mxc_gpio_cfg_t gpio_cfg_i2s0b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };

289
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c Normal file
View File

@ -0,0 +1,289 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
/**
* @file mxc_sys.c
* @brief System layer driver.
* @details This driver is used to control the system layer of the device.
*/
/* **** Includes **** */
#include <stddef.h>
#include "mxc_errors.h"
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "gcr_regs.h"
#include "fcr_regs.h"
/**
* @ingroup mxc_sys
* @{
*/
/* **** Definitions **** */
#define MXC_SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1)
/* **** Globals **** */
/* **** Functions **** */
/* ************************************************************************** */
int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock)
{
/* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */
if (clock > 31) {
clock -= 32;
return ! (MXC_GCR->pclk_dis1 & (0x1 << clock));
}
else {
return ! (MXC_GCR->pclk_dis0 & (0x1 << clock));
}
}
/* ************************************************************************** */
void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock)
{
/* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */
if (clock > 31) {
clock -= 32;
MXC_GCR->pclk_dis1 |= (0x1 << clock);
}
else {
MXC_GCR->pclk_dis0 |= (0x1 << clock);
}
}
/* ************************************************************************** */
void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock)
{
/* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */
if (clock > 31) {
clock -= 32;
MXC_GCR->pclk_dis1 &= ~ (0x1 << clock);
}
else {
MXC_GCR->pclk_dis0 &= ~ (0x1 << clock);
}
}
/* ************************************************************************** */
void MXC_SYS_RTCClockEnable()
{
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN;
}
/* ************************************************************************** */
int MXC_SYS_RTCClockDisable (void)
{
/* Check that the RTC is not the system clock source */
if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) != MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) {
MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN;
return E_NO_ERROR;
}
else {
return E_BAD_STATE;
}
}
/******************************************************************************/
int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock)
{
switch (clock) {
case MXC_SYS_CLOCK_HIRC:
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN;
return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY);
break;
case MXC_SYS_CLOCK_HFXIN:
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN;
return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY);
break;
case MXC_SYS_CLOCK_NANORING:
// MXC_GCR->clk_ctrl |= MXC_F_GCR_CLKCTRL_EXTCLK_EN;
// return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY);
return E_NOT_SUPPORTED;
break;
default:
return E_BAD_PARAM;
break;
}
}
/******************************************************************************/
int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock)
{
uint32_t current_clock;
current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL;
// Don't turn off the clock we're running on
if (clock == current_clock) {
return E_BAD_PARAM;
}
switch (clock) {
case MXC_SYS_CLOCK_HIRC:
MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_HIRC_EN;
break;
case MXC_SYS_CLOCK_HFXIN:
MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN;
break;
case MXC_SYS_CLOCK_NANORING:
// MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLKCTRL_EXTCLK_EN;
return E_BAD_PARAM;
default:
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int MXC_SYS_Clock_Timeout (uint32_t ready)
{
// Start timeout, wait for ready
MXC_DelayAsync (MXC_SYS_CLOCK_TIMEOUT, NULL);
do {
if (MXC_GCR->clk_ctrl & ready) {
MXC_DelayAbort();
return E_NO_ERROR;
}
}
while (MXC_DelayCheck() == E_BUSY);
return E_TIME_OUT;
}
/* ************************************************************************** */
int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock)
{
uint32_t current_clock;
// Save the current system clock
current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL;
switch (clock) {
case MXC_SYS_CLOCK_HIRC:
// Enable HIRC clock
if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC_EN)) {
MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN;
// Check if HIRC clock is ready
if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY) != E_NO_ERROR) {
return E_TIME_OUT;
}
}
// Set HIRC clock as System Clock
MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC);
break;
case MXC_SYS_CLOCK_HFXIN:
// Enable HFXtal clock
if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_X32K_EN)) {
MXC_GCR->clk_ctrl |=MXC_F_GCR_CLK_CTRL_X32K_EN;
// Check if HFXtal clock is ready
if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY) != E_NO_ERROR) {
return E_TIME_OUT;
}
}
// Set HFXtal clock as System Clock
MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN);
break;
case MXC_SYS_CLOCK_NANORING:
// Enable HIRC clock
// if(!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLKCTRL_EXTCLK_EN)) {
// MXC_GCR->clk_ctrl |=MXC_F_GCR_CLKCTRL_EXTCLK_EN;
// // Check if HIRC clock is ready
// if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY) != E_NO_ERROR) {
// return E_TIME_OUT;
// }
// }
// Set HIRC clock as System Clock
// MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK);
MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING);
break;
default:
return E_BAD_PARAM;
}
// Wait for system clock to be ready
if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_CLKRDY) != E_NO_ERROR) {
// Restore the old system clock if timeout
MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, current_clock);
return E_TIME_OUT;
}
// Update the system core clock
SystemCoreClockUpdate();
return E_NO_ERROR;
}
/* ************************************************************************** */
void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset)
{
/* The mxc_sys_reset_t enum uses enum values that are the offset by 32 for the rstr1 register. */
if (reset > 31) {
reset -= 32;
MXC_GCR->rst1 = (0x1 << reset);
}
else {
MXC_GCR->rst0 = (0x1 << reset);
}
}
/**@} end of mxc_sys */

131
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c Normal file
View File

@ -0,0 +1,131 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include <stddef.h>
#include "mxc_assert.h"
#include "tmr.h"
#include "tmr_common.h"
/* **** Functions **** */
void MXC_TMR_Common_Delay(mxc_tmr_regs_t* tmr, unsigned long us)
{
// Return immediately if delay is 0
if (!us) {
return;
}
MXC_TMR_TO_Start(tmr, us);
while (MXC_TMR_TO_Check(tmr) != E_TIME_OUT) {}
}
int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t* tmr)
{
if (MXC_TMR_GetFlags(tmr)) {
return E_TIME_OUT;
}
return E_NO_ERROR;
}
void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t* tmr)
{
MXC_TMR_Stop(tmr);
MXC_TMR_SetCount(tmr, 0x0);
}
void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t* tmr)
{
MXC_TMR_ClearFlags(tmr);
MXC_TMR_SetCount(tmr, 0x0);
}
unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t* tmr)
{
uint32_t remaining_ticks, remaining_time;
mxc_tmr_unit_t units;
remaining_ticks = MXC_TMR_GetCompare(tmr) - MXC_TMR_GetCount(tmr);
MXC_TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units);
switch (units) {
case TMR_UNIT_NANOSEC:
default:
return (remaining_time / 1000);
case TMR_UNIT_MICROSEC:
return (remaining_time);
case TMR_UNIT_MILLISEC:
return (remaining_time * 1000);
case TMR_UNIT_SEC:
return (remaining_time * 1000000);
}
}
void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t* tmr)
{
MXC_TMR_TO_Start(tmr, 0xFFFFFFFF);
}
unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t* tmr)
{
unsigned int elapsed = MXC_TMR_TO_Elapsed(tmr);
MXC_TMR_TO_Stop(tmr);
return elapsed;
}
unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t* tmr)
{
uint32_t elapsed;
mxc_tmr_unit_t units;
MXC_TMR_GetTime (tmr, tmr->cnt, &elapsed, &units);
switch (units) {
case TMR_UNIT_NANOSEC:
default:
return (elapsed / 1000);
case TMR_UNIT_MICROSEC:
return (elapsed);
case TMR_UNIT_MILLISEC:
return (elapsed * 1000);
case TMR_UNIT_SEC:
return (elapsed * 1000000);
}
}

48
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h Normal file
View File

@ -0,0 +1,48 @@
/* *****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include <stddef.h>
#include "mxc_assert.h"
#include "tmr.h"
/* **** Functions **** */
void MXC_TMR_Common_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
void MXC_TMR_Common_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
int MXC_TMR_Common_TO_Check (mxc_tmr_regs_t *tmr);
void MXC_TMR_Common_TO_Stop (mxc_tmr_regs_t *tmr);
void MXC_TMR_Common_TO_Clear (mxc_tmr_regs_t *tmr);
unsigned int MXC_TMR_Common_TO_Elapsed (mxc_tmr_regs_t *tmr);
unsigned int MXC_TMR_Common_TO_Remaining (mxc_tmr_regs_t *tmr);
void MXC_TMR_Common_SW_Start (mxc_tmr_regs_t *tmr);
unsigned int MXC_TMR_Common_SW_Stop (mxc_tmr_regs_t *tmr);

234
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c Normal file
View File

@ -0,0 +1,234 @@
/* *****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
#include "tmr.h"
#include "tmr_reva.h"
#include "tmr_common.h"
int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg)
{
int tmr_id = MXC_TMR_GET_IDX(tmr);
MXC_ASSERT(tmr_id >= 0);
switch(cfg->clock){
case MXC_TMR_EXT_CLK:
MXC_GPIO_Config(&gpio_cfg_32kcal);
break;
case MXC_TMR_HFIO_CLK:
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_HIRC);
break;
case MXC_TMR_NANORING_CLK:
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_NANORING);
break;
default:
return E_BAD_PARAM;
break;
}
//enable peripheral clock and configure gpio pins
switch(tmr_id) {
case 0:
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER0);
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0);
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
MXC_GPIO_Config(&gpio_cfg_tmr0);
break;
case 1:
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER1);
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1);
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
break;
case 2:
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER2);
while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2);
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
break;
}
MXC_TMR_RevA_Init((mxc_tmr_reva_regs_t*) tmr, cfg);
return E_NO_ERROR;
}
void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX(tmr);
MXC_ASSERT(tmr_id >= 0);
MXC_TMR_RevA_Shutdown((mxc_tmr_reva_regs_t*) tmr);
// System settigns
//diasble peripheral clock
switch(tmr_id) {
case 0:
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
break;
case 1:
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
break;
case 2:
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
break;
}
}
void MXC_TMR_Start(mxc_tmr_regs_t* tmr)
{
MXC_TMR_RevA_Start((mxc_tmr_reva_regs_t*) tmr);
}
void MXC_TMR_Stop(mxc_tmr_regs_t* tmr)
{
MXC_TMR_RevA_Stop((mxc_tmr_reva_regs_t*) tmr);
}
int MXC_TMR_SetPWM(mxc_tmr_regs_t* tmr, uint32_t pwm)
{
return MXC_TMR_RevA_SetPWM((mxc_tmr_reva_regs_t*) tmr, pwm);
}
uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t* tmr)
{
return MXC_TMR_RevA_GetCompare((mxc_tmr_reva_regs_t*) tmr);
}
uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t* tmr)
{
return MXC_TMR_RevA_GetCapture((mxc_tmr_reva_regs_t*) tmr);
}
uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency)
{
uint32_t retVal, clkFreq;
switch(clock) {
case MXC_TMR_HFIO_CLK:
clkFreq = PeripheralClock;
break;
case MXC_TMR_NANORING_CLK:
clkFreq = 80000;
break;
case MXC_TMR_EXT_CLK:
clkFreq = HFX_FREQ;
break;
default:
clkFreq = PeripheralClock;
break;
}
if(frequency == 0) {
return 0;
}
else {
retVal = clkFreq / (prescalar * frequency);
return retVal;
}
return retVal;
}
uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t* tmr)
{
return MXC_TMR_RevA_GetCount((mxc_tmr_reva_regs_t*) tmr);
}
void MXC_TMR_ClearFlags(mxc_tmr_regs_t* tmr)
{
MXC_TMR_RevA_ClearFlags((mxc_tmr_reva_regs_t*) tmr);
}
uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t* tmr)
{
return MXC_TMR_RevA_GetFlags((mxc_tmr_reva_regs_t*) tmr);
}
void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
{
MXC_TMR_RevA_SetCompare((mxc_tmr_reva_regs_t*) tmr, cmp_cnt);
}
void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
{
MXC_TMR_RevA_SetCount((mxc_tmr_reva_regs_t*) tmr, cnt);
}
void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us)
{
MXC_TMR_Common_Delay(tmr, us);
}
void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us)
{
MXC_TMR_RevA_TO_Start((mxc_tmr_reva_regs_t*) tmr, us);
}
int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr)
{
return MXC_TMR_Common_TO_Check(tmr);
}
void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr)
{
MXC_TMR_Common_TO_Stop(tmr);
}
void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr)
{
MXC_TMR_Common_TO_Clear(tmr);
}
unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
{
return MXC_TMR_Common_TO_Elapsed(tmr);
}
unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
{
return MXC_TMR_Common_TO_Remaining(tmr);
}
void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr)
{
return MXC_TMR_Common_SW_Start(tmr);
}
unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr)
{
return MXC_TMR_Common_SW_Stop(tmr);
}
int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
{
return MXC_TMR_RevA_GetTime((mxc_tmr_reva_regs_t*) tmr, ticks, time, units);
}

304
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c Normal file
View File

@ -0,0 +1,304 @@
/* *****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include <stddef.h>
#include "mxc_assert.h"
#include "tmr.h"
#include "tmr_reva.h"
#include "gpio.h"
#include "mxc_pins.h"
#include "mxc_lock.h"
/* **** Functions **** */
void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg)
{
// Clear interrupt flag
tmr->intr = MXC_F_TMR_REVA_INTR_IRQ;
// Set the prescaler
switch(cfg->pres) {
case TMR_PRES_1:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1);
break;
case TMR_PRES_2:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV2);
break;
case TMR_PRES_4:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4);
break;
case TMR_PRES_8:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8);
break;
case TMR_PRES_16:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16);
break;
case TMR_PRES_32:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32);
break;
case TMR_PRES_64:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV64);
break;
case TMR_PRES_128:
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
break;
case TMR_PRES_256:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
break;
case TMR_PRES_512:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4);
break;
case TMR_PRES_1024:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8);
break;
case TMR_PRES_2048:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16);
break;
case TMR_PRES_4096:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
break;
default:
tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3);
tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128);
break;
}
tmr->cn |= cfg->mode << MXC_F_TMR_REVA_CN_TMODE_POS;
tmr->cn |= (cfg->pol) << MXC_F_TMR_REVA_CN_TPOL_POS;
//enable timer interrupt if needed
tmr->cnt = 0x1;
tmr->cmp = cfg->cmp_cnt;
}
void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
// Disable timer and clear settings
tmr->cn = 0;
}
void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
tmr->cn |= MXC_F_TMR_REVA_CN_TEN;
}
void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
tmr->cn &= ~MXC_F_TMR_REVA_CN_TEN;
}
int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
if(pwm > (tmr->cmp)) {
return E_BAD_PARAM;
}
tmr->pwm = pwm;
return E_NO_ERROR;
}
uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
return tmr->cmp;
}
uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
return tmr->pwm;//check this
}
uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
return tmr->cnt;
}
void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
tmr->intr = MXC_F_TMR_REVA_INTR_IRQ;
}
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
return tmr->intr;
}
void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
tmr->cmp = cmp_cnt;
}
void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt)
{
int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr);
if (tmr_id < 0) {
MXC_ASSERT(0);
}
tmr->cnt = cnt;
}
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us)
{
uint64_t ticks;
int clk_shift = 0;
ticks = (uint64_t) us * (uint64_t) PeripheralClock / (uint64_t) 1000000;
while(ticks > 0xFFFFFFFFUL) {
ticks >>= 1;
++clk_shift;
}
mxc_tmr_pres_t prescale = (mxc_tmr_pres_t) clk_shift << MXC_F_TMR_REVA_CN_PRES_POS;
mxc_tmr_cfg_t cfg = {0, 0, 0, 0}; // = (mxc_tmr_cfg_t) {.pres=0, .mode=0, .cmp_cnt=0, .pol=0};
// Initialize the timer in one-shot mode
cfg.pres = prescale;
cfg.mode = TMR_MODE_ONESHOT;
cfg.cmp_cnt = ticks;
cfg.pol = 0;
MXC_TMR_Stop((mxc_tmr_regs_t*) tmr);
MXC_TMR_Init((mxc_tmr_regs_t*) tmr, &cfg);
MXC_TMR_ClearFlags((mxc_tmr_regs_t*) tmr);
MXC_TMR_Start((mxc_tmr_regs_t*) tmr);
}
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
{
uint64_t temp_time = 0;
uint32_t timerClock = PeripheralClock;
uint32_t prescale = ((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS)
|(((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) <<3);
temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000000);
if(!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_NANOSEC;
return E_NO_ERROR;
}
temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000);
if(!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_MICROSEC;
return E_NO_ERROR;
}
temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / timerClock;
if(!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_MILLISEC;
return E_NO_ERROR;
}
temp_time = (uint64_t) ticks * (1 <<(prescale & 0xF)) / timerClock;
if(!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_SEC;
return E_NO_ERROR;
}
return E_INVALID;
}

58
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h Normal file
View File

@ -0,0 +1,58 @@
/* *****************************************************************************
* Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files(the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
**************************************************************************** */
/* **** Includes **** */
#include <stddef.h>
#include "mxc_assert.h"
#include "tmr.h"
#include "gpio.h"
#include "mxc_pins.h"
#include "mxc_lock.h"
#include "tmr_reva_regs.h"
/* **** Functions **** */
void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg);
void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr);
void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr);
void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr);
int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm);
uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr);
uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr);
uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr);
void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr);
uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr);
void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt);
void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt);
void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us);
int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);

209
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h Normal file
View File

@ -0,0 +1,209 @@
/**
* @file tmr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _TMR_REVA_REGS_H_
#define _TMR_REVA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup tmr
* @defgroup tmr_registers TMR_Registers
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @details 32-bit reloadable timer that can be used for timing and event counting.
*/
/**
* @ingroup tmr_registers
* Structure type to access the TMR Registers.
*/
typedef struct {
__IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR CNT Register */
__IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR CMP Register */
__IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR PWM Register */
__IO uint32_t intr; /**< <tt>\b 0x0C:</tt> TMR INTR Register */
__IO uint32_t cn; /**< <tt>\b 0x10:</tt> TMR CN Register */
__IO uint32_t nolcmp; /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */
} mxc_tmr_reva_regs_t;
/* Register offsets for module TMR */
/**
* @ingroup tmr_registers
* @defgroup TMR_Register_Offsets Register Offsets
* @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address.
* @{
*/
#define MXC_R_TMR_REVA_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */
#define MXC_R_TMR_REVA_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */
#define MXC_R_TMR_REVA_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */
#define MXC_R_TMR_REVA_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */
#define MXC_R_TMR_REVA_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */
#define MXC_R_TMR_REVA_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */
/**@} end of group tmr_registers */
/**
* @ingroup tmr_registers
* @defgroup TMR_INTR TMR_INTR
* @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the
* associated interrupt.
* @{
*/
#define MXC_F_TMR_REVA_INTR_IRQ_POS 0 /**< INTR_IRQ Position */
#define MXC_F_TMR_REVA_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_REVA_INTR_IRQ_POS)) /**< INTR_IRQ Mask */
/**@} end of group TMR_INTR_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_CN TMR_CN
* @brief Timer Control Register.
* @{
*/
#define MXC_F_TMR_REVA_CN_TMODE_POS 0 /**< CN_TMODE Position */
#define MXC_F_TMR_REVA_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_REVA_CN_TMODE_POS)) /**< CN_TMODE Mask */
#define MXC_V_TMR_REVA_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
#define MXC_S_TMR_REVA_CN_TMODE_ONESHOT (MXC_V_TMR_REVA_CN_TMODE_ONESHOT << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
#define MXC_V_TMR_REVA_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
#define MXC_S_TMR_REVA_CN_TMODE_CONTINUOUS (MXC_V_TMR_REVA_CN_TMODE_CONTINUOUS << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
#define MXC_V_TMR_REVA_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
#define MXC_S_TMR_REVA_CN_TMODE_COUNTER (MXC_V_TMR_REVA_CN_TMODE_COUNTER << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
#define MXC_V_TMR_REVA_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
#define MXC_S_TMR_REVA_CN_TMODE_PWM (MXC_V_TMR_REVA_CN_TMODE_PWM << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
#define MXC_V_TMR_REVA_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
#define MXC_S_TMR_REVA_CN_TMODE_CAPTURE (MXC_V_TMR_REVA_CN_TMODE_CAPTURE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
#define MXC_V_TMR_REVA_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
#define MXC_S_TMR_REVA_CN_TMODE_COMPARE (MXC_V_TMR_REVA_CN_TMODE_COMPARE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
#define MXC_V_TMR_REVA_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */
#define MXC_S_TMR_REVA_CN_TMODE_GATED (MXC_V_TMR_REVA_CN_TMODE_GATED << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
#define MXC_V_TMR_REVA_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
#define MXC_S_TMR_REVA_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_REVA_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
#define MXC_F_TMR_REVA_CN_PRES_POS 3 /**< CN_PRES Position */
#define MXC_F_TMR_REVA_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_REVA_CN_PRES_POS)) /**< CN_PRES Mask */
#define MXC_V_TMR_REVA_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV1 (MXC_V_TMR_REVA_CN_PRES_DIV1 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */
#define MXC_V_TMR_REVA_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV2 (MXC_V_TMR_REVA_CN_PRES_DIV2 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */
#define MXC_V_TMR_REVA_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV4 (MXC_V_TMR_REVA_CN_PRES_DIV4 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */
#define MXC_V_TMR_REVA_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV8 (MXC_V_TMR_REVA_CN_PRES_DIV8 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */
#define MXC_V_TMR_REVA_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV16 (MXC_V_TMR_REVA_CN_PRES_DIV16 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */
#define MXC_V_TMR_REVA_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV32 (MXC_V_TMR_REVA_CN_PRES_DIV32 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */
#define MXC_V_TMR_REVA_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV64 (MXC_V_TMR_REVA_CN_PRES_DIV64 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
#define MXC_V_TMR_REVA_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */
#define MXC_S_TMR_REVA_CN_PRES_DIV128 (MXC_V_TMR_REVA_CN_PRES_DIV128 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
#define MXC_F_TMR_REVA_CN_TPOL_POS 6 /**< CN_TPOL Position */
#define MXC_F_TMR_REVA_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_TPOL_POS)) /**< CN_TPOL Mask */
#define MXC_F_TMR_REVA_CN_TEN_POS 7 /**< CN_TEN Position */
#define MXC_F_TMR_REVA_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_TEN_POS)) /**< CN_TEN Mask */
#define MXC_F_TMR_REVA_CN_PRES3_POS 8 /**< CN_PRES3 Position */
#define MXC_F_TMR_REVA_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PRES3_POS)) /**< CN_PRES3 Mask */
#define MXC_F_TMR_REVA_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
#define MXC_F_TMR_REVA_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */
#define MXC_F_TMR_REVA_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
#define MXC_F_TMR_REVA_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */
#define MXC_F_TMR_REVA_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
#define MXC_F_TMR_REVA_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */
#define MXC_F_TMR_REVA_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
#define MXC_F_TMR_REVA_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */
/**@} end of group TMR_CN_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_NOLCMP TMR_NOLCMP
* @brief Timer Non-Overlapping Compare Register.
* @{
*/
#define MXC_F_TMR_REVA_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
#define MXC_F_TMR_REVA_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_REVA_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
#define MXC_F_TMR_REVA_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
#define MXC_F_TMR_REVA_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_REVA_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
/**@} end of group TMR_NOLCMP_Register */
#ifdef __cplusplus
}
#endif
#endif /* _TMR_REVA_REGS_H_ */

53
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c Normal file
View File

@ -0,0 +1,53 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include "uart_common.h"
#include "uart.h"
int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t* uart)
{
// Wait until FIFO has a character ready.
while (MXC_UART_GetRXFIFOAvailable(uart) < 1);
// Read the character using the non-blocking function.
return MXC_UART_ReadCharacterRaw(uart);
}
int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character)
{
// Wait until FIFO has space for the character.
while (MXC_UART_GetTXFIFOAvailable(uart) < 1);
// Write the character using the non-blocking function.
return MXC_UART_WriteCharacterRaw(uart, character);
}

38
targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h Normal file
View File

@ -0,0 +1,38 @@
/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*************************************************************************** */
#include "uart_regs.h"
int MXC_UART_Common_ReadCharacter (mxc_uart_regs_t* uart);
int MXC_UART_Common_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character);

Some files were not shown because too many files have changed in this diff Show More