From 987567ee59718671054637c5b404802569481d55 Mon Sep 17 00:00:00 2001 From: vimalrajr Date: Wed, 29 Jul 2015 11:33:14 +0530 Subject: [PATCH] Adding PWM API implementation --- .../TARGET_SAM0/PeripheralNames.h | 14 +- .../TARGET_Atmel/TARGET_SAM0/PeripheralPins.h | 2 +- .../TARGET_SAMR21G18A/PeripheralPins.c | 21 + .../drivers/tcc/quick_start/qs_tcc_basic.h | 97 + .../quick_start_buffering/qs_tcc_buffering.h | 103 + .../drivers/tcc/quick_start_dma/qs_tcc_dma.h | 220 ++ .../TARGET_SAM0/drivers/tcc/tcc.c | 1547 +++++++++++ .../TARGET_SAM0/drivers/tcc/tcc.h | 2338 +++++++++++++++++ .../hal/TARGET_Atmel/TARGET_SAM0/objects.h | 8 + .../TARGET_SAM0/pinmap_function.c | 52 +- .../TARGET_SAM0/pinmap_function.h | 8 + .../hal/TARGET_Atmel/TARGET_SAM0/pwmout_api.c | 152 ++ 12 files changed, 4552 insertions(+), 10 deletions(-) create mode 100644 libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start/qs_tcc_basic.h create mode 100644 libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_buffering/qs_tcc_buffering.h create mode 100644 libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_dma/qs_tcc_dma.h create mode 100644 libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.c create mode 100644 libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralNames.h index 0317895012..0488bc8383 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralNames.h @@ -95,15 +95,13 @@ typedef enum { /* Pad 3 definitions */ MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) } SercomPadName; -/* + typedef enum { - PWM_1 = 1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6 -} PWMName;*/ + PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */ + PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */ + PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */ +} PWMName; + #define STDIO_UART_TX USBTX #define STDIO_UART_RX USBRX diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralPins.h index 88c88a25b0..4c87432ddb 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/PeripheralPins.h @@ -31,7 +31,7 @@ extern const PinMap PinMap_SERCOM_PAD[]; extern const PinMap PinMap_SERCOM_PADEx[]; /************PWM***************/ -//extern const PinMap PinMap_PWM[]; +extern const PinMap PinMap_PWM[]; /**********EXTINT*************/ extern const PinMap PinMap_EXTINT[]; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMR21G18A/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMR21G18A/PeripheralPins.c index deba47072f..e39f857b15 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMR21G18A/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/TARGET_SAMR21G18A/PeripheralPins.c @@ -96,6 +96,27 @@ const PinMap PinMap_SERCOM_PADEx[] = { /************PWM***************/ const PinMap PinMap_PWM[] = { + {PA00, PWM_2, 4}, + {PA01, PWM_2, 4}, + {PA04, PWM_0, 4}, + {PA05, PWM_0, 4}, + {PA06, PWM_1, 4}, + {PA07, PWM_1, 4}, + {PA08, PWM_0, 4}, + {PA09, PWM_0, 4}, + {PA12, PWM_2, 4}, + {PA13, PWM_2, 4}, + {PA16, PWM_2, 4}, + {PA17, PWM_2, 4}, + {PA18, PWM_0, 5}, + {PA19, PWM_0, 5}, + {PA22, PWM_0, 5}, + {PA23, PWM_0, 5}, + {PA24, PWM_1, 5}, + {PA25, PWM_1, 5}, + {PA30, PWM_1, 4}, + {PA31, PWM_1, 4}, + /* Not connected */ {NC , NC , NC} }; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start/qs_tcc_basic.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start/qs_tcc_basic.h new file mode 100644 index 0000000000..8064a58574 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start/qs_tcc_basic.h @@ -0,0 +1,97 @@ +/** + * \page asfdoc_sam0_tcc_basic_use_case Quick Start Guide for TCC - Basic + * + * The supported board list: + * - SAM D21/R21/L21 Xplained Pro + * + * In this use case, the TCC will be used to generate a PWM signal. Here + * the pulse width is set to one quarter of the period. + * When connect PWM output to LED it makes the LED light. To see the waveform, + * you may need an oscilloscope. + * + * The PWM output is set up as follows: + * + * + * + * + * + *
Board Pin Connect to
SAMD21 Xpro PB30 LED0
SAMR21 Xpro PA19 LED0
SAML21 Xpro PB10 LED0
+ * + * The TCC module will be set up as follows: + * - GCLK generator 0 (GCLK main) clock source + * - Use double buffering write when set top, compare, or pattern through API + * - No dithering on the counter or compare + * - No prescaler + * - Single Slope PWM wave generation + * - GCLK reload action + * - Don't run in standby + * - No fault or waveform extensions + * - No inversion of waveform output + * - No capture enabled + * - Count upward + * - Don't perform one-shot operations + * - No event input enabled + * - No event action + * - No event generation enabled + * - Counter starts on 0 + * - Counter top set to 0xFFFF + * - Capture compare channel 0 set to 0xFFFF/4 + * + * \section asfdoc_sam0_tcc_basic_use_case_setup Quick Start + * + * \subsection asfdoc_sam0_tcc_basic_use_case_prereq Prerequisites + * There are no prerequisites for this use case. + * + * \subsection asfdoc_sam0_tcc_basic_use_case_setup_code Code + * + * Add to the main application source file, before any functions: + * \snippet conf_quick_start.h definition_pwm + * + * Add to the main application source file, outside of any functions: + * \snippet qs_tcc_basic.c module_inst + * + * Copy-paste the following setup code to your user application: + * \snippet qs_tcc_basic.c setup + * + * Add to user application initialization (typically the start of \c main()): + * \snippet qs_tcc_basic.c setup_init + * + * \subsection asfdoc_sam0_tcc_basic_use_case_setup_flow Workflow + * -# Create a module software instance structure for the TCC module to store + * the TCC driver state while it is in use. + * \snippet qs_tcc_basic.c module_inst + * \note This should never go out of scope as long as the module is in use. + * In most cases, this should be global. + * + * -# Configure the TCC module. + * -# Create a TCC module configuration struct, which can be filled out to + * adjust the configuration of a physical TCC peripheral. + * \snippet qs_tcc_basic.c setup_config + * -# Initialize the TCC configuration struct with the module's default values. + * \snippet qs_tcc_basic.c setup_config_defaults + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Alter the TCC settings to configure the counter width, wave generation + * mode and the compare channel 0 value. + * \snippet qs_tcc_basic.c setup_change_config + * -# Alter the TCC settings to configure the PWM output on a physical device + * pin. + * \snippet qs_tcc_basic.c setup_change_config_pwm + * -# Configure the TCC module with the desired settings. + * \snippet qs_tcc_basic.c setup_set_config + * -# Enable the TCC module to start the timer and begin PWM signal generation. + * \snippet qs_tcc_basic.c setup_enable + * + * + * \section asfdoc_sam0_tcc_basic_use_case_main Use Case + * + * \subsection asfdoc_sam0_tcc_basic_use_case_main_code Code + * Copy-paste the following code to your user application: + * \snippet qs_tcc_basic.c main + * + * \subsection asfdoc_sam0_tcc_basic_use_case_main_flow Workflow + * -# Enter an infinite loop while the PWM wave is generated via the TCC module. + * \snippet qs_tcc_basic.c main_loop + */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_buffering/qs_tcc_buffering.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_buffering/qs_tcc_buffering.h new file mode 100644 index 0000000000..1c7d2deec5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_buffering/qs_tcc_buffering.h @@ -0,0 +1,103 @@ +/** + * \page asfdoc_sam0_tcc_buffering_use_case Quick Start Guide for TCC - Double Buffering and Circular + * + * The supported board list: + * - SAM D21/R21/L21 Xplained Pro + * + * In this use case, the TCC will be used to generate a PWM signal. Here + * the pulse width alters in one quarter and three quarter of the period. + * When connect PWM output to LED it makes the LED light. To see the waveform, + * you may need an oscilloscope. + * + * The PWM output is set up as follows: + * + * + * + * + * + *
Board Pin Connect to
SAMD21 Xpro PB30 LED0
SAMR21 Xpro PA19 LED0
SAML21 Xpro PB10 LED0
+ * + * The TCC module will be set up as follows: + * - GCLK generator 0 (GCLK main) clock source + * - Use double buffering write when set top, compare, or pattern through API + * - No dithering on the counter or compare + * - Prescaler is set to 1024 + * - Single Slope PWM wave generation + * - GCLK reload action + * - Don't run in standby + * - No fault or waveform extensions + * - No inversion of waveform output + * - No capture enabled + * - Count upward + * - Don't perform one-shot operations + * - No event input enabled + * - No event action + * - No event generation enabled + * - Counter starts on 0 + * - Counter top set to 8000 + * - Capture compare channel set to 8000/4 + * - Capture compare channel buffer set to 8000*3/4 + * - Circular option for compare channel is enabled so that the compare + * values keep switching on update condition + * + * \section asfdoc_sam0_tcc_buffering_use_case_setup Quick Start + * + * \subsection asfdoc_sam0_tcc_buffering_use_case_prereq Prerequisites + * There are no prerequisites for this use case. + * + * \subsection asfdoc_sam0_tcc_buffering_use_case_setup_code Code + * + * Add to the main application source file, before any functions: + * \snippet conf_quick_start_buffering.h definition_pwm + * + * Add to the main application source file, outside of any functions: + * \snippet qs_tcc_buffering.c module_inst + * + * Copy-paste the following setup code to your user application: + * \snippet qs_tcc_buffering.c setup + * + * Add to user application initialization (typically the start of \c main()): + * \snippet qs_tcc_buffering.c setup_init + * + * \subsection asfdoc_sam0_tcc_buffering_use_case_setup_flow Workflow + * -# Create a module software instance structure for the TCC module to store + * the TCC driver state while it is in use. + * \snippet qs_tcc_buffering.c module_inst + * \note This should never go out of scope as long as the module is in use. + * In most cases, this should be global. + * + * -# Configure the TCC module. + * -# Create a TCC module configuration struct, which can be filled out to + * adjust the configuration of a physical TCC peripheral. + * \snippet qs_tcc_buffering.c setup_config + * -# Initialize the TCC configuration struct with the module's default values. + * \snippet qs_tcc_buffering.c setup_config_defaults + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Alter the TCC settings to configure the counter width, wave generation + * mode and the compare channel 0 value. + * \snippet qs_tcc_buffering.c setup_change_config + * -# Alter the TCC settings to configure the PWM output on a physical device + * pin. + * \snippet qs_tcc_buffering.c setup_change_config_pwm + * -# Configure the TCC module with the desired settings. + * \snippet qs_tcc_buffering.c setup_set_config + * -# Set to compare buffer value and enable circular of double buffered + * compare values. + * \snippet qs_tcc_buffering.c setup_set_buffering + * -# Enable the TCC module to start the timer and begin PWM signal generation. + * \snippet qs_tcc_buffering.c setup_enable + * + * + * \section asfdoc_sam0_tcc_buffering_use_case_main Use Case + * + * \subsection asfdoc_sam0_tcc_buffering_use_case_main_code Code + * Copy-paste the following code to your user application: + * \snippet qs_tcc_buffering.c main + * + * \subsection asfdoc_sam0_tcc_buffering_use_case_main_flow Workflow + * -# Enter an infinite loop while the PWM wave is generated via the TCC module. + * \snippet qs_tcc_buffering.c main_loop + */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_dma/qs_tcc_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_dma/qs_tcc_dma.h new file mode 100644 index 0000000000..da25e20f1f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/quick_start_dma/qs_tcc_dma.h @@ -0,0 +1,220 @@ +/** + * \page asfdoc_sam0_tcc_dma_use_case Quick Start Guide for Using DMA with TCC + * + * The supported board list: + * - SAM D21/R21/L21 Xplained Pro + * + * In this use case, the TCC will be used to generate a PWM signal. Here + * the pulse width varies through following values with the help of DMA + * transfer: one quarter of the period, half of the period, and three quarters + * of the period. + * The PWM output can be used to drive an LED. The waveform can also be + * viewed using an oscilloscope. + * The output signal is also fed back to another TCC channel by event system, + * the event stamps are captured and transferred to a buffer by DMA. + * + * The PWM output is set up as follows: + * + * + * + * + * + *
Board Pin Connect to
SAMD21 Xpro PB30 LED0
SAMR21 Xpro PA19 LED0
SAML21 Xpro PB10 LED0
+ * + * The TCC module will be setup as follows: + * - GCLK generator 0 (GCLK main) clock source + * - Use double buffering write when set top, compare, or pattern through API + * - No dithering on the counter or compare + * - No prescaler + * - Single Slope PWM wave generation + * - GCLK reload action + * - Don't run in standby + * - No fault or waveform extensions + * - No inversion of waveform output + * - No capture enabled + * - Count upward + * - Don't perform one-shot operations + * - Counter starts on 0 + * - Counter top set to 0x1000 + * - Channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is set to + * compare and match value 0x1000*3/4 and generate event + * - Channel 1 is set to capture on input event + * + * The event resource of EVSYS module will be setup as follows: + * - TCC match capture channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is + * selected as event generator + * - Event generation is synchronous, with rising edge detected + * - TCC match capture channel 1 is the event user + * + * The DMA resource of DMAC module will be setup as follows: + * - Two DMA resources are used + * - Both DMA resources use peripheral trigger + * - Both DMA resources perform beat transfer on trigger + * - Both DMA resources use beat size of 16 bits + * - Both DMA resources are configured to transfer three beats and + * then repeat again in same buffer + * - On DMA resource which controls the compare value + * - TCC0 overflow triggers DMA transfer + * - The source address increment is enabled + * - The destination address is fixed to TCC channel 0 Compare/Capture + *register + * - On DMA resource which reads the captured value + * - TCC0 capture on channel 1 triggers DMA transfer + * - The source address is fixed to TCC channel 1 Compare/Capture register + * - The destination address increment is enabled + * - The captured value is transferred to an array in SRAM + * + * \section asfdoc_sam0_tcc_dma_use_case_setup Quick Start + * + * \subsection asfdoc_sam0_tcc_dma_use_case_prereq Prerequisites + * There are no prerequisites for this use case. + * + * \subsection asfdoc_sam0_tcc_dma_use_case_setup_code Code + * + * Add to the main application source file, before any functions, according to + * the kit used: + * - SAM D21 Xplained Pro. + * \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_pwm + * \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_feedback + * \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger + * \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_dma_capture_trigger + * - SAM R21 Xplained Pro. + * \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_pwm + * \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_feedback + * \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger + * \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_dma_capture_trigger + * - SAM L21 Xplained Pro. + * \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_pwm + * \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_feedback + * \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger + * + * Add to the main application source file, outside of any functions: + * \snippet qs_tcc_dma.c module_inst + * \snippet qs_tcc_dma.c capture_variables + * \snippet qs_tcc_dma.c compare_variables + * + * Copy-paste the following setup code to your user application: + * \snippet qs_tcc_dma.c config_event_for_capture + * \snippet qs_tcc_dma.c config_dma_for_capture + * \snippet qs_tcc_dma.c config_dma_for_wave + * \snippet qs_tcc_dma.c setup + * + * Add to user application initialization (typically the start of \c main()): + * \snippet qs_tcc_dma.c setup_init + * + * \subsection asfdoc_sam0_tcc_dma_use_case_setup_flow Workflow + * \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_tcc Configure the TCC + * -# Create a module software instance structure for the TCC module to store + * the TCC driver state while it is in use. + * \snippet qs_tcc_dma.c module_inst + * \note This should never go out of scope as long as the module is in use. + * In most cases, this should be global. + * -# Create a TCC module configuration struct, which can be filled out to + * adjust the configuration of a physical TCC peripheral. + * \snippet qs_tcc_dma.c setup_config + * -# Initialize the TCC configuration struct with the module's default values. + * \snippet qs_tcc_dma.c setup_config_defaults + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * -# Alter the TCC settings to configure the counter width, wave generation + * mode and the compare channel 0 value. + * \snippet qs_tcc_dma.c setup_change_config + * -# Alter the TCC settings to configure the PWM output on a physical device + * pin. + * \snippet qs_tcc_dma.c setup_change_config_pwm + * -# Configure the TCC module with the desired settings. + * \snippet qs_tcc_dma.c setup_set_config + * -# Configure and enable the desired events for the TCC module. + * \snippet qs_tcc_dma.c setup_events + * \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_event Configure the Event System + * Configure the EVSYS module to wire channel 0 event to channel 1. + * -# Create an event resource instance. + * \snippet qs_tcc_dma.c capture_event_resource + * \note This should never go out of scope as long as the resource is in + * use. In most cases, this should be global. + * + * -# Create an event resource configuration struct. + * \snippet qs_tcc_dma.c event_setup_1 + * -# Initialize the event resource configuration struct with default values. + * \snippet qs_tcc_dma.c event_setup_2 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * -# Adjust the event resource configuration to desired values. + * \snippet qs_tcc_dma.c event_setup_3 + * -# Allocate and configure the resource using the configuration structure. + * \snippet qs_tcc_dma.c event_setup_4 + * -# Attach a user to the resource. + * \snippet qs_tcc_dma.c event_setup_5 + * \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_dma_capture Configure the DMA for Capture TCC Channel 1 + * Configure the DMAC module to obtain captured value from TCC channel 1. + * -# Create a DMA resource instance. + * \snippet qs_tcc_dma.c capture_dma_resource + * \note This should never go out of scope as long as the resource is in + * use. In most cases, this should be global. + * -# Create a DMA resource configuration struct. + * \snippet qs_tcc_dma.c dma_setup_1 + * -# Initialize the DMA resource configuration struct with default values. + * \snippet qs_tcc_dma.c dma_setup_2 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * -# Adjust the DMA resource configurations. + * \snippet qs_tcc_dma.c dma_setup_3 + * -# Allocate a DMA resource with the configurations. + * \snippet qs_tcc_dma.c dma_setup_4 + * -# Prepare DMA transfer descriptor. + * -# Create a DMA transfer descriptor. + * \snippet qs_tcc_dma.c capture_dma_descriptor + * \note When multiple descriptors are linked, the linked item should + * never go out of scope before it is loaded (to DMA Write-Back + * memory section). In most cases, if more than one descriptors are + * used, they should be global except the very first one. + * -# Create a DMA transfer descriptor struct. + * -# Create a DMA transfer descriptor configuration structure, which can be + * filled out to adjust the configuration of a single DMA transfer. + * \snippet qs_tcc_dma.c dma_setup_5 + * -# Initialize the DMA transfer descriptor configuration struct with + * default values. + * \snippet qs_tcc_dma.c dma_setup_6 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * -# Adjust the DMA transfer descriptor configurations. + * \snippet qs_tcc_dma.c dma_setup_7 + * -# Create the DMA transfer descriptor with the given configuration. + * \snippet qs_tcc_dma.c dma_setup_8 + * -# Start DMA transfer job with prepared descriptor. + * -# Add the DMA transfer descriptor to the allocated DMA resource. + * \snippet qs_tcc_dma.c dma_setup_10 + * \note When adding multiple descriptors, the last added one is linked + * at the end of descriptor queue. If ringed list is needed, just + * add the first descriptor again to build the circle. + * -# Start the DMA transfer job with the allocated DMA resource and + * transfer descriptor. + * \snippet qs_tcc_dma.c dma_setup_11 + * \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_dma_compare Configure the DMA for Compare TCC Channel 0 + * Configure the DMAC module to update TCC channel 0 compare value. + * The flow is similar to last DMA configure step for capture. + * -# Allocate and configure the DMA resource. + * \snippet qs_tcc_dma.c compare_dma_resource + * \snippet qs_tcc_dma.c config_dma_resource_for_wave + * -# Prepare DMA transfer descriptor. + * \snippet qs_tcc_dma.c compare_dma_descriptor + * \snippet qs_tcc_dma.c config_dma_descriptor_for_wave + * -# Start DMA transfer job with prepared descriptor. + * \snippet qs_tcc_dma.c config_dma_job_for_wave + * -# Enable the TCC module to start the timer and begin PWM signal generation. + * \snippet qs_tcc_dma.c setup_enable + * + * \section asfdoc_sam0_tcc_dma_use_case_main Use Case + * + * \subsection asfdoc_sam0_tcc_dma_use_case_main_code Code + * Copy-paste the following code to your user application: + * \snippet qs_tcc_dma.c main + * + * \subsection asfdoc_sam0_tcc_dma_use_case_main_flow Workflow + * -# Enter an infinite loop while the PWM wave is generated via the TCC module. + * \snippet qs_tcc_dma.c main_loop + */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.c new file mode 100644 index 0000000000..77094b2946 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.c @@ -0,0 +1,1547 @@ +#include "tcc.h" + +#if TCC_ASYNC == true +# include "tcc_callback.h" +# include + +/** \internal + * Converts a given TCC index to its interrupt vector index. + */ +# define _TCC_INTERRUPT_VECT_NUM(n, unused) \ + SYSTEM_INTERRUPT_MODULE_TCC##n, +#endif + +#define _SIZE_MAX(size) ((size==32u) ? 0xFFFFFFFF : ( \ + (1u << size) - 1)) + +#define _SIZE_MAX_WITH_DITHER 0x03FFFFFF + +/* Extension support mapping bits */ +#define _TCC_DITHERING_B 16u +#define _TCC_PG_B 8u +#define _TCC_SWAP_B 4u +#define _TCC_DTI_B 2u +#define _TCC_OTMX_B 1u + +#if !defined(__DOXYGEN__) + +# define _TCC_GCLK_ID(n,unused) TPASTE3(TCC,n,_GCLK_ID), +# if (SAML21) +# define _TCC_APBCMASK(n,unused) TPASTE2(MCLK_APBCMASK_TCC,n), +# else +# define _TCC_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TCC,n), +# endif + +# define _TCC_SIZE(n,unused) TPASTE3(TCC,n,_SIZE), +# define _TCC_MAX(n,unused) _SIZE_MAX(TPASTE3(TCC,n,_SIZE)), +# define _TCC_EXT(n,unused) TPASTE3(TCC,n,_EXT), +# define _TCC_CC_NUM(n,unused) min(TPASTE3(TCC,n,_CC_NUM),TCC_NUM_CHANNELS), +# define _TCC_OW_NUM(n,unused) min(TPASTE3(TCC,n,_OW_NUM),TCC_NUM_WAVE_OUTPUTS), + +# define TCC_GCLK_IDS { MREPEAT(TCC_INST_NUM, _TCC_GCLK_ID, 0) } +# define TCC_APBCMASKS { MREPEAT(TCC_INST_NUM, _TCC_APBCMASK, 0) } + +# define TCC_SIZES { MREPEAT(TCC_INST_NUM, _TCC_SIZE, 0) } +# define TCC_MAXS { MREPEAT(TCC_INST_NUM, _TCC_MAX, 0) } +# define TCC_EXTS { MREPEAT(TCC_INST_NUM, _TCC_EXT, 0) } +# define TCC_CC_NUMS { MREPEAT(TCC_INST_NUM, _TCC_CC_NUM, 0) } +# define TCC_OW_NUMS { MREPEAT(TCC_INST_NUM, _TCC_OW_NUM, 0) } + +#endif + +/* List of available TCC modules. */ +const Tcc *const tcc_modules[TCC_INST_NUM] = TCC_INSTS; + +/* List of TCC GCLK IDs */ +const uint8_t _tcc_gclk_ids[TCC_INST_NUM] = TCC_GCLK_IDS; + +/* List of TCC APBC Masks */ +const uint32_t _tcc_apbcmasks[TCC_INST_NUM] = TCC_APBCMASKS; + +/* List of extension support of TCC modules. */ +const uint8_t _tcc_exts[TCC_INST_NUM] = TCC_EXTS; + +/* List of sizes support of TCC modules. */ +const uint8_t _tcc_sizes[TCC_INST_NUM] = TCC_SIZES; + +/* List of maximumvalues supported of TCC modules. */ +const uint32_t _tcc_maxs[TCC_INST_NUM] = TCC_MAXS; + +/* List of available channel number of TCC modules. */ +const uint8_t _tcc_cc_nums[TCC_INST_NUM] = TCC_CC_NUMS; + +/* List of available output number of TCC modules. */ +const uint8_t _tcc_ow_nums[TCC_INST_NUM] = TCC_OW_NUMS; + +/** + * \internal Find the index of the given TCC module instance. + * + * \param[in] The TCC module instance pointer + * + * \return Index of the given TCC module instance. + */ +uint8_t _tcc_get_inst_index( + Tcc *const hw) +{ + /* Find index for TCC instance. */ + for (uint32_t i = 0; i < TCC_INST_NUM; i++) { + if (hw == tcc_modules[i]) { + return i; + } + } + + /* Invalid data given. */ + Assert(false); + return 0; +} + +/** + * \brief Initializes config with predefined default values. + * + * This function will initialize a given TCC configuration structure to + * a set of known default values. This function should be called on + * any new instance of the configuration structures before being + * modified by the user application. + * + * The default configuration is as follows: + * \li Don't run in standby + * \li When setting top,compare or pattern by API, do double buffering write + * \li The base timer/counter configurations: + * - GCLK generator 0 clock source + * - No prescaler + * - GCLK reload action + * - Count upward + * - Don't perform one-shot operations + * - Counter starts on 0 + * - Period/top value set to maximum + * \li The match/capture configurations: + * - All Capture compare channel value set to 0 + * - No capture enabled (all channels use compare function) + * - Normal frequency wave generation + * - Waveform generation polarity set to 0 + * - Don't perform ramp on waveform + * \li The waveform extension configurations: + * - No recoverable fault is enabled, fault actions are disabled, filter + * is set to 0 + * - No non-recoverable fault state output is enabled and filter is 0 + * - No inversion of waveform output + * \li No channel output enabled + * \li No PWM pin output enabled + * \li Pin and MUX configuration not set + * + * \param[out] config Pointer to a TCC module configuration structure to set + * \param[in] hw Pointer to the TCC hardware module + * + */ +void tcc_get_config_defaults( + struct tcc_config *const config, + Tcc *const hw) +{ + /* TCC instance index */ + uint8_t module_index = _tcc_get_inst_index(hw); + + /* Base counter defaults */ + config->counter.count = 0; + + config->counter.period = _tcc_maxs[module_index]; + + config->counter.clock_source = GCLK_GENERATOR_0; + config->counter.clock_prescaler = TCC_CLOCK_PRESCALER_DIV1; + config->counter.reload_action = TCC_RELOAD_ACTION_GCLK; + + config->counter.direction = TCC_COUNT_DIRECTION_UP; + config->counter.oneshot = false; + + /* Match/Capture defaults */ +# define _TCC_CHANNEL_MATCH_VALUE_INIT(n, value) \ + config->compare.match[n] = value; + MREPEAT(TCC_NUM_CHANNELS, + _TCC_CHANNEL_MATCH_VALUE_INIT, 0) +# undef _TCC_CHANNEL_MATCH_VALUE_INIT + + /* Wave polarity defaults */ +# define _TCC_CHANNEL_WAVE_POLARITY_INIT(n, value) \ + config->compare.wave_polarity[n] = value; + MREPEAT(TCC_NUM_CHANNELS, + _TCC_CHANNEL_WAVE_POLARITY_INIT, TCC_WAVE_POLARITY_0) +# undef _TCC_CHANNEL_WAVE_POLARITY_INIT + + config->compare.wave_generation = TCC_WAVE_GENERATION_NORMAL_FREQ; + config->compare.wave_ramp = TCC_RAMP_RAMP1; + +# define _TCC_CHANNEL_FUNCTION_INIT(n, value) \ + config->compare.channel_function[n] = value; + MREPEAT(TCC_NUM_CHANNELS, + _TCC_CHANNEL_FUNCTION_INIT, TCC_CHANNEL_FUNCTION_COMPARE) +# undef _TCC_CHANNEL_FUNCTION_INIT + + /* Recoverable fault defaults */ +# define _TCC_FAULT_FUNCTION_INIT(n, dummy) \ + config->wave_ext.recoverable_fault[n].filter_value = 0; \ + config->wave_ext.recoverable_fault[n].blanking_cycles = 0; \ + config->wave_ext.recoverable_fault[n].restart = false; \ + config->wave_ext.recoverable_fault[n].keep = false; \ + config->wave_ext.recoverable_fault[n].qualification = false; \ + config->wave_ext.recoverable_fault[n].source = TCC_FAULT_SOURCE_DISABLE; \ + config->wave_ext.recoverable_fault[n].blanking = TCC_FAULT_BLANKING_DISABLE; \ + config->wave_ext.recoverable_fault[n].halt_action = TCC_FAULT_HALT_ACTION_DISABLE; \ + config->wave_ext.recoverable_fault[n].capture_action = TCC_FAULT_CAPTURE_DISABLE; \ + config->wave_ext.recoverable_fault[n].capture_channel = TCC_FAULT_CAPTURE_CHANNEL_0; + MREPEAT(TCC_NUM_FAULTS, _TCC_FAULT_FUNCTION_INIT, 0) +# undef _TCC_FAULT_FUNCTION_INIT + + /* Non-recoverable fault defaults */ +# define _TCC_NRF_FUNCTION_INIT(n, dummy) \ + config->wave_ext.non_recoverable_fault[n].filter_value = 0; \ + config->wave_ext.non_recoverable_fault[n].output = TCC_FAULT_STATE_OUTPUT_OFF; + MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_NRF_FUNCTION_INIT, 0) +# undef _TCC_NRF_FUNCTION_INIT + + /* Output inversion defaults */ +# define _TCC_OUT_INVERT_INIT(n, value) \ + config->wave_ext.invert[n] = value; + MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_OUT_INVERT_INIT, false) +# undef _TCC_OUT_INVERT_INIT + +# define _TCC_CHANNEL_OUT_PIN_INIT(n, dummy) \ + config->pins.enable_wave_out_pin[n] = false;\ + config->pins.wave_out_pin[TCC_WAVE_OUTPUT_##n] = 0; \ + config->pins.wave_out_pin_mux[TCC_WAVE_OUTPUT_##n] = 0; + MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_CHANNEL_OUT_PIN_INIT, 0) +# undef _TCC_CHANNEL_OUT_PIN_INIT + + config->double_buffering_enabled = true; + config->run_in_standby = false; +} + + +/** + * \brief Build CTRLA register value from configuration. + * + * \param[in] module_index The software module instance index + * \param[in] config Pointer to the TCC configuration options struct + * \param[out] value_buffer Pointer to the buffer to fill with built value + * + * \return Configuration validation status. + * + * \retval STATUS_OK Configuration values are good and register + * value built and save to buffer + * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: + * assigned dither mode is invalid for module; + * used capture channel is invalid for module + */ +static inline enum status_code _tcc_build_ctrla( + const uint8_t module_index, + const struct tcc_config *const config, + uint32_t *value_buffer) +{ + uint32_t ctrla = 0; + + int i; + for (i = 0; i < TCC_NUM_CHANNELS; i ++) { + if (config->capture.channel_function[i] == + TCC_CHANNEL_FUNCTION_CAPTURE) { + + if (i > _tcc_cc_nums[module_index]) { + /* Channel not supported */ + return STATUS_ERR_INVALID_ARG; + } + ctrla |= (TCC_CTRLA_CPTEN0 << i); + } + } + + if (config->run_in_standby) { + ctrla |= TCC_CTRLA_RUNSTDBY; + } + ctrla |= config->counter.reload_action << TCC_CTRLA_PRESCSYNC_Pos; + ctrla |= config->counter.clock_prescaler << TCC_CTRLA_PRESCALER_Pos; + + *value_buffer = ctrla; + return STATUS_OK; +} + +/** + * \brief Build CTRLB register value from configuration. + * + * \param[in] module_index The software module instance index + * \param[in] config Pointer to the TCC configuration options struct + * \param[out] value_buffer Pointer to the buffer to fill with built value + */ +static inline void _tcc_build_ctrlb( + const uint8_t module_index, + const struct tcc_config *const config, + uint8_t *value_buffer) +{ + uint8_t ctrlb = 0; + + if (config->counter.oneshot) { + ctrlb |= TCC_CTRLBSET_ONESHOT; + } + if (config->counter.direction == TCC_COUNT_DIRECTION_DOWN) { + ctrlb |= TCC_CTRLBSET_DIR; + } + + *value_buffer = ctrlb; +} + +/** + * \brief Build FAULTs register values from configuration. + * + * \param[in] module_index The software module instance index + * \param[in] config Pointer to the TCC configuration options struct + * \param[out] value_buffer Pointer to the buffer to fill with built values + * + * \retval STATUS_OK Configuration values are good and register + * value built and save to buffer + * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned fault + * capture channel is invalid; assigned filter + * value is invalid + */ +static inline enum status_code _tcc_build_faults( + const uint8_t module_index, + const struct tcc_config *const config, + uint32_t *value_buffer) +{ + struct tcc_recoverable_fault_config *cfg; + uint8_t cc_num = _tcc_cc_nums[module_index]; + uint32_t fault; + int i; + for (i = 0; i < TCC_NUM_FAULTS; i ++) { + cfg = (struct tcc_recoverable_fault_config *) + &config->wave_ext.recoverable_fault[i]; + if (cfg->capture_channel >= cc_num) { + return STATUS_ERR_INVALID_ARG; + } + if (cfg->filter_value > 0xF) { + return STATUS_ERR_INVALID_ARG; + } + fault = TCC_FCTRLA_FILTERVAL(cfg->filter_value) + | TCC_FCTRLA_BLANKVAL(cfg->blanking_cycles) + | (cfg->restart ? TCC_FCTRLA_RESTART : 0) + | (cfg->keep ? TCC_FCTRLA_KEEP : 0) + | (cfg->qualification ? TCC_FCTRLA_QUAL : 0) + | TCC_FCTRLA_SRC(cfg->source) + | TCC_FCTRLA_BLANK(cfg->blanking) + | TCC_FCTRLA_HALT(cfg->halt_action) + | TCC_FCTRLA_CAPTURE(cfg->capture_action) + | TCC_FCTRLA_CHSEL(cfg->capture_channel); + value_buffer[i] = fault; + } + return STATUS_OK; +} + +/** + * \brief Build DRVCTRL register values from configuration. + * + * \param[in] module_index The software module instance index + * \param[in] config Pointer to the TCC configuration options struct + * \param[out] value_buffer Pointer to the buffer to fill with built value + * + * \retval STATUS_OK Configuration values are good and register + * value built and save to buffer + * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line + * is invalid; filter value is invalid + */ +static inline enum status_code _tcc_build_drvctrl( + const uint8_t module_index, + const struct tcc_config *const config, + uint32_t *value_buffer) +{ + uint32_t i; + uint8_t ow_num = _tcc_ow_nums[module_index]; + uint32_t drvctrl; + + drvctrl = 0; + + for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) { + if (config->wave_ext.invert[i]) { + if (i >= ow_num) { + return STATUS_ERR_INVALID_ARG; + } + drvctrl |= (TCC_DRVCTRL_INVEN0 << i); + } + if (config->wave_ext.non_recoverable_fault[i].output != + TCC_FAULT_STATE_OUTPUT_OFF) { + if (i >= ow_num) { + return STATUS_ERR_INVALID_ARG; + } + if (config->wave_ext.non_recoverable_fault[i].output == + TCC_FAULT_STATE_OUTPUT_1) { + drvctrl |= (TCC_DRVCTRL_NRE0 | TCC_DRVCTRL_NRV0) << i; + } else { + drvctrl |= (TCC_DRVCTRL_NRE0) << i; + } + } + } + *value_buffer = drvctrl; + return STATUS_OK; +} + +/** + * \brief Build WAVE & WAVEB register values from configuration. + * + * \param[in] module_index The software module instance index + * \param[in] config Pointer to the TCC configuration options struct + * \param[out] value_buffer Pointer to the buffer to fill with built value + * + * \retval STATUS_OK Configuration values are good and register + * value built and save to buffer + * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line + * is invalid; circular and double buffering + * conflict; assigned function not supported by + * module + */ +static inline enum status_code _tcc_build_waves( + const uint8_t module_index, + const struct tcc_config *const config, + uint32_t *value_buffer) +{ + int n; + + uint8_t cc_num = _tcc_cc_nums[module_index]; + struct tcc_match_wave_config const *wav_cfg = &config->compare; + + uint32_t wave; + + wave = TCC_WAVE_RAMP(wav_cfg->wave_ramp) | + TCC_WAVE_WAVEGEN(wav_cfg->wave_generation); + + for (n = 0; n < TCC_NUM_CHANNELS; n++) { + if (wav_cfg->wave_polarity[n]) { + if (n >= cc_num) { + return STATUS_ERR_INVALID_ARG; + } + wave |= (TCC_WAVE_POL0 << n); + } + } + + value_buffer[0] = wave; + + return STATUS_OK; +} + +/** + * \brief Initializes a hardware TCC module instance. + * + * Enables the clock and initializes the given TCC module, based on the given + * configuration values. + * + * \param[in,out] module_inst Pointer to the software module instance struct + * \param[in] hw Pointer to the TCC hardware module + * \param[in] config Pointer to the TCC configuration options struct + * + * \return Status of the initialization procedure. + * + * \retval STATUS_OK The module was initialized successfully + * \retval STATUS_BUSY Hardware module was busy when the + * initialization procedure was attempted + * \retval STATUS_INVALID_ARG An invalid configuration option or argument + * was supplied + * \retval STATUS_ERR_DENIED Hardware module was already enabled + */ +enum status_code tcc_init( + struct tcc_module *const module_inst, + Tcc *const hw, + const struct tcc_config *const config) +{ + int i; + + /* Sanity check arguments */ + Assert(hw); + Assert(module_inst); + Assert(config); + + /* TCC instance index */ + uint8_t module_index = _tcc_get_inst_index(hw); + + /* Enable the user interface clock for TCC */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, + _tcc_apbcmasks[module_index]); + + /* Check if it's enabled. */ + if (hw->CTRLA.reg & TCC_CTRLA_ENABLE) { + return STATUS_ERR_DENIED; + } + /* Check if it's resetting */ + if (hw->CTRLA.reg & TCC_CTRLA_SWRST) { + return STATUS_ERR_DENIED; + } + + enum status_code status; + + /* Check COUNT, PER, CCx */ + uint32_t count_max = _tcc_maxs[module_index]; + + /* Check all counter values */ + if ((config->counter.count > count_max) + || (config->counter.period > count_max) + ) { + return STATUS_ERR_INVALID_ARG; + } + + /* Check all channel values */ + for (i = 0; i < TCC_NUM_CHANNELS; i ++) { + if ((config->compare.match[i] > count_max) + ) { + return STATUS_ERR_INVALID_ARG; + } + } + + /* Check all outputs */ + for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) { + if (!config->pins.enable_wave_out_pin[i]) { + continue; + } + /* Output line is not supported */ + if (i >= _tcc_ow_nums[module_index]) { + return STATUS_ERR_INVALID_ARG; + } + } + + /* CTRLA settings */ + uint32_t ctrla = 0; + status = _tcc_build_ctrla(module_index, config, &ctrla); + if (STATUS_OK != status) { + return status; + } + + /* CTRLB settings */ + uint8_t ctrlb; + _tcc_build_ctrlb(module_index, config, &ctrlb); + + /* FAULTs settings */ + uint32_t faults[TCC_NUM_FAULTS]; + + status = _tcc_build_faults(module_index, config, faults); + if (STATUS_OK != status) { + return status; + } + + /* DRVCTRL */ + uint32_t drvctrl = 0; + + status = _tcc_build_drvctrl(module_index, config, &drvctrl); + if (STATUS_OK != status) { + return status; + } + + /* WAVE */ + uint32_t waves[1]; + + status = _tcc_build_waves(module_index, config, waves); + if (STATUS_OK != status) { + return status; + } + + /* Initialize module */ +#if TCC_ASYNC + /* Initialize parameters */ + for (i = 0; i < TCC_CALLBACK_N; i ++) { + module_inst->callback[i] = NULL; + } + module_inst->register_callback_mask = 0; + module_inst->enable_callback_mask = 0; + _tcc_instances[module_index] = module_inst; +#endif + + module_inst->hw = hw; + + module_inst->double_buffering_enabled = config->double_buffering_enabled; + + /* Setup clock for module */ + struct system_gclk_chan_config gclk_chan_config; + system_gclk_chan_get_config_defaults(&gclk_chan_config); + gclk_chan_config.source_generator = config->counter.clock_source; + system_gclk_chan_set_config(_tcc_gclk_ids[module_index], &gclk_chan_config); + system_gclk_chan_enable(_tcc_gclk_ids[module_index]); + + /* Initialize pins */ + struct system_pinmux_config pin_config; + for (i = 0; i < _tcc_ow_nums[module_index]; i ++) { + if (!config->pins.enable_wave_out_pin[i]) { + continue; + } + + system_pinmux_get_config_defaults(&pin_config); + pin_config.mux_position = config->pins.wave_out_pin_mux[i]; + pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; + system_pinmux_pin_set_config( + config->pins.wave_out_pin[i], &pin_config); + } + + /* Write to registers */ + + hw->CTRLA.reg = ctrla; + while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { + /* Wait for sync */ + } + + hw->CTRLBCLR.reg = 0xFF; + while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { + /* Wait for sync */ + } + hw->CTRLBSET.reg = ctrlb; + + hw->FCTRLA.reg = faults[0]; + hw->FCTRLB.reg = faults[1]; + + hw->DRVCTRL.reg = drvctrl; + +#if (!SAML21) + while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_WAVE | TCC_SYNCBUSY_WAVEB)) { + /* Wait for sync */ + } +#endif + hw->WAVE.reg = waves[0]; + + while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) { + /* Wait for sync */ + } + hw->COUNT.reg = config->counter.count; + +#if (!SAML21) + while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_PER | TCC_SYNCBUSY_PERB)) { + /* Wait for sync */ + } +#endif + hw->PER.reg = (config->counter.period); + + for (i = 0; i < _tcc_cc_nums[module_index]; i ++) { +#if (!SAML21) + while (hw->SYNCBUSY.reg & ( + (TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CCB0) << i)) { + /* Wait for sync */ + } +#endif + hw->CC[i].reg = (config->compare.match[i]); + } + + return STATUS_OK; +} + + +/** + * \brief Enables the TCC module event input or output. + * + * Enables one or more input or output events to or from the TCC module. + * See \ref tcc_events for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] events Struct containing flags of events to enable or + * configure + * + * \return Status of the events setup procedure. + * + * \retval STATUS_OK The module was initialized successfully + * \retval STATUS_INVALID_ARG An invalid configuration option or argument + * was supplied + */ +enum status_code tcc_enable_events( + struct tcc_module *const module_inst, + struct tcc_events *const events) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); + + Tcc *const tcc_module = module_inst->hw; + + /* Check if it's enabled or resetting. */ + if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) { + return STATUS_ERR_DENIED; + } + + uint32_t evctrl = tcc_module->EVCTRL.reg; + + /* Setup event output action */ + if (events->output_config.modify_generation_selection) { + evctrl &= ~ TCC_EVCTRL_CNTSEL_Msk; + switch(events->output_config.generation_selection) { + case TCC_EVENT_GENERATION_SELECTION_START: + evctrl |= TCC_EVCTRL_CNTSEL_START; + break; + case TCC_EVENT_GENERATION_SELECTION_END: + evctrl |= TCC_EVCTRL_CNTSEL_END; + break; + case TCC_EVENT_GENERATION_SELECTION_BETWEEN: + evctrl |= TCC_EVCTRL_CNTSEL_BETWEEN; + break; + case TCC_EVENT_GENERATION_SELECTION_BOUNDARY: + evctrl |= TCC_EVCTRL_CNTSEL_BOUNDARY; + break; + default: + Assert(false); + /* Wrong configuration */ + return STATUS_ERR_INVALID_ARG; + } + } + /* Setup input event0 */ + if (events->on_input_event_perform_action[0]) { + evctrl |= TCC_EVCTRL_TCEI0; + } + if (events->input_config[0].invert) { + evctrl |= TCC_EVCTRL_TCINV0; + } + if (events->input_config[0].modify_action) { + evctrl &= ~ TCC_EVCTRL_EVACT0_Msk; + switch(events->input_config[0].action) { + case TCC_EVENT0_ACTION_OFF: + evctrl |= TCC_EVCTRL_EVACT0_OFF; + break; + case TCC_EVENT0_ACTION_RETRIGGER: + evctrl |= TCC_EVCTRL_EVACT0_RETRIGGER; + break; + case TCC_EVENT0_ACTION_COUNT_EVENT: + evctrl |= TCC_EVCTRL_EVACT0_COUNTEV; + break; + case TCC_EVENT0_ACTION_START: + evctrl |= TCC_EVCTRL_EVACT0_START; + break; + case TCC_EVENT0_ACTION_INCREMENT: + evctrl |= TCC_EVCTRL_EVACT0_INC; + break; + case TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE: + evctrl |= TCC_EVCTRL_EVACT0_COUNT; + break; + case TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT: + evctrl |= TCC_EVCTRL_EVACT0_FAULT; + break; + default: + Assert(false); + /* Wrong configuration */ + return STATUS_ERR_INVALID_ARG; + } + } + /* Setup input event1 */ + if (events->on_input_event_perform_action[1]) { + evctrl |= TCC_EVCTRL_TCEI1; + } + if (events->input_config[1].invert) { + evctrl |= TCC_EVCTRL_TCINV1; + } + if (events->input_config[1].modify_action) { + evctrl &= ~ TCC_EVCTRL_EVACT1_Msk; + switch(events->input_config[1].action) { + case TCC_EVENT1_ACTION_OFF: + evctrl |= TCC_EVCTRL_EVACT1_OFF; + break; + case TCC_EVENT1_ACTION_RETRIGGER: + evctrl |= TCC_EVCTRL_EVACT1_RETRIGGER; + break; + case TCC_EVENT1_ACTION_DIR_CONTROL: + evctrl |= TCC_EVCTRL_EVACT1_DIR; + break; + case TCC_EVENT1_ACTION_STOP: + evctrl |= TCC_EVCTRL_EVACT1_STOP; + break; + case TCC_EVENT1_ACTION_DECREMENT: + evctrl |= TCC_EVCTRL_EVACT1_DEC; + break; + case TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE: + evctrl |= TCC_EVCTRL_EVACT1_PPW | + TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1; + break; + case TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE: + evctrl |= TCC_EVCTRL_EVACT1_PWP | + TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1; + break; + case TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT: + evctrl |= TCC_EVCTRL_EVACT1_FAULT; + break; + default: + Assert(false); + /* Wrong configuration */ + return STATUS_ERR_INVALID_ARG; + } + } + uint32_t ch; + for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) { + if (events->generate_event_on_channel[ch]) { + evctrl |= (TCC_EVCTRL_MCEO(1) << ch); + } + if (events->on_event_perform_channel_action[ch]) { + evctrl |= (TCC_EVCTRL_MCEI(1) << ch); + } + } + if (events->generate_event_on_counter_overflow) { + evctrl |= TCC_EVCTRL_OVFEO; + } + if (events->generate_event_on_counter_retrigger) { + evctrl |= TCC_EVCTRL_TRGEO; + } + if (events->generate_event_on_counter_event) { + evctrl |= TCC_EVCTRL_CNTEO; + } + + tcc_module->EVCTRL.reg = evctrl; + + return STATUS_OK; +} + +/** + * \brief Disables the event input or output of a TCC instance. + * + * Disables one or more input or output events for the given TCC module. + * See \ref tcc_events for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] events Struct containing flags of events to disable + */ +void tcc_disable_events( + struct tcc_module *const module_inst, + struct tcc_events *const events) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); + + Tcc *const tcc_module = module_inst->hw; + + /* Check if it's enabled or resetting. */ + if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) { + return; + } + + + uint32_t evctrl = 0; + uint32_t ch; + for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) { + if (events->generate_event_on_channel[ch]) { + evctrl |= (TCC_EVCTRL_MCEO(1) << ch); + } + if (events->on_event_perform_channel_action[ch]) { + evctrl |= (TCC_EVCTRL_MCEI(1) << ch); + } + } + if (events->generate_event_on_counter_overflow) { + evctrl |= TCC_EVCTRL_OVFEO; + } + if (events->generate_event_on_counter_retrigger) { + evctrl |= TCC_EVCTRL_TRGEO; + } + if (events->generate_event_on_counter_event) { + evctrl |= TCC_EVCTRL_CNTEO; + } + if (events->on_input_event_perform_action[0]) { + evctrl |= TCC_EVCTRL_TCEI0; + } + if (events->on_input_event_perform_action[1]) { + evctrl |= TCC_EVCTRL_TCEI1; + } + if (events->input_config[0].invert) { + evctrl |= TCC_EVCTRL_TCINV0; + } + if (events->input_config[1].invert) { + evctrl |= TCC_EVCTRL_TCINV1; + } + + tcc_module->EVCTRL.reg &= ~evctrl; +} + + + +/** + * \brief Sets count value for the given TCC module. + * + * Sets the timer count value of an initialized TCC module. The + * specified TCC module can remain running or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] count New timer count value to set + * + * \return Status which indicates whether the new value is set. + * + * \retval STATUS_OK The timer count was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified + */ +enum status_code tcc_set_count_value( + const struct tcc_module *const module_inst, + const uint32_t count) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance*/ + Tcc *const tcc_module = module_inst->hw; + /* Get a index of the module */ + uint8_t module_index = _tcc_get_inst_index(tcc_module); + + uint32_t max_count = _tcc_maxs[module_index]; + + if (count > max_count) { + return STATUS_ERR_INVALID_ARG; + } + + while (tcc_module->SYNCBUSY.bit.COUNT) { + /* Wait for sync */ + } + + /* Write to based on the TCC dithering */ + tcc_module->COUNT.reg = (count); + + return STATUS_OK; +} + +/** + * \brief Get count value of the given TCC module. + * + * Retrieves the current count value of a TCC module. The specified TCC module + * can remain running or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + * + * \return Count value of the specified TCC module. + */ +uint32_t tcc_get_count_value( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance*/ + Tcc *const tcc_module = module_inst->hw; + uint32_t last_cmd; + + /* Wait last command done */ + do { + while (tcc_module->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; + if (TCC_CTRLBSET_CMD_NONE == last_cmd) { + /* Issue read command and break */ + tcc_module->CTRLBSET.bit.CMD = TCC_CTRLBSET_CMD_READSYNC_Val; + break; + } else if (TCC_CTRLBSET_CMD_READSYNC == last_cmd) { + /* Command have been issued */ + break; + } + } while (1); + + while (tcc_module->SYNCBUSY.bit.COUNT) { + /* Wait for sync */ + } + return (tcc_module->COUNT.reg); +} + + + +/** + * \brief Gets the TCC module capture value. + * + * Retrieves the capture value in the indicated TCC module capture channel. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the Compare Capture channel to read + * + * \return Capture value stored in the specified timer channel. + */ +uint32_t tcc_get_capture_value( + const struct tcc_module *const module_inst, + const enum tcc_match_capture_channel channel_index) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Assert(channel_index < _tcc_cc_nums[_tcc_get_inst_index(module_inst->hw)]); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + + while(tcc_module->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << channel_index)) { + /* Sync wait */ + } + + return tcc_module->CC[channel_index].reg; +} + +/** + * \internal + * \brief Sets a TCC module compare value/buffer. + * + * Writes a compare value to the given TCC module compare/capture channel or + * buffer one. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the compare channel to write to + * \param[in] compare New compare value/buffer value to set + * \param[in] double_buffering_enabled Set to \c true to write to CCBx + * + * \return Status of the compare update procedure. + * + * \retval STATUS_OK The compare value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or + * compare value exceed resolution + */ +static enum status_code _tcc_set_compare_value( + const struct tcc_module *const module_inst, + const enum tcc_match_capture_channel channel_index, + const uint32_t compare, + const bool double_buffering_enabled) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + /* Get a index of the module */ + uint8_t module_index = _tcc_get_inst_index(tcc_module); + + /* Check index */ + if (channel_index >= _tcc_cc_nums[module_index]) { + return STATUS_ERR_INVALID_ARG; + } + + uint32_t max_count = _tcc_maxs[module_index]; + + /* Check compare value */ + if (compare > max_count) { + return STATUS_ERR_INVALID_ARG; + } + + if (double_buffering_enabled) { +#if (SAML21) + tcc_module->CCBUF[channel_index].reg = compare; +#else + while(tcc_module->SYNCBUSY.reg & + (TCC_SYNCBUSY_CCB0 << channel_index)) { + /* Sync wait */ + } + tcc_module->CCB[channel_index].reg = compare; +#endif + } else { + while(tcc_module->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << channel_index)) { + /* Sync wait */ + } + tcc_module->CC[channel_index].reg = compare; + } + return STATUS_OK; +} + + +/** + * \brief Sets a TCC module compare value. + * + * Writes a compare value to the given TCC module compare/capture channel. + * + * If double buffering is enabled it always write to the buffer + * register. The value will then be updated immediately by calling + * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit + * is cleared and the UPDATE condition happen. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the compare channel to write to + * \param[in] compare New compare value to set + * + * \return Status of the compare update procedure. + * + * \retval STATUS_OK The compare value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or + * compare value exceed resolution + */ +enum status_code tcc_set_compare_value( + const struct tcc_module *const module_inst, + const enum tcc_match_capture_channel channel_index, + const uint32_t compare) +{ + /* Sanity check arguments */ + Assert(module_inst); + + return _tcc_set_compare_value(module_inst, channel_index, compare, + module_inst->double_buffering_enabled); +} + +/** + * \brief Sets a TCC module compare value and buffer value. + * + * Writes compare value and buffer to the given TCC module compare/capture + * channel. Usually as preparation for double buffer or circulared double buffer + * (circular buffer). + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the compare channel to write to + * \param[in] compare New compare value to set + * \param[in] compare_buffer New compare buffer value to set + * + * \return Status of the compare update procedure. + * + * \retval STATUS_OK The compare value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or + * compare value exceed resolution + */ +enum status_code tcc_set_double_buffer_compare_values( + struct tcc_module *const module_inst, + const enum tcc_match_capture_channel channel_index, + const uint32_t compare, const uint32_t compare_buffer) +{ + /* Sanity check arguments */ + Assert(module_inst); + + enum status_code status; + status = _tcc_set_compare_value(module_inst, channel_index, compare, false); + if (status != STATUS_OK) { + return status; + } + return _tcc_set_compare_value(module_inst, channel_index, compare_buffer, + true); +} + + +/** + * \internal + * \brief Set the timer TOP/PERIOD buffer/value. + * + * This function writes the given value to the PER/PERB register. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] top_value New value to be loaded into the PER/PERB register + * \param[in] double_buffering_enabled Set to \c true to write to PERB + * + * \return Status of the TOP set procedure. + * + * \retval STATUS_OK The timer TOP value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or + * top/period value exceed resolution + */ +static enum status_code _tcc_set_top_value( + const struct tcc_module *const module_inst, + const uint32_t top_value, + const bool double_buffering_enabled) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + /* Get a index of the module */ + uint8_t module_index = _tcc_get_inst_index(tcc_module); + + uint32_t max_count = _tcc_maxs[module_index]; + + /* Check compare value */ + if (top_value > max_count) { + return STATUS_ERR_INVALID_ARG; + } + + if (double_buffering_enabled) { +#if (SAML21) + tcc_module->PERBUF.reg = top_value; +#else + while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PERB) { + /* Sync wait */ + } + tcc_module->PERB.reg = top_value; +#endif + } else { + while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PER) { + /* Sync wait */ + } + tcc_module->PER.reg = top_value; + } + return STATUS_OK; +} + + +/** + * \brief Set the timer TOP/PERIOD value. + * + * This function writes the given value to the PER/PERB register. + * + * If double buffering is enabled it always write to the buffer + * register (PERB). The value will then be updated immediately by calling + * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit + * is cleared and the UPDATE condition happen. + * + * When using MFRQ, the top value is defined by the CC0 register value and the + * PER value is ignored, so + * \ref tcc_set_compare_value (module,channel_0,value) must be used instead of + * this function to change the actual top value in that case. + * For all other waveforms operation the top value is defined by PER register + * value. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] top_value New value to be loaded into the PER/PERB register + * + * \return Status of the TOP set procedure. + * + * \retval STATUS_OK The timer TOP value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or + * top/period value exceed resolution + */ +enum status_code tcc_set_top_value( + const struct tcc_module *const module_inst, + const uint32_t top_value) +{ + /* Sanity check arguments */ + Assert(module_inst); + + return _tcc_set_top_value(module_inst, top_value, + module_inst->double_buffering_enabled); +} + +/** + * \brief Set the timer TOP/PERIOD value and buffer value. + * + * This function writes the given value to the PER and PERB register. Usually as + * preparation for double buffer or circulared double buffer (circular buffer). + * + * When using MFRQ, the top values are defined by the CC0 and CCB0, the PER and + * PERB values are ignored, so + * \ref tcc_set_double_buffer_compare_values (module,channel_0,value,buffer) must + * be used instead of this function to change the actual top values in that + * case. For all other waveforms operation the top values are defined by PER and + * PERB registers values. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] top_value New value to be loaded into the PER register + * \param[in] top_buffer_value New value to be loaded into the PERB register + * + * \return Status of the TOP set procedure. + * + * \retval STATUS_OK The timer TOP value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or + * top/period value exceed resolution + */ +enum status_code tcc_set_double_buffer_top_values( + const struct tcc_module *const module_inst, + const uint32_t top_value, const uint32_t top_buffer_value) +{ + /* Sanity check arguments */ + Assert(module_inst); + + enum status_code status; + status = _tcc_set_top_value(module_inst, top_value, false); + if (status != STATUS_OK) { + return status; + } + return _tcc_set_top_value(module_inst, top_buffer_value, true); +} + + +/** + * \brief Sets the TCC module waveform output pattern. + * + * Force waveform output line to generate specific pattern (0, 1, or as is). + * + * If double buffering is enabled it always write to the buffer + * register. The value will then be updated immediately by calling + * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit + * is cleared and the UPDATE condition happen. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] line_index Output line index + * \param[in] pattern Output pattern to use (\ref tcc_output_pattern) + * + * \return Status of the pattern set procedure. + * + * \retval STATUS_OK The PATT register is updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid line index was supplied + */ +enum status_code tcc_set_pattern( + const struct tcc_module *const module_inst, + const uint32_t line_index, + const enum tcc_output_pattern pattern) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + /* Get a index of the module */ + uint8_t module_index = _tcc_get_inst_index(tcc_module); + /* Get number of output lines */ + uint8_t ow_num = _tcc_ow_nums[module_index]; + + /* Check if line number is OK */ + if (line_index >= ow_num) { + return STATUS_ERR_INVALID_ARG; + } + + uint32_t patt_value; + + while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) { + /* Sync wait */ + } + patt_value = tcc_module->PATT.reg; + if (TCC_OUTPUT_PATTERN_DISABLE == pattern) { + patt_value &= ~(TCC_PATT_PGE0 << line_index); + } else if (TCC_OUTPUT_PATTERN_0 == pattern) { + patt_value &= ~(TCC_PATT_PGV0 << line_index); + patt_value |= (TCC_PATT_PGE0 << line_index); + } else { + patt_value |= ((TCC_PATT_PGE0 | TCC_PATT_PGV0) << line_index); + } + + if (module_inst->double_buffering_enabled) { +#if (SAML21) + tcc_module->PATTBUF.reg = patt_value; +#else + while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PATTB) { + /* Sync wait */ + } + tcc_module->PATTB.reg = patt_value; +#endif + } else { + tcc_module->PATT.reg = patt_value; + } + return STATUS_OK; +} + +/** + * \brief Retrieves the current module status. + * + * Retrieves the status of the module, giving overall state information. + * + * \param[in] module_inst Pointer to the TCC software instance struct + * + * \return Bitmask of \c TCC_STATUS_* flags. + * + * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occured + * \retval TCC_STATUS_CHANNEL_OUTPUT(n) Channel n match/capture output state + * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occured + * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occured + * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present + * \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) Recoverable fault n input present + * \retval TCC_STATUS_SYNC_READY None of register is syncing + * \retval TCC_STATUS_CAPTURE_OVERFLOW Timer capture data has overflowed + * \retval TCC_STATUS_COUNTER_EVENT Timer counter event has occurred + * \retval TCC_STATUS_COUNT_OVERFLOW Timer count value has overflowed + * \retval TCC_STATUS_COUNTER_RETRIGGERED Timer counter has been retriggered + * \retval TCC_STATUS_STOP Timer counter has been stopped + * \retval TCC_STATUS_RAMP_CYCLE_INDEX Wave ramp index for cycle + */ +uint32_t tcc_get_status( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + uint32_t int_flags = module_inst->hw->INTFLAG.reg; + uint32_t status_flags = module_inst->hw->STATUS.reg; + uint32_t status = 0; + int i; + + /* SYNC */ + if (module_inst->hw->SYNCBUSY.reg == 0) { + status |= TCC_STATUS_SYNC_READY; + } + + /* Channels */ + for (i = 0; i < TCC_NUM_CHANNELS; i++) { + if (int_flags & TCC_INTFLAG_MC(i)) { + status |= TCC_STATUS_CHANNEL_MATCH_CAPTURE(i); + } + if (status_flags & TCC_STATUS_CMP(i)) { + status |= TCC_STATUS_CHANNEL_OUTPUT(i); + } + } + /* Non-recoverable fault state */ + if ((int_flags & TCC_INTFLAG_FAULT1) || + (status_flags & TCC_STATUS_FAULT1)) { + status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1); + } + if ((int_flags & TCC_INTFLAG_FAULT0) || + (status_flags & TCC_STATUS_FAULT0)) { + status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0); + } + /* Non-recoverable fault inputs */ + if (status_flags & TCC_STATUS_FAULT0IN) { + status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(0); + } + if (status_flags & TCC_STATUS_FAULT1IN) { + status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(1); + } + /* Recoverable fault state */ + if ((int_flags & TCC_INTFLAG_FAULTB) || + (status_flags & TCC_STATUS_FAULTB)) { + status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1); + } + if ((int_flags & TCC_INTFLAG_FAULTA) || + (status_flags & TCC_STATUS_FAULTA)) { + status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0); + } + /* Recoverable fault inputs */ + if (status_flags & TCC_STATUS_FAULTAIN) { + status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(0); + } + if (status_flags & TCC_STATUS_FAULTBIN) { + status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(1); + } + + /* Check for TCC capture overflow */ + if (int_flags & TCC_INTFLAG_ERR) { + status |= TCC_STATUS_CAPTURE_OVERFLOW; + } + /* Check for TCC count counter */ + if (int_flags & TCC_INTFLAG_CNT) { + status |= TCC_STATUS_COUNTER_EVENT; + } + /* Check for TCC count retrigger */ + if (int_flags & TCC_INTFLAG_TRG) { + status |= TCC_STATUS_COUNTER_RETRIGGERED; + } + /* Check for TCC count overflow */ + if (int_flags & TCC_INTFLAG_OVF) { + status |= TCC_STATUS_COUNT_OVERFLOW; + } + /* Check for TCC count stop */ + if (status_flags & TCC_STATUS_STOP) { + status |= TCC_STATUS_STOPPED; + } + return status; +} + +/** + * \brief Clears a module status flag. + * + * Clears the given status flag of the module. + * + * \param[in] module_inst Pointer to the TCC software instance struct + * \param[in] status_flags Bitmask of \c TCC_STATUS_* flags to clear + */ +void tcc_clear_status( + struct tcc_module *const module_inst, + const uint32_t status_flags) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + uint32_t int_clr = 0; + uint32_t status_clr = 0; + int i; + + /* Channels */ + for (i = 0; i < TCC_NUM_CHANNELS; i++) { + if (status_flags & TCC_STATUS_CHANNEL_MATCH_CAPTURE(i)) { + int_clr |= TCC_INTFLAG_MC(i); + } + } + /* Faults */ + if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1)) { + int_clr |= TCC_INTFLAG_FAULT1; + status_clr |= TCC_STATUS_FAULT1; + } + if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0)) { + int_clr |= TCC_INTFLAG_FAULT0; + status_clr |= TCC_STATUS_FAULT0; + } + if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1)) { + int_clr |= TCC_INTFLAG_FAULTB; + status_clr |= TCC_STATUS_FAULTB; + } + if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0)) { + int_clr |= TCC_INTFLAG_FAULTA; + status_clr |= TCC_STATUS_FAULTA; + } + /* Check for TCC capture overflow */ + if (status_flags & TCC_STATUS_CAPTURE_OVERFLOW) { + int_clr |= TCC_INTFLAG_ERR; + } + /* Check for TCC count counter */ + if (status_flags & TCC_STATUS_COUNTER_EVENT) { + int_clr |= TCC_INTFLAG_CNT; + } + /* Check for TCC count retrigger */ + if (status_flags & TCC_STATUS_COUNTER_RETRIGGERED) { + int_clr = TCC_INTFLAG_TRG; + } + /* Check for TCC count overflow */ + if (status_flags & TCC_STATUS_COUNT_OVERFLOW) { + int_clr |= TCC_INTFLAG_OVF; + } + /* Clear status flag */ + module_inst->hw->STATUS.reg = status_clr; + /* Clear interrupt flag */ + module_inst->hw->INTFLAG.reg = int_clr; +} + +/** + * \brief Enable circular option for double buffered compare values. + * + * Enable circular option for the double buffered channel compare values. + * On each UPDATE condition, the contents of CCBx and CCx are switched, meaning + * that the contents of CCBx are transferred to CCx and the contents of CCx are + * transferred to CCBx. + * + * \param[in] module_inst Pointer to the TCC software instance struct + * \param[in] channel_index Index of the compare channel to set up to + * + * \retval STATUS_OK The module was initialized successfully + * \retval STATUS_INVALID_ARG An invalid channel index is supplied + */ +enum status_code tcc_enable_circular_buffer_compare( + struct tcc_module *const module_inst, + enum tcc_match_capture_channel channel_index) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + /* Get a index of the module */ + uint8_t module_index = _tcc_get_inst_index(tcc_module); + + /* Check index */ + if (channel_index > 3) { + return STATUS_ERR_INVALID_ARG; + } + if (channel_index >= _tcc_cc_nums[module_index]) { + return STATUS_ERR_INVALID_ARG; + } + + tcc_module->WAVE.reg |= (TCC_WAVE_CICCEN0 << channel_index); + + return STATUS_OK; +} + +/** + * \brief Disable circular option for double buffered compare values. + * + * Stop circularing the double buffered compare values. + * + * \param[in] module_inst Pointer to the TCC software instance struct + * \param[in] channel_index Index of the compare channel to set up to + * + * \retval STATUS_OK The module was initialized successfully + * \retval STATUS_INVALID_ARG An invalid channel index is supplied + */ +enum status_code tcc_disable_circular_buffer_compare( + struct tcc_module *const module_inst, + enum tcc_match_capture_channel channel_index) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + /* Get a index of the module */ + uint8_t module_index = _tcc_get_inst_index(tcc_module); + + /* Check index */ + if (channel_index > 3) { + return STATUS_ERR_INVALID_ARG; + } + if (channel_index >= _tcc_cc_nums[module_index]) { + return STATUS_ERR_INVALID_ARG; + } + + tcc_module->WAVE.reg &= ~(TCC_WAVE_CICCEN0 << channel_index); + + return STATUS_OK; +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.h new file mode 100644 index 0000000000..b048225b39 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/drivers/tcc/tcc.h @@ -0,0 +1,2338 @@ +#ifndef TCC_H_INCLUDED +#define TCC_H_INCLUDED + +/** + * \defgroup asfdoc_sam0_tcc_group SAM Timer Counter for Control Applications Driver (TCC) + * + * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration + * and management of the TCC module within the device, for waveform + * generation and timing operations. It also provides extended options for + * control applications. + * + * The following driver API modes are covered + * by this manual: + * + * - Polled APIs + * \if TCC_CALLBACK_MODE + * - Callback APIs + * \endif + * + * The following peripherals are used by this module: + * - TCC (Timer/Counter for Control Applications) + * + * The following devices can use this module: + * - Atmel | SMART SAM D21 + * - Atmel | SMART SAM R21 + * - Atmel | SMART SAM D10/D11 + * - Atmel | SMART SAM L21 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam0_tcc_prerequisites + * - \ref asfdoc_sam0_tcc_module_overview + * - \ref asfdoc_sam0_tcc_special_considerations + * - \ref asfdoc_sam0_tcc_extra_info + * - \ref asfdoc_sam0_tcc_examples + * - \ref asfdoc_sam0_tcc_api_overview + * + * \section asfdoc_sam0_tcc_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * \section asfdoc_sam0_tcc_module_overview Module Overview + * + * The Timer/Counter for Control Applications (TCC) module provides a set of + * timing and counting related functionality, such as the generation of periodic + * waveforms, the capturing of a periodic waveform's frequency/duty cycle, + * software timekeeping for periodic operations, waveform extension control, + * fault detection etc. + * + * The counter size of the TCC modules can be 16- or 24-bit depending on + * the TCC instance. + * Refer \ref asfdoc_sam0_tcc_special_considerations_tcc_d21 and + * \ref asfdoc_sam0_tcc_special_considerations_tcc_d11 for details on TCC instances. + * + * The TCC module for the SAM includes the following functions: + * + * - Generation of PWM signals + * - Generation of timestamps for events + * - General time counting + * - Waveform period capture + * - Waveform frequency capture + * - Additional control for generated waveform outputs + * - Fault protection for waveform generation + * + * \ref asfdoc_sam0_tcc_block_diagram "The diagram below" shows the overview + * of the TCC Module. + * + * \anchor asfdoc_sam0_tcc_block_diagram + * \image html overview.svg "Overview of the TCC Module" + * + * \subsection asfdoc_sam0_tcc_module_overview_parts Functional Description + * The TCC module consists of following sections: + * - Base Counter + * - Compare/Capture channels, with waveform generation + * - Waveform extension control and fault detection + * - Interface to the event system, DMAC, and the interrupt system + * + * The base counter can be configured to either count a prescaled generic + * clock or events from the event system.(TCEx, with event action configured + * to counting). + * The counter value can be used by compare/capture channels which can be + * set up either in compare mode or capture mode. + * + * In capture mode, the counter value is stored when a configurable event + * occurs. This mode can be used to generate timestamps used in event capture, + * or it can be used for the measurement of a periodic input signal's + * frequency/duty cycle. + * + * In compare mode, the counter value is compared against one or more of the + * configured channels' compare values. When the counter value coincides with a + * compare value an action can be taken automatically by the module, such as + * generating an output event or toggling a pin when used for frequency or PWM + * signal generation. + * + * \note The connection of events between modules requires the use of the + * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" + * to route output event of one module to the the input event of another. + * For more information on event routing, refer to the event driver + * documentation. + * + * In compare mode, when output signal is generated, extended waveform controls + * are available, to arrange the compare outputs into specific formats. + * The Output matrix can change the channel output routing. Pattern generation + * unit can overwrite the output signal line to specific state. + * The Fault protection feature of the TCC supports recoverable and + * non-recoverable faults. + * + * \subsection asfdoc_sam0_tcc_module_overview_tc Base Timer/Counter + * + * \subsubsection asfdoc_sam0_tcc_module_overview_tc_size Timer/Counter Size + * Each TCC has a counter size of either 16- or 24-bits. The size of the + * counter determines the maximum value it can count to before an overflow + * occurs. + * \ref asfdoc_sam0_tcc_count_size_vs_top "The table below" shows the + * maximum values for each of the possible counter sizes. + * + * \anchor asfdoc_sam0_tcc_count_size_vs_top + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Timer Counter Sizes and Their Maximum Count Values
Counter sizeMax. (hexadecimal)Max. (decimal)
16-bit0xFFFF65,535
24-bit0xFFFFFF16,777,215
+ * + * The period/top value of the counter can be set, to define counting period. + * This will allow the counter to overflow when the counter value reaches the + * period/top value. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_tc_clk Timer/Counter Clock and Prescaler + * TCC is clocked asynchronously to the system clock by a GCLK + * (Generic Clock) channel. The GCLK channel can be connected to any of the GCLK + * generators. The GCLK generators are configured to use one of the available + * clock sources in the system such as internal oscillator, external crystals, + * etc. - see the \ref asfdoc_sam0_system_clock_group "Generic Clock driver" for + * more information. + * + * Each TCC module in the SAM has its own individual clock prescaler, which + * can be used to divide the input clock frequency used by the counter. This + * prescaler only scales the clock used to provide clock pulses for the counter + * to count, and does not affect the digital register interface portion of + * the module, thus the timer registers will synchronized to the raw GCLK + * frequency input to the module. + * + * As a result of this, when selecting a GCLK frequency and timer prescaler + * value the user application should consider both the timer resolution + * required and the synchronization frequency, to avoid lengthy + * synchronization times of the module if a very slow GCLK frequency is fed + * into the TCC module. It is preferable to use a higher module GCLK frequency + * as the input to the timer and prescale this down as much as possible to + * obtain a suitable counter frequency in latency-sensitive applications. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_tc_ctrl Timer/Counter Control Inputs (Events) + * + * The TCC can take several actions on the occurrence of an input event. + * The event actions are listed + * in \ref asfdoc_sam0_tcc_module_event_act "events action settings". + * + * \anchor asfdoc_sam0_tcc_module_event_act + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
TCC Module Event Actions
Event actionDescriptionApplied event
TCC_EVENT_ACTION_OFFNo action on the event inputAll
TCC_EVENT_ACTION_RETRIGGERRe-trigger Counter on eventAll
TCC_EVENT_ACTION_NON_RECOVERABLE_FAULTGenerate Non-Recoverable Fault on eventAll
TCC_EVENT_ACTION_STARTCounter start on eventEV0
TCC_EVENT_ACTION_DIR_CONTROLCounter direction controlEV0
TCC_EVENT_ACTION_DECREMENTCounter decrement on eventEV0
TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURECapture pulse period and pulse widthEV0
TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURECapture pulse width and pulse periodEV0
TCC_EVENT_ACTION_STOPCounter stop on eventEV1
TCC_EVENT_ACTION_COUNT_EVENTCounter count on eventEV1
TCC_EVENT_ACTION_INCREMENTCounter increment on eventEV1
TCC_EVENT_ACTION_COUNT_DURING_ACTIVECounter count during active state of asynchronous eventEV1
+ * + * \subsubsection asfdoc_sam0_tcc_module_overview_tc_reload Timer/Counter Reloading + * + * The TCC also has a configurable reload action, used when a + * re-trigger event occurs. Examples of a re-trigger event could be the counter + * reaching the maximum value when counting up, or when an event from the event + * system makes the counter to re-trigger. The reload action determines if the + * prescaler should be reset, and on which clock. The counter will + * always be reloaded with the value it is set to start counting. The user + * can choose between three different reload actions, described in + * \ref asfdoc_sam0_tcc_module_reload_act "the table below". + * + * \anchor asfdoc_sam0_tcc_module_reload_act + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
TCC Module Reload Actions
Reload actionDescription
TCC_RELOAD_ACTION_GCLKReload TCC counter value on next GCLK cycle. Leave prescaler + * as-is.
TCC_RELOAD_ACTION_PRESCReloads TCC counter value on next prescaler clock. Leave prescaler + * as-is.
TCC_RELOAD_ACTION_RESYNCReload TCC counter value on next GCLK cycle. Clear prescaler to + * zero.
+ * + * The reload action to use will depend on the specific application being + * implemented. One example is when an external trigger for a reload occurs; if + * the TCC uses the prescaler, the counter in the prescaler should not have a + * value between zero and the division factor. The counter in the TCC module + * and the counter in the prescaler should both start at zero. + * If the counter is set to re-trigger when it reaches the maximum value, + * this is not the right option to use. In such a case it would be better if + * the prescaler is left unaltered when the re-trigger happens, letting the + * counter reset on the next GCLK cycle. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_tc_oneshot One-shot Mode + * + * The TCC module can be configured in one-shot mode. When configured in this + * manner, starting the timer will cause it to count until the next overflow + * or underflow condition before automatically halting, waiting to be manually + * triggered by the user application software or an event from the event + * system. + * + * \subsection asfdoc_sam0_tcc_module_overview_capt Capture Operations + * + * In capture operations, any event from the event system or a pin change can + * trigger a capture of the counter value. This captured counter value can be + * used as timestamps for the events, or it can be used in frequency and pulse + * width capture. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_capt_ev Capture Operations - Event + * + * Event capture is a simple use of the capture functionality, + * designed to create timestamps for specific events. When the input event + * appears, the current counter value is copied into the corresponding + * compare/capture register, which can then be read by the user application. + * + * Note that when performing any capture operation, there is a risk that the + * counter reaches its top value (MAX) when counting up, or the bottom value + * (zero) when counting down, before the capture event occurs. This can distort + * the result, making event timestamps to appear shorter than they really are. + * In this case, the user application should check for timer overflow when + * reading a capture result in order to detect this situation and perform an + * appropriate adjustment. + * + * Before checking for a new capture, \ref TCC_STATUS_COUNT_OVERFLOW + * should be checked. The response to an overflow error is left to the user + * application, however it may be necessary to clear both the overflow + * flag and the capture flag upon each capture reading. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_capt_pulse Capture Operations - Pulse Width + * + * Pulse Width Capture mode makes it possible to measure the pulse width and + * period of PWM signals. This mode uses two capture channels of the counter. + * There are two modes for pulse width capture; + * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture + * channel 0 is used for storing the pulse width and capture channel 1 stores + * the observed period. While in PPW mode, the roles of the two capture channels + * are reversed. + * + * As in the above example it is necessary to poll on interrupt flags to see + * if a new capture has happened and check that a capture overflow error has + * not occurred. + * + * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to set up the input + * event to perform pulse width capture. + * + * \subsection asfdoc_sam0_tcc_module_overview_mc Compare Match Operation + * + * In compare match operation, Compare/Capture registers are compared + * with the counter value. When the timer's count value matches the value of a + * compare channel, a user defined action can be taken. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_mc_timer Basic Timer + * + * A Basic Timer is a simple application where compare match operation is used + * to determine when a specific period has elapsed. In Basic Timer operations, + * one or more values in the module's Compare/Capture registers are used to + * specify the time (in terms of the number of prescaled GCLK cycles, or + * input events) at which + * an action should be taken by the microcontroller. This can be an Interrupt + * Service Routine (ISR), event generation via the event system, or a software + * flag that is polled from the user application. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave Waveform Generation + * + * Waveform generation enables the TCC module to generate square waves, or if + * combined with an external passive low-pass filter, analog waveforms. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_pwm Waveform Generation - PWM + * + * Pulse width modulation is a form of waveform generation and a signalling + * technique that can be useful in many applications. When PWM mode is used, + * a digital pulse train with a configurable frequency and duty cycle can be + * generated by the TCC module and output to a GPIO pin of the device. + * + * Often PWM is used to communicate a control or information parameter to an + * external circuit or component. Differing impedances of the source generator + * and sink receiver circuits is less of an issue when using PWM compared to + * using an analog voltage value, as noise will not generally affect the + * signal's integrity to a meaningful extent. + * + * \ref asfdoc_sam0_tcc_module_pwm_single_diag "The figure below" illustrates + * operations and different states of the counter and its output when using + * the timer in Normal PWM mode (Single Slope). As can be seen, the TOP/PERIOD + * value is + * unchanged and is set to MAX. The compare match value is changed at several + * points to illustrate the resulting waveform output changes. The PWM output is + * set to normal (i.e. non-inverted) output mode. + * + * \anchor asfdoc_sam0_tcc_module_pwm_single_diag + * \image html pwm_single_ex.svg "Example Of PWM In Single-Slope Mode, and Different Counter Operations" + * + * Several PWM modes are supported by the TCC module, refer to + * datasheet for the details on PWM waveform generation. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_freq Waveform Generation - Frequency + * + * Normal Frequency Generation is in many ways identical to PWM generation. + * However, only in Frequency Generation, a toggle occurs on the output when a + * match on a compare channels occurs. + * + * When the Match Frequency Generation is used, the timer value is reset on + * match condition, resulting in a variable frequency square wave with a + * fixed 50% duty cycle. + * + * \subsection asfdoc_sam0_tcc_module_overview_ext Waveform Extended Controls + * + * \subsubsection asfdoc_sam0_tcc_module_overview_ext_pat Pattern Generation + * + * Pattern insertion allows the TCC module to change the actual pin output level + * without modifying the compare/match settings. + * + * \anchor asfdoc_sam0_tcc_module_pattern_gen + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
TCC Module Output Pattern Generation
PatternDescription
TCC_OUTPUT_PATTERN_DISABLEPattern disabled, generate output as is
TCC_OUTPUT_PATTERN_0Generate pattern 0 on output (keep the output LOW)
TCC_OUTPUT_PATTERN_1Generate pattern 1 on output (keep the output HIGH)
+ * + * \subsubsection asfdoc_sam0_tcc_module_overview_ext_r_fault Recoverable Faults + * + * The recoverable faults can trigger one or several of following fault actions: + * -# *Halt* action: The recoverable faults can halt the TCC timer/counter, + * so that the final output wave is kept at a defined state. When the fault + * state is removed it is possible to recover the counter and waveform + * generation. The halt action is defined as: + * \anchor asfdoc_sam0_tcc_module_fault_halt_action + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
TCC Module Recoverable Fault Halt Actions
ActionDescription
TCC_FAULT_HALT_ACTION_DISABLEHalt action is disabled
TCC_FAULT_HALT_ACTION_HW_HALTThe timer/counter is halted as long as the corresponding fault is + * present
TCC_FAULT_HALT_ACTION_SW_HALTThe timer/counter is halted until the corresponding fault is removed + * and fault state cleared by software
TCC_FAULT_HALT_ACTION_NON_RECOVERABLEForce all the TCC output pins to a pre-defined level, as what + * Non-Recoverable Fault do
+ * -# *Restart* action: When enabled, the recoverable faults can restart the TCC + * timer/counter. + * -# *Keep* action: When enabled, the recoverable faults can keep the + * corresponding channel output to zero when the fault condition is present. + * -# *Capture* action: When the recoverable fault occurs, the capture action can + * time stamps the corresponding fault. The following capture mode is + * supported: + * \anchor asfdoc_sam0_tcc_module_fault_capt_action + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
TCC Module Recoverable Fault Capture Actions
ActionDescription
TCC_FAULT_CAPTURE_DISABLECapture action is disabled
TCC_FAULT_CAPTURE_EACHEquivalent to standard capture operation, on each fault occurrence + * the time stamp is captured
TCC_FAULT_CAPTURE_MINIMUMGet the minimum time stamped value in all time stamps
TCC_FAULT_CAPTURE_MAXIMUMGet the maximum time stamped value in all time stamps
TCC_FAULT_CAPTURE_SMALLERTime stamp the fault input if the value is smaller than last one
TCC_FAULT_CAPTURE_BIGGERTime stamp the fault input if the value is bigger than last one
TCC_FAULT_CAPTURE_CHANGETime stamp the fault input if the time stamps changes its increment + * direction
+ * + * In TCC module, only the first two compare channels (CC0 and CC1) can work + * with recoverable fault inputs. The corresponding event inputs (TCCx MC0 + * and TCCx MC1) are then used as fault inputs respectively. + * The faults are called Fault A and Fault B. + * + * The recoverable fault can be filtered or effected by corresponding channel + * output. On fault condition there are many other settings that can be chosen. + * Refer to data sheet for more details about the recoverable fault + * operations. + * + * \subsubsection asfdoc_sam0_tcc_module_overview_ext_n_fault Non-Recoverable Faults + * + * The non-recoverable faults force all the TCC output pins to a pre-defined + * level (can be forced to 0 or 1). The input control signal of non-recoverable + * fault is from timer/counter event (TCCx EV0 and TCCx EV1). + * To enable non-recoverable fault, + * corresponding TCEx event action must be set to non-recoverable fault action + * (\ref TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT). + * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to see the available + * event input action. + * + * \subsection asfdoc_sam0_tcc_module_overview_buffering Double and Circular Buffering + * + * The pattern, period and the compare channels registers are double buffered. + * For these options there are effective registers (PATT, PER, and CCx) and + * buffer registers (PATTB, PERB, and CCx). When writing to the buffer + * registers, the values are buffered and will be committed to effective + * registers on UPDATE condition. + * + * Usually the buffered value is cleared after it's committed, but there is also + * option to circular the register buffers. The period (PER) and four lowest + * compare channels register (CCx, x is 0 ~ 3) support this function. When + * circular buffer is used, on UPDATE the previous period or compare values are + * copied back into the corresponding period buffer and compare buffers. + * This way, the register value and its buffer register value is actually + * switched on UPDATE condition, and will be switched back on next UPDATE + * condition. + * + * For input capture, the buffer register (CCBx) and the corresponding capture + * channel register (CCx) act like a FIFO. When regular register (CCx) is empty + * or read, any content in the buffer register is passed to regular one. + * + * In TCC module driver, when the double buffering write is enabled, any + * write through \ref tcc_set_top_value(), \ref tcc_set_compare_value(), and + * \ref tcc_set_pattern() will be done to the corresponding buffer register. + * Then the value in the buffer register will be transferred to the regular + * register on the next UPDATE condition or by a force UPDATE using + * \ref tcc_force_double_buffer_update(). + * + * \subsection asfdoc_sam0_tcc_module_overview_sleep Sleep Mode + * + * TCC modules can be configured to operate in any sleep mode, with its "run + * in standby" function enabled. It can wake up the device using interrupts or + * perform internal actions with the help of the Event System. + * + * \section asfdoc_sam0_tcc_special_considerations Special Considerations + * + * \subsection asfdoc_sam0_tcc_special_considerations_tcc_feature Module Features + * + * The features of TCC, such as timer/counter size, number of compare capture + * channels, and number of outputs, are dependent on the TCC module instance being + * used. + * + * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d21 SAM TCC Feature List + * For SAM D21/R21/L21, the TCC features are: + * \anchor asfdoc_sam0_tcc_features_d21 + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
TCC module features for SAM D21/R21/L21
TCC#Match/Capture channelsWave outputsCounter size [bits]FaultDitheringOutput matrixDead-Time insertionSWAPPattern
04824YYYYYY
12424YYY
22216Y
+ * + * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d11 SAM D10/D11 TCC Feature List + * For SAM D10/D11, the TCC features are: + * \anchor asfdoc_sam0_tcc_features_d11 + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
TCC Module Features For SAM D10/D11
TCC#Match/Capture channelsWave outputsCounter size [bits]FaultDitheringOutput matrixDead-Time insertionSWAPPattern
04824YYYYYY
+ * + * \subsection asfdoc_sam0_tcc_special_considerations_tcc_pin Channels vs. Pin outs + * + * As the TCC module may have more waveform output pins than the number of + * compare/capture channels, the free pins (with number higher than number of + * channels) will reuse the waveform generated by channels subsequently. E.g., + * if the number of channels is four and the number of wave output pins is eight, channel + * 0 output will be available on out pin 0 and 4, channel 1 output + * on wave out pin 1 and 5, and so on. + * + * \section asfdoc_sam0_tcc_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam0_tcc_extra. This includes: + * - \ref asfdoc_sam0_tcc_extra_acronyms + * - \ref asfdoc_sam0_tcc_extra_dependencies + * - \ref asfdoc_sam0_tcc_extra_errata + * - \ref asfdoc_sam0_tcc_extra_history + * + * + * \section asfdoc_sam0_tcc_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam0_tcc_exqsg. + * + * \section asfdoc_sam0_tcc_api_overview API Overview + * @{ + */ + +#include +#include +#include +#include + +/** Maximum number of channels supported by the driver + * (Channel index from 0 to \c TCC_NUM_CHANNELS - 1). + */ +#define TCC_NUM_CHANNELS 4 + +/** Maximum number of wave outputs lines supported by the driver + * (Output line index from 0 to \c TCC_NUM_WAVE_OUTPUTS - 1). + */ +#define TCC_NUM_WAVE_OUTPUTS 8 + +/** Maximum number of (recoverable) faults supported by the driver. */ +#define TCC_NUM_FAULTS 2 + +#if TCC_ASYNC == true +# include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generates a table enum list entry for a given type + and index (e.g. "TCC_CALLBACK_MC_CHANNEL_0,"). */ +#define _TCC_ENUM(n, type) TCC_##type##_##n, + +/* Generates table enum list entries for all channels of a + given type and channel number on TCC module. */ +#define _TCC_CHANNEL_ENUM_LIST(type) \ + MREPEAT(TCC_NUM_CHANNELS, _TCC_ENUM, type##_CHANNEL) +/* Generates table enum list entries for all output of a + given type and waveform output number on TCC module. */ +#define _TCC_WO_ENUM_LIST(type) \ + MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_ENUM, type) + + +#if TCC_ASYNC == true +/** Enum for the possible callback types for the TCC module. */ +enum tcc_callback { + /** Callback for TCC overflow. */ + TCC_CALLBACK_OVERFLOW, + /** Callback for TCC Retrigger. */ + TCC_CALLBACK_RETRIGGER, + /** Callback for TCC counter event. */ + TCC_CALLBACK_COUNTER_EVENT, + /** Callback for capture overflow error. */ + TCC_CALLBACK_ERROR, + /** Callback for Recoverable Fault A. */ + TCC_CALLBACK_FAULTA, + /** Callback for Recoverable Fault B. */ + TCC_CALLBACK_FAULTB, + /** Callback for Non-Recoverable Fault 0. */ + TCC_CALLBACK_FAULT0, + /** Callback for Non-Recoverable Fault 1. */ + TCC_CALLBACK_FAULT1, + +# if defined(__DOXYGEN__) + /** Channel callback type table for TCC + * + * Each TCC module may contain several callback types for channels; each + * channel will have its own callback type in the table, with the channel + * index number substituted for "n" in the channel callback type + * (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0). + */ + TCC_CALLBACK_CHANNEL_n = n, +# else + /** Callbacks for Match/Capture channels, e.g., TCC_CALLBACK_CHANNEL_0. */ + _TCC_CHANNEL_ENUM_LIST(CALLBACK) +# endif + +# if !defined(__DOXYGEN__) + /** Number of available callbacks. */ + TCC_CALLBACK_N +# endif +}; +#endif /* #if TCC_ASYNC == true */ + +/** + * \name Module Status Flags + * + * TCC status flags, returned by \ref tcc_get_status() and cleared by + * \ref tcc_clear_status(). + * + * @{ + */ + +/** Timer channel \c ch (0 ~ 3) has matched against its compare value, + * or has captured a new value. + */ +#define TCC_STATUS_CHANNEL_MATCH_CAPTURE(ch) (1UL << (ch)) +/** Timer channel \c ch (0 ~ 3) match/compare output state. */ +#define TCC_STATUS_CHANNEL_OUTPUT(ch) (1UL << ((ch)+8)) +/** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */ +#define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) (1UL << ((x)+16)) +/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occured. */ +#define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) (1UL << ((n)+18)) +/** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */ +#define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20)) +/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) is present. */ +#define TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) (1UL << ((n)+22)) +/** Timer registers synchronization has completed, and the synchronized count + * value may be read. + */ +#define TCC_STATUS_SYNC_READY (1UL << 23) +/** A new value was captured before the previous value was read, resulting in + * lost data. + */ +#define TCC_STATUS_CAPTURE_OVERFLOW (1UL << 24) +/** A counter event occurred. */ +#define TCC_STATUS_COUNTER_EVENT (1UL << 25) +/** A counter retrigger occurred. */ +#define TCC_STATUS_COUNTER_RETRIGGERED (1UL << 26) +/** The timer count value has overflowed from its maximum value to its minimum + * when counting upward, or from its minimum value to its maximum when + * counting downward. + */ +#define TCC_STATUS_COUNT_OVERFLOW (1UL << 27) +/** Ramp period cycle index. + * In ramp operation, each two period cycles are marked as cycle A and B, + * the index 0 represents cycle A and 1 represents cycle B. */ +#define TCC_STATUS_RAMP_CYCLE_INDEX (1UL << 28) +/** The counter has been stopped (due to disable, stop command or one-shot). */ +#define TCC_STATUS_STOPPED (1UL << 29) + +/** @} */ + +/** + * \brief Index of the match capture channels + * + * This enum is used to specify which capture/match channel to do + * operations on. + */ +enum tcc_match_capture_channel { +# if defined(__DOXYGEN__) + /** Match capture channel index table for TCC + * + * Each TCC module may contain several match capture channels; each channel + * will have its own index in the table, with the index number substituted + * for "n" in the index name (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0). + */ + TCC_MATCH_CAPTURE_CHANNEL_n = n, +# else + /** Indexes of match capture channels, e.g., TCC_MATCH_CAPTURE_CHANNEL_0. */ + _TCC_CHANNEL_ENUM_LIST(MATCH_CAPTURE) +# endif +# if !defined(__DOXYGEN__) + /** Number of supported channels. */ + TCC_MATCH_CAPTURE_CHANNEL_N +# endif +}; + +/** + * \brief Index of the wave outputs + * + * This enum is used to specify which wave output to do + * operations on. + */ +enum tcc_wave_output { +# if defined(__DOXYGEN__) + /** Waveform output index table for TCC + * + * Each TCC module may contain several wave outputs; each output + * will have its own index in the table, with the index number substituted + * for "n" in the index name (e.g. \c TCC_WAVE_OUTPUT_0). + */ + TCC_WAVE_OUTPUT_n = n, +# else + /** Indexes of match capture channels, e.g., TCC_WAVEFORM_OUTPUT_0. */ + _TCC_WO_ENUM_LIST(WAVE_OUTPUT) +# endif +# if !defined(__DOXYGEN__) + /** Number of supported channels. */ + TCC_WAVE_OUTPUT_N +# endif +}; + +/** + * \brief TCC wave generation mode enum + * + * This enum is used to specify the waveform generation mode. + * + */ +enum tcc_wave_generation { + /** Normal Frequency: Top is the PER register, output toggled on each + * compare match. */ + TCC_WAVE_GENERATION_NORMAL_FREQ = 0, + /** Match Frequency: Top is CC0 register, output toggles on each update + * condition. */ + TCC_WAVE_GENERATION_MATCH_FREQ = 1, + /** Single-Slope PWM: Top is the PER register, CCx controls duty cycle ( + * output active when count is greater than CCx). */ + TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM = 2, + + /** Double-slope (count up and down), non centre-aligned: Top is the PER + * register, CC[x] controls duty cycle while counting up and CC[x+N/2] + * controls it while counting down. */ + TCC_WAVE_GENERATION_DOUBLE_SLOPE_CRITICAL = 4, + /** Double-slope (count up and down), interrupt/event at Bottom (Top is the + * PER register, output active when count is greater than CCx). */ + TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTTOM = 5, + /** Double-slope (count up and down), interrupt/event at Bottom and Top: (Top is the + * PER register, output active when count is lower than CCx). */ + TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTH = 6, + /** Double-slope (count up and down), interrupt/event at Top (Top is the + * PER register, output active when count is greater than CCx). */ + TCC_WAVE_GENERATION_DOUBLE_SLOPE_TOP = 7, +}; + +/** + * \brief Polarity of TCC wave generation on channels + * + * Specifies whether the wave output needs to be inverted or not. + */ +enum tcc_wave_polarity { + /** Wave output is not inverted. */ + TCC_WAVE_POLARITY_0, + /** Wave output is inverted. */ + TCC_WAVE_POLARITY_1 +}; + +/** + * \brief TCC pattern generator for outputs + * + * Used when disabling output pattern or when selecting a specific pattern. + */ +enum tcc_output_pattern { + /** SWAP output pattern is not used. */ + TCC_OUTPUT_PATTERN_DISABLE, + /** Pattern 0 is applied to SWAP output. */ + TCC_OUTPUT_PATTERN_0, + /** Pattern 1 is applied to SWAP output. */ + TCC_OUTPUT_PATTERN_1 +}; + +/** + * \brief Ramp Operations which are supported in single-slope PWM generation + * + * Ramp operations which are supported in single-slope PWM generation. + */ +enum tcc_ramp { + /** Default timer/counter PWM operation. */ + TCC_RAMP_RAMP1 = 0, + + /** Uses a single channel (CC0) to control both CC0/CC1 compare outputs. + * In cycle A, the channel 0 output is disabled, and + * in cycle B, the channel 1 output is disabled. */ + TCC_RAMP_RAMP2A, + + /** Uses channels CC0 and CC1 to control compare outputs. + * In cycle A, the channel 0 output is disabled, and + * in cycle B, the channel 1 output is disabled.*/ + TCC_RAMP_RAMP2 +}; + +/** + * \brief Ramp Index for TCC wave generation + * + * In ramp operation, each two period cycles are marked as cycle A and B, + * the index 0 represents cycle A and 1 represents cycle B. + */ +enum tcc_ramp_index { + /** Default, cycle index toggles. */ + TCC_RAMP_INDEX_DEFAULT, + /** Force next cycle to be cycle B (set to 1). */ + TCC_RAMP_INDEX_FORCE_B, + /** Force next cycle to be cycle A (clear to 0). */ + TCC_RAMP_INDEX_FORCE_A, + /** Force next cycle keeping the same as current. */ + TCC_RAMP_INDEX_FORCE_KEEP +}; + +/** + * \brief TCC output inversion + * + * Used when enabling or disabling output inversion. + */ +enum tcc_output_invertion { + /** Output inversion not to be enabled. */ + TCC_OUTPUT_INVERTION_DISABLE, + /** Invert the output from WO[x]. */ + TCC_OUTPUT_INVERTION_ENABLE +}; + +/** + * \brief TCC Counter reload action enum + * + * This enum specify how the counter is reloaded and whether the prescaler + * should be restarted. + */ +enum tcc_reload_action { + /** The counter is reloaded/reset on the next GCLK and starts + * counting on the prescaler clock. + */ + TCC_RELOAD_ACTION_GCLK, + /** The counter is reloaded/reset on the next prescaler clock. + */ + TCC_RELOAD_ACTION_PRESC, + /** The counter is reloaded/reset on the next GCLK, and the + * prescaler is restarted as well. + */ + TCC_RELOAD_ACTION_RESYNC +}; + + +/** + * \brief TCC clock prescaler values + * + * This enum is used to choose the clock prescaler + * configuration. The prescaler divides the clock frequency of the TCC + * module to operate TCC at a slower clock rate. + */ +enum tcc_clock_prescaler { + /** Divide clock by 1. */ + TCC_CLOCK_PRESCALER_DIV1, + /** Divide clock by 2. */ + TCC_CLOCK_PRESCALER_DIV2, + /** Divide clock by 4. */ + TCC_CLOCK_PRESCALER_DIV4, + /** Divide clock by 8. */ + TCC_CLOCK_PRESCALER_DIV8, + /** Divide clock by 16. */ + TCC_CLOCK_PRESCALER_DIV16, + /** Divide clock by 64. */ + TCC_CLOCK_PRESCALER_DIV64, + /** Divide clock by 256. */ + TCC_CLOCK_PRESCALER_DIV256, + /** Divide clock by 1024. */ + TCC_CLOCK_PRESCALER_DIV1024 +}; + +/** + * \brief TCC module count direction + * + * Used when selecting the Timer/Counter count direction. + */ +enum tcc_count_direction { + /** Timer should count upward. */ + TCC_COUNT_DIRECTION_UP, + /** Timer should count downward. */ + TCC_COUNT_DIRECTION_DOWN, +}; + +/** + * \brief Action to perform when the TCC module is triggered by events + * + * Event action to perform when the module is triggered by events. + */ +enum tcc_event_action { + /** No event action. */ + TCC_EVENT_ACTION_OFF, + /** Stop counting, the counter will maintain its current value, waveforms + * are set to a defined Non-Recoverable State output + * (\ref tcc_non_recoverable_state_output). */ + TCC_EVENT_ACTION_STOP, + /** Re-trigger counter on event, may generate an event if the re-trigger + * event output is enabled. + * \note When re-trigger event action is enabled, enabling the counter + * will not start until the next incoming event appears. */ + TCC_EVENT_ACTION_RETRIGGER, + + /** Start counter when previously stopped. + * Start counting on the event rising edge. Further events will not + * restart the counter; + * the counter keeps on counting using prescaled GCLK_TCCx, until it + * reaches TOP or Zero + * depending on the direction. */ + TCC_EVENT_ACTION_START, + /** Count events; i.e. Increment or decrement depending on count + * direction. */ + TCC_EVENT_ACTION_COUNT_EVENT, + /** The event source must be an asynchronous event, input value will + * overrides the direction settings (input low: counting up, input high + * counting down). */ + TCC_EVENT_ACTION_DIR_CONTROL, + /** Increment the counter on event, irrespective of count direction. */ + TCC_EVENT_ACTION_INCREMENT, + /** Decrement the counter on event, irrespective of count direction. */ + TCC_EVENT_ACTION_DECREMENT, + /** Count during active state of asynchronous event. In this case, + * depending on the count direction, the count will be incremented + * or decremented on each + * prescaled GCLK_TCCx, as long as the input event remains active. */ + TCC_EVENT_ACTION_COUNT_DURING_ACTIVE, + + /** Store period in capture register 0, pulse width in capture + * register 1. + */ + TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE, + /** Store pulse width in capture register 0, period in capture + * register 1. + */ + TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE, + + /** Generate Non-Recoverable Fault on event. */ + TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT, +}; + + +/** + * \brief Action to be performed when the TCC module is triggered by event0 + * + * Event action to perform when the module is triggered by event0. + */ +enum tcc_event0_action { + /** No event action. */ + TCC_EVENT0_ACTION_OFF = TCC_EVENT_ACTION_OFF, + /** Re-trigger Counter on event. */ + TCC_EVENT0_ACTION_RETRIGGER = TCC_EVENT_ACTION_RETRIGGER, + /** Count events (increment or decrement, depending on count direction). + */ + TCC_EVENT0_ACTION_COUNT_EVENT = TCC_EVENT_ACTION_COUNT_EVENT, + /** Start counter on event. */ + TCC_EVENT0_ACTION_START = TCC_EVENT_ACTION_START, + /** Increment counter on event. */ + TCC_EVENT0_ACTION_INCREMENT = TCC_EVENT_ACTION_INCREMENT, + /** Count during active state of asynchronous event. */ + TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE = TCC_EVENT_ACTION_COUNT_DURING_ACTIVE, + + /** Generate Non-Recoverable Fault on event. */ + TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT +}; + +/** + * \brief Action to perform when the TCC module is triggered by event1 + * + * Event action to perform when the module is triggered by event1. + */ +enum tcc_event1_action { + /** No event action. */ + TCC_EVENT1_ACTION_OFF = TCC_EVENT_ACTION_OFF, + /** Re-trigger Counter on event. */ + TCC_EVENT1_ACTION_RETRIGGER = TCC_EVENT_ACTION_RETRIGGER, + /** The event source must be an asynchronous event, input value will + * override the direction settings. + * If TCEINVx is 0 and input event is LOW: counter will count up. + * If TCEINVx is 0 and input event is HIGH: counter will count down. + */ + TCC_EVENT1_ACTION_DIR_CONTROL = TCC_EVENT_ACTION_DIR_CONTROL, + /** Stop counter on event. */ + TCC_EVENT1_ACTION_STOP = TCC_EVENT_ACTION_STOP, + /** Decrement on event. */ + TCC_EVENT1_ACTION_DECREMENT = TCC_EVENT_ACTION_DECREMENT, + + /** Store period in capture register 0, pulse width in capture + * register 1. + */ + TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE = TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE, + /** Store pulse width in capture register 0, period in capture + * register 1. + */ + TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE = TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE, + + /** Generate Non-Recoverable Fault on event. */ + TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT +}; + +/** + * \brief On which part of the counter cycle the counter event output is generated + * + * This enum is used to define the point at which the counter event is generated. + */ +enum tcc_event_generation_selection { + /** Counter Event is generated when a new counter cycle starts. */ + TCC_EVENT_GENERATION_SELECTION_START, + /** Counter Event is generated when a counter cycle ends. */ + TCC_EVENT_GENERATION_SELECTION_END, + /** Counter Event is generated when a counter cycle ends, except for the + * first and last cycles. */ + TCC_EVENT_GENERATION_SELECTION_BETWEEN, + /** Counter Event is generated when a new counter cycle starts or ends. */ + TCC_EVENT_GENERATION_SELECTION_BOUNDARY +}; + +/** + * \brief TCC channel operation modes + * + * To set a timer channel either in compare or in capture mode. + */ +enum tcc_channel_function { + /** TCC channel performs compare operation. */ + TCC_CHANNEL_FUNCTION_COMPARE, + /** TCC channel performs capture operation. */ + TCC_CHANNEL_FUNCTION_CAPTURE +}; + +/** + * \brief TCC (recoverable) fault Halt action + */ +enum tcc_fault_halt_action { + /** Halt action disabled. */ + TCC_FAULT_HALT_ACTION_DISABLE, + /** Hardware halt action, counter is halted until restart. */ + TCC_FAULT_HALT_ACTION_HW_HALT, + /** Software halt action, counter is halted until fault bit cleared. */ + TCC_FAULT_HALT_ACTION_SW_HALT, + /** Non-Recoverable fault, force output to pre-defined level. */ + TCC_FAULT_HALT_ACTION_NON_RECOVERABLE +}; + +/** + * \brief TCC (recoverable) fault Capture action + */ +enum tcc_fault_capture_action { + /** Capture disabled. */ + TCC_FAULT_CAPTURE_DISABLE, + /** Capture on Fault, each value is captured. */ + TCC_FAULT_CAPTURE_EACH, + /** Capture the minimum detection, but notify on smaller ones. */ + TCC_FAULT_CAPTURE_MINIMUM, + /** Capture the maximum detection, but notify on bigger ones. */ + TCC_FAULT_CAPTURE_MAXIMUM, + /** Capture if the value is smaller than last, notify event or interrupt + * if previous stamp is confirmed to be "local minimum" (not bigger than + * current stamp). */ + TCC_FAULT_CAPTURE_SMALLER, + /** Capture if the value is bigger than last, notify event or interrupt + * if previous stamp is confirmed to be "local maximum" (not smaller than + * current stamp). */ + TCC_FAULT_CAPTURE_BIGGER, + /** Capture if the time stamps changes its increment direction. */ + TCC_FAULT_CAPTURE_CHANGE +}; + +/** + * \brief Capture Channel triggered by TCC (recoverable) fault + */ +enum tcc_fault_capture_channel { + /** Recoverable fault triggers channel 0 capture operation. */ + TCC_FAULT_CAPTURE_CHANNEL_0, + /** Recoverable fault triggers channel 1 capture operation. */ + TCC_FAULT_CAPTURE_CHANNEL_1, + /** Recoverable fault triggers channel 2 capture operation. */ + TCC_FAULT_CAPTURE_CHANNEL_2, + /** Recoverable fault triggers channel 3 capture operation. */ + TCC_FAULT_CAPTURE_CHANNEL_3 +}; + +/** + * \brief TCC (recoverable) fault Input Source + */ +enum tcc_fault_source { + /** Fault input is disabled. */ + TCC_FAULT_SOURCE_DISABLE, + /** Match Capture Event x (x=0,1) input. */ + TCC_FAULT_SOURCE_ENABLE, + /** Inverted MCEx (x=0,1) event input. */ + TCC_FAULT_SOURCE_INVERT, + /** Alternate fault (A or B) state at the end of the previous period. */ + TCC_FAULT_SOURCE_ALTFAULT +}; + +/** + * \brief TCC (recoverable) fault Input Blanking Start Point + */ +enum tcc_fault_blanking { + /** No blanking. */ + TCC_FAULT_BLANKING_DISABLE, + /** Blanking applied from rising edge of the output waveform. */ + TCC_FAULT_BLANKING_RISING_EDGE, + /** Blanking applied from falling edge of the output waveform. */ + TCC_FAULT_BLANKING_FALLING_EDGE, + /** Blanking applied from each toggle of the output waveform. */ + TCC_FAULT_BLANKING_BOTH_EDGE +}; + +/** + * \brief TCC (recoverable) fault Input Qualification Action + */ +enum tcc_fault_qualification { + /** The input is not disabled on compare condition. */ + TCC_FAULT_QUALIFICATION_DISABLE, + /** The input is disabled when match output signal is at inactive level. */ + TCC_FAULT_QUALIFICATION_BY_OUTPUT +}; + +/** + * \brief TCC (recoverable) fault Output Keep Action + */ +enum tcc_fault_keep { + /** Disable keeping, wave output released as soon as fault is released. */ + TCC_FAULT_KEEP_DISABLE, + /** Keep wave output until end of TCC cycle. */ + TCC_FAULT_KEEP_TILL_END +}; + +/** + * \brief TCC Non-recoverable State Outupt + */ +enum tcc_fault_state_output { + /** Non-recoverable fault output is tri-stated. */ + TCC_FAULT_STATE_OUTPUT_OFF, + /** Non-recoverable fault force output 0. */ + TCC_FAULT_STATE_OUTPUT_0, + /** Non-recoverable fault force output 1. */ + TCC_FAULT_STATE_OUTPUT_1 +}; + +/** + * \brief TCC (recoverable) fault Restart Action + */ +enum tcc_fault_restart { + /** Restart Action disabled. */ + TCC_FAULT_RESTART_DISABLE, + /** Restart Action enabled. */ + TCC_FAULT_RESTART_ENABLE +}; + +/** + * \brief Configuration struct for TCC module recoverable fault + */ +struct tcc_recoverable_fault_config { + /** Fault filter value applied on MCEx event input line (0x0 ~ 0xF). + * Must be 0 when MCEx event is used as synchronous event. + * Apply to both recoverable and non-recoverable fault. */ + uint8_t filter_value; + /** Fault blanking value (0 ~ 255), disable input source for several TCC + * clocks after the detection of the waveform edge. */ + uint8_t blanking_cycles; + + /** Set to \c true to enable restart action. */ + bool restart; + /** Set to \c true to enable keep action (keep until end of TCC cycle). */ + bool keep; + + /** Set to \c true to enable input qualification + * (disable input when output is inactive). */ + bool qualification; + + /** Specifies if the event input generates recoverable Fault. + * The event system channel connected to MCEx event input must be + * configured as asynchronous. + */ + enum tcc_fault_source source; + /** Fault Blanking Start Point for recoverable Fault. */ + enum tcc_fault_blanking blanking; + + /** Halt action for recoverable Fault. */ + enum tcc_fault_halt_action halt_action; + /** Capture action for recoverable Fault. */ + enum tcc_fault_capture_action capture_action; + /** Channel triggered by recoverable Fault. */ + enum tcc_fault_capture_channel capture_channel; +}; + +/** + * \brief Configuration struct for TCC module non-recoverable fault + */ +struct tcc_non_recoverable_fault_config { + /** Fault filter value applied on TCEx event input line (0x0 ~ 0xF). + * Must be 0 when TCEx event is used as synchronous event. */ + uint8_t filter_value; + /** Output. */ + enum tcc_fault_state_output output; +}; + +/** + * \brief TCC input event enable/disable/configure structure + * + * For configuring an input event. + */ +struct tcc_input_event_config { + /** Event action on incoming event. */ + enum tcc_event_action action; + /** Modify event action. */ + bool modify_action; + /** Invert incoming event input line. */ + bool invert; +}; + +/** + * \brief TCC output event enable/disable/configure structure + * + * Structure used for configuring an output event. + */ +struct tcc_output_event_config { + /** It decides which part of the counter cycle the counter event output + * is generated. */ + enum tcc_event_generation_selection generation_selection; + /** A switch to allow enable/disable of events, without modifying the + * event output configuration. + */ + bool modify_generation_selection; +}; + +/** + * \brief TCC event enable/disable structure + * + * Event flags for the \ref tcc_enable_events() and \ref tcc_disable_events(). + */ +struct tcc_events { + /** Input events configuration. */ + struct tcc_input_event_config input_config[2]; + /** Output event configuration. */ + struct tcc_output_event_config output_config; + + /** Perform the configured event action when an incoming event is + * signalled. */ + bool on_input_event_perform_action[2]; + + /** Perform the configured event action when an incoming channel event is + * signalled. */ + bool on_event_perform_channel_action[TCC_NUM_CHANNELS]; + /** Generate an output event on a channel capture/match. + * Specify which channels will generate events. */ + bool generate_event_on_channel[TCC_NUM_CHANNELS]; + + /** Generate an output event on counter overflow/underflow. */ + bool generate_event_on_counter_overflow; + /** Generate an output event on counter retrigger. */ + bool generate_event_on_counter_retrigger; + /** Generate an output event on counter boundary. + * See \ref tcc_event_output_action. */ + bool generate_event_on_counter_event; +}; + +/** + * \brief Configuration struct for the TCC module base counter + * + * Structure for configuring a TCC as a counter. + */ +struct tcc_counter_config { + /** Value to initialize the count register. */ + uint32_t count; + /** Period/top and period/top buffer values for counter. */ + uint32_t period; + + /** When \c true, counter will be stopped on the next hardware or + * software re-trigger event or overflow/underflow. + */ + bool oneshot; + + /** Specifies the direction for the TCC to count. */ + enum tcc_count_direction direction; + + /** GCLK generator used to clock the peripheral. */ + enum gclk_generator clock_source; + /** Specifies the prescaler value for GCLK_TCC. */ + enum tcc_clock_prescaler clock_prescaler; + /** Specifies the reload or reset time of the counter and prescaler + * resynchronization on a re-trigger event for the TCC. + */ + enum tcc_reload_action reload_action; +}; + +/** + * \brief Configuration struct for the TCC module capture + * + * Structure used when configuring TCC channels in capture mode. + */ +struct tcc_capture_config { + /** Channel functions selection (capture/match). */ + enum tcc_channel_function channel_function[TCC_NUM_CHANNELS]; +}; + +/** + * \brief Configuration struct for the TCC module match/wave generation + * + * The structure, which helps to configure a TCC channel for compare + * operation and wave generation. + */ +struct tcc_match_wave_config { + /** Channel functions selection (capture/match). */ + enum tcc_channel_function channel_function[TCC_NUM_CHANNELS]; + + /** Specifies polarity for match output waveform generation. */ + enum tcc_wave_polarity wave_polarity[TCC_NUM_CHANNELS]; + /** Specifies which waveform generation mode to use. */ + enum tcc_wave_generation wave_generation; + /** Specifies Ramp mode for waveform generation. */ + enum tcc_ramp wave_ramp; + + /** Value to be used for compare match on each channel. */ + uint32_t match[TCC_NUM_CHANNELS]; +}; + +/** + * \brief Configuration struct for the TCC module waveform extension + * + * This structure is used to specify the waveform extension features for TCC. + */ +struct tcc_wave_extension_config { + /** Configuration for recoverable faults. */ + struct tcc_recoverable_fault_config + recoverable_fault[TCC_NUM_FAULTS]; + /** Configuration for non-recoverable faults. */ + struct tcc_non_recoverable_fault_config + non_recoverable_fault[TCC_NUM_WAVE_OUTPUTS]; + + /** Invert waveform final outputs lines. */ + bool invert[TCC_NUM_WAVE_OUTPUTS]; +}; + +/** + * \brief Configuration struct for the TCC module output pins + * + * Structure which is used when taking wave output from TCC. + */ +struct tcc_pins_config { + /** Specifies pin output for each channel. */ + uint32_t wave_out_pin[TCC_NUM_WAVE_OUTPUTS]; + /** Specifies MUX setting for each output channel pin. */ + uint32_t wave_out_pin_mux[TCC_NUM_WAVE_OUTPUTS]; + /** When \c true, PWM output pin for the given channel is enabled. */ + bool enable_wave_out_pin[TCC_NUM_WAVE_OUTPUTS]; +}; + +/** + * \brief TCC configuration structure + * + * Configuration struct for a TCC instance. This structure should be + * initialized by the \ref tcc_get_config_defaults function before being + * modified by the user application. + */ +struct tcc_config { + /** Structure for configuring TCC base timer/counter. */ + struct tcc_counter_config counter; + /** TCC match/capture configurations. */ + union { + /** Helps to configure a TCC channel in capture mode. */ + struct tcc_capture_config capture; + /** For configuring a TCC channel in compare mode. */ + struct tcc_match_wave_config compare; + /** Serves the same purpose as compare. Used as an alias for + * compare, + * when a TCC channel is configured for wave generation. */ + struct tcc_match_wave_config wave; + }; + + /** Structure for configuring TCC waveform extension. */ + struct tcc_wave_extension_config wave_ext; + + /** Structure for configuring TCC output pins. */ + struct tcc_pins_config pins; + + /** Set to \c true to enable double buffering write. When enabled any write + * through \ref tcc_set_top_value(), \ref tcc_set_compare_value() and + * \ref tcc_set_pattern() will direct to the buffer register as buffered + * value, and the buffered value will be committed to effective register + * on UPDATE condition, if update is not locked. + * + * \note The init values in \ref tcc_config for \ref tcc_init are always + * filled to effective registers, no matter double buffering + * enabled or not. + */ + bool double_buffering_enabled; + + /** When \c true the module is enabled during standby. */ + bool run_in_standby; +}; + +#if TCC_ASYNC == true +/* Forward Declaration for the device instance. */ +struct tcc_module; + +/** Type definition for the TCC callback function. */ +typedef void (*tcc_callback_t)(struct tcc_module *const module); +#endif + +/** + * \brief TCC software device instance structure + * + * TCC software instance structure, used to retain software state information + * of an associated hardware module instance. + * + * \note The fields of this structure should not be altered by the user + * application; they are reserved only for module-internal use. + */ +struct tcc_module { + /** Hardware module pointer of the associated Timer/Counter peripheral. */ + Tcc *hw; + +# if TCC_ASYNC == true + /** Array of callbacks. */ + tcc_callback_t callback[TCC_CALLBACK_N]; + /** Bit mask for callbacks registered. */ + uint32_t register_callback_mask; + /** Bit mask for callbacks enabled. */ + uint32_t enable_callback_mask; +# endif + + /** Set to \c true to write to buffered registers. */ + bool double_buffering_enabled; +}; + +#if !defined(__DOXYGEN__) +uint8_t _tcc_get_inst_index( + Tcc *const hw); +#endif + +/** + * \name Driver Initialization and Configuration + * @{ + */ + +/** + * \brief Determines if the hardware module is currently synchronizing to the bus + * + * Checks to see if the underlying hardware peripheral module is currently + * synchronizing across multiple clock domains to the hardware bus. This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \param[in] module_inst Pointer to the software module instance struct + * + * \return Synchronization status of the underlying hardware module. + * + * \retval false If the module has completed synchronization + * \retval true If the module synchronization is ongoing + */ +static inline bool tcc_is_syncing( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + return (module_inst->hw->SYNCBUSY.reg > 0); +} + + +void tcc_get_config_defaults( + struct tcc_config *const config, + Tcc *const hw); + +enum status_code tcc_init( + struct tcc_module *const module_inst, + Tcc *const hw, + const struct tcc_config *const config); + +/** @} */ + +/** + * \name Event Management + * @{ + */ + +enum status_code tcc_enable_events( + struct tcc_module *const module_inst, + struct tcc_events *const events); + +void tcc_disable_events( + struct tcc_module *const module_inst, + struct tcc_events *const events); + +/** @} */ + +/** + * \name Enable/Disable/Reset + * @{ + */ + +/** + * \brief Enable the TCC module + * + * Enables a TCC module that has been previously initialized. The counter will + * start when the counter is enabled. + * + * \note When the counter is configured to re-trigger on an event, the counter + * will not start until the next incoming event appears. Then it + * restarts on any following event. + * + * \param[in] module_inst Pointer to the software module instance struct + */ +static inline void tcc_enable( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + + while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) { + /* Wait for sync */ + } + + /* Enable the TCC module */ + tcc_module->CTRLA.reg |= TCC_CTRLA_ENABLE; +} + +/** + * \brief Disables the TCC module + * + * Disables a TCC module and stops the counter. + * + * \param[in] module_inst Pointer to the software module instance struct + */ +static inline void tcc_disable( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + + while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) { + /* Wait for sync */ + } + + /* Disable the TCC module */ + tcc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; +} + +/** + * \brief Resets the TCC module + * + * Resets the TCC module, restoring all hardware module registers to their + * default values and disabling the module. The TCC module will not be + * accessible while the reset is being performed. + * + * \note When resetting a 32-bit counter only the master TCC module's instance + * structure should be passed to the function. + * + * \param[in] module_inst Pointer to the software module instance struct + * + */ +static inline void tcc_reset( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module hardware instance */ + Tcc *const tcc_module = module_inst->hw; + + /* Disable this module if it is running */ + if (tcc_module->CTRLA.reg & TCC_CTRLA_ENABLE) { + tcc_disable(module_inst); + while (tcc_is_syncing(module_inst)) { + /* wait while module is disabling */ + } + } + + /* Reset this TC module */ + tcc_module->CTRLA.reg |= TCC_CTRLA_SWRST; +} + +/** @} */ + + +/** + * \name Set/Toggle Count Direction + * @{ + */ + +/** + * \brief Sets the TCC module count direction + * + * Sets the count direction of an initialized TCC module. The + * specified TCC module can remain running or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] dir New timer count direction to set + */ +static inline void tcc_set_count_direction( + const struct tcc_module *const module_inst, + enum tcc_count_direction dir) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + + while (tcc_module->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + + /* Set count direction */ + if (TCC_COUNT_DIRECTION_DOWN == dir) { + tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR; + return; + } + tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR; +} + +/** + * \brief Toggles the TCC module count direction + * + * Toggles the count direction of an initialized TCC module. The + * specified TCC module can remain running or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + */ +static inline void tcc_toggle_count_direction( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + + while (tcc_module->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + bool dir_value_1 = tcc_module->CTRLBSET.bit.DIR; + if (dir_value_1) { + tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR; + } else { + tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +/** @} */ + +/** + * \name Get/Set Count Value + * @{ + */ + +uint32_t tcc_get_count_value( + const struct tcc_module *const module_inst); + +enum status_code tcc_set_count_value( + const struct tcc_module *const module_inst, + const uint32_t count); + +/** @} */ + +/** + * \name Stop/Restart Counter + * @{ + */ + +/** + * \brief Stops the counter + * + * This function will stop the counter. When the counter is stopped + * the value in the count register is set to 0 if the counter was + * counting up, or maximum or the top value if the counter was counting + * down. + * + * \param[in] module_inst Pointer to the software module instance struct + */ +static inline void tcc_stop_counter( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + uint32_t last_cmd; + + /* Wait until last command is done */ + do { + while (tcc_module->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; + if (last_cmd == TCC_CTRLBSET_CMD_NONE) { + break; + } else if (last_cmd == TCC_CTRLBSET_CMD_STOP) { + /* Command have been issued */ + return; + } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) { + /* Cancel RETRIGGER command and issue STOP */ + tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk; + } + } while (1); + + /* Write command to execute */ + tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_STOP; +} + +/** + * \brief Starts the counter from beginning + * + * Restarts an initialized TCC module's counter. + * + * \param[in] module_inst Pointer to the software module instance struct + */ +static inline void tcc_restart_counter( + const struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + uint32_t last_cmd; + + /* Wait until last command is done */ + do { + while (tcc_module->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; + if (last_cmd == TCC_CTRLBSET_CMD_NONE) { + break; + } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) { + /* Command have been issued */ + return; + } else if (last_cmd == TCC_CTRLBSET_CMD_STOP) { + /* Cancel STOP command and issue RETRIGGER */ + tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk; + } + } while (1); + + /* Write command to execute */ + tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_RETRIGGER; +} + +/** @} */ + +/** + * \name Get/Set Compare/Capture Register + * @{ + */ + +uint32_t tcc_get_capture_value( + const struct tcc_module *const module_inst, + const enum tcc_match_capture_channel channel_index); + +enum status_code tcc_set_compare_value( + const struct tcc_module *const module_inst, + const enum tcc_match_capture_channel channel_index, + const uint32_t compare); + +/** @} */ + +/** + * \name Set Top Value + * @{ + */ + +enum status_code tcc_set_top_value( + const struct tcc_module *const module_inst, + const uint32_t top_value); + +/** @} */ + + +/** + * \name Set Output Pattern + * @{ + */ + +enum status_code tcc_set_pattern( + const struct tcc_module *const module_inst, + const uint32_t line_index, + const enum tcc_output_pattern pattern); + +/** @} */ + + +/** + * \name Set Ramp Index + * @{ + */ + +/** + * \brief Sets the TCC module ramp index on next cycle + * + * In RAMP2 and RAMP2A operation, we can force either cycle A or cycle B at + * the output, on the next clock cycle. + * When ramp index command is disabled, cycle A and cycle B will appear at + * the output, on alternate clock cycles. + * See \ref tcc_ramp. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] ramp_index Ramp index (\ref tcc_ramp_index) of the next cycle + */ +static inline void tcc_set_ramp_index( + const struct tcc_module *const module_inst, + const enum tcc_ramp_index ramp_index) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + uint32_t last_cmd; + + /* Wait until last command is done */ + do { + while (tcc_module->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + if (TCC_RAMP_INDEX_DEFAULT == ramp_index) { + /* Cancel pending command */ + tcc_module->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD_DISABLE; + return; + } + last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_IDXCMD_Msk; + if (last_cmd == TCC_CTRLBSET_IDXCMD_DISABLE) { + break; + } else if (last_cmd == TCC_CTRLBSET_CMD(ramp_index)) { + /* Command have been issued */ + return; + } + } while (1); + + /* Write command to execute */ + tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD(ramp_index); +} + +/** @} */ + +/** + * \name Status Management + * @{ + */ + +/** + * \brief Checks if the timer/counter is running + * + * \param[in] module_inst Pointer to the TCC software instance struct + * + * \return Status which indicates whether the module is running. + * + * \retval true The timer/counter is running + * \retval false The timer/counter is stopped + */ +static inline bool tcc_is_running( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + return !module_inst->hw->STATUS.bit.STOP; +} + +uint32_t tcc_get_status( + struct tcc_module *const module_inst); + +void tcc_clear_status( + struct tcc_module *const module_inst, + const uint32_t status_flags); + +/** @} */ + +/** + * \name Double Buffering Management + * @{ + */ + +/** + * \brief Enable TCC double buffering write + * + * When double buffering write is enabled, following function will write values + * to buffered registers instead of effective ones (buffered): + * - PERB: through \ref tcc_set_top_value() + * - CCBx(x is 0~3): through \ref tcc_set_compare_value() + * - PATTB: through \ref tcc_set_pattern() + * + * Then on UPDATE condition the buffered registers are committed to regular ones + * to take effect. + * + * \param[in] module_inst Pointer to the TCC software instance struct + */ +static inline void tcc_enable_double_buffering( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + + module_inst->double_buffering_enabled = true; +} + +/** + * \brief Disable TCC double buffering Write + * + * When double buffering write is disabled, following function will write values + * to effective registers (not buffered): + * - PER: through \ref tcc_set_top_value() + * - CCx(x is 0~3): through \ref tcc_set_compare_value() + * - PATT: through \ref tcc_set_pattern() + * + * \note This function does not lock double buffer update, which means on next + * UPDATE condition the last written buffered values will be committed to + * take effect. Invoke \ref tcc_lock_double_buffer_update() before this + * function to disable double buffering update, if this change is not + * expected. + * + * \param[in] module_inst Pointer to the TCC software instance struct + */ +static inline void tcc_disable_double_buffering( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + module_inst->double_buffering_enabled = false; +} + +/** + * \brief Lock the TCC double buffered registers updates + * + * Locks the double buffered registers so they will not be updated through + * their buffered values on UPDATE conditions. + * + * \param[in] module_inst Pointer to the TCC software instance struct + * + */ +static inline void tcc_lock_double_buffer_update( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + while (module_inst->hw->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + module_inst->hw->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +/** + * \brief Unlock the TCC double buffered registers updates + * + * Unlock the double buffered registers so they will be updated through + * their buffered values on UPDATE conditions. + * + * \param[in] module_inst Pointer to the TCC software instance struct + * + */ +static inline void tcc_unlock_double_buffer_update( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + while (module_inst->hw->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + module_inst->hw->CTRLBCLR.reg = TCC_CTRLBCLR_LUPD; +} + +/** + * \brief Force the TCC double buffered registers to update once + * + * \param[in] module_inst Pointer to the TCC software instance struct + * + */ +static inline void tcc_force_double_buffer_update( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tcc *const tcc_module = module_inst->hw; + uint32_t last_cmd; + + /* Wait until last command is done */ + do { + while (tcc_module->SYNCBUSY.bit.CTRLB) { + /* Wait for sync */ + } + last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; + if (last_cmd == TCC_CTRLBSET_CMD_NONE) { + break; + } else if (last_cmd == TCC_CTRLBSET_CMD_UPDATE) { + /* Command have been issued */ + return; + } + } while (1); + + /* Write command to execute */ + tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_UPDATE; +} + +/** + * \brief Enable Circular option for double buffered Top/Period Values + * + * Enable circular option for the double buffered top/period values. + * On each UPDATE condition, the contents of PERB and PER are switched, meaning + * that the contents of PERB are transferred to PER and the contents of PER are + * transferred to PERB. + * + * \param[in] module_inst Pointer to the TCC software instance struct + */ +static inline void tcc_enable_circular_buffer_top( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + module_inst->hw->WAVE.reg |= TCC_WAVE_CIPEREN; +} + +/** + * \brief Disable Circular option for double buffered Top/Period Values + * + * Stop circularing the double buffered top/period values. + * + * \param[in] module_inst Pointer to the TCC software instance struct + */ +static inline void tcc_disable_circular_buffer_top( + struct tcc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + module_inst->hw->WAVE.reg &= ~TCC_WAVE_CIPEREN; +} + +enum status_code tcc_set_double_buffer_top_values( + const struct tcc_module *const module_inst, + const uint32_t top_value, const uint32_t top_buffer_value); + + +enum status_code tcc_enable_circular_buffer_compare( + struct tcc_module *const module_inst, + enum tcc_match_capture_channel channel_index); +enum status_code tcc_disable_circular_buffer_compare( + struct tcc_module *const module_inst, + enum tcc_match_capture_channel channel_index); +enum status_code tcc_set_double_buffer_compare_values( + struct tcc_module *const module_inst, + enum tcc_match_capture_channel channel_index, + const uint32_t compare, + const uint32_t compare_buffer); + + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +/** + * \page asfdoc_sam0_tcc_extra Extra Information for TCC Driver + * + * \section asfdoc_sam0_tcc_extra_acronyms Acronyms + * The table below presents the acronyms used in this module: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AcronymDescription
DMADirect Memory Access
TCCTimer Counter for Control Applications
PWMPulse Width Modulation
PWPPulse Width Period
PPWPeriod Pulse Width
+ * + * + * \section asfdoc_sam0_tcc_extra_dependencies Dependencies + * This driver has the following dependencies: + * + * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" + * + * + * \section asfdoc_sam0_tcc_extra_errata Errata + * There are no errata related to this driver. + * + * + * \section asfdoc_sam0_tcc_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Changelog
Add double buffering functionality
Add fault handling functionality
Initial Release
+ */ + +/** + * \page asfdoc_sam0_tcc_exqsg Examples for TCC Driver + * + * This is a list of the available Quick Start guides (QSGs) and example + * applications for \ref asfdoc_sam0_tcc_group. QSGs are simple examples with + * step-by-step instructions to configure and use this driver in a selection of + * use cases. Note that QSGs can be compiled as a standalone application or be + * added to the user application. + * + * - \subpage asfdoc_sam0_tcc_basic_use_case + * - \subpage asfdoc_sam0_tcc_buffering_use_case + * \if TCC_CALLBACK_MODE + * - \subpage asfdoc_sam0_tcc_timer_use_case + * - \subpage asfdoc_sam0_tcc_callback_use_case + * - \subpage asfdoc_sam0_tcc_faultx_use_case + * - \subpage asfdoc_sam0_tcc_faultn_use_case + * \endif + * - \subpage asfdoc_sam0_tcc_dma_use_case + * + * \page asfdoc_sam0_tcc_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Doc. Rev. + * Date + * Comments + *
C11/2014Added support for SAML21
B12/2014Added fault handling functionality; + * Added double buffering functionality with use case; + * Added timer use case; + * Added SAM R21/D10/D11 support
A01/2014Initial release
+ */ + +#endif /* TCC_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/objects.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/objects.h index 119dc9b630..26c3cd1e7c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/objects.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/objects.h @@ -20,6 +20,8 @@ #include "PortNames.h" #include "PeripheralNames.h" #include "gpio_object.h" +#include "tc.h" +#include "tcc.h" #include "adc.h" #include "extint.h" #include "i2c_master.h" @@ -72,6 +74,12 @@ struct analogin_s { }; struct pwmout_s { + struct tcc_module tcc; + PinName pin; + uint32_t period; + float duty_cycle; + enum gclk_generator clock_source; + enum tc_clock_prescaler clock_prescaler; }; struct i2c_s { diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.c index a384beaa42..e22af3b21d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.c @@ -23,6 +23,37 @@ #include "pinmap_function.h" +struct pwm_pin_channel { + PinName pin; + PWMName pwm; + uint8_t channel_index; +}; + +static struct pwm_pin_channel pwn_pins[] = { + {PA00, PWM_2, 0}, + {PA01, PWM_2, 1}, + {PA04, PWM_0, 0}, + {PA05, PWM_0, 1}, + {PA06, PWM_1, 0}, + {PA07, PWM_1, 1}, + {PA08, PWM_0, 0}, + {PA09, PWM_0, 1}, + {PA12, PWM_2, 0}, + {PA13, PWM_2, 1}, + {PA16, PWM_2, 0}, + {PA17, PWM_2, 1}, + {PA18, PWM_0, 2}, + {PA19, PWM_0, 3}, + {PA22, PWM_0, 4}, + {PA23, PWM_0, 5}, + {PA24, PWM_1, 2}, + {PA25, PWM_1, 3}, + {PA30, PWM_1, 0}, + {PA31, PWM_1, 1}, + + {NC, NC, NC} +}; + static uint32_t pinmap_merge_pins(uint32_t a, uint32_t b) { // both are the same (inc both NC) @@ -218,4 +249,23 @@ uint32_t pinmap_peripheral_sercom(PinName pin, uint32_t sercom_index) return NC; } return sercom_address[(sercom_index&0x0F)]; -} \ No newline at end of file +} + +/** Find the channel index of a pin specific to a PWM instance + * + * @param[in] pin pin name + * @param[in] pwm pwm peripheral (unused now) + * @return Channel index of the specified pin + */ +uint32_t pinmap_channel_pwm(PinName pin, PWMName pwm) +{ + struct pwm_pin_channel *pwm_ch = pwn_pins; + + while (pwm_ch->pin != NC) { + if (pin == pwm_ch->pin) { + return (uint32_t)pwm_ch->channel_index; + } + pwm_ch++; + } + return NC; +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.h index afab1bc2e6..fc1e74b91e 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pinmap_function.h @@ -75,6 +75,14 @@ uint32_t pinmap_pad_sercom(PinName pin, uint32_t sercom_index); */ uint32_t pinmap_peripheral_sercom(PinName pin, uint32_t sercom_index); +/** Find the channel index of a pin specific to a PWM instance + * + * @param[in] pin pin name + * @param[in] pwm pwm peripheral (unused now) + * @return Channel index of the specified pin + */ +uint32_t pinmap_channel_pwm(PinName pin, PWMName pwm); + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pwmout_api.c index 4c1cf257d0..72d728682f 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM0/pwmout_api.c @@ -20,43 +20,195 @@ #include "pinmap.h" #include "PeripheralPins.h" +#include "pinmap_function.h" + + +#define PWMOUT_CTRL_CHANNEL 3 + +const uint32_t tcc_prescaler[] = { + TCC_CLOCK_PRESCALER_DIV1, + TCC_CLOCK_PRESCALER_DIV2, + TCC_CLOCK_PRESCALER_DIV4, + TCC_CLOCK_PRESCALER_DIV8, + TCC_CLOCK_PRESCALER_DIV16, + TCC_CLOCK_PRESCALER_DIV64, + TCC_CLOCK_PRESCALER_DIV256, + TCC_CLOCK_PRESCALER_DIV1024 +}; + +extern const uint32_t _tcc_maxs[TCC_INST_NUM]; + +static void pwmout_set_period(pwmout_t* obj, int period_us) +{ + uint32_t i; + uint32_t freq_hz; + double us_per_cycle; + uint64_t max_period = 0; + uint32_t us_period = period_us; + + /* Sanity check arguments */ + MBED_ASSERT(obj); + + /* TCC instance index */ + uint8_t module_index = _tcc_get_inst_index(obj->tcc.hw); + + uint32_t count_max = _tcc_maxs[module_index]; + + freq_hz = system_gclk_gen_get_hz(obj->clock_source); + + for (i=0; i> tcc_prescaler[i]); + max_period = us_per_cycle * count_max; + if (max_period >= us_period) { + obj->clock_prescaler = tcc_prescaler[i]; + obj->period = us_period / us_per_cycle; + break; + } + } +} + +void pwmout_init_hw(pwmout_t* obj) +{ + uint32_t mux_func = NC; + uint32_t pwm = NC; + PinName pin; + uint32_t ch_index = NC; + struct tcc_config config_tcc; + + /* Sanity check arguments */ + MBED_ASSERT(obj); + + pin = obj->pin; + pwm = pinmap_peripheral(pin, PinMap_PWM); + if (pwm == (uint32_t)NC) return; /* Pin not supported */ + + mux_func = pinmap_function(pin, PinMap_PWM); + ch_index = pinmap_channel_pwm(pin, pwm); + if ((mux_func == (uint32_t)NC) || (ch_index == (uint32_t)NC)) { + /* Pin not supported */ + return; + } + + tcc_get_config_defaults(&config_tcc, (Tcc*)pwm); + + config_tcc.counter.clock_source = obj->clock_source; + config_tcc.counter.clock_prescaler = obj->clock_prescaler; + + config_tcc.counter.period = obj->period; + config_tcc.compare.wave_generation = TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM; + config_tcc.compare.match[PWMOUT_CTRL_CHANNEL] = obj->period * obj->duty_cycle; + + config_tcc.pins.enable_wave_out_pin[ch_index] = true; + config_tcc.pins.wave_out_pin[ch_index] = pin; + config_tcc.pins.wave_out_pin_mux[ch_index] = mux_func; + + tcc_init(&obj->tcc, (Tcc*)pwm, &config_tcc); + +} void pwmout_init(pwmout_t* obj, PinName pin) { + /* Sanity check arguments */ + MBED_ASSERT(obj); + + obj->pin = pin; + obj->period = 0xFFFF; + obj->duty_cycle = 1; + obj->clock_source = GCLK_GENERATOR_0; /* 8Mhz input clock */ + obj->clock_prescaler = TCC_CLOCK_PRESCALER_DIV8; /* Default to 1MHz for 8Mhz input clock */ + + pwmout_init_hw(obj); + + tcc_enable(&obj->tcc); } void pwmout_free(pwmout_t* obj) { + /* Sanity check arguments */ + MBED_ASSERT(obj); + + tcc_disable(&obj->tcc); } void pwmout_write(pwmout_t* obj, float value) { + /* Sanity check arguments */ + MBED_ASSERT(obj); + + if (value < 0.0f) { + value = 0; + } else if (value > 1.0f) { + value = 1; + } + + /* Modify the pulse width keeping period same */ + obj->duty_cycle = value; + + /* Disable PWM Module */ + tcc_disable(&obj->tcc); + + /* Update the changes */ + pwmout_init_hw(obj); + + /* Enable PWM Module */ + tcc_enable(&obj->tcc); + } float pwmout_read(pwmout_t* obj) { + /* Sanity check arguments */ + MBED_ASSERT(obj); + + return obj->duty_cycle; } void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); } void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); } void pwmout_period_us(pwmout_t* obj, int us) { + /* Sanity check arguments */ + MBED_ASSERT(obj); + + /* Disable PWM Module */ + tcc_disable(&obj->tcc); + + /* TODO: Find and set the period */ + pwmout_set_period(obj, us); + + /* Update the changes */ + pwmout_init_hw(obj); + + /* Enable PWM Module */ + tcc_enable(&obj->tcc); } void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); } void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); } void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + /* Sanity check arguments */ + MBED_ASSERT(obj); + + /* Find the new duty cycle */ + double duty_cycle = us / (double)obj->period; + + /* This call updates pulse width as well as period */ + pwmout_write(obj, duty_cycle); }