From 981b6259b67e53749024e38432bc919030d554bc Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 27 Nov 2018 09:17:36 -0600 Subject: [PATCH] MCUXpresso: Update the LPC GPIO drivers Update to the latest SDK GPIO driver Signed-off-by: Mahesh Mahadevan --- .../TARGET_LPC/gpio_api.c | 4 +- .../TARGET_LPC/port_api.c | 4 +- .../TARGET_LPC54114/drivers/fsl_gpio.c | 100 ++++++++++---- .../TARGET_LPC54114/drivers/fsl_gpio.h | 61 ++++----- .../TARGET_LPC54114/drivers/fsl_reset.h | 8 +- .../TARGET_MCU_LPC546XX/drivers/fsl_gpio.c | 89 ++++++++----- .../TARGET_MCU_LPC546XX/drivers/fsl_gpio.h | 122 +----------------- .../TARGET_MCU_LPC546XX/drivers/fsl_reset.h | 2 +- 8 files changed, 176 insertions(+), 214 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_api.c index c7dc09ca3f..64f686b8df 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_api.c @@ -62,7 +62,7 @@ void gpio_write(gpio_t *obj, int value) uint32_t pin_number = obj->pin & 0x1F; uint8_t port_number = obj->pin / 32; - GPIO_WritePinOutput(GPIO, port_number, pin_number, value); + GPIO_PinWrite(GPIO, port_number, pin_number, value); } int gpio_read(gpio_t *obj) @@ -71,5 +71,5 @@ int gpio_read(gpio_t *obj) uint32_t pin_number = obj->pin & 0x1F; uint8_t port_number = obj->pin / 32; - return (int)GPIO_ReadPinInput(GPIO, port_number, pin_number); + return (int)GPIO_PinRead(GPIO, port_number, pin_number); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/port_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/port_api.c index 35e7514494..a8a907a97d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/port_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/port_api.c @@ -71,12 +71,12 @@ void port_dir(port_t *obj, PinDirection dir) void port_write(port_t *obj, int value) { - GPIO_WriteMPort(GPIO, obj->port, value); + GPIO_PortMaskedWrite(GPIO, obj->port, value); } int port_read(port_t *obj) { - return (int)(GPIO_ReadMPort(GPIO, obj->port)); + return (int)(GPIO_PortMaskedRead(GPIO, obj->port)); } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.c index cd07e47082..ae5bd6f4a2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.c @@ -1,39 +1,30 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_gpio.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + /******************************************************************************* * Variables ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif /******************************************************************************* * Prototypes ************ ******************************************************************/ @@ -41,16 +32,67 @@ /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) { if (config->pinDirection == kGPIO_DigitalInput) { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1U << pin; +#else base->DIR[port] &= ~(1U << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ } else { - base->DIR[port] |= 1U << pin; /* Set default output value */ if (config->outputLogic == 0U) { @@ -58,7 +100,13 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c } else { - base->PIN[port] = (1U << pin); + base->SET[port] = (1U << pin); } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1U << pin; +#else + base->DIR[port] |= 1U << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.h index d8471143d8..f61b40d0d7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _LPC_GPIO_H_ @@ -46,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPC GPIO driver version 1.0.0. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*! @brief LPC GPIO driver version 2.1.3. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*@}*/ /*! @brief LPC GPIO direction definition */ @@ -80,6 +58,16 @@ extern "C" { /*! @name GPIO Configuration */ /*@{*/ +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + /*! * @brief Initializes a GPIO pin used by the board. * @@ -124,10 +112,11 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c * - 0: corresponding pin output low-logic level. * - 1: corresponding pin output high-logic level. */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) { base->B[port][pin] = output; } + /*@}*/ /*! @name GPIO Input Operations */ /*@{*/ @@ -142,10 +131,11 @@ static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t * - 0: corresponding pin input low-logic level. * - 1: corresponding pin input high-logic level. */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) { return (uint32_t)base->B[port][pin]; } + /*@}*/ /*! @@ -155,7 +145,7 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_ * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) { base->SET[port] = mask; } @@ -167,7 +157,7 @@ static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t m * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) { base->CLR[port] = mask; } @@ -179,10 +169,11 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) { base->NOT[port] = mask; } + /*@}*/ /*! @@ -191,7 +182,7 @@ static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_ * @param base GPIO peripheral base pointer(Typically GPIO) * @param port GPIO port number */ -static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) { return (uint32_t)base->PIN[port]; } @@ -207,7 +198,7 @@ static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) * @param port GPIO port number * @param mask GPIO pin number macro */ -static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) { base->MASK[port] = mask; } @@ -219,7 +210,7 @@ static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mas * @param port GPIO port number * @param output GPIO port output value. */ -static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) { base->MPIN[port] = output; } @@ -232,7 +223,7 @@ static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t outp * @param port GPIO port number * @retval masked GPIO port value */ -static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) { return (uint32_t)base->MPIN[port]; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_reset.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_reset.h index c75cf1a20c..a18f06ebfd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_reset.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_reset.h @@ -46,6 +46,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.0. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + /*! * @brief Enumeration for peripheral reset control bits * @@ -111,7 +117,7 @@ typedef enum _SYSCON_RSTn { \ kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS \ +#define GPIO_RSTS_N \ { \ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ } /* Reset bits for GPIO peripheral */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.c index 2581df0f9b..ae5bd6f4a2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.c @@ -1,39 +1,18 @@ /* - * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_gpio.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -41,6 +20,11 @@ /*! @brief Array to map FGPIO instance number to clock name. */ static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif /******************************************************************************* * Prototypes ************ ******************************************************************/ @@ -48,6 +32,14 @@ static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; /******************************************************************************* * Code ******************************************************************************/ +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ void GPIO_PortInit(GPIO_Type *base, uint32_t port) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -56,13 +48,48 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port) /* Upgate the GPIO clock */ CLOCK_EnableClock(s_gpioClockName[port]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif } +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) { if (config->pinDirection == kGPIO_DigitalInput) { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1U << pin; +#else base->DIR[port] &= ~(1U << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ } else { @@ -75,7 +102,11 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c { base->SET[port] = (1U << pin); } - /* Set pin direction */ +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1U << pin; +#else base->DIR[port] |= 1U << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.h index b43140fc0a..f61b40d0d7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_gpio.h @@ -1,35 +1,9 @@ /* - * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _LPC_GPIO_H_ @@ -50,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPC GPIO driver version 2.1.1. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief LPC GPIO driver version 2.1.3. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*@}*/ /*! @brief LPC GPIO direction definition */ @@ -94,15 +68,6 @@ extern "C" { */ void GPIO_PortInit(GPIO_Type *base, uint32_t port); -/*! - * @brief Initializes the GPIO peripheral. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortInit. - */ -static inline void GPIO_Init(GPIO_Type *base, uint32_t port) -{ - GPIO_PortInit(base, port); -} - /*! * @brief Initializes a GPIO pin used by the board. * @@ -152,14 +117,6 @@ static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, u base->B[port][pin] = output; } -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. - */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} /*@}*/ /*! @name GPIO Input Operations */ /*@{*/ @@ -179,14 +136,6 @@ static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin return (uint32_t)base->B[port][pin]; } -/*! - * @brief Reads the current input value of the GPIO PIN. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. - */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return GPIO_PinRead(base, port, pin); -} /*@}*/ /*! @@ -201,15 +150,6 @@ static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) base->SET[port] = mask; } -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. - */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortSet(base, port, mask); -} - /*! * @brief Sets the output level of the multiple GPIO pins to the logic 0. * @@ -222,15 +162,6 @@ static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) base->CLR[port] = mask; } -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. - */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortClear(base, port, mask); -} - /*! * @brief Reverses current output logic of the multiple GPIO pins. * @@ -243,14 +174,6 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask base->NOT[port] = mask; } -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortToggle. - */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortToggle(base, port, mask); -} /*@}*/ /*! @@ -264,15 +187,6 @@ static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) return (uint32_t)base->PIN[port]; } -/*! - * @brief Reads the current input value of the whole GPIO port. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortRead - */ -static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) -{ - return GPIO_PortRead(base, port); -} - /*@}*/ /*! @name GPIO Mask Operations */ /*@{*/ @@ -289,15 +203,6 @@ static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t m base->MASK[port] = mask; } -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedSet. - */ -static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - GPIO_PortMaskedSet(base, port, mask); -} - /*! * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. * @@ -310,15 +215,6 @@ static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t base->MPIN[port] = output; } -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedWrite. - */ -static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) -{ - GPIO_PortMaskedWrite(base, port, output); -} - /*! * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be * affected. @@ -332,16 +228,6 @@ static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) return (uint32_t)base->MPIN[port]; } -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedRead. - */ -static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) -{ - return GPIO_PortMaskedRead(base, port); -} - /*@}*/ #if defined(__cplusplus) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_reset.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_reset.h index 167f7d158f..5127ced541 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_reset.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_reset.h @@ -167,7 +167,7 @@ typedef enum _SYSCON_RSTn { \ kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS \ +#define GPIO_RSTS_N \ { \ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \