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Merge pull request #10873 from ganesh-ramachandran/m3hq_newfeatures 

Add new features to Toshiba's TMPM3HQ
pull/10976/head
Martin Kojtal 2019-07-05 13:06:46 +01:00 committed by GitHub
parent e08b7137a6 3d48b7c1cc
commit 97d50ed936
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
14 changed files with 1894 additions and 67 deletions
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79
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/crc_api.c Normal file
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@ -0,0 +1,79 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdbool.h>
#include "crc_api.h"
#include "device.h"
#ifdef DEVICE_CRC
static uint32_t final_xor;
bool hal_crc_is_supported(const crc_mbed_config_t *config)
{
if (config == NULL) {
return false;
}
// Currently supported only CRC16_CCITT polynomial.
if (config->polynomial != POLY_16BIT_CCITT) {
return false;
}
if (config->width != 16) {
return false;
}
// Not support for reflect_in and reflect_out.
if ((config->reflect_in == true) || (config->reflect_out == true)) {
return false;
}
return true;
}
void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
{
TSB_CG_FSYSENB_IPENB20 = 1;
// Intial Value as initial_xor
TSB_CRC->CLC = config->initial_xor;
final_xor = config->final_xor;
// Data width setting CRC data width is 8 bits.
// Form setting CRC form is CRC16.
TSB_CRC->TYP = 0x01;
}
void hal_crc_compute_partial(const uint8_t *data, const size_t size)
{
if (data && size) {
uint32_t index = 0U;
for(index = 0U; index < size; index++) {
TSB_CRC->DIN = data[index];
}
}
}
uint32_t hal_crc_get_result(void)
{
uint32_t result;
// Note: Please read [CRCCLC] twice and use the result of the 2nd time
result = TSB_CRC->CLC;
result = TSB_CRC->CLC ^ final_xor;
return (result);
}
#endif // DEVICE_CRC

3
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device.h
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@ -16,7 +16,8 @@
#ifndef MBED_DEVICE_H #ifndef MBED_DEVICE_H
#define MBED_DEVICE_H #define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32 #define DEVICE_ID_LENGTH 32
#define TRANSACTION_QUEUE_SIZE_SPI 4
#include "objects.h" #include "objects.h"

3
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct
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@ -40,9 +40,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE
RW_IRAM1 0x200002D8 (0x10000 - 0x2D8 - Stack_Size) RW_IRAM1 0x200002D8 (0x10000 - 0x2D8 - Stack_Size)
{ {
tmpm3hq_fc.o (+RO)
.ANY (+RW, +ZI) .ANY (+RW, +ZI)
} }
ARM_LIB_STACK (0x200002D8+0x10000) EMPTY -Stack_Size { ; stack ARM_LIB_STACK (0x20000000+0x10000) EMPTY -Stack_Size { ; stack
} }
} }

2
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld
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@ -109,7 +109,7 @@ SECTIONS
__data_start__ = .; __data_start__ = .;
*(vtable) *(vtable)
*(.data*) *(.data*)
*(.ram_func*)
. = ALIGN(4); . = ALIGN(4);
/* preinit data */ /* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .); PROVIDE_HIDDEN (__preinit_array_start = .);

9
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf
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@ -37,6 +37,15 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit }; do not initialize { section .noinit };
initialize by copy { section RAMCODE };
/* Place both in a block */
define block RamCode { section RAMCODE };
define block RamCodeInit { section RAMCODE_init };
/* Place them in ROM and RAM */
place in ROM_region { block RamCodeInit };
place in RAM_region { block RamCode };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };

130
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/flash_api.c Normal file
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@ -0,0 +1,130 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "flash_api.h"
#include "mbed_critical.h"
#include "tmpm3hq_fc.h"
#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once
#define SECTOR_SIZE (0x8000) // 32KB each sectors or block
#define FLASH_CHIP_SIZE (0x00080000) // Flash chip size is 512KByte
#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL)
#define SUCCESS (0U)
#define FAIL (-1)
// IHOSC1EN
#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask
#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable
#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable
static void internal_hosc_enable(void);
int32_t flash_init(flash_t *obj)
{
obj->flash_inited = 0;
obj->flash_inited = 1;
internal_hosc_enable(); // Internal HOSC enable
return 0;
}
int32_t flash_free(flash_t *obj)
{
obj->flash_inited = 0;
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
int status = FAIL;
if (obj->flash_inited == 0) {
flash_init(obj);
}
// We need to prevent flash accesses during erase operation
core_util_critical_section_enter();
if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t*)address)) {
status = SUCCESS;
} else {
// Do nothing
}
core_util_critical_section_exit();
return status;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
int status = SUCCESS;
address &= MASK_CHIP_ID_FROM_ADD;
// We need to prevent flash accesses during program operation
core_util_critical_section_enter();
if (TXZ_SUCCESS == fc_write_code_flash((uint32_t*)data, (uint32_t*)address, size)) {
// Do nothing
} else {
status = FAIL;
}
core_util_critical_section_exit();
return status;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) {
return SECTOR_SIZE;
} else {
// Do nothing
}
return MBED_FLASH_INVALID_SIZE;
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return PROGRAM_WRITE_MAX;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return FC_CODE_FLASH_ADDRESS_TOP;
}
uint32_t flash_get_size(const flash_t *obj)
{
return FLASH_CHIP_SIZE;
}
static void internal_hosc_enable(void)
{
uint32_t work;
work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK);
TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE);
}
uint8_t flash_get_erase_value(const flash_t *obj)
{
(void)obj;
return 0xFF;
}

377
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/i2c_api.c
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@ -21,6 +21,12 @@
#include "pinmap.h" #include "pinmap.h"
#include "gpio_include.h" #include "gpio_include.h"
#if DEVICE_I2C_ASYNCH
#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
#else
#define I2C_S(obj) (struct i2c_s *) (obj)
#endif
static const PinMap PinMap_I2C_SDA[] = { static const PinMap PinMap_I2C_SDA[] = {
{PC1, I2C_0, PIN_DATA(1, 2)}, {PC1, I2C_0, PIN_DATA(1, 2)},
{PA5, I2C_1, PIN_DATA(1, 2)}, {PA5, I2C_1, PIN_DATA(1, 2)},
@ -51,13 +57,51 @@ static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {
I2C_clock_setting_t clk; I2C_clock_setting_t clk;
static uint32_t start_flag = 0; static uint32_t start_flag = 0;
#if DEVICE_I2C_ASYNCH
enum {
I2C_TRANSFER_STATE_IDLE = 0U,
I2C_TRANSFER_STATE_START,
I2C_TRANSFER_STATE_WRITE,
I2C_TRANSFER_STATE_RESTART,
I2C_TRANSFER_STATE_READ,
I2C_TRANSFER_STATE_MAX
} TransferState;
typedef struct {
IRQn_Type i2c;
} i2c_irq_t;
static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = {
{ INTI2C0_IRQn }
};
static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = {
{ INTI2C1_IRQn }
};
static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = {
{ INTI2C2_IRQn }
};
static const i2c_irq_t I2C_CH3_IRQN_TBL[1] = {
{ INTI2C3_IRQn }
};
#endif
static int32_t wait_status(i2c_t *p_obj); static int32_t wait_status(i2c_t *p_obj);
static void i2c_start_bit(i2c_t *obj); static void i2c_start_bit(i2c_t *obj);
#if DEVICE_I2C_ASYNCH
static void disable_irq(uint32_t irqn);
static void clear_irq(uint32_t irqn);
static void i2c_irq_handler(i2c_t *obj);
#endif
// Initialize the I2C peripheral. It sets the default parameters for I2C // Initialize the I2C peripheral. It sets the default parameters for I2C
void i2c_init(i2c_t *obj, PinName sda, PinName scl) void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{ {
MBED_ASSERT(obj != NULL); struct i2c_s *obj_s = I2C_S(obj);
MBED_ASSERT(obj_s != NULL);
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
@ -69,28 +113,42 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
case I2C_0: case I2C_0:
TSB_CG_FSYSENB_IPENB11 = ENABLE; TSB_CG_FSYSENB_IPENB11 = ENABLE;
TSB_CG_FSYSENA_IPENA02 = ENABLE; TSB_CG_FSYSENA_IPENA02 = ENABLE;
obj->i2c = TSB_I2C0; obj_s->i2c = TSB_I2C0;
#if DEVICE_I2C_ASYNCH
obj_s->irqn = (uint32_t)&I2C_CH0_IRQN_TBL;
#endif
break; break;
case I2C_1: case I2C_1:
TSB_CG_FSYSENB_IPENB12 = ENABLE; TSB_CG_FSYSENB_IPENB12 = ENABLE;
TSB_CG_FSYSENA_IPENA00 = ENABLE; TSB_CG_FSYSENA_IPENA00 = ENABLE;
obj->i2c = TSB_I2C1; obj_s->i2c = TSB_I2C1;
#if DEVICE_I2C_ASYNCH
obj_s->irqn = (uint32_t)&I2C_CH1_IRQN_TBL;
#endif
break; break;
case I2C_2: case I2C_2:
TSB_CG_FSYSENB_IPENB13 = ENABLE; TSB_CG_FSYSENB_IPENB13 = ENABLE;
TSB_CG_FSYSENA_IPENA10 = ENABLE; TSB_CG_FSYSENA_IPENA10 = ENABLE;
obj->i2c = TSB_I2C2; obj_s->i2c = TSB_I2C2;
#if DEVICE_I2C_ASYNCH
obj_s->irqn = (uint32_t)&I2C_CH2_IRQN_TBL;
#endif
break; break;
case I2C_3: case I2C_3:
TSB_CG_FSYSENB_IPENB14 = ENABLE; TSB_CG_FSYSENB_IPENB14 = ENABLE;
TSB_CG_FSYSENA_IPENA15 = ENABLE; TSB_CG_FSYSENA_IPENA15 = ENABLE;
obj->i2c = TSB_I2C3; obj_s->i2c = TSB_I2C3;
#if DEVICE_I2C_ASYNCH
obj_s->irqn = (uint32_t)&I2C_CH3_IRQN_TBL;
#endif
break; break;
default: default:
error("I2C is not available"); error("I2C is not available");
break; break;
} }
#if DEVICE_I2C_ASYNCH
obj_s->state = I2C_TRANSFER_STATE_IDLE;
#endif
pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain); pin_mode(sda, OpenDrain);
pin_mode(sda, PullUp); pin_mode(sda, PullUp);
@ -101,15 +159,16 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
i2c_reset(obj); i2c_reset(obj);
i2c_frequency(obj, 100000); i2c_frequency(obj, 100000);
obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR |
I2CxCR2_INIT); I2CxCR2_INIT);
obj->i2c->OP = I2CxOP_INIT; obj_s->i2c->OP = I2CxOP_INIT;
obj->i2c->IE = I2CxIE_CLEAR; obj_s->i2c->IE = I2CxIE_CLEAR;
} }
// Configure the I2C frequency // Configure the I2C frequency
void i2c_frequency(i2c_t *obj, int hz) void i2c_frequency(i2c_t *obj, int hz)
{ {
struct i2c_s *obj_s = I2C_S(obj);
uint64_t sck; uint64_t sck;
uint64_t tmp_sck; uint64_t tmp_sck;
uint64_t prsck; uint64_t prsck;
@ -141,8 +200,8 @@ void i2c_frequency(i2c_t *obj, int hz)
clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0; clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0;
} }
obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
} }
int i2c_start(i2c_t *obj) int i2c_start(i2c_t *obj)
@ -153,11 +212,12 @@ int i2c_start(i2c_t *obj)
int i2c_stop(i2c_t *obj) int i2c_stop(i2c_t *obj)
{ {
struct i2c_s *obj_s = I2C_S(obj);
uint32_t timeout = I2C_TIMEOUT; uint32_t timeout = I2C_TIMEOUT;
obj->i2c->CR2 = I2CxCR2_STOP_CONDITION; obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION;
while ((obj->i2c->SR & I2CxSR_BB) == I2CxSR_BB) { while ((obj_s->i2c->SR & I2CxSR_BB) == I2CxSR_BB) {
if (timeout == 0) { if (timeout == 0) {
break; break;
} }
@ -169,8 +229,9 @@ int i2c_stop(i2c_t *obj)
void i2c_reset(i2c_t *obj) void i2c_reset(i2c_t *obj)
{ {
obj->i2c->CR2 = I2CxCR2_SWRES_10; struct i2c_s *obj_s = I2C_S(obj);
obj->i2c->CR2 = I2CxCR2_SWRES_01; obj_s->i2c->CR2 = I2CxCR2_SWRES_10;
obj_s->i2c->CR2 = I2CxCR2_SWRES_01;
} }
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
@ -231,22 +292,23 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
int i2c_byte_read(i2c_t *obj, int last) int i2c_byte_read(i2c_t *obj, int last)
{ {
struct i2c_s *obj_s = I2C_S(obj);
int32_t result = 0; int32_t result = 0;
obj->i2c->ST = I2CxST_CLEAR; obj_s->i2c->ST = I2CxST_CLEAR;
if (last) { if (last) {
obj->i2c->OP |= I2CxOP_MFACK; obj_s->i2c->OP |= I2CxOP_MFACK;
} else { } else {
obj->i2c->OP &= ~I2CxOP_MFACK; obj_s->i2c->OP &= ~I2CxOP_MFACK;
} }
obj->i2c->DBR = (0 & I2CxDBR_DB_MASK); obj_s->i2c->DBR = (0 & I2CxDBR_DB_MASK);
if (wait_status(obj) < 0) { if (wait_status(obj) < 0) {
result = -1; result = -1;
} else { } else {
result = (int32_t)(obj->i2c->DBR & I2CxDBR_DB_MASK); result = (int32_t)(obj_s->i2c->DBR & I2CxDBR_DB_MASK);
} }
return result; return result;
@ -254,22 +316,23 @@ int i2c_byte_read(i2c_t *obj, int last)
int i2c_byte_write(i2c_t *obj, int data) int i2c_byte_write(i2c_t *obj, int data)
{ {
struct i2c_s *obj_s = I2C_S(obj);
int32_t result = 0; int32_t result = 0;
obj->i2c->ST = I2CxST_CLEAR; obj_s->i2c->ST = I2CxST_CLEAR;
if (start_flag == 1) { if (start_flag == 1) {
obj->i2c->DBR = (data & I2CxDBR_DB_MASK); obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK);
i2c_start_bit(obj); i2c_start_bit(obj);
start_flag = 0; start_flag = 0;
} else { } else {
obj->i2c->DBR = (data & I2CxDBR_DB_MASK); obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK);
} }
if (wait_status(obj) < 0) { if (wait_status(obj) < 0) {
return -1; return -1;
} }
if (!((obj->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
result = 1; result = 1;
} else { } else {
result = 0; result = 0;
@ -280,25 +343,27 @@ int i2c_byte_write(i2c_t *obj, int data)
static void i2c_start_bit(i2c_t *obj) // Send START command static void i2c_start_bit(i2c_t *obj) // Send START command
{ {
struct i2c_s *obj_s = I2C_S(obj);
uint32_t opreg = 0; uint32_t opreg = 0;
opreg = obj->i2c->OP; opreg = obj_s->i2c->OP;
opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN);
if ((obj->i2c->SR & I2CxSR_BB)) { if ((obj_s->i2c->SR & I2CxSR_BB)) {
opreg |= I2CxOP_SREN; opreg |= I2CxOP_SREN;
} }
obj->i2c->OP = opreg; obj_s->i2c->OP = opreg;
obj->i2c->CR2 |= I2CxCR2_START_CONDITION; obj_s->i2c->CR2 |= I2CxCR2_START_CONDITION;
} }
static int32_t wait_status(i2c_t *p_obj) static int32_t wait_status(i2c_t *p_obj)
{ {
struct i2c_s *obj_s = I2C_S(p_obj);
volatile int32_t timeout; volatile int32_t timeout;
timeout = I2C_TIMEOUT; timeout = I2C_TIMEOUT;
while (!((p_obj->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) { while (!((obj_s->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) {
if ((timeout--) == 0) { if ((timeout--) == 0) {
return (-1); return (-1);
} }
@ -309,32 +374,39 @@ static int32_t wait_status(i2c_t *p_obj)
void i2c_slave_mode(i2c_t *obj, int enable_slave) void i2c_slave_mode(i2c_t *obj, int enable_slave)
{ {
struct i2c_s *obj_s = I2C_S(obj);
if (enable_slave) { if (enable_slave) {
obj->i2c->OP = I2CxOP_SLAVE_INIT; i2c_reset(obj);
obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); obj_s->i2c->OP = I2CxOP_SLAVE_INIT;
obj->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); obj_s->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR);
obj->i2c->AR = (obj->address & I2CAR_SA_MASK); obj_s->i2c->CR2 = I2CxCR2_INIT;
obj->i2c->IE = I2CxIE_INTI2C; obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
obj_s->i2c->AR = (obj_s->address & I2CAR_SA_MASK);
obj_s->i2c->IE = I2CxIE_INTI2C;
} else { } else {
i2c_reset(obj); i2c_reset(obj);
obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR |
I2CxCR2_INIT); I2CxCR2_INIT);
obj->i2c->OP = I2CxOP_INIT; obj_s->i2c->OP = I2CxOP_INIT;
obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
NVIC_DisableIRQ(obj->IRQn); obj_s->i2c->ST = I2CxST_CLEAR;
NVIC_ClearPendingIRQ(obj->IRQn);
obj->i2c->ST = I2CxST_CLEAR;
} }
} }
int i2c_slave_receive(i2c_t *obj) int i2c_slave_receive(i2c_t *obj)
{ {
struct i2c_s *obj_s = I2C_S(obj);
int32_t result = I2C_NO_DATA; int32_t result = I2C_NO_DATA;
if ((obj->i2c->ST & I2CxST_I2C) && (obj->i2c->OP & I2CxOP_SAST)) { if ((obj_s->i2c->ST & I2CxST_I2C) && (obj_s->i2c->OP & I2CxOP_SAST)) {
if ((obj->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) { // Detect and clear arbitration lost.
if(!(obj_s->i2c->SR & 0x08)) {
obj_s->i2c->DBR = 0x00;
}
if ((obj_s->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) {
result = I2C_READ_ADDRESSED; result = I2C_READ_ADDRESSED;
} else { } else {
result = I2C_WRITE_ADDRESSED; result = I2C_WRITE_ADDRESSED;
@ -346,11 +418,12 @@ int i2c_slave_receive(i2c_t *obj)
int i2c_slave_read(i2c_t *obj, char *data, int length) int i2c_slave_read(i2c_t *obj, char *data, int length)
{ {
struct i2c_s *obj_s = I2C_S(obj);
int32_t count = 0; int32_t count = 0;
while (count < length) { while (count < length) {
int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); int32_t pdata = i2c_byte_read(obj, 0);
if ((obj->i2c->SR & I2CxSR_TRX)) { if ((obj_s->i2c->SR & I2CxSR_TRX)) {
return (count); return (count);
} else { } else {
if (pdata < 0) { if (pdata < 0) {
@ -382,7 +455,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length)
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{ {
obj->address = address & I2CAR_SA_MASK; struct i2c_s *obj_s = I2C_S(obj);
obj_s->address = address & I2CAR_SA_MASK;
i2c_slave_mode(obj,1); i2c_slave_mode(obj,1);
} }
@ -406,4 +480,209 @@ const PinMap *i2c_slave_scl_pinmap()
return PinMap_I2C_SCL; return PinMap_I2C_SCL;
} }
#if DEVICE_I2C_ASYNCH
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address,
uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_irq_t *p_irqn = (i2c_irq_t *)obj_s->irqn;
if(obj_s->state == I2C_TRANSFER_STATE_IDLE) {
// Disable and clear interrupt flag.
disable_irq(obj_s->irqn);
obj_s->i2c->IE = I2CxIE_CLEAR;
obj_s->i2c->ST = I2CxST_CLEAR;
clear_irq(obj_s->irqn);
// Store given buffer data and lenght into I2C object and set state as I2C_TRANSFER_STATE_START.
obj_s->address = address;
obj_s->event = 0;
obj_s->stop = stop;
obj->tx_buff.buffer = (void *)tx;
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
obj->rx_buff.buffer = rx;
obj->rx_buff.length = rx_length;
obj->rx_buff.pos = 0;
obj_s->state = I2C_TRANSFER_STATE_START;
// Enable I2C interrupt.
obj_s->i2c->IE = I2CxIE_INTI2C;
if ((tx_length == 0) && (rx_length != 0)) {
i2c_start_bit(obj);
obj_s->i2c->DBR = ((address | 1U) & I2CxDBR_DB_MASK);
} else {
i2c_start_bit(obj);
obj_s->i2c->DBR = (address & I2CxDBR_DB_MASK);
}
// Enable I2C interrupr in NVIC.
NVIC_EnableIRQ(p_irqn->i2c);
NVIC_SetVector(p_irqn->i2c, handler);
}
}
uint32_t i2c_irq_handler_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_irq_handler(obj);
return (obj_s->event & I2C_EVENT_ALL);
}
uint8_t i2c_active(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
uint8_t ret_val = 0;
if ((obj_s->i2c->CR2 & 0x08)) {
ret_val = 1;
}
return ret_val;
}
void i2c_abort_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
// Generate Stop condition on I2C bus
i2c_stop(obj);
// Set state as idle and disable I2C interrupt.
obj_s->state = I2C_TRANSFER_STATE_IDLE;
disable_irq(obj_s->irqn);
clear_irq(obj_s->irqn);
obj_s->i2c->IE = I2CxIE_CLEAR;
// Given I2C Software Reset
i2c_reset(obj);
// Re-Store the I2C configuration
obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | I2CxCR2_INIT);
obj_s->i2c->OP = I2CxOP_INIT;
obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
obj_s->i2c->ST = I2CxST_CLEAR;
}
static void disable_irq(uint32_t irqn)
{
i2c_irq_t *p_irqn = (i2c_irq_t *)irqn;
NVIC_DisableIRQ(p_irqn->i2c);
}
static void clear_irq(uint32_t irqn)
{
i2c_irq_t *p_irqn = (i2c_irq_t *)irqn;
NVIC_ClearPendingIRQ(p_irqn->i2c);
}
static void i2c_irq_handler(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
obj_s->i2c->ST = I2CxST_CLEAR;
switch(obj_s->state) {
case I2C_TRANSFER_STATE_START:
// Check ACK for sent slave address.
if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
if(obj->tx_buff.length != (unsigned long)0) { // Check Tx buff length.
obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK;
obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t);
obj->tx_buff.pos++;
obj_s->state = I2C_TRANSFER_STATE_WRITE;
} else if(obj->rx_buff.length != 0) { // Check Rx buff length.
if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) {
obj_s->i2c->OP &= ~I2CxOP_MFACK;
} else {
obj_s->i2c->OP |= I2CxOP_MFACK;
}
obj_s->i2c->DBR = 0x00;
obj_s->state = I2C_TRANSFER_STATE_READ;
} else { // Return transfer complete because of not given any Tx/Rx data.
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
} else { // Return "No Slave", Because of Did not get any ACK for sent slave address.
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
case I2C_TRANSFER_STATE_WRITE:
if(obj->tx_buff.pos < obj->tx_buff.length) {
if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK;
obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t);
obj->tx_buff.pos++;
} else {
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
} else if(obj->rx_buff.length != 0) {
if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
i2c_start_bit(obj);
obj_s->i2c->DBR = ((obj_s->address | 1U) & I2CxDBR_DB_MASK);
obj_s->state = I2C_TRANSFER_STATE_RESTART;
} else {
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
} else {
if(obj_s->stop) {
obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION;
}
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
case I2C_TRANSFER_STATE_RESTART:
if(!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
// Set ACK/NACK
if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) {
obj_s->i2c->OP &= ~I2CxOP_MFACK;
} else {
obj_s->i2c->OP |= I2CxOP_MFACK;
}
obj_s->i2c->DBR = 0x00;
obj_s->state = I2C_TRANSFER_STATE_READ;
} else {
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
case I2C_TRANSFER_STATE_READ:
if(obj->rx_buff.pos < obj->rx_buff.length) {
*((uint8_t *)obj->rx_buff.buffer) = (uint8_t)obj_s->i2c->DBR & I2CxDBR_DB_MASK;
obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + sizeof(uint8_t);
obj->rx_buff.pos++;
}
if(obj->rx_buff.pos < obj->rx_buff.length) {
// Set ACK/NACK
if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) {
obj_s->i2c->OP &= ~I2CxOP_MFACK;
} else {
obj_s->i2c->OP |= I2CxOP_MFACK;
}
obj_s->i2c->DBR = 0x00;
} else {
if(obj_s->stop) {
obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION;
}
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
default:
break;
}
if(obj_s->state == I2C_TRANSFER_STATE_IDLE) {
disable_irq(obj_s->irqn);
obj_s->i2c->IE = I2CxIE_CLEAR;
}
}
#endif // #if DEVICE_I2C_ASYNCH
#endif // #if DEVICE_I2C #endif // #if DEVICE_I2C

27
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/objects.h
View File

@ -92,15 +92,32 @@ struct pwmout_s {
}; };
struct i2c_s { struct i2c_s {
uint32_t address; uint32_t address;
IRQn_Type IRQn; IRQn_Type IRQn;
TSB_I2C_TypeDef *i2c; TSB_I2C_TypeDef *i2c;
#if DEVICE_I2C_ASYNCH
uint32_t irqn;
uint32_t state;
uint32_t event;
uint32_t stop;
#endif
}; };
struct spi_s { struct spi_s {
tspi_t p_obj; tspi_t p_obj;
SPIName module; SPIName module;
uint8_t bits; uint8_t bits;
PinName Slave_SCK;
#if DEVICE_SPI_ASYNCH
uint32_t irqn;
uint32_t event;
uint32_t max_size;
uint32_t state;
#endif
};
struct flash_s {
int flash_inited;
}; };
extern const gpio_regtypedef_t GPIO_SFRs[]; extern const gpio_regtypedef_t GPIO_SFRs[];

623
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/tmpm3hq_fc.c Normal file
View File

@ -0,0 +1,623 @@
/**
*******************************************************************************
* @file tmpm3hq_fc.c
* @brief Flash_Userboot Sample Application.
* @version V1.0.1.0
* $Date:: 2016-11-28 08:16:17 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* (C)Copyright TOSHIBA CORPORATION 2016 All rights reserved
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include <string.h>
#include "tmpm3hq_fc.h"
#include "TMPM3HQ.h"
/**
* @addtogroup Example
* @{
*/
/**
* @defgroup Flash_Userboot Flash_Userboot Sample Appli
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group Flash_Userboot_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
* @{
*/
/**
* @}
*/ /* End of group Flash_Userboot_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
* @{
*/
#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */
#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */
#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */
#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */
#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */
/* FCSR0 register */
#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area0 */
#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) /*!< RW, Selects area0 */
#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFFF8FFF8UL) /*!< RW, Selects area0 */
#define FC_AREASEL_WRITE_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode */
static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = {
(0x5E000000UL), /*!< CODE FLASH Page0 */
(0x5E001000UL), /*!< CODE FLASH Page1 */
(0x5E002000UL), /*!< CODE FLASH Page2 */
(0x5E003000UL), /*!< CODE FLASH Page3 */
(0x5E004000UL), /*!< CODE FLASH Page4 */
(0x5E005000UL), /*!< CODE FLASH Page5 */
(0x5E006000UL), /*!< CODE FLASH Page6 */
(0x5E007000UL), /*!< CODE FLASH Page7 */
(0x5E008000UL), /*!< CODE FLASH Page8 */
(0x5E009000UL), /*!< CODE FLASH Page9 */
(0x5E00A000UL), /*!< CODE FLASH Page10 */
(0x5E00B000UL), /*!< CODE FLASH Page11 */
(0x5E00C000UL), /*!< CODE FLASH Page12 */
(0x5E00D000UL), /*!< CODE FLASH Page13 */
(0x5E00E000UL), /*!< CODE FLASH Page14 */
(0x5E00F000UL), /*!< CODE FLASH Page15 */
(0x5E010000UL), /*!< CODE FLASH Page16 */
(0x5E011000UL), /*!< CODE FLASH Page17 */
(0x5E012000UL), /*!< CODE FLASH Page18 */
(0x5E013000UL), /*!< CODE FLASH Page19 */
(0x5E014000UL), /*!< CODE FLASH Page20 */
(0x5E015000UL), /*!< CODE FLASH Page21 */
(0x5E016000UL), /*!< CODE FLASH Page22 */
(0x5E017000UL), /*!< CODE FLASH Page23 */
(0x5E018000UL), /*!< CODE FLASH Page24 */
(0x5E019000UL), /*!< CODE FLASH Page25 */
(0x5E01A000UL), /*!< CODE FLASH Page26 */
(0x5E01B000UL), /*!< CODE FLASH Page27 */
(0x5E01C000UL), /*!< CODE FLASH Page28 */
(0x5E01D000UL), /*!< CODE FLASH Page29 */
(0x5E01E000UL), /*!< CODE FLASH Page30 */
(0x5E01F000UL) /*!< CODE FLASH Page31 */
};
/**
* @}
*/ /* End of group Flash_Userboot_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
* @{
*/
/**
* @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef
* @{
*/
/**
* @}
*/ /* End of group Flash_Userboot_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Member */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables
* @{
*/
/**
* @}
*/ /* End of group Flash_Userboot_Private_variables */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions
* @{
*/
__STATIC_INLINE TXZ_Result fc_enable_areasel(void);
__STATIC_INLINE TXZ_Result fc_disable_areasel(void);
static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size);
static TXZ_Result fc_verify_check(uint32_t* src_address, uint32_t* dst_address, uint32_t size);
static void fc_erase_command(uint32_t* flash_top_address, uint32_t* erase_top_address, fc_erase_kind_t kind);
/*--------------------------------------------------*/
/**
* @brief Enables the AREA0.
* @param -
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function write the FCAREASEL regiset.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
__STATIC_INLINE TXZ_Result fc_enable_areasel(void)
{
TXZ_Result retval = TXZ_ERROR;
/* Writes the FCKER register the KEYCODE. */
TSB_FC->KCR = FC_KCR_KEYCODE;
/* Selects the area0 */
{
uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0;
TSB_FC->AREASEL = reg | FC_AREASEL_AREA0;
}
/* Confirms the FCAREASEL register the SSF0 was set. */
while(1){
uint32_t i = TSB_FC->AREASEL;
if((i & FC_AREASEL_WRITE_MODE) == FC_AREASEL_WRITE_MODE){
retval = TXZ_SUCCESS;
break;
}
}
return(retval);
}
/*--------------------------------------------------*/
/**
* @brief Disables the AREA0.
* @param -
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function write the FCAREASEL regiset.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
__STATIC_INLINE TXZ_Result fc_disable_areasel(void)
{
TXZ_Result retval = TXZ_ERROR;
/* Writes the FCKER register the KEYCODE. */
TSB_FC->KCR = FC_KCR_KEYCODE;
/* Selects the area0 */
{
uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0;
TSB_FC->AREASEL = reg | FC_AREASEL_EXPECT_AREA0;
}
/* Confirms the SSF0 of the FCAREASEL register is not set. */
while(1){
uint32_t i = TSB_FC->AREASEL;
if((i & FC_AREASEL_WRITE_MODE) != FC_AREASEL_WRITE_MODE){
retval = TXZ_SUCCESS;
break;
}
}
return(retval);
}
/*--------------------------------------------------*/
/**
* @brief Writes data of the Flash ROM.
* @param uint32_t* : src_address
* @param uint32_t* : dst_address
* @param uint32_t : size
* @return -
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size)
{
TXZ_Result retval;
volatile uint32_t* addr1 = (uint32_t *) (FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR);
volatile uint32_t* addr2 = (uint32_t *) (FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR);
volatile uint32_t* addr3 = (uint32_t *) ((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP);
uint32_t* source = (uint32_t *) src_address;
/* Enables the AREA0. Write Mode. */
retval = fc_enable_areasel();
if(retval == TXZ_SUCCESS){
uint32_t i;
*addr1 = (0x000000AAUL); /* bus cycle 1 */
*addr2 = (0x00000055UL); /* bus cycle 2 */
*addr1 = (0x000000A0UL); /* bus cycle 3 */
for(i=(0UL); i<size; i+=(0x4UL)){
*addr3 = *source;
source++;
}
/* Confirmation of the works start of ROM. */
while(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
};
/* Waits for a finish of the works in the code Flash ROM. */
while(fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY){
};
}
/* Disables the AREA0. Read Mode. */
retval = fc_disable_areasel();
}
/*--------------------------------------------------*/
/**
* @brief Verifies data of the Flash ROM.
* @param uint32_t* : src_address
* @param uint32_t* : dst_address
* @param uint32_t : size
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static TXZ_Result fc_verify_check(uint32_t* src_address, uint32_t* dst_address, uint32_t size)
{
TXZ_Result retval = TXZ_ERROR;
int res = memcmp(src_address, dst_address, size);
if(res == 0){
retval = TXZ_SUCCESS;
}
return(retval);
}
/*--------------------------------------------------*/
/**
* @brief Auro page erase command of the flash ROM.
* @param uint32_t* flash_top_address : flash top address
* @param uint32_t* erase_top_address : erase top address
* @param fc_erase_kind_t kind : Chip, Area, Block, Page, etc.
* @return -
* @note This function erases specified place of the flash ROM.
*/
/*--------------------------------------------------*/
//static void fc_erase_pages_flash(uint32_t* top_address, uint32_t* erase_top_address)
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static void fc_erase_command(uint32_t* flash_top_address, uint32_t* erase_top_address, fc_erase_kind_t kind)
{
TXZ_Result retval;
volatile uint32_t *addr1 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC1_ADDR);
volatile uint32_t *addr2 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC2_ADDR);
volatile uint32_t *addr3 = (uint32_t *) erase_top_address;
/* Enables the AREA0. Write Mode. */
retval = fc_enable_areasel();
if(retval == TXZ_SUCCESS){
*addr1 = (0x000000AAUL);
*addr2 = (0x00000055UL);
*addr1 = (0x00000080UL);
*addr1 = (0x000000AAUL);
*addr2 = (0x00000055UL);
*addr3 = kind;
/* Confirmation of the works start of ROM. */
while(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
};
/* Waits for a finish of the works in the code Flash ROM. */
while(fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY){
};
}
/* Disables the AREA0. Read Mode. */
retval = fc_disable_areasel();
}
/*--------------------------------------------------*/
/**
* @brief Checks a blank of the Flash ROM every 4bytes.
* @param uint32_t* : addrress
* @param uint32_t : size
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
static TXZ_Result fc_blank_check(uint32_t* address, uint32_t size)
{
TXZ_Result retval = TXZ_SUCCESS;
uint32_t i;
for(i=0; i<(size/sizeof(uint32_t)); i++){
uint32_t* addr = &address[i];
if(*addr != FC_BRANK_VALUE){
retval = TXZ_ERROR;
break;
}
}
return (retval);
}
/**
* @}
*/ /* End of group Flash_Userboot_Private_fuctions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Userboot_Exported_functions Flash_Userboot Exported Functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Get the status of the flash auto operation.
* @param fc_sr0_t : status
* @return Result.
* @retval TXZ_BUSY : Busy.
* @retval TXZ_DONE : Done.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_WorkState fc_get_status(fc_sr0_t status)
{
TXZ_WorkState retval = TXZ_BUSY;
uint32_t work32;
/* Reads the FCSR0. Masks the other specfic status */
work32 = TSB_FC->SR0 & (uint32_t)status;
/* Confirms the specific status of the flash ROM */
if(work32 == (uint32_t)status){
retval = TXZ_DONE;
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Auto write command of the code flash ROM.
* @param uint32_t* : src_address
* @param uint32_t* : dst_address
* @param uint32_t : size
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function writes 16bytes data to the code Flash ROM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size)
{
TXZ_Result retval = TXZ_SUCCESS;
/* Checks the code Flash ROM status */
if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
uint32_t i;
/* Checks the code Flash ROM status */
for(i=0;i<size;i+=(uint32_t)(0x10UL)){
/* Writes 16bytes data. */
fc_write_command((uint32_t*)((uint32_t)src_address+i), (uint32_t*)((uint32_t)dst_address+i), (uint32_t)(0x10UL));
}
/* Verifies user data and data of the Flash ROM. */
retval = fc_verify_check(src_address, dst_address, size);
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Auro page erase command of the code flash ROM.
* @param first_page : The first page to erase
* @param num_of_pages : The number of pages to erase.
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
* This function erases specified page of the code Flash ROM and checks a blank.
*/
/*--------------------------------------------------*/
TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages)
{
TXZ_Result retval = TXZ_SUCCESS;
/* Checks the code Flash ROM status */
if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
/* Checks the number of maximum pages. */
if((first_page + num_of_pages) <= FC_MAX_PAGES){
uint8_t i;
for(i=0; i<num_of_pages ; i++){
/* Erases the specific page. */
fc_erase_command((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP,
(uint32_t*)fc_const_code_flash_address[first_page+i],
FC_ERASE_KIND_PAGE);
}
/* Checks a blank of the specific page. */
if(fc_blank_check((uint32_t*)fc_const_code_flash_address[first_page],
FC_PAGE_SIZE*(uint32_t)num_of_pages) == TXZ_ERROR){
retval = TXZ_ERROR;
}
}
else{
retval = TXZ_ERROR;
}
}
else {
retval = TXZ_ERROR;
}
return (retval);
}
/*--------------------------------------------------*/
/**
* @brief Checks a blank of the code Flash ROM of specified pages.
* @param first_page : The first page which checks a blank.
* @param last_page : The last page which checks a blank..
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t last_page)
{
TXZ_Result retval;
uint32_t* address = (uint32_t*)fc_const_code_flash_address[first_page];
uint32_t size = ((uint32_t)(last_page - first_page + 1) * (uint32_t)FC_PAGE_SIZE);
retval = fc_blank_check(address, size);
return (retval);
}
/*--------------------------------------------------*/
/*************** written by TSIP ******************/
/**
* @brief Erases the entire block of code Flash ROM of specified address.
* @param uint32_t *top_addr : top address of Flash ROM.
* @param uint32_t *blk_addr : start address of block to be erased.
* @return Result.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note It works in the inner RAM.
*/
/*--------------------------------------------------*/
#if defined ( __GNUC__ ) /* GCC Compiler */
__attribute__((section(".ram_func")))
#endif
#if defined ( __ICCARM__ ) // IAR Compiler
__ramfunc
#endif
TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr)
{
TXZ_Result retval = TXZ_SUCCESS;
/* Checks the code Flash ROM status */
if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
/* Erases the specific block. */
fc_erase_command((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, blk_addr, FC_ERASE_KIND_BLOCK);
/* Checks a blank of the specific block. */
if(fc_blank_check(blk_addr, (uint32_t)0x8000) == TXZ_ERROR){
retval = TXZ_ERROR;
} else{
// do nothing
}
}
else {
retval = TXZ_ERROR;
}
return (retval);
}
/**
* @}
*/ /* End of group Flash_Userboot_Exported_functions */
/**
* @}
*/ /* End of group Flash_Userboot */
/**
* @}
*/ /* End of group Example */
#ifdef __cplusplus
}
#endif /* __cplusplus */

132
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/tmpm3hq_fc.h Normal file
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@ -0,0 +1,132 @@
/**
*******************************************************************************
* @file tmpm3hq_fc.h
* @brief Flash_Userboot Sample Application.
* @version V1.0.0.0
* $date:: $
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* (C)Copyright TOSHIBA CORPORATION 2016 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __FC_H
#define __FC_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "txz_driver_def.h"
#if defined(__FC_H)
/** @addtogroup Periph driver
* @{
*/
/** @defgroup fc
* @brief fc
* @{
*/
/** @defgroup FlashApi_Exported_Types
* @{
*/
/**
* @enum fc_sr0_t
* @brief Enumerated type definition of the FCSR0 register.
*/
typedef enum {
FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */
} fc_sr0_t;
/*----------------------------------*/
/**
* @enum fc_erase_kind_t
* @brief FC Erase Flash Kind structure definenition.
*/
/*----------------------------------*/
typedef enum {
FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */
FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Page Erase */
} fc_erase_kind_t;
typedef enum {
FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */
FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */
FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */
FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */
FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */
FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */
FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */
FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */
FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */
FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */
FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */
FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */
FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */
FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */
FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */
FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */
FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */
FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */
FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */
FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */
FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */
FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */
FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */
FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */
FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */
FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */
FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */
FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */
FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */
FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */
FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */
FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */
} fc_code_flash_page_number_t;
/** @} */
/* End of group FlashApi_Exported_Types */
/** @defgroup FlashApi_Exported_Constants
* @{
*/
#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */
#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */
#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */
/** @} */
/* End of group FlashApi_Exported_Constants */
/** @weakgroup FlashApi_Exported_FunctionPrototypes
* @{
*/
TXZ_WorkState fc_get_status(fc_sr0_t status);
TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size);
TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages);
TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page);
/** @} */
/* End of group FlashApi_Exported_FunctionPrototypes */
/** @} */
/* End of group fc */
/** @} */
/* End of group Periph_driver */
#endif /* defined(__FC_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __FC_H */

228
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/rtc_api.c Normal file
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@ -0,0 +1,228 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#include "mbed_mktime.h"
#define RTC_24_HOUR_MODE ((uint8_t)0x01)
#define PAGER_PAGE_ONE ((uint8_t)0x01)
#define PAGER_PAGE_ZERO ((uint8_t)0xEE)
#define RTC_CLK_ENABLE ((uint8_t)0x08)
#define RTC_CLK_DISABLE ((uint8_t)0xE7)
#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20)
#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20)
#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000)
#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002)
#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000)
#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001)
#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001)
#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000))
#define ELOSC_CFG_CLOCK ((uint64_t)(32768))
#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro
#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro
static int rtc_inited = 0;
static int diff_year = 100; //our RTC register only support 2000~2099
static void external_losc_enable(void);
void rtc_init(void)
{
if (!rtc_inited) {
TSB_CG_FSYSENA_IPENA23 = 1; // Enable Sys Clock for RTC
external_losc_enable(); // Enable low-speed oscillator
TSB_RTC->PAGER = 0x00; // Disable clock and alarm
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter
}
TSB_RTC->RESTR = 0xE7;
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter
}
TSB_RTC->PAGER |= PAGER_PAGE_ONE;
TSB_RTC->YEARR = 0x03; // Set leap year state
TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode
TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode
TSB_RTC->YEARR = 0x01; // Set year value
TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value
TSB_RTC->DATER = (uint8_t)0x01; // Set date value
TSB_RTC->DAYR = (uint8_t)0x0; // Set day value
TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value
TSB_RTC->MINR = (uint8_t)0x02; // Set minute value
TSB_RTC->SECR = (uint8_t)0x22; // Set second value
TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock
rtc_inited = 1; // Enable RTC initialzed status
}
}
void rtc_free(void)
{
rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE
}
int rtc_isenabled(void)
{
return rtc_inited; // Return status of RTC peripheral driver
}
time_t rtc_read(void)
{
if (!rtc_inited) {
// Return invalid time for now!
return 0;
}
struct tm timeinfo;
uint8_t read_1 = 0U;
uint8_t read_2 = 0U;
timeinfo.tm_isdst = 0;//no summer time
TSB_RTC->PAGER &= PAGER_PAGE_ZERO;
read_1 = TSB_RTC->SECR; // Get sec value
timeinfo.tm_sec = HEX2DEC(read_1);
do { // Get minute value
read_1 = TSB_RTC->MINR;
read_2 = TSB_RTC->MINR;
} while (read_1 != read_2);
timeinfo.tm_min = HEX2DEC(read_1);
do { // Get hour value
read_1 = TSB_RTC->HOURR;
read_2 = TSB_RTC->HOURR;
} while (read_1 != read_2);
timeinfo.tm_hour = HEX2DEC(read_1);
do { // Get Month date value
read_1 = TSB_RTC->DATER;
read_2 = TSB_RTC->DATER;
} while (read_1 != read_2);
timeinfo.tm_mday = HEX2DEC(read_1);
do { // Get Month value
read_1 = TSB_RTC->MONTHR;
read_2 = TSB_RTC->MONTHR;
} while (read_1 != read_2);
timeinfo.tm_mon = HEX2DEC(read_1)-1;
do { // Get weekday value
read_1 = TSB_RTC->DAYR;
read_2 = TSB_RTC->DAYR;
} while (read_1 != read_2);
timeinfo.tm_wday = HEX2DEC(read_1);
do { // Get year value
read_1 = TSB_RTC->YEARR;
read_2 = TSB_RTC->YEARR;
} while (read_1 != read_2);
timeinfo.tm_year = (HEX2DEC(read_1)+ diff_year);
time_t t;
if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return 0;
}
return t;
}
void rtc_write(time_t t)
{
if (!rtc_inited) {
// Initialize the RTC as not yet initialized
rtc_init();
}
struct tm timeinfo;
if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return;
}
diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100);
TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock
// Check current year is leap year or not
if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) ||
(timeinfo.tm_year % 400) == 0) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year
TSB_RTC->YEARR = 0x00;
} else if ((timeinfo.tm_year % 4) == 1) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year
TSB_RTC->YEARR = 0x01;
} else if ((timeinfo.tm_year % 4) == 2) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year
TSB_RTC->YEARR = 0x02;
} else {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year
TSB_RTC->YEARR = 0x03;
}
TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0
TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value
// Set month value, tm_mon=0 means Jan while 1 is Jan
TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon+1));
TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value
TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value
TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value
TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value
TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value
TSB_RTC->RESTR |= RTCRESTR_RSTTMR_R_RUN;
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter, otherwise the 1st second will not be accurate
}
// Setting Wait
// When stop mode is selected, CaseA or CaseB is need.
// CaseA: Wait for RTC 1Hz interrupt.
// CaseB: Check the clock register setting.
{
uint8_t flag = 1;
time_t time_read = {0};
while(flag) {
time_read = rtc_read();
if( time_read == t) { // Wait for setting successfully
flag = 0;
}
}
}
TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock
}
static void external_losc_enable(void)
{
uint32_t work;
if( (TSB_RLM->LOSCCR & 0x01) == 0 ) { //external losc is not enabled.
uint64_t x = (uint64_t)(ELOSC_CFG_WARM_UP_TIME * ELOSC_CFG_CLOCK);
x = (uint64_t)(x / (uint64_t)(1000000));
work = (uint32_t)x;
work &= (uint32_t)(0xFFFFFFF0);
work <<= 8;
TSB_CG->WUPLCR = work;
TSB_RLM->LOSCCR = RLMLOSCCR_XTEN_RW_ENABLE;
work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK);
TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE);
while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) {
// No processing
}
}
}

43
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/serial_api.c
View File

@ -23,7 +23,7 @@
static const PinMap PinMap_UART_TX[] = { static const PinMap PinMap_UART_TX[] = {
{PA1, SERIAL_0, PIN_DATA(1, 1)}, {PA1, SERIAL_0, PIN_DATA(1, 1)},
{PJ1, SERIAL_1, PIN_DATA(1, 1)}, {PJ1, SERIAL_1, PIN_DATA(1, 1)},
{PB2, SERIAL_2, PIN_DATA(5, 1)}, {PB2, SERIAL_2, PIN_DATA(1, 1)},
{PA6, SERIAL_3, PIN_DATA(2, 1)}, {PA6, SERIAL_3, PIN_DATA(2, 1)},
{PV6, SERIAL_4, PIN_DATA(1, 1)}, {PV6, SERIAL_4, PIN_DATA(1, 1)},
{PN2, SERIAL_5, PIN_DATA(2, 1)}, {PN2, SERIAL_5, PIN_DATA(2, 1)},
@ -33,13 +33,33 @@ static const PinMap PinMap_UART_TX[] = {
static const PinMap PinMap_UART_RX[] = { static const PinMap PinMap_UART_RX[] = {
{PA2, SERIAL_0, PIN_DATA(1, 0)}, {PA2, SERIAL_0, PIN_DATA(1, 0)},
{PJ2, SERIAL_1, PIN_DATA(1, 0)}, {PJ2, SERIAL_1, PIN_DATA(1, 0)},
{PB3, SERIAL_2, PIN_DATA(5, 0)}, {PB3, SERIAL_2, PIN_DATA(1, 0)},
{PA7, SERIAL_3, PIN_DATA(2, 0)}, {PA7, SERIAL_3, PIN_DATA(2, 0)},
{PV7, SERIAL_4, PIN_DATA(1, 0)}, {PV7, SERIAL_4, PIN_DATA(1, 0)},
{PN3, SERIAL_5, PIN_DATA(2, 0)}, {PN3, SERIAL_5, PIN_DATA(2, 0)},
{NC, NC, 0} {NC, NC, 0}
}; };
#if DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{PM3, SERIAL_0, PIN_DATA(1, 0)},
{PJ3, SERIAL_1, PIN_DATA(1, 0)},
{PB4, SERIAL_2, PIN_DATA(1, 0)},
{PC5, SERIAL_4, PIN_DATA(1, 0)},
{PN0, SERIAL_5, PIN_DATA(2, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RTS[] = {
{PM4, SERIAL_0, PIN_DATA(1, 1)},
{PJ4, SERIAL_1, PIN_DATA(1, 1)},
{PB5, SERIAL_2, PIN_DATA(1, 1)},
{PC6, SERIAL_4, PIN_DATA(1, 1)},
{PN1, SERIAL_5, PIN_DATA(2, 1)},
{NC, NC, 0}
};
#endif
static uint32_t serial_irq_ids[UART_NUM] = {0}; static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler; static uart_irq_handler irq_handler;
int stdio_uart_inited = 0; int stdio_uart_inited = 0;
@ -63,6 +83,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
obj->UARTx = TSB_UART0; obj->UARTx = TSB_UART0;
TSB_CG_FSYSENB_IPENB05 = ENABLE; TSB_CG_FSYSENB_IPENB05 = ENABLE;
TSB_CG_FSYSENA_IPENA00 = ENABLE; TSB_CG_FSYSENA_IPENA00 = ENABLE;
TSB_CG_FSYSENA_IPENA11 = ENABLE;
break; break;
case SERIAL_1: case SERIAL_1:
obj->UARTx = TSB_UART1; obj->UARTx = TSB_UART1;
@ -83,6 +104,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
obj->UARTx = TSB_UART4; obj->UARTx = TSB_UART4;
TSB_CG_FSYSENB_IPENB09 = ENABLE; TSB_CG_FSYSENB_IPENB09 = ENABLE;
TSB_CG_FSYSENA_IPENA17 = ENABLE; TSB_CG_FSYSENA_IPENA17 = ENABLE;
TSB_CG_FSYSENA_IPENA02 = ENABLE;
break; break;
case SERIAL_5: case SERIAL_5:
obj->UARTx = TSB_UART5; obj->UARTx = TSB_UART5;
@ -362,6 +384,23 @@ void serial_break_clear(serial_t *obj)
obj->UARTx->TRANS &= ~(0x08); obj->UARTx->TRANS &= ~(0x08);
} }
#if DEVICE_SERIAL_FC
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT((int)uart_name != NC);
pinmap_pinout(rxflow, PinMap_UART_RTS);
pinmap_pinout(txflow, PinMap_UART_CTS);
pin_mode(txflow, PullUp);
pin_mode(rxflow, PullUp);
obj->UARTx->CR0 |= (3U << 9);
}
#endif
static void uart_swreset(TSB_UART_TypeDef *UARTx) static void uart_swreset(TSB_UART_TypeDef *UARTx)
{ {
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {

298
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/spi_api.c
View File

@ -13,11 +13,57 @@
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#include <stdbool.h>
#include "spi_api.h" #include "spi_api.h"
#include "mbed_error.h" #include "mbed_error.h"
#include "pinmap.h" #include "pinmap.h"
#include "gpio_include.h" #include "gpio_include.h"
#include "txz_tspi.h" #include "txz_tspi.h"
#define TIMEOUT 1000
#define INITIAL_SPI_FREQ 1000000
#if DEVICE_I2C_ASYNCH
#define SPI_S(obj) (struct spi_s *) (&((obj)->spi))
#else
#define SPI_S(obj) (struct spi_s *) (obj)
#endif
#if DEVICE_SPI_ASYNCH
static void spi_irq_handler(spi_t *obj);
static void disable_irq(uint32_t irqn);
static void clear_irq(uint32_t irqn);
enum {
SPI_TRANSFER_STATE_IDLE = 0U,
SPI_TRANSFER_STATE_BUSY
} SPI_TransferState;
typedef struct {
IRQn_Type Tx;
IRQn_Type Rx;
IRQn_Type Error;
} spi_irq_t;
static const spi_irq_t SPI_CH0_IRQN_TBL[1] = {
{ INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn }
};
static const spi_irq_t SPI_CH1_IRQN_TBL[1] = {
{ INTT1RX_IRQn, INTT1TX_IRQn, INTT1ERR_IRQn }
};
static const spi_irq_t SPI_CH2_IRQN_TBL[1] = {
{ INTT2RX_IRQn, INTT2TX_IRQn, INTT2ERR_IRQn }
};
static const spi_irq_t SPI_CH3_IRQN_TBL[1] = {
{ INTT3RX_IRQn, INTT3TX_IRQn, INTT3ERR_IRQn }
};
static const spi_irq_t SPI_CH4_IRQN_TBL[1] = {
{ INTT4RX_IRQn, INTT4TX_IRQn, INTT4ERR_IRQn }
};
#endif
static const PinMap PinMap_SPI_SCLK[] = { static const PinMap PinMap_SPI_SCLK[] = {
{PM0, SPI_0, PIN_DATA(3, 1)}, {PM0, SPI_0, PIN_DATA(3, 1)},
@ -54,8 +100,18 @@ static const PinMap PinMap_SPI_SSEL[] = {
{NC, NC, 0} {NC, NC, 0}
}; };
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) static const PinMap PinMap_SPISLAVE_SCLK[] = {
{PM0, SPI_0, PIN_DATA(3, 0)},
{PB2, SPI_1, PIN_DATA(3, 0)},
{PT2, SPI_2, PIN_DATA(1, 0)},
{PP5, SPI_3, PIN_DATA(1, 0)},
{PH4, SPI_4, PIN_DATA(1, 0)},
{NC, NC, 0}
};
void spi_init(spi_t *t_obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{ {
struct spi_s *obj = SPI_S(t_obj);
// Check pin parameters // Check pin parameters
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
@ -74,26 +130,41 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->p_obj.p_instance = TSB_TSPI0; obj->p_obj.p_instance = TSB_TSPI0;
TSB_CG_FSYSENA_IPENA11 = ENABLE; TSB_CG_FSYSENA_IPENA11 = ENABLE;
TSB_CG_FSYSENB_IPENB00 = ENABLE; TSB_CG_FSYSENB_IPENB00 = ENABLE;
#if DEVICE_SPI_ASYNCH
obj->irqn = (uint32_t)&SPI_CH0_IRQN_TBL;
#endif
break; break;
case SPI_1: case SPI_1:
obj->p_obj.p_instance = TSB_TSPI1; obj->p_obj.p_instance = TSB_TSPI1;
TSB_CG_FSYSENA_IPENA01 = ENABLE; TSB_CG_FSYSENA_IPENA01 = ENABLE;
TSB_CG_FSYSENB_IPENB01 = ENABLE; TSB_CG_FSYSENB_IPENB01 = ENABLE;
#if DEVICE_SPI_ASYNCH
obj->irqn = (uint32_t)&SPI_CH1_IRQN_TBL;
#endif
break; break;
case SPI_2: case SPI_2:
obj->p_obj.p_instance = TSB_TSPI2; obj->p_obj.p_instance = TSB_TSPI2;
TSB_CG_FSYSENA_IPENA15 = ENABLE; TSB_CG_FSYSENA_IPENA15 = ENABLE;
TSB_CG_FSYSENB_IPENB02 = ENABLE; TSB_CG_FSYSENB_IPENB02 = ENABLE;
#if DEVICE_SPI_ASYNCH
obj->irqn = (uint32_t)&SPI_CH2_IRQN_TBL;
#endif
break; break;
case SPI_3: case SPI_3:
obj->p_obj.p_instance = TSB_TSPI3; obj->p_obj.p_instance = TSB_TSPI3;
TSB_CG_FSYSENA_IPENA13 = ENABLE; TSB_CG_FSYSENA_IPENA13 = ENABLE;
TSB_CG_FSYSENB_IPENB03 = ENABLE; TSB_CG_FSYSENB_IPENB03 = ENABLE;
#if DEVICE_SPI_ASYNCH
obj->irqn = (uint32_t)&SPI_CH3_IRQN_TBL;
#endif
break; break;
case SPI_4: case SPI_4:
obj->p_obj.p_instance = TSB_TSPI4; obj->p_obj.p_instance = TSB_TSPI4;
TSB_CG_FSYSENA_IPENA07 = ENABLE; TSB_CG_FSYSENA_IPENA07 = ENABLE;
TSB_CG_FSYSENB_IPENB04 = ENABLE; TSB_CG_FSYSENB_IPENB04 = ENABLE;
#if DEVICE_SPI_ASYNCH
obj->irqn = (uint32_t)&SPI_CH4_IRQN_TBL;
#endif
break; break;
default: default:
error("Cannot found SPI module corresponding with input pins."); error("Cannot found SPI module corresponding with input pins.");
@ -104,6 +175,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO); pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK); pinmap_pinout(sclk, PinMap_SPI_SCLK);
obj->Slave_SCK = sclk;
if (ssel != NC) { if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL); pinmap_pinout(ssel, PinMap_SPI_SSEL);
@ -138,7 +210,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear
//baudrate settings //baudrate settings
spi_frequency(obj, (int)INITIAL_SPI_FREQ); spi_frequency(t_obj, (int)INITIAL_SPI_FREQ);
//Format Control 0 settings //Format Control 0 settings
obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first
@ -166,14 +238,16 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
tspi_init(&obj->p_obj); tspi_init(&obj->p_obj);
} }
void spi_free(spi_t *obj) void spi_free(spi_t *t_obj)
{ {
struct spi_s *obj = SPI_S(t_obj);
tspi_deinit(&obj->p_obj); tspi_deinit(&obj->p_obj);
obj->module = (SPIName)NC; obj->module = (SPIName)NC;
} }
void spi_format(spi_t *obj, int bits, int mode, int slave) void spi_format(spi_t *t_obj, int bits, int mode, int slave)
{ {
struct spi_s *obj = SPI_S(t_obj);
MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode
MBED_ASSERT((bits >= 8) && (bits <= 32)); MBED_ASSERT((bits >= 8) && (bits <= 32));
@ -192,11 +266,16 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
} }
if(slave) {
pinmap_pinout(obj->Slave_SCK, PinMap_SPISLAVE_SCLK);
obj->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation
}
tspi_init(&obj->p_obj); tspi_init(&obj->p_obj);
} }
void spi_frequency(spi_t *obj, int hz) void spi_frequency(spi_t *t_obj, int hz)
{ {
struct spi_s *obj = SPI_S(t_obj);
uint8_t brs = 0; uint8_t brs = 0;
uint8_t brck = 0; uint8_t brck = 0;
uint16_t prsck = 1; uint16_t prsck = 1;
@ -228,8 +307,9 @@ void spi_frequency(spi_t *obj, int hz)
tspi_init(&obj->p_obj); tspi_init(&obj->p_obj);
} }
int spi_master_write(spi_t *obj, int value) int spi_master_write(spi_t *t_obj, int value)
{ {
struct spi_s *obj = SPI_S(t_obj);
uint8_t ret_value = 0; uint8_t ret_value = 0;
tspi_transmit_t send_obj; tspi_transmit_t send_obj;
@ -264,8 +344,9 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
return total; return total;
} }
int spi_busy(spi_t *obj) int spi_busy(spi_t *t_obj)
{ {
struct spi_s *obj = SPI_S(t_obj);
int ret = 1; int ret = 1;
uint32_t status = 0; uint32_t status = 0;
@ -278,8 +359,45 @@ int spi_busy(spi_t *obj)
return ret; return ret;
} }
uint8_t spi_get_module(spi_t *obj) int spi_slave_receive(spi_t *t_obj)
{ {
struct spi_s *obj = SPI_S(t_obj);
int ret = 1;
uint32_t status;
tspi_get_status(&obj->p_obj, &status);
if((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) {
ret = 0;
}
return ret;
}
int spi_slave_read(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
uint8_t ret_value = 0;
ret_value = obj->p_obj.p_instance->DR & 0xFF;
// Receive Complete Flag is clear.
obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR;
obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
return ret_value;
}
void spi_slave_write(spi_t *t_obj, int value)
{
struct spi_s *obj = SPI_S(t_obj);
// Enable TSPI Transmission Control.
obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
obj->p_obj.p_instance->DR = value & 0xFF;
}
uint8_t spi_get_module(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
return (uint8_t)(obj->module); return (uint8_t)(obj->module);
} }
@ -322,3 +440,167 @@ const PinMap *spi_slave_cs_pinmap()
{ {
return PinMap_SPI_SSEL; return PinMap_SPI_SSEL;
} }
#if DEVICE_SPI_ASYNCH
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width,
uint32_t handler, uint32_t event, DMAUsage hint)
{
struct spi_s *spiobj = SPI_S(obj);
spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn;
bool use_tx = (tx != NULL && tx_length > 0);
bool use_rx = (rx != NULL && rx_length > 0);
// don't do anything, if the buffers aren't valid
if (!use_tx && !use_rx) {
return;
}
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
obj->tx_buff.buffer = (void *)tx;
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
obj->rx_buff.buffer = (void *)rx;
obj->rx_buff.length = rx_length;
obj->rx_buff.pos = 0;
spiobj->event = 0;
spiobj->state = SPI_TRANSFER_STATE_IDLE;
NVIC_SetVector(p_irqn->Error, (uint32_t)handler);
NVIC_SetVector(p_irqn->Tx, (uint32_t)handler);
NVIC_SetVector(p_irqn->Rx, (uint32_t)handler);
// Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt
spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE);
if (use_tx && use_rx) {
spiobj->max_size = tx_length < rx_length ? rx_length:tx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF;
} else if(use_tx) {
spiobj->max_size = tx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF;
} else if(use_rx) {
spiobj->max_size = rx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = 0xFF;
}
spiobj->state = SPI_TRANSFER_STATE_BUSY;
NVIC_EnableIRQ(p_irqn->Error);
NVIC_EnableIRQ(p_irqn->Tx);
NVIC_EnableIRQ(p_irqn->Rx);
}
uint32_t spi_irq_handler_asynch(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
spi_irq_handler(obj);
return ((spiobj->event & SPI_EVENT_ALL)| SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ;
}
uint8_t spi_active(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
uint8_t ret_val = 0;
if (spiobj->state != SPI_TRANSFER_STATE_IDLE) {
ret_val = 1;
}
return ret_val;
}
void spi_abort_asynch(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
disable_irq(spiobj->irqn);
clear_irq(spiobj->irqn);
tspi_init(&spiobj->p_obj);
}
static void spi_irq_handler(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
// Check for revceive complete flag.
if((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) &&
(spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) {
// Check receiver FIFO level
uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF;
while((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) {
((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF;
rlvl--;
}
if(obj->rx_buff.pos == spiobj->max_size) {
spiobj->state = SPI_TRANSFER_STATE_IDLE;
}
// Clear rx buffer
spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE;
}
// Check for transmit completion flag
if(spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) {
obj->tx_buff.pos++;
spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR;
if(obj->tx_buff.pos == (spiobj->max_size)) {
spiobj->state = SPI_TRANSFER_STATE_IDLE;
}
if((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) {
spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF);
} else if (obj->tx_buff.pos < spiobj->max_size) {
spiobj->p_obj.p_instance->DR = 0xFF;
}
}
// Check for error flag
if(spiobj->p_obj.p_instance->ERR) {
spiobj->event = SPI_EVENT_ERROR;
spiobj->state = SPI_TRANSFER_STATE_IDLE;
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
return;
}
if(spiobj->state == SPI_TRANSFER_STATE_IDLE) {
spiobj->event = SPI_EVENT_COMPLETE;
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
}
}
static void disable_irq(uint32_t irqn)
{
spi_irq_t *p_irqn = (spi_irq_t *)irqn;
NVIC_DisableIRQ(p_irqn->Tx);
NVIC_DisableIRQ(p_irqn->Rx);
NVIC_DisableIRQ(p_irqn->Error);
}
static void clear_irq(uint32_t irqn)
{
spi_irq_t *p_irqn = (spi_irq_t *)irqn;
NVIC_ClearPendingIRQ(p_irqn->Tx);
NVIC_ClearPendingIRQ(p_irqn->Rx);
NVIC_ClearPendingIRQ(p_irqn->Error);
}
#endif

7
targets/targets.json
View File

@ -8583,18 +8583,25 @@
"USTICKER", "USTICKER",
"ANALOGIN", "ANALOGIN",
"ANALOGOUT", "ANALOGOUT",
"CRC",
"INTERRUPTIN", "INTERRUPTIN",
"PORTIN", "PORTIN",
"PORTINOUT", "PORTINOUT",
"PORTOUT", "PORTOUT",
"PWMOUT", "PWMOUT",
"RESET_REASON", "RESET_REASON",
"RTC",
"SERIAL", "SERIAL",
"SERIAL_FC",
"SLEEP", "SLEEP",
"SPI", "SPI",
"SPI_ASYNCH",
"SPISLAVE",
"I2C", "I2C",
"I2C_ASYNCH",
"I2CSLAVE", "I2CSLAVE",
"STDIO_MESSAGES", "STDIO_MESSAGES",
"FLASH",
"MPU" "MPU"
], ],
"device_name": "TMPM3HQFDFG", "device_name": "TMPM3HQFDFG",