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Merge commit 'ce830296d0297a8da543c24134bf859710fd7698' into epr_integration 

Merge the EPR tag and the nordic branch together.
pull/2234/head
Vincent Coubard 2016-07-13 12:06:02 +01:00
parent eaa9d3ba4f ce830296d0
commit 9745eff74c
687 changed files with 266307 additions and 109723 deletions
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4
.travis.yml
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@ -1,7 +1,9 @@
python:
- "2.7"
script: "python tools/build_travis.py"
script:
- PYTHONPATH=. python tools/test/config_test/config_test.py
- python tools/build_travis.py
before_install:
- sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded
- sudo apt-get update -qq

2
README.md
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@ -67,7 +67,7 @@ STMicroelectronics:
* [Nucleo-F302R8](https://developer.mbed.org/platforms/ST-Nucleo-F302R8/) (Cortex-M4F)
* [Nucleo-F334R8](https://developer.mbed.org/platforms/ST-Nucleo-F334R8/) (Cortex-M4F)
* [Nucleo-F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4F)
* Nucleo-F410RB (Cortex-M4F)
* [Nucleo-F410RB](https://developper.mbed.org/platforms/ST-Nucleo-F410RB/) (Cortex-M4F)
* [Nucleo-F411RE](https://developer.mbed.org/platforms/ST-Nucleo-F411RE/) (Cortex-M4F)
* [Nucleo-L476RG](https://developer.mbed.org/platforms/ST-Nucleo-L476RG/) (Cortex-M4F)
* STM32F4XX (Cortex-M4F)

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docs/config_system.md Normal file
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# About the configuration system
The mbed configuration system can be used to customize the compile time configuration of various mbed components (targets, libraries and applications). Each such component can define a number of *configuration parameters*. The values of these configuration parameters can then be *overridden* in various ways. Configuration is defined using [JSON](http://www.json.org/). Some examples of configuration parameters:
- the sampling period for a data acquisition application.
- the default stack size for a newly created OS thread.
- the receive buffer size of a serial communication library.
- the flash and RAM memory size of a mbed target.
The configuration system gathers and interprets all the configuration defined in the source tree. The output of the configuration system is a list of macros that are automatically defined when compiling the code.
# Defining configuration parameters
The configuration system understands configuration data defined in targets, libraries and applications. While there are some slight differences in the way the configuration system works in these cases, the configuration parameters are always defined in a JSON object called "config". An example is given below:
```
{
"config": {
"param1": {
"help": "The first configuration parameter",
"macro_name": "CUSTOM_MACRO_NAME",
"value": 0
},
"param2": {
"help": "The second configuration parameter",
"required": true
},
"param3": 10
}
}
```
The JSON fragment above defines 3 configuration parameters named `param1`, `param2` and `param3`. There are two ways to define a configuration parameter:
- the short way: by name and value. `param3` above is an example of a short definition for a parameter named `param3` with value `10`.
- the long way: by name and description (another JSON object), like `param1` and `param2` above. The JSON description object can have the following keys:
- `help`: an optional help message that describes the purpose of the parameter.
- `value`: an optional field that defines the value of the parameter.
- `required`: an optional key that specifies if the parameter **must** be given a value before compiling the code (`false` by default). It's not possible to compile a source tree with one or more required parameters that don't have a value. Generally, it makes sense to define a required parameter only when it doesn't have a `value` key.
- `macro_name`: an optional name for the macro defined at compile time for this configuration parameter. The configuration system will automatically figure out the corresponding macro name for a configuration parameter, but the user can override this automatically computed name by specifying `macro_name`.
Note that the name of a parameter in `config` can't contain a dot (`.`) character.
The configuration system automatically appends an *implicit prefix* to the name of each parameter, so you don't have to worry about a name clash if you define a parameter with the same name in a library and a target, for example. The implicit prefix is:
- **target.** if the parameter is defined in a target.
- **app.** if the parameter is defined in the application.
- the name of the library followed by a dot (.) if the parameter is defined in a library.
# Configuration data in libraries
Each mbed library can have an optional `mbed_lib.json` file located in the root folder of the library that defines its configuration. For a library called `mylib`, the configuration file could look like this:
```
{
"name": "mylib",
"config": {
"buffer_size": 1024,
"timer_period": {
"help": "The timer period (in us)",
"macro_name": "INTERNAL_GPTMR_PERIOD",
"required": true
},
"queue_size": {
"help": "Size of event queue (entries)",
"value": 10
}
},
"macros": ["MYMOD_MACRO1", "MYMOD_MACRO2=\"TEST\""],
"target_overrides": {
"K64F": {
"timer_period": 100,
"queue_size": 40
},
"NXP": {
"queue_size": 20,
"buffer_size": 128
}
}
}
```
In this JSON file:
- `name` is the name of the library. **This is a required field.**
- `config` defines the configuration parameters of the library, as explained [here](#defining-configuration-parameters).
- `macros` is a list of extra macros that will be defined when compiling a project that includes this library. A macro can be defined without a value (like `MYMOD_MACRO1` above) or with a value (like `MYMOD_MACRO2` above).
- `target_overrides` is a dictionary with target-specific values for the configuration parameters.
`target_overrides` is used to override the values of the parameters depending on the current compilation target. The keys in `target_overrides` are matched against toolchain *labels* (a description of mbed targets can be found [here](mbed_targets.md)). If a key inside `target_overrides` matches one of the target labels, the parameter values are changed according to the value of the key. In the example above:
- `config` is always processed first, independent of the target. `config` might define values for some of the parameters. In this case, `buffer_size` will be set to 1024, `queue_size` will be set to 10 and `timer_period` will not have a value.
- if the library is compiled for the `K64F` target, `timer_period` will be set to 100 and `queue_size` will be set to 40, since they are overridden by the `K64F` key in `target_overrides`. `buffer_size` will be set to 1024, as defined in `config`.
- assuming that `NXP` is a label defined by **all** NXP based targets, if the library is compiled for **any** `NXP` target (like `LPC1768` or `LPC11U24`), `buffer_size` will be set to 128 and `queue_size` will be set to 20, while `timer_period` will not have a value (since it doesn't get one neither in `config`, nor in the `NXP` override).
- the keys in `target_overrides` are processed in order: if a hypothetical target defines both `K64F` and `NXP` as labels, `timer_period` will be set to 100, `queue_size` will be set to 20 and `buffer_size` will be set to 128.
- if the library is compiled for a target that doesn't have `K64F` or `NXP` as labels, the values of the parameters will be the ones set in `config`.
Except `name`, all the above keys in the JSON file are optional, but if `target_overrides` is defined, `config` must also be defined.
As explained [here](#defining-configuration-parameters), the parameters have an implicit `mylib.` prefix. Outside `mylib`, `buffer_size` is accessible using the name `mylib.buffer_size`. An application will be able to override the value of this parameter, as described in [this section](#configuration-data-in-applications).
If the source tree has code for more than one library, each library needs its own `mbed_lib.json` file in its root folder.
# Configuration data in targets
Like libraries, targets can define their own configuration data. Additionally, tables can override the configuration of the target(s) they inherit from (for more details about how do define a target and target inheritance, check [this link](mbed_targets.md)). Target configuration data is defined in `targets.json` using `config`, as described [here](#defining-configuration-parameters). An example for a hypothetical `Base` target is given below:
```
"Base": {
"core": "Cortex-M0",
"extra_labels": ["BASE_LABEL"],
"config": {
"serial_console_speed": {
"help": "Baud rate of the serial console",
"value": 115200,
"macro_name": "MBED_SERIAL_UART_SPEED"
},
"stack_size": {
"help": "Initial stack size of the application",
"value": 128
}
}
}
```
Similar to libraries, the target defined parameters have an implicit prefix. For a target, the prefix is always called `target` (no matter what the actual target name is), so the above configuration parameters will be accessible outside the definition in `Base` (and any other target) as `target.serial_console_speed` and `target.stack_size`.
Targets can inherit from other targets, and their configuration data is also inherited. A target that inherits from one or more other targets can add new parameters in its own `config` section and can also override the configuration parameters defined by its parent(s) in a `overrides` section. For example:
```
"Derived": {
"inherits": ["Base"],
"extra_labels_add": ["NXP"],
"config": {
"my_own_config": {
"help": "My very own configuration parameter",
"value": 0
}
},
"overrides": {
"stack_size": 256
}
}
```
`Derived` above defines its own configuration parameter called `my_own_config` and inherits the configuration parameters from `Base`, so its configuration parameters are `serial_console_speed`, `stack_size` and `my_own_config`. It also overrides the value of the `stack_size` parameter defined in `Base`. This means that:
- when compiling for `Base`, the target will define two configuration parameters: `serial_console_speed` with the value 115200 and `stack_size` with the value 128.
- when compiling for `Derived`, the target will define three configuration parameters: `serial_console_speed` with the value 115200, `stack_size` with the value 256 and `my_own_config` with the value 0.
It is an error for a derived target to re-define a configuration parameter already defined by its parent(s) in its `config` section. It is also an error for a derived target to override a configuration parameter that was not defined by its parent(s) in its `overrides` section.
# Configuration data in applications
Like the configuration for targets and libraries, application configuration is optional; if it exists, it must be defined in a `mbed_app.json` file. Unlike library configuration, there can be a single `mbed_app.json` file in the source tree.
There are quite a few similarities between configuration data in applications and libraries:
- applications define their configuration parameters in the `config` section of `mbed_app.json`, as explained [here](#defining-configuration-parameters).
- applications can specify target-dependent values in their `target_overrides` section, as described in the [library configuration paragraph][#configuration-data-in-libraries) (but see below for differences).
- applications can define macros that will be define at compile time by declaring them in `macros`.
There are also a few differences:
- applications **can't** have a `name` key in `mbed_app.json`. The prefix for the configuration parameters defined in an application is always `app.`.
- applications can also override configuration of libraries and targets in addition to its own configuration in its `target_overrides` section.
The last point above is important. The application can freely override the configuration of any of the libraries it depends on, as well as the configuration data in targets, so it has complete control over the configuration of the whole build. For an application called myapp that depends on mylib above, the configuration can look like this:
```
{
"config": {
"welcome_string": {
"help": "The string printed on the display on start-up",
"value": "\"Hello!\""
}
},
"target_overrides": {
"*": {
"target.serial_console_speed": 2400,
"mylib.timer_period": 100
},
"Base": {
"target.serial_console_speed": 9600
}
}
}
```
`target_overrides` works a lot like it does in libraries, but there are a few differences:
- since the application can override any configuration parameter, it must specify them using their prefix (like `mylib.timer_period`). If an overridden parameter doesn't have a prefix, it is assumed that it is one of the parameters defined by the application in its own `config` section.
- the `*` key in `target_overrides` will match *any* target. It is possible to use the `*` key in a library's `target_overrides` too, but it'd make little sense to do so, since it will always override the values defined in the library's `config` section. In an application it might make sense to use the `*` key, since it can be used to override the configuration defined by the target or the dependent libraries, no matter which target is used for building.
Other than this, `target_overrides` works exactly like it does for libraries. Keys in `target_overrides` are still processed in the order they are defined, so for the example above, the `*` override is always processed first (since it matches all targets) and then `Base` is only processed for the `Base` target.
`myapp` above defines its own configuration parameter (`welcome_string`) and overrides the configuration in both the target (`target.serial_console_speed`) and its `mylib` dependency (`mylib.timer_period`):
- when compiling for `Base`, `app.welcome_string` will be set to `"Hello!"`, `target.serial_console_speed` will be set to 9600 (from the `Base` override) and `mylib.timer_period` will be set to 100 (from the `*` override).
- when compiling for `Derived`, `app.welcome_string` will be set to `"Hello!"`, `target.serial_console_speed` will be set to 2400 (from the `*` override) and `mylib.timer_period` will be set to 100 (also from the `*` override).
It is an error for the application configuration to override configuration parameters that were not defined.
## Custom targets
Application configuration can optionally define application-specific targets. These are mbed targets that are needed just to compile this specific application, so it doesn't make sense to add them to the list of official mbed targets; on the contrary, since they're part of `mbed_app.json`, they're versioned together with the application and only known by the application. Application-specific targets are defined with the key `custom_targets` in the `mbed_app.json` file and have the same syntax as a regular target definition, for example:
```
{
"custom_targets": {
"k64f_myapp": {
"inherits": ["K64F"],
"extra_labels_add": ["CUSTOM_K64F_LIB"]
}
}
}
```
This will define a new target named `k64f_myapp` that inherits from the `K64F` mbed target, but with an extra label defined, which will change the way the build system looks for sources in the tree.
# Configuration data precedence
The order in which the various bits of configurations are considered is this:
- the configuration defined by an inherited target overrides the configuration defined by its parent(s), as described [above](#configuration-data-in-targets).
- the configuration of the top level application overrides the configuration defined by the target and any of the libraries on which it depends.
For `myapp` above:
- the value of `target.serial_console_speed` will be 9600 when compiling for `Base` because of the `Base` override in myapp's `target_overrides`.
- the value of `target.serial_console_speed` will be 2400 when compiling for any other target because of the `*` override in myapp's `target_overrides`.
- the value of `target.stack_size` will be 256 when compiling for `Derived` and 128 when compiling for `Base` or any other target that derives from `Base` (assuming of course that `Derived` is the only target that redefines `stack_size`).
- the value of `mylib.timer_period` will be 100, since that's overridden by the application and thus takes precedence over the values defined in `mylib`.
- when compiling for `Base`, the values of `mylib.buffer_size` and `mylib.queue_size` will be 1024 and 10 respectively, as defined in the `config` section of `mylib`.
- when compiling for `Derived`, the values of `mylib.buffer_size `and `mylib.queue_size` will be 128 and 20 respectively, since `Derived` defines the `NXP` label and `mylib` defines a specific configuration for this label. Also, since `Derived` has its own `my_own_config` configuration parameter, `target.my_own_config` will also be defined in this case.
# Using configuration data in the code
When compiling, the configuration system will automatically generate macro definitions for the configuration parameters and all the macros defined in libraries and the application in their `macros` keys. These definitions will be appended to the compiler's command line. When compiling `myapp` for target `Base`, the following extra macros will be generated (not necessarily in this order):
```
-DMBED_CONF_MYAPP_WELCOME_STRING="Hello!"
-DMBED_SERIAL_UART_SPEED=9600
-DMBED_CONF_TARGET_STACK_SIZE=128
-DINTERNAL_GPTMR_PERIOD=100
-DMBED_CONF_MYLIB_BUFFER_SIZE=1024
-DMBED_CONF_MYLIB_QUEUE_SIZE=10
-DMYMOD_MACRO1
-DMYMOD_MACRO2="TEST"
```
When compiling for `Derived`, the following extra macros will be generated:
```
-DMBED_CONF_MYAPP_WELCOME_STRING="Hello!"
-DMBED_SERIAL_UART_SPEED=2400
-DMBED_CONF_TARGET_STACK_SIZE=256
-DMBED_CONF_TARGET_MY_OWN_CONFIG=0
-DINTERNAL_GPTMR_PERIOD=100
-DMBED_CONF_MYLIB_BUFFER_SIZE=128
-DMBED_CONF_MYLIB_QUEUE_SIZE=20
-DMYMOD_MACRO1
-DMYMOD_MACRO2="TEST"
```
Note that a macro definition will *not* be generated for a parameter that doesn't have a value.
The names of the macros for the configuration parameter (unless explicitly specified by `macro_name`) are prefixed by **MBED_CONF_**, followed by the full (prefixed) name of the parameter, capitalized and converted to a valid C macro name (if needed).

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# memap - Static Memory Map Analysis
## Introduction
*memap* is a simple utility that displays static memory information required by [mbed](https://github.com/mbedmicro/mbed) applications. This information is produced by analysing the memory map file previously generated by your toolchain.
**Note**: this tool shows static RAM usage and the total size of allocated heap and stack space defined at compile time, not the actual heap and stack usage (which may be different depending on your application).
## Table of contents
1. [Using memap](#using-memap)
1. [Information on memory sections](#info-mem-sections)
1. [Current support](#current-support)
1. [Known problems](#known-problems)
## Using memap
*memap* is automatically invoked after an mbed build finishes successfully. It's also possible to manually run the program with different command line options, for example:
```
$> python memap.py
usage: memap.py [-h] -t TOOLCHAIN [-o OUTPUT] [-e EXPORT] [-v] file
Memory Map File Analyser for ARM mbed version 0.3.11
positional arguments:
file memory map file
optional arguments:
-h, --help show this help message and exit
-t TOOLCHAIN, --toolchain TOOLCHAIN
select a toolchain used to build the memory map file
(ARM, GCC_ARM, IAR)
-o OUTPUT, --output OUTPUT
output file name
-e EXPORT, --export EXPORT
export format (examples: 'json', 'csv-ci', 'table':
default)
-v, --version show program's version number and exit
```
Result example:
```
$> python memap.py GCC_ARM\myprog3.map -t GCC_ARM
+----------------------------+-------+-------+------+
| Module | .text | .data | .bss |
+----------------------------+-------+-------+------+
| Fill | 170 | 0 | 2294 |
| Misc | 36282 | 2220 | 2152 |
| core/hal | 15396 | 16 | 568 |
| core/rtos | 6751 | 24 | 2662 |
| features/FEATURE_IPV4 | 96 | 0 | 48 |
| frameworks/greentea-client | 912 | 28 | 44 |
| frameworks/utest | 3079 | 0 | 732 |
| Subtotals | 62686 | 2288 | 8500 |
+----------------------------+-------+-------+------+
Allocated Heap: 65540 bytes
Allocated Stack: 32768 bytes
Total Static RAM memory (data + bss): 10788 bytes
Total RAM memory (data + bss + heap + stack): 109096 bytes
Total Flash memory (text + data + misc): 66014 bytes
```
## Information on memory sections
The table above showed multiple memory sections.
- ``.text``: is where the code application and constants are located in Flash.
- ``.data``: non-zero initialized variables; allocated in both RAM and Flash memory (variables are copied from Flash to RAM at run time)
- ``.bss``: uninitialized data allocated in RAM, or variables initialized to zero.
- ``Heap``: dynamic allocations in the Heap area in RAM (for example, used by ``malloc``). The maximum size value may be defined at build time.
- ``Stack``: dynamic allocations in the Stack area in RAM (for example, used to store local data, temporary data when branching to a subroutine or context switch information). The maximum size value may be defined at build time.
There are other entries that require a bit of clarification:
- Fill: represents the bytes in multiple sections (RAM and Flash) that the toolchain has filled with zeros because it requires subsequent data or code to be aligned appropriately in memory.
- Misc: usually represents helper libraries introduced by the toolchain (like ``libc``), but can also represent modules that are not part of mbed.
## Current support
*memap* has been tested on Windows 7, Linux and Mac OS X and works with memory map files are generated by the GCC_ARM, ARM (ARM Compiler 5) and IAR toochains.
## Known issues and new features
This utility is considered 'alpha' quality at the moment. The information generated by this utility may not be fully accurate and may vary from one toolchain to another.
If you are experiencing problems, or would like additional features, please raise a ticket on [GitHub](https://github.com/mbedmicro/mbed/issues) and use ```[memap] ``` in the title.

12
features/FEATURE_UVISOR/AUTHORS.txt
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@ -1,12 +1,12 @@
519 Milosch Meriac
420 Alessandro Angelino
16 Niklas Hauser
15 Jaeden Amero
512 Milosch Meriac
434 Alessandro Angelino
28 Niklas Hauser
22 Jaeden Amero
3 Hugo Vincent
3 JaredCJR
3 Jim Huang
2 tonyyanxuan
1 Aksel Skauge Mellbye
1 Irit Arkin
1 Nathan Chong
1 Irit Arkin
1 ccli8
1 Aksel Skauge Mellbye

2
features/FEATURE_UVISOR/VERSION.txt
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@ -1 +1 @@
v0.9.14-alpha
v0.9.21-alpha

3
features/FEATURE_UVISOR/importer/Makefile
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@ -33,7 +33,7 @@ TARGET_LIB_INC:=$(TARGET_PREFIX)includes/uvisor-lib
# uVisor source directory - hidden from mbed via TARGET_IGNORE
UVISOR_GIT_URL:=https://github.com/ARMmbed/uvisor
UVISOR_GIT_BRANCH:=dev
UVISOR_GIT_BRANCH:=unstable
UVISOR_DIR:=TARGET_IGNORE/uvisor
UVISOR_API:=$(UVISOR_DIR)/api
UVISOR_GIT_CFG=$(UVISOR_DIR)/.git/config
@ -72,6 +72,7 @@ rsync:
rm -rf $(TARGET_LIB_SRC)
mkdir -p $(TARGET_LIB_SRC)
cp $(UVISOR_DIR)/core/system/src/page_allocator.c $(TARGET_LIB_SRC)/page_allocator.c_inc
cp $(UVISOR_DIR)/core/system/inc/page_allocator_config.h $(TARGET_LIB_SRC)/page_allocator_config.h
rsync -a --delete $(UVISOR_API)/rtx/src/ $(TARGET_LIB_SRC)/rtx
#
# Copying licenses

9
features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h
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@ -45,6 +45,7 @@ UVISOR_EXTERN const uint32_t __uvisor_mode;
sizeof(RtxBoxIndex), \
0, \
0, \
0, \
NULL, \
acl_list, \
acl_list_count \
@ -76,6 +77,7 @@ UVISOR_EXTERN const uint32_t __uvisor_mode;
sizeof(RtxBoxIndex), \
context_size, \
__uvisor_box_heapsize, \
__uvisor_box_lib_config, \
__uvisor_box_namespace, \
acl_list, \
acl_list_count \
@ -116,6 +118,13 @@ UVISOR_EXTERN const uint32_t __uvisor_mode;
#define UVISOR_BOX_NAMESPACE(box_namespace) \
static const char *const __uvisor_box_namespace = box_namespace
/* Use this macro before UVISOR_BOX_CONFIG to define the function the main
* thread of your box will use for its body. If you don't want a main thread,
* too bad: you have to have one. */
#define UVISOR_BOX_MAIN(function, priority, stack_size) \
static osThreadDef(function, priority, stack_size); \
static const void * const __uvisor_box_lib_config = osThread(function);
#define UVISOR_BOX_HEAPSIZE(heap_size) \
static const uint32_t __uvisor_box_heapsize = heap_size;

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/*
* Copyright (c) 2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __UVISOR_API_NVIC_VIRTUAL_H__
#define __UVISOR_API_NVIC_VIRTUAL_H__
#include "api/inc/interrupts.h"
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ vIRQ_EnableIRQ
#define NVIC_DisableIRQ vIRQ_DisableIRQ
#define NVIC_GetPendingIRQ vIRQ_GetPendingIRQ
#define NVIC_SetPendingIRQ vIRQ_SetPendingIRQ
#define NVIC_ClearPendingIRQ vIRQ_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority vIRQ_SetPriority
#define NVIC_GetPriority vIRQ_GetPriority
#endif /* __UVISOR_API_NVIC_VIRTUAL_H__ */

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/*
* Copyright (c) 2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __UVISOR_API_VECTAB_VIRTUAL_H__
#define __UVISOR_API_VECTAB_VIRTUAL_H__
#include "api/inc/interrupts.h"
#define NVIC_SetVector vIRQ_SetVector
#define NVIC_GetVector vIRQ_GetVector
#endif /* __UVISOR_API_VECTAB_VIRTUAL_H__ */

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@ -60,16 +60,17 @@
*
* @param box_name[in] The name of the source box as decalred in
* `UVISOR_BOX_CONFIG`.
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param addr[in] The address for the data access.
* @param operation[in] The operation to perform at the address for the read. It
* is chosen among the `UVISOR_RGW_OP_*` macros.
* @param shared[in] True if the gateway can be performed by any box. In this
* case, the box_name field does not guarantee exclusivity.
* @param mask[in] The mask to apply for the read operation.
* @returns The value read from address using the operation and mask provided
* (or their respective defaults if they have not been provided).
*/
#define uvisor_read(box_name, addr, op, shared, msk) \
#define uvisor_read(box_name, shared, addr, op, msk) \
({ \
/* Instanstiate the gateway. This gets resolved at link-time. */ \
__attribute__((aligned(4))) static TRegisterGateway const register_gateway = { \
@ -106,15 +107,16 @@
*
* @param box_name[in] The name of the source box as decalred in
* `UVISOR_BOX_CONFIG`.
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param addr[in] The address for the data access.
* @param val[in] The value to write at address.
* @param operation[in] The operation to perform at the address for the read. It
* is chosen among the `UVISOR_RGW_OP_*` macros.
* @param shared[in] True if the gateway can be performed by any box. In this
* case, the box_name field does not guarantee exclusivity.
* @param mask[in] The mask to apply for the write operation.
*/
#define uvisor_write(box_name, addr, val, op, shared, msk) \
#define uvisor_write(box_name, shared, addr, val, op, msk) \
{ \
/* Instanstiate the gateway. This gets resolved at link-time. */ \
__attribute__((aligned(4))) static TRegisterGateway const register_gateway = { \
@ -143,77 +145,95 @@
/** Get the selected bits at the target address.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @returns The value `*address & mask`.
*/
#define UVISOR_BITS_GET(box_name, address, mask) \
#define UVISOR_BITS_GET(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address & mask */ \
uvisor_read(box_name, address, UVISOR_RGW_OP_READ_AND, false, mask)
uvisor_read(box_name, shared, address, UVISOR_RGW_OP_READ_AND, mask)
/** Check the selected bits at the target address.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Address at which to check the bits
* @param mask[in] Bits to select out of the target address
* @returns The value `(bool) (*address & mask) == mask)`.
* @returns The value `((*address & mask) == mask)`.
*/
#define UVISOR_BITS_CHECK(box_name, address, mask) \
((bool) (UVISOR_BITS_GET(box_name, address, mask) == mask))
#define UVISOR_BITS_CHECK(box_name, shared, address, mask) \
((UVISOR_BITS_GET(box_name, shared, address, mask)) == (mask))
/** Set the selected bits to 1 at the target address.
*
* Equivalent to: `*address |= mask`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define UVISOR_BITS_SET(box_name, address, mask) \
#define UVISOR_BITS_SET(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address |= (mask & mask) */ \
uvisor_write(box_name, address, mask, UVISOR_RGW_OP_WRITE_OR, false, mask)
uvisor_write(box_name, shared, address, mask, UVISOR_RGW_OP_WRITE_OR, mask)
/** Clear the selected bits at the target address.
*
* Equivalent to: `*address &= ~mask`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define UVISOR_BITS_CLEAR(box_name, address, mask) \
#define UVISOR_BITS_CLEAR(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address &= (0x00000000 | ~mask) */ \
uvisor_write(box_name, address, 0x00000000, UVISOR_RGW_OP_WRITE_AND, false, mask)
uvisor_write(box_name, shared, address, 0x00000000, UVISOR_RGW_OP_WRITE_AND, mask)
/** Set the selected bits at the target address to the given value.
*
* Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @param value[in] Value to write at the address location. Note: The value
* must be already shifted to the correct bit position
*/
#define UVISOR_BITS_SET_VALUE(box_name, address, mask, value) \
#define UVISOR_BITS_SET_VALUE(box_name, shared, address, mask, value) \
/* Register gateway implementation:
* *address = (*address & ~mask) | (value & mask) */ \
uvisor_write(box_name, address, value, UVISOR_RGW_OP_WRITE_REPLACE, false, mask)
uvisor_write(box_name, shared, address, value, UVISOR_RGW_OP_WRITE_REPLACE, mask)
/** Toggle the selected bits at the target address.
*
* Equivalent to: `*address ^= mask`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define UVISOR_BITS_TOGGLE(box_name, address, mask) \
#define UVISOR_BITS_TOGGLE(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address ^= (0xFFFFFFFF & mask) */ \
uvisor_write(box_name, address, 0xFFFFFFFF, UVISOR_RGW_OP_WRITE_XOR, false, mask)
uvisor_write(box_name, shared, address, 0xFFFFFFFF, UVISOR_RGW_OP_WRITE_XOR, mask)
#endif /* __UVISOR_API_REGISTER_GATEWAY_H__ */

4
features/FEATURE_UVISOR/includes/uvisor/api/inc/register_gateway_exports.h
View File

@ -79,6 +79,10 @@ typedef struct {
(((uint16_t) (width) << __UVISOR_RGW_OP_WIDTH_POS) & __UVISOR_RGW_OP_WIDTH_MASK) | \
(((uint16_t) (shared) << __UVISOR_RGW_OP_SHARED_POS) & __UVISOR_RGW_OP_SHARED_MASK)))
/** Register gateway operation - Shared */
#define UVISOR_RGW_SHARED 1
#define UVISOR_RGW_EXCLUSIVE 0
/** Register gateway operation - Type */
#define UVISOR_RGW_OP_READ 0 /**< value = *address */
#define UVISOR_RGW_OP_READ_AND 1 /**< value = *address & mask */

8
features/FEATURE_UVISOR/includes/uvisor/api/inc/svc_exports.h
View File

@ -114,8 +114,12 @@
#define UVISOR_SVC_ID_PAGE_FREE UVISOR_SVC_CUSTOM_TABLE(23)
/* SVC immediate values for hardcoded table (call from unprivileged) */
#define UVISOR_SVC_ID_UNVIC_OUT UVISOR_SVC_FIXED_TABLE(0, 0)
#define UVISOR_SVC_ID_REGISTER_GATEWAY UVISOR_SVC_FIXED_TABLE(3, 0)
#define UVISOR_SVC_ID_UNVIC_OUT UVISOR_SVC_FIXED_TABLE(0, 0)
/* Deprecated: UVISOR_SVC_ID_CX_IN(nargs) UVISOR_SVC_FIXED_TABLE(1, nargs) */
/* Deprecated: UVISOR_SVC_ID_CX_OUT UVISOR_SVC_FIXED_TABLE(2, 0) */
#define UVISOR_SVC_ID_REGISTER_GATEWAY UVISOR_SVC_FIXED_TABLE(3, 0)
#define UVISOR_SVC_ID_BOX_INIT_FIRST UVISOR_SVC_FIXED_TABLE(4, 0)
#define UVISOR_SVC_ID_BOX_INIT_NEXT UVISOR_SVC_FIXED_TABLE(5, 0)
/* SVC immediate values for hardcoded table (call from privileged) */
#define UVISOR_SVC_ID_UNVIC_IN UVISOR_SVC_FIXED_TABLE(0, 0)

19
features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h
View File

@ -104,13 +104,24 @@
#if defined(UVISOR_PRESENT) && UVISOR_PRESENT == 1
/** Round an address down to the closest 32-byte boundary.
* @param address[in] The address to round.
*/
#define UVISOR_ROUND32_DOWN(address) ((address) & ~0x1FUL)
/** Round an address up to the closest 32-byte boundary.
* @param address[in] The address to round.
*/
#define UVISOR_ROUND32_UP(address) UVISOR_ROUND32_DOWN((address) + 31UL)
#if defined(ARCH_MPU_ARMv7M)
#define UVISOR_REGION_ROUND_DOWN(x) ((x) & ~((1UL << UVISOR_REGION_BITS(x)) - 1))
#define UVISOR_REGION_ROUND_UP(x) (1UL << UVISOR_REGION_BITS(x))
#define UVISOR_STACK_SIZE_ROUND(x) UVISOR_REGION_ROUND_UP(x)
#elif defined(ARCH_MPU_KINETIS)
#define UVISOR_REGION_ROUND_DOWN(x) ((x) & ~0x1FUL)
#define UVISOR_REGION_ROUND_UP(x) UVISOR_REGION_ROUND_DOWN((x) + 31UL)
#define UVISOR_REGION_ROUND_DOWN(x) UVISOR_ROUND32_DOWN(x)
#define UVISOR_REGION_ROUND_UP(x) UVISOR_ROUND32_UP(x)
#define UVISOR_STACK_SIZE_ROUND(x) UVISOR_REGION_ROUND_UP((x) + (UVISOR_STACK_BAND_SIZE * 2))
#else
#error "Unknown MPU architecture. uvisor: Check your Makefile. uvisor-lib: Check if uVisor is supported"
@ -158,6 +169,10 @@ typedef struct {
/* Contains user provided size of box heap without guards of buffers. */
uint32_t heap_size;
/* Opaque-to-uVisor data that potentially contains uvisor-lib-specific or
* OS-specific per-box configuration */
const void * const lib_config;
const char * box_namespace;
const UvisorBoxAclItem * const acl_list;
uint32_t acl_count;

4
features/FEATURE_UVISOR/mbed_lib.json Normal file
View File

@ -0,0 +1,4 @@
{
"name": "uvisor-lib",
"macros": ["CMSIS_NVIC_VIRTUAL", "CMSIS_VECTAB_VIRTUAL"]
}

55
features/FEATURE_UVISOR/source/page_allocator.c_inc
View File

@ -22,6 +22,7 @@
#include <uvisor.h>
#include "page_allocator.h"
#include "page_allocator_faults.h"
#include "mpu/vmpu_unpriv_access.h"
#include "mpu/vmpu.h"
#include "halt.h"
@ -38,40 +39,31 @@
#endif /* defined(UVISOR_PRESENT) && (UVISOR_PRESENT == 1) */
/* We can only protect a small number of pages efficiently, so there should be
* a relatively low limit to the number of pages.
* By default a maximum of 16 pages are allowed. This can only be overridden
* by the porting engineer for the current platform. */
#ifndef UVISOR_PAGE_TABLE_MAX_COUNT
#define UVISOR_PAGE_TABLE_MAX_COUNT ((uint32_t) 16)
#endif
/* The number of pages is decided by the page size. A small page size leads to
* a lot of pages, however, number of pages is capped for efficiency.
* Furthermore, when allocating large continous memory, a too small page size
* will lead to allocation failures. This can only be overridden
* by the porting engineer for the current platform. */
#ifndef UVISOR_PAGE_SIZE_MINIMUM
#define UVISOR_PAGE_SIZE_MINIMUM ((uint32_t) 1024)
#endif
#include "page_allocator_config.h"
/* The page box_id is the box id which is 8-bit large. */
typedef uint8_t page_owner_t;
/* Maps the page to the owning box handle. */
static page_owner_t g_page_owner_table[UVISOR_PAGE_TABLE_MAX_COUNT];
/* Define a unused value for the page table. */
#define UVISOR_PAGE_UNUSED ((page_owner_t) (-1))
page_owner_t g_page_owner_table[UVISOR_PAGE_TABLE_MAX_COUNT];
/* Contains the configured page size. */
static uint32_t g_page_size;
uint32_t g_page_size;
/* Points to the beginning of the page heap. */
static const void * g_page_heap_start;
const void * g_page_heap_start;
/* Points to the end of the page heap. */
static const void * g_page_heap_end;
const void * g_page_heap_end;
/* Contains the number of free pages. */
static uint8_t g_page_count_free;
uint8_t g_page_count_free;
/* Contains the total number of available pages. */
static uint8_t g_page_count_total;
uint8_t g_page_count_total;
/* Helper function maps pointer to page id, or UVISOR_PAGE_UNUSED. */
uint8_t page_allocator_get_page_from_address(uint32_t address)
{
/* Range check the returned pointer. */
if (address < (uint32_t) g_page_heap_start || address >= (uint32_t) g_page_heap_end) {
return UVISOR_PAGE_UNUSED;
}
/* Compute the index for the pointer. */
return (address - (uint32_t) g_page_heap_start) / g_page_size;
}
void page_allocator_init(void * const heap_start, void * const heap_end, const uint32_t * const page_size)
{
@ -142,8 +134,9 @@ void page_allocator_init(void * const heap_start, void * const heap_end, const u
(unsigned int) (g_page_size / 1024));
uint32_t page = 0;
for (; page < g_page_count_total; page++) {
for (; page < UVISOR_PAGE_TABLE_MAX_COUNT; page++) {
g_page_owner_table[page] = UVISOR_PAGE_UNUSED;
page_allocator_reset_faults(page);
}
}
@ -187,6 +180,8 @@ int page_allocator_malloc(UvisorPageTable * const table)
if (g_page_owner_table[page] == UVISOR_PAGE_UNUSED) {
/* Marry this page to the box id. */
g_page_owner_table[page] = box_id;
/* Reset the fault count for this page. */
page_allocator_reset_faults(page);
/* Get the pointer to the page. */
void * ptr = (void *) g_page_heap_start + page * g_page_size;
/* Zero the entire page before handing it out. */
@ -239,14 +234,14 @@ int page_allocator_free(const UvisorPageTable * const table)
int table_size = page_count;
for (; table_size > 0; page_table++, table_size--) {
void * page = (void *) page_table_read((uint32_t) page_table);
/* Compute the index for the pointer. */
uint8_t page_index = page_allocator_get_page_from_address((uint32_t) page);
/* Range check the returned pointer. */
if (page < g_page_heap_start || page >= g_page_heap_end) {
if (page_index == UVISOR_PAGE_UNUSED) {
DPRINTF("uvisor_page_free: FAIL: Pointer 0x%08x does not belong to any page!\n\n", (unsigned int) page);
UVISOR_PAGE_ALLOCATOR_MUTEX_RELEASE;
return UVISOR_ERROR_PAGE_INVALID_PAGE_ORIGIN;
}
/* Compute the index for the pointer. */
uint32_t page_index = (page - g_page_heap_start) / g_page_size;
/* Check if the page belongs to the caller. */
if (g_page_owner_table[page_index] == box_id) {
g_page_owner_table[page_index] = UVISOR_PAGE_UNUSED;

45
features/FEATURE_UVISOR/source/page_allocator_config.h Normal file
View File

@ -0,0 +1,45 @@
/*
* Copyright (c) 2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __PAGE_ALLOCATOR_CONFIG_H__
#define __PAGE_ALLOCATOR_CONFIG_H__
/* This file can be compiled externally to provide the page allocator algorithm
* for devices NOT supported by uVisor. For this purpose this file is copied as
* is into the target build folder and compiled by the target build system. */
/* We can only protect a small number of pages efficiently, so there should be
* a relatively low limit to the number of pages.
* By default a maximum of 16 pages are allowed. This can only be overwritten
* by the porting engineer for the current platform. */
#ifndef UVISOR_PAGE_TABLE_MAX_COUNT
#define UVISOR_PAGE_TABLE_MAX_COUNT ((uint32_t) 16)
#endif
/* The number of pages is decided by the page size. A small page size leads to
* a lot of pages, however, number of pages is capped for efficiency.
* Furthermore, when allocating large continous memory, a too small page size
* will lead to allocation failures. This can only be overwritten
* by the porting engineer for the current platform. */
#ifndef UVISOR_PAGE_SIZE_MINIMUM
#define UVISOR_PAGE_SIZE_MINIMUM ((uint32_t) 1024)
#endif
/* The page box_id is the box id which is 8-bit large. */
typedef uint8_t page_owner_t;
/* Define a unused value for the page table. */
#define UVISOR_PAGE_UNUSED ((page_owner_t) (-1))
#endif /* __PAGE_ALLOCATOR_CONFIG_H__ */

56
features/FEATURE_UVISOR/source/rtx/box_init.c Normal file
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@ -0,0 +1,56 @@
/*
* Copyright (c) 2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "uvisor-lib/uvisor-lib.h"
#include "mbed_interface.h"
#include "cmsis_os.h"
#include <stdint.h>
#include <string.h>
/* This function is called by uVisor in unprivileged mode. On this OS, we
* create box main threads for the box. */
void __uvisor_lib_box_init(void * lib_config)
{
osThreadId thread_id;
osThreadDef_t * flash_thread_def = lib_config;
osThreadDef_t thread_def;
/* Copy thread definition from flash to RAM. The thread definition is most
* likely in flash, so we need to copy it to box-local RAM before we can
* modify it. */
memcpy(&thread_def, flash_thread_def, sizeof(thread_def));
/* Note that the box main thread stack is separate from the box stack. This
* is because the thread must be created to use a different stack than the
* stack osCreateThread() is called from, as context information is saved
* to the thread stack by the call to osCreateThread(). */
/* Allocate memory for the main thread from the process heap (which is
* private to the process). This memory is never freed, even if the box's
* main thread exits. */
thread_def.stack_pointer = malloc_p(thread_def.stacksize);
if (thread_def.stack_pointer == NULL) {
/* No process heap memory available */
mbed_die();
}
thread_id = osThreadCreate(&thread_def, NULL);
if (thread_id == NULL) {
/* Failed to create thread */
mbed_die();
}
}

3
features/FEATURE_UVISOR/source/rtx/rtx_malloc_wrapper.c
View File

@ -111,7 +111,8 @@ static void * memory(void * ptr, size_t size, int heap, int operation)
return NULL;
}
/* Check if we need to aquire the mutex. */
int mutexed = (is_kernel_initialized() && (heap == HEAP_PROCESS));
int mutexed = is_kernel_initialized() &&
((heap == HEAP_PROCESS) || __uvisor_ps->index.box_heap == __uvisor_ps->index.active_heap);
void * allocator = (heap == HEAP_PROCESS) ?
(__uvisor_ps->index.box_heap) :
(__uvisor_ps->index.active_heap);

1
features/FEATURE_UVISOR/source/rtx/unsupported_page_allocator.c
View File

@ -33,6 +33,7 @@
#define HALT_ERROR(id, ...) {}
#define UVISOR_PAGE_ALLOCATOR_MUTEX_AQUIRE page_allocator_mutex_aquire()
#define UVISOR_PAGE_ALLOCATOR_MUTEX_RELEASE osMutexRelease(g_page_allocator_mutex_id)
#define page_allocator_reset_faults(...) {}
/* Forward declaration of the page allocator API. */
int page_allocator_malloc(UvisorPageTable * const table);

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12
hal/api/critical.h
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@ -24,6 +24,18 @@
extern "C" {
#endif
/** Determine the current interrupts enabled state
*
* This function can be called to determine whether or not interrupts are currently enabled.
* \note
* NOTE:
* This function works for both cortex-A and cortex-M, although the underlyng implementation
* differs.
* @return true if interrupts are enabled, false otherwise
*/
bool core_util_are_interrupts_enabled(void);
/** Mark the start of a critical section
*
* This function should be called to mark the start of a critical section of code.

29
hal/common/critical.c
View File

@ -27,35 +27,39 @@
#define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
static volatile uint32_t interrupt_enable_counter = 0;
static volatile uint32_t critical_interrupts_disabled = 0;
static volatile bool critical_interrupts_disabled = false;
static inline uint32_t get_interrupts_disabled(void)
bool core_util_are_interrupts_enabled(void)
{
#if defined(__CORTEX_A9)
uint32_t interrupts_disabled = (__get_CPSR() & 0x80) >> 7;
return ((__get_CPSR() & 0x80) == 0);
#else
uint32_t interrupts_disabled = __get_PRIMASK();
return ((__get_PRIMASK() & 0x1) == 0);
#endif
return interrupts_disabled;
}
void core_util_critical_section_enter()
{
uint32_t interrupts_disabled = get_interrupts_disabled();
bool interrupts_disabled = !core_util_are_interrupts_enabled();
__disable_irq();
/* Save the interrupt disabled state as it was prior to any nested critical section lock use */
if (!interrupt_enable_counter) {
critical_interrupts_disabled = interrupts_disabled & 0x1;
critical_interrupts_disabled = interrupts_disabled;
}
/* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
are enabled, then something has gone badly wrong thus assert an error.
*/
MBED_ASSERT(interrupt_enable_counter < UINT32_MAX);
// FIXME
#ifndef FEATURE_UVISOR
if (interrupt_enable_counter > 0) {
MBED_ASSERT(interrupts_disabled & 0x1);
MBED_ASSERT(interrupts_disabled);
}
#else
#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
#endif /* FEATURE_UVISOR */
interrupt_enable_counter++;
}
@ -64,9 +68,14 @@ void core_util_critical_section_exit()
/* If critical_section_enter has not previously been called, do nothing */
if (interrupt_enable_counter) {
uint32_t interrupts_disabled = get_interrupts_disabled(); /* get the current interrupt disabled state */
// FIXME
#ifndef FEATURE_UVISOR
bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
MBED_ASSERT(interrupts_disabled & 0x1); /* Interrupts must be disabled on invoking an exit from a critical section */
MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
#else
#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
#endif /* FEATURE_UVISOR */
interrupt_enable_counter--;

35
hal/common/retarget.cpp
View File

@ -88,6 +88,10 @@ FileHandle::~FileHandle() {
#if DEVICE_SERIAL
extern int stdio_uart_inited;
extern serial_t stdio_uart;
#if MBED_CONF_CORE_STDIO_CONVERT_NEWLINES
static char stdio_in_prev;
static char stdio_out_prev;
#endif
#endif
static void init_serial() {
@ -226,9 +230,19 @@ extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsign
if (fh < 3) {
#if DEVICE_SERIAL
if (!stdio_uart_inited) init_serial();
#if MBED_CONF_CORE_STDIO_CONVERT_NEWLINES
for (unsigned int i = 0; i < length; i++) {
if (buffer[i] == '\n' && stdio_out_prev != '\r') {
serial_putc(&stdio_uart, '\r');
}
serial_putc(&stdio_uart, buffer[i]);
stdio_out_prev = buffer[i];
}
#else
for (unsigned int i = 0; i < length; i++) {
serial_putc(&stdio_uart, buffer[i]);
}
#endif
#endif
n = length;
} else {
@ -254,7 +268,28 @@ extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int
// only read a character at a time from stdin
#if DEVICE_SERIAL
if (!stdio_uart_inited) init_serial();
#if MBED_CONF_CORE_STDIO_CONVERT_NEWLINES
while (true) {
char c = serial_getc(&stdio_uart);
if ((c == '\r' && stdio_in_prev != '\n') ||
(c == '\n' && stdio_in_prev != '\r')) {
stdio_in_prev = c;
*buffer = '\n';
break;
} else if ((c == '\r' && stdio_in_prev == '\n') ||
(c == '\n' && stdio_in_prev == '\r')) {
stdio_in_prev = c;
// onto next character
continue;
} else {
stdio_in_prev = c;
*buffer = c;
break;
}
}
#else
*buffer = serial_getc(&stdio_uart);
#endif
#endif
n = 1;
} else {

3
hal/hal/spi_api.h
View File

@ -81,7 +81,8 @@ void spi_free(spi_t *obj);
/** Configure the SPI format
*
* Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
* Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
* The default bit order is MSB.
* @param[in,out] obj The SPI object to configure
* @param[in] bits The number of bits per frame
* @param[in] mode The SPI mode (clock polarity, phase, and shift direction)

178
hal/targets.json
View File

@ -60,10 +60,7 @@
"extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"progen": {
"target": "lpc1114_102",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc1114_102"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "small"
@ -75,10 +72,7 @@
"extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"progen": {
"target": "lpc11u24_201",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u24_201"
},
"detect_code": ["1040"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
@ -88,10 +82,7 @@
"inherits": ["LPC11U24"],
"macros": ["TARGET_LPC11U24"],
"progen": {
"target": "lpc11u24_201",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u24_201"
},
"extra_labels": ["NXP", "LPC11UXX"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
@ -124,10 +115,7 @@
"extra_labels": ["NXP", "LPC11UXX"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"progen": {
"target": "lpc11u35_401",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u35_401"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -139,10 +127,7 @@
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"progen": {
"target": "lpc11u35_501",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u35_501"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -154,10 +139,7 @@
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"progen": {
"target": "lpc11u35_501",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u35_501"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -169,10 +151,7 @@
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"progen": {
"target": "lpc11u35_501",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u35_501"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -184,10 +163,7 @@
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"progen": {
"target": "lpc11u35_501",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u35_501"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -199,20 +175,14 @@
"extra_labels": ["NXP", "LPC11UXX"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"progen": {
"target": "lpc11u37_501",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u37_501"
},
"default_build": "small"
},
"LPCCAPPUCCINO": {
"inherits": ["LPC11U37_501"],
"progen": {
"target": "lpc11u37_501",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u37_501"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
},
@ -224,10 +194,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"inherits": ["LPCTarget"],
"progen": {
"target": "lpc11u37_501",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u37_501"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -240,10 +207,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"],
"inherits": ["LPCTarget"],
"progen": {
"target": "lpc11u68",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u68"
},
"detect_code": ["1168"],
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI"],
@ -265,10 +229,7 @@
"supported_toolchains": ["uARM", "GCC_CR", "GCC_ARM", "IAR"],
"inherits": ["LPCTarget"],
"progen": {
"target": "lpc1549",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc1549"
},
"detect_code": ["1549"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE"],
@ -337,10 +298,7 @@
"is_disk_virtual": true,
"supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
"progen": {
"target": "lpc810",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc810"
},
"device_has": ["ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -354,10 +312,7 @@
"supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
"inherits": ["LPCTarget"],
"progen": {
"target": "lpc812m101",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc812m101"
},
"detect_code": ["1050"],
"device_has": ["ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
@ -372,10 +327,7 @@
"supported_toolchains": ["uARM", "GCC_ARM", "GCC_CR", "IAR"],
"inherits": ["LPCTarget"],
"progen": {
"target": "lpc824m201",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc824m201"
},
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -388,10 +340,7 @@
"is_disk_virtual": true,
"supported_toolchains": ["uARM", "GCC_ARM"],
"progen": {
"target": "ssci824",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "ssci824"
},
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -450,10 +399,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR"],
"inherits": ["LPCTarget"],
"progen": {
"target": "lpc11u37_401",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "lpc11u37_401"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_build": "small"
@ -467,10 +413,7 @@
"is_disk_virtual": true,
"detect_code": ["C000"],
"progen": {
"target": "cocorico",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "cocorico"
},
"default_build": "small"
},
@ -483,10 +426,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"progen": {
"target": "frdm-kl05z",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "frdm-kl05z"
},
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "small"
@ -581,7 +521,7 @@
"default_toolchain": "ARM",
"detect_code": ["0261"],
"progen_target": {"target": "frdm-kl27z"},
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "standard"
},
"K64F": {
@ -594,7 +534,8 @@
"inherits": ["Target"],
"progen": {"target": "frdm-k64f"},
"detect_code": ["0240"],
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "STORAGE"]
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "STORAGE"],
"features": ["IPV4"]
},
"MTS_GAMBIT": {
"inherits": ["Target"],
@ -628,7 +569,7 @@
"inherits": ["Target"],
"progen": {"target": "nucleo-f030r8"},
"detect_code": ["0725"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "small"
},
"NUCLEO_F031K6": {
@ -664,7 +605,7 @@
"inherits": ["Target"],
"progen": {"target": "nucleo-f070rb"},
"detect_code": ["0755"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "small"
},
"NUCLEO_F072RB": {
@ -676,7 +617,7 @@
"inherits": ["Target"],
"progen": {"target": "nucleo-f072rb"},
"detect_code": ["0730"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "small"
},
"NUCLEO_F091RC": {
@ -688,7 +629,7 @@
"inherits": ["Target"],
"progen": {"target": "nucleo-f091rc"},
"detect_code": ["0750"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "small"
},
"NUCLEO_F103RB": {
@ -826,14 +767,39 @@
"core": "Cortex-M7F",
"extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746ZG"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"default_toolchain": "ARM",
"progen": {
"target": "nucleo-f746zg",
"iar": {
"template": ["iar_nucleo_f746zg.ewp.tmpl"]
}
},
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0816"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"features": ["IPV4"]
},
"NUCLEO_L011K4": {
"inherits": ["Target"],
"core": "Cortex-M0+",
"extra_labels": ["STM", "STM32L0", "STM32L011K4"],
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"default_toolchain": "uARM",
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0780"],
"progen": {"target":"nucleo-l011k4"},
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
},
"NUCLEO_F767ZI": {
"inherits": ["Target"],
"core": "Cortex-M7F",
"extra_labels": ["STM", "STM32F7", "STM32F767", "STM32F767ZI"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"default_toolchain": "ARM",
"progen": {"target": "nucleo-f767zi"},
"detect_code": ["0818"],
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "standard"
},
"NUCLEO_L031K6": {
"inherits": ["Target"],
@ -883,6 +849,17 @@
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "small"
},
"NUCLEO_L432KC": {
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M4F",
"default_toolchain": "uARM",
"extra_labels": ["STM", "STM32L4", "STM32L432KC"],
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"],
"progen": {"target": "nucleo-l432kc"},
"detect_code": ["0770"],
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "CAN", "STDIO_MESSAGES"]
},
"NUCLEO_L476RG": {
"supported_form_factors": ["ARDUINO", "MORPHO"],
"core": "Cortex-M4F",
@ -1003,9 +980,11 @@
"core": "Cortex-M7F",
"extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746NG"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"default_toolchain": "ARM",
"progen": {"target": "disco-f746ng"},
"detect_code": ["0815"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_build": "standard"
},
"DISCO_L476VG": {
"inherits": ["Target"],
@ -1127,6 +1106,7 @@
"toolchains": ["ARM_STD", "GCC_ARM"]
},
"program_cycle_s": 6,
"default_build": "small",
"features": ["BLE"]
},
"MCU_NRF51_16K_BASE": {
@ -1543,7 +1523,8 @@
"template": ["iar_rz_a1h.ewp.tmpl"]
}
},
"device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
"device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"features": ["IPV4"]
},
"VK_RZ_A1H": {
"inherits": ["Target"],
@ -1614,10 +1595,7 @@
"extra_labels": ["Silicon_Labs", "EFM32"],
"macros": ["EFM32ZG222F32"],
"progen": {
"target": "efm32zg-stk",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "efm32zg-stk"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"default_build": "small"
@ -1630,10 +1608,7 @@
"extra_labels": ["Silicon_Labs", "EFM32"],
"macros": ["EFM32HG322F64"],
"progen": {
"target": "efm32hg-stk",
"uvision": {
"template": ["uvision_microlib.uvproj.tmpl"]
}
"target": "efm32hg-stk"
},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"default_build": "small"
@ -1774,5 +1749,14 @@
"NRF52_PAN_63"
],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"]
},
"BLUEPILL_F103C8": {
"core": "Cortex-M3",
"default_toolchain": "GCC_ARM",
"extra_labels": ["STM", "STM32F1", "STM32F103C8"],
"supported_toolchains": ["GCC_ARM"],
"inherits": ["Target"],
"progen": {"target": "bluepill-f103c8"},
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
}
}

20
hal/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct
View File

@ -50,10 +50,6 @@
*/
#define __ram_vector_table__ 1
/* Heap 1/4 of ram and stack 1/8 */
#define __stack_size__ 0x4000
#define __heap_size__ 0x8000
#if (defined(__ram_vector_table__))
#define __ram_vector_table_size__ 0x00000400
#else
@ -78,18 +74,6 @@
#define m_data_2_start 0x20000000
#define m_data_2_size 0x00010000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
@ -105,11 +89,9 @@ LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size {
RW_m_data m_data_start m_data_size { ; RW data
.ANY (+RW +ZI)
}
RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
RW_IRAM1 m_data_2_start m_data_2_size { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 ((ImageLimit(RW_m_data_2) == m_data_2_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up
}
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
}
}

20
hal/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct
View File

@ -49,10 +49,6 @@
*/
#define __ram_vector_table__ 1
/* Heap 1/4 of ram and stack 1/8 */
#define __stack_size__ 0x8000
#define __heap_size__ 0x10000
#if (defined(__ram_vector_table__))
#define __ram_vector_table_size__ 0x00000400
#else
@ -77,18 +73,6 @@
#define m_data_2_start 0x20000000
#define m_data_2_size 0x00030000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
@ -104,11 +88,9 @@ LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size {
RW_m_data m_data_start m_data_size { ; RW data
.ANY (+RW +ZI)
}
RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
RW_IRAM1 m_data_2_start m_data_2_size { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 ((ImageLimit(RW_m_data_2) == m_data_2_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up
}
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
}
}

8
hal/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld
View File

@ -90,7 +90,11 @@ SECTIONS
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
/* Note: The uVisor expects this section at a fixed location, as specified by
* the porting process configuration parameter: FLASH_OFFSET. */
__UVISOR_TEXT_OFFSET = 0x410;
__UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;
.text __UVISOR_TEXT_START :
{
/* uVisor code and data */
. = ALIGN(4);
@ -200,7 +204,7 @@ SECTIONS
__UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,
"The ISR relocation region overlaps with the uVisor BSS section.")
.uvisor.bss (NOLOAD):
.uvisor.bss __UVISOR_BSS_START (NOLOAD):
{
. = ALIGN(32);
__uvisor_bss_start = .;

4
hal/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.c
View File

@ -32,11 +32,11 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
InstallIRQHandler(IRQn, vector);
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

4
hal/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.h
View File

@ -41,8 +41,8 @@
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t __NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}

20
hal/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct
View File

@ -50,10 +50,6 @@
*/
#define __ram_vector_table__ 1
/* Heap 1/4 of ram and stack 1/8 */
#define __stack_size__ 0x800
#define __heap_size__ 0x1000
#if (defined(__ram_vector_table__))
#define __ram_vector_table_size__ 0x00000200
#else
@ -75,18 +71,6 @@
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
#define m_data_size (0x00004000 - m_interrupts_ram_size)
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start 0x10000 { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
@ -101,10 +85,8 @@ LR_m_text m_interrupts_start 0x10000 { ; load region size_region
}
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
RW_IRAM1 m_data_start m_data_size { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 +0 EMPTY Heap_Size { ; Heap region growing up
}
}

440
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_deprecated.h Normal file
View File

@ -0,0 +1,440 @@
/*
* Copyright (c) Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF51_DEPRECATED_H
#define NRF51_DEPRECATED_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and
* nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
*/
/* NVMC */
/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* LPCOMP */
/* The interrupt ISR was renamed. Adding old name to the macros. */
#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn LPCOMP_IRQn
/* MPU */
/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos
#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk
#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1
#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0
/* POWER */
/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM3_Pos (19UL)
#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos)
#define POWER_RAMON_OFFRAM3_RAM3Off (0UL)
#define POWER_RAMON_OFFRAM3_RAM3On (1UL)
/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM2_Pos (18UL)
#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos)
#define POWER_RAMON_OFFRAM2_RAM2Off (0UL)
#define POWER_RAMON_OFFRAM2_RAM2On (1UL)
/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM3_Pos (3UL)
#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos)
#define POWER_RAMON_ONRAM3_RAM3Off (0UL)
#define POWER_RAMON_ONRAM3_RAM3On (1UL)
/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM2_Pos (2UL)
#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos)
#define POWER_RAMON_ONRAM2_RAM2Off (0UL)
#define POWER_RAMON_ONRAM2_RAM2On (1UL)
/* RADIO */
/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos
#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk
#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled
#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled
/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos
#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk
#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled
#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled
/* FICR */
/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
#define SIZERAMBLOCK0 SIZERAMBLOCKS
#define SIZERAMBLOCK1 SIZERAMBLOCKS
#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
/*lint --flb "Leave library region" */
#endif /* NRF51_DEPRECATED_H */

20
hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_IAR/startup_RZA1H.s
View File

@ -29,8 +29,8 @@
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector
PUBLIC __iar_program_start
PUBLIC __vector_core_a9
PUBLIC __RST_Handler
PUBLIC Undefined_Handler
EXTERN SWI_Handler
PUBLIC Prefetch_Handler
@ -52,7 +52,7 @@
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
__vector: ; Make this a DATA label, so that stack usage
__vector_core_a9: ; Make this a DATA label, so that stack usage
; analysis doesn't consider it an uncalled fun
ARM
@ -71,7 +71,7 @@ __vector: ; Make this a DATA label, so that stack usage
DATA
Reset_Addr: DCD __iar_program_start
Reset_Addr: DCD __RST_Handler
Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD SWI_Handler
Prefetch_Addr: DCD Prefetch_Handler
@ -94,15 +94,15 @@ FIQ_Addr: DCD FIQ_Handler
EXTERN create_translation_table
EXTERN SystemInit
EXTERN InitMemorySubsystem
EXTERN __cmain
REQUIRE __vector
EXTERN __iar_program_start
REQUIRE __vector_core_a9
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
ARM
__iar_program_start:
__RST_Handler:
?cstartup:
@ -138,7 +138,7 @@ goToSleep:
;; Set Vector Base Address Register (VBAR) to point to this application's vector table
ldr r0, =__vector
ldr r0, =__vector_core_a9
mcr p15, 0, r0, c12, c0, 0
@ -256,8 +256,8 @@ goToSleep:
;;; Continue to __cmain for C-level initialization.
FUNCALL __iar_program_start, __cmain
B __cmain
FUNCALL __RST_Handler, __iar_program_start
B __iar_program_start
ldr r0, sf_boot ;@ dummy to keep boot loader area

1743
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html
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File diff suppressed because one or more lines are too long

6818
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h
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File diff suppressed because it is too large Load Diff

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/hal_tick.c
View File

@ -43,7 +43,6 @@ void set_compare(uint16_t count);
extern volatile uint32_t SlaveCounter;
extern volatile uint32_t oc_int_part;
extern volatile uint16_t oc_rem_part;
extern volatile uint16_t cnt_val;
// Used to increment the slave counter
void timer_update_irq_handler(void)
@ -60,7 +59,7 @@ void timer_update_irq_handler(void)
// Used for mbed timeout (channel 1) and HAL tick (channel 2)
void timer_oc_irq_handler(void)
{
cnt_val = TIM_MST->CNT;
uint16_t cval = TIM_MST->CNT;
TimMasterHandle.Instance = TIM_MST;
// Channel 1 for mbed timeout
@ -72,7 +71,7 @@ void timer_oc_irq_handler(void)
} else {
if (oc_int_part > 0) {
set_compare(0xFFFF);
oc_rem_part = cnt_val; // To finish the counter loop the next time
oc_rem_part = cval; // To finish the counter loop the next time
oc_int_part--;
} else {
us_ticker_irq_handler();
@ -129,8 +128,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
// Output compare channel 2 interrupt for HAL tick
NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
NVIC_EnableIRQ(TIM_MST_UP_IRQ);
NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
NVIC_EnableIRQ(TIM_MST_OC_IRQ);
NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
// Enable interrupts
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter

5399
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h
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File diff suppressed because it is too large Load Diff

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

5676
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

11738
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c
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@ -43,7 +43,6 @@ void set_compare(uint16_t count);
extern volatile uint32_t SlaveCounter;
extern volatile uint32_t oc_int_part;
extern volatile uint16_t oc_rem_part;
extern volatile uint16_t cnt_val;
// Used to increment the slave counter
void timer_update_irq_handler(void)
@ -60,7 +59,7 @@ void timer_update_irq_handler(void)
// Used for mbed timeout (channel 1) and HAL tick (channel 2)
void timer_oc_irq_handler(void)
{
cnt_val = TIM_MST->CNT;
uint16_t cval = TIM_MST->CNT;
TimMasterHandle.Instance = TIM_MST;
// Channel 1 for mbed timeout
@ -72,7 +71,7 @@ void timer_oc_irq_handler(void)
} else {
if (oc_int_part > 0) {
set_compare(0xFFFF);
oc_rem_part = cnt_val; // To finish the counter loop the next time
oc_rem_part = cval; // To finish the counter loop the next time
oc_int_part--;
} else {
us_ticker_irq_handler();
@ -131,8 +130,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
// Output compare channel 2 interrupt for HAL tick
NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
NVIC_EnableIRQ(TIM_MST_UP_IRQ);
NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
NVIC_EnableIRQ(TIM_MST_OC_IRQ);
NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
// Enable interrupts
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter

5718
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

13113
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

188
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32_hal_legacy.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -129,7 +129,6 @@
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
@ -144,6 +143,73 @@
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif
#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif
#endif
/**
* @}
*/
@ -384,6 +450,7 @@
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
/**
* @}
*/
@ -424,7 +491,7 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -488,6 +555,11 @@
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
#define NAND_AddressTypedef NAND_AddressTypeDef
#define __ARRAY_ADDRESS ARRAY_ADDRESS
@ -551,6 +623,9 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
*/
@ -646,7 +721,7 @@
*/
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
@ -664,7 +739,7 @@
* @}
*/
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
@ -867,9 +942,12 @@
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
@ -881,6 +959,49 @@
/**
* @}
*/
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
#define DCMI_IT_OVF DCMI_IT_OVR
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
/**
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888 DMA2D_INPUT_RGB888
#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8 DMA2D_INPUT_L8
#define CM_AL44 DMA2D_INPUT_AL44
#define CM_AL88 DMA2D_INPUT_AL88
#define CM_L4 DMA2D_INPUT_L4
#define CM_A8 DMA2D_INPUT_A8
#define CM_A4 DMA2D_INPUT_A4
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -938,7 +1059,10 @@
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
@ -1067,7 +1191,7 @@
*/
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
@ -1442,10 +1566,28 @@
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro */
/* is COMP_FLAG_LOCK. */
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
/* argument. */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
* @}
*/
#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
* @}
*/
#endif
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
@ -2489,7 +2631,7 @@
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
@ -2603,6 +2745,34 @@
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2891,6 +3061,8 @@
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
* @}
*/

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -70,11 +70,11 @@
* @{
*/
/**
* @brief STM32F0xx HAL Driver version number V1.3.1
* @brief STM32F0xx HAL Driver version number V1.4.0
*/
#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F0xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24)\
|(__STM32F0xx_HAL_VERSION_SUB1 << 16)\
@ -98,7 +98,7 @@
/** @defgroup HAL_Private_Variables HAL Private Variables
* @{
*/
static __IO uint32_t uwTick;
__IO uint32_t uwTick;
/**
* @}
*/

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of ADC HAL Extension module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_can.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_can.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -234,7 +234,7 @@ typedef struct
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
__IO uint32_t ErrorCode; /*!< CAN Error code
This parameter can be a value of @ref HAL_CAN_Error_Code */
This parameter can be a value of @ref CAN_Error_Code */
}CAN_HandleTypeDef;
/**
@ -247,7 +247,7 @@ typedef struct
* @{
*/
/** @defgroup HAL_CAN_Error_Code CAN Error Code
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cec.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cec.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention

133
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_comp.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
@ -19,14 +19,12 @@
[..]
The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2:
(+) The non inverting input and inverting input can be set to GPIO pins
as shown in table1. COMP Inputs below.
(+) The non inverting input and inverting input can be set to GPIO pins.
(+) The COMP output is available using HAL_COMP_GetOutputLevel()
and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
(+) The COMP output is available using HAL_COMP_GetOutputLevel()
and can be set on GPIO pins.
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3)
Refer to table 3. COMP Outputs redirection to embedded timers below.
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3).
(+) The comparators COMP1 and COMP2 can be combined in window mode.
@ -39,50 +37,6 @@
macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
[..] Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
+--------------------------------------------------+
| | | COMP1 | COMP2 |
|-----------------|----------------|---------------|
| | 1/4 VREFINT | OK | OK |
| | 1/2 VREFINT | OK | OK |
| | 3/4 VREFINT | OK | OK |
| Inverting Input | VREFINT | OK | OK |
| | DAC1 OUT (PA4) | OK | OK |
| | DAC2 OUT (PA5) | OK | OK |
| | IO1 | PA0 | PA2 |
|-----------------|----------------|-------|-------|
| Non Inverting | | PA1 | PA3 |
| Input | | | |
+--------------------------------------------------+
[..] Table 2. COMP Outputs for the STM32F05x, STM32F07x and STM32F09x devices
+---------------+
| COMP1 | COMP2 |
|-------|-------|
| PA0 | PA2 |
| PA6 | PA7 |
| PA11 | PA12 |
+---------------+
[..] Table 3. COMP Outputs redirection to embedded timers for the STM32F05x, STM32F07x and STM32F09x devices
+---------------------------------+
| COMP1 | COMP2 |
|----------------|----------------|
| TIM1 BKIN | TIM1 BKIN |
| | |
| TIM1 OCREFCLR | TIM1 OCREFCLR |
| | |
| TIM1 IC1 | TIM1 IC1 |
| | |
| TIM2 IC4 | TIM2 IC4 |
| | |
| TIM2 OCREFCLR | TIM2 OCREFCLR |
| | |
| TIM3 IC1 | TIM3 IC1 |
| | |
| TIM3 OCREFCLR | TIM3 OCREFCLR |
+---------------------------------+
##### How to use this driver #####
================================================================================
[..]
@ -155,6 +109,55 @@
******************************************************************************
*/
/*
Additional Tables:
Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
+--------------------------------------------------+
| | | COMP1 | COMP2 |
|-----------------|----------------|---------------|
| | 1/4 VREFINT | OK | OK |
| | 1/2 VREFINT | OK | OK |
| | 3/4 VREFINT | OK | OK |
| Inverting Input | VREFINT | OK | OK |
| | DAC1 OUT (PA4) | OK | OK |
| | DAC2 OUT (PA5) | OK | OK |
| | IO1 | PA0 | PA2 |
|-----------------|----------------|-------|-------|
| Non Inverting | | PA1 | PA3 |
| Input | | | |
+--------------------------------------------------+
Table 2. COMP Outputs for the STM32F05x, STM32F07x and STM32F09x devices
+---------------+
| COMP1 | COMP2 |
|-------|-------|
| PA0 | PA2 |
| PA6 | PA7 |
| PA11 | PA12 |
+---------------+
Table 3. COMP Outputs redirection to embedded timers for the STM32F05x, STM32F07x and STM32F09x devices
+---------------------------------+
| COMP1 | COMP2 |
|----------------|----------------|
| TIM1 BKIN | TIM1 BKIN |
| | |
| TIM1 OCREFCLR | TIM1 OCREFCLR |
| | |
| TIM1 IC1 | TIM1 IC1 |
| | |
| TIM2 IC4 | TIM2 IC4 |
| | |
| TIM2 OCREFCLR | TIM2 OCREFCLR |
| | |
| TIM3 IC1 | TIM3 IC1 |
| | |
| TIM3 OCREFCLR | TIM3 OCREFCLR |
+---------------------------------+
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@ -175,9 +178,18 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup COMP_Private_Constants COMP Private Constants
* @{
*/
/* Delay for COMP startup time. */
/* Note: Delay required to reach propagation delay specification. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U) /*!< Delay for COMP startup time */
/* CSR register reset value */
#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
/* CSR register masks */
@ -222,7 +234,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
@ -399,6 +411,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
uint32_t wait_loop_index = 0;
HAL_StatusTypeDef status = HAL_OK;
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
@ -420,8 +433,16 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
regshift = COMP_CSR_COMP2_SHIFT;
}
SET_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
hcomp->State = HAL_COMP_STATE_BUSY;
/* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_BUSY;
/* Delay for COMP startup time */
wait_loop_index = (LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000));
while(wait_loop_index != 0)
{
wait_loop_index--;
}
}
else
{
@ -478,7 +499,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
{
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t extiline = 0;

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_comp.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_conf.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief HAL configuration file.
******************************************************************************
* @attention
@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cortex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cortex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -204,6 +204,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@ -166,11 +166,17 @@ typedef struct
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#else
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) ((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE)
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CRC peripheral:

14
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
@ -117,7 +117,7 @@
#define HAL_CRC_LENGTH_7B 7
#else
#define HAL_CRC_LENGTH_32B 32
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}
*/
@ -145,7 +145,7 @@
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ : CRC handle
@ -153,7 +153,7 @@
* @retval None.
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}
*/
@ -173,9 +173,9 @@ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}
*/

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_def.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************

67
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@ -247,21 +247,15 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
{
return HAL_ERROR;
}
/* Disable the selected DMA Channelx */
__HAL_DMA_DISABLE(hdma);
/* Reset DMA Channel control register */
hdma->Instance->CCR = 0;
/* Reset DMA Channel Number of Data to Transfer register */
hdma->Instance->CNDTR = 0;
/* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0;
@ -272,7 +266,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -430,6 +424,49 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
return HAL_OK;
}
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
status = HAL_ERROR;
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
}
return status;
}
/**
* @brief Polling for transfer complete.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@ -549,7 +586,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if (hdma->XferErrorCallback != (void (*)(DMA_HandleTypeDef *))NULL)
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
@ -574,7 +611,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF;
if(hdma->XferHalfCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
@ -604,7 +641,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);

22
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@ -143,6 +143,8 @@ typedef struct __DMA_HandleTypeDef
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
} DMA_HandleTypeDef;
@ -159,9 +161,10 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
*/
@ -414,6 +417,14 @@ typedef struct __DMA_HandleTypeDef
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__: DMA handle
*
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
#if defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
@ -455,6 +466,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
/**

49
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DMA HAL Extension module.
******************************************************************************
* @attention
@ -563,6 +563,20 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
DMA_FLAG_GL7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
@ -648,6 +662,25 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
@ -716,6 +749,18 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle

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