From 96f9915fa0e2d36df167ed2aa9ac1e0eb047ee6b Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Tue, 28 Apr 2020 12:22:31 -0700 Subject: [PATCH] Remove CY8CPROTO_063_BLE target --- .../GeneratedSource/cycfg.c | 36 - .../GeneratedSource/cycfg.h | 49 - .../GeneratedSource/cycfg.timestamp | 26 - .../GeneratedSource/cycfg_clocks.c | 47 - .../GeneratedSource/cycfg_clocks.h | 55 - .../GeneratedSource/cycfg_notices.h | 32 - .../GeneratedSource/cycfg_peripherals.c | 44 - .../GeneratedSource/cycfg_peripherals.h | 59 - .../GeneratedSource/cycfg_pins.c | 148 --- .../GeneratedSource/cycfg_pins.h | 162 --- .../GeneratedSource/cycfg_routing.c | 31 - .../GeneratedSource/cycfg_routing.h | 47 - .../GeneratedSource/cycfg_system.c | 528 -------- .../GeneratedSource/cycfg_system.h | 102 -- .../cyreservedresources.list | 4 - .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 208 --- .../TARGET_CY8CPROTO_063_BLE/PeripheralPins.c | 229 ---- .../TARGET_CY8CPROTO_063_BLE/cybsp.c | 128 -- .../TARGET_CY8CPROTO_063_BLE/cybsp.h | 76 -- .../TARGET_CY8CPROTO_063_BLE/cybsp_types.h | 155 --- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 311 ----- .../TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S | 261 ---- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld | 470 ------- .../startup_psoc6_01_cm0plus.S | 399 ------ .../TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf | 287 ----- .../TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S | 413 ------ .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 526 -------- .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 311 ----- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 638 --------- .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 461 ------- .../TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S | 631 --------- .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 286 ----- .../TOOLCHAIN_IAR/startup_psoc6_01_cm4.S | 1137 ----------------- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 390 ------ .../device/system_psoc6.h | 658 ---------- targets/targets.json | 32 - 36 files changed, 9377 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c deleted file mode 100644 index ed8102601f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.c -* -* Description: -* Wrapper function to initialize all generated code. -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg.h" - -void init_cycfg_all(void) -{ - init_cycfg_system(); - init_cycfg_clocks(); - init_cycfg_routing(); - init_cycfg_peripherals(); - init_cycfg_pins(); -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h deleted file mode 100644 index 55f9bd74fa..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ /dev/null @@ -1,49 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.h -* -* Description: -* Simple wrapper header containing all generated files. -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_H) -#define CYCFG_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -#include "cycfg_system.h" -#include "cycfg_clocks.h" -#include "cycfg_routing.h" -#include "cycfg_peripherals.h" -#include "cycfg_pins.h" - -void init_cycfg_all(void); - - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp deleted file mode 100644 index 46ae60d212..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ /dev/null @@ -1,26 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.timestamp -* -* Description: -* Sentinel file for determining if generated source is up to date. -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c deleted file mode 100644 index a37bc200ab..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ /dev/null @@ -1,47 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_clocks.c -* -* Description: -* Clock configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_clocks.h" - -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_I2C_CLK_DIV_HW, - .channel_num = CYBSP_I2C_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_clocks(void) -{ - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h deleted file mode 100644 index 95a4298dc7..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ /dev/null @@ -1,55 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_clocks.h -* -* Description: -* Clock configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_CLOCKS_H) -#define CYCFG_CLOCKS_H - -#include "cycfg_notices.h" -#include "cy_sysclk.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_I2C_CLK_DIV_ENABLED 1U -#define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_I2C_CLK_DIV_NUM 1U - -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_clocks(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h deleted file mode 100644 index 682af2fcd3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ /dev/null @@ -1,32 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_notices.h -* -* Description: -* Contains warnings and errors that occurred while generating code for the -* design. -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_NOTICES_H) -#define CYCFG_NOTICES_H - - -#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c deleted file mode 100644 index ecb8b1aed0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ /dev/null @@ -1,44 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.c -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_peripherals.h" - -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BLE_obj = - { - .type = CYHAL_RSC_BLESS, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_peripherals(void) -{ -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BLE_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h deleted file mode 100644 index 0c3a44a4ba..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ /dev/null @@ -1,59 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.h -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PERIPHERALS_H) -#define CYCFG_PERIPHERALS_H - -#include "cycfg_notices.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_BLE_ENABLED 1U -#define CY_BLE_CORE_CORTEX_M4 4U -#define CY_BLE_CORE_CORTEX_M0P 0U -#define CY_BLE_CORE_DUAL 255U -#ifndef CY_BLE_CORE - #define CY_BLE_CORE 4U -#endif -#define CY_BLE_IRQ bless_interrupt_IRQn - -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BLE_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_peripherals(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c deleted file mode 100644 index af64f35652..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ /dev/null @@ -1,148 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.c -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_pins.h" - -const cy_stc_gpio_pin_config_t WCO_IN_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = WCO_IN_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t WCO_IN_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = WCO_IN_PORT_NUM, - .channel_num = WCO_IN_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t WCO_OUT_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = WCO_OUT_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t WCO_OUT_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = WCO_OUT_PORT_NUM, - .channel_num = WCO_OUT_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t SWDIO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLUP, - .hsiom = SWDIO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t SWDIO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = SWDIO_PORT_NUM, - .channel_num = SWDIO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t SWCLK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLDOWN, - .hsiom = SWCLK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t SWCLK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = SWCLK_PORT_NUM, - .channel_num = SWCLK_PIN, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_pins(void) -{ - Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&WCO_IN_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&SWDIO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(SWCLK_PORT, SWCLK_PIN, &SWCLK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&SWCLK_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h deleted file mode 100644 index 2ff717c9da..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ /dev/null @@ -1,162 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.h -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PINS_H) -#define CYCFG_PINS_H - -#include "cycfg_notices.h" -#include "cy_gpio.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cycfg_routing.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define WCO_IN_ENABLED 1U -#define WCO_IN_PORT GPIO_PRT0 -#define WCO_IN_PORT_NUM 0U -#define WCO_IN_PIN 0U -#define WCO_IN_NUM 0U -#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG -#define WCO_IN_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_0_HSIOM - #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM -#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define WCO_IN_HAL_PORT_PIN P0_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define WCO_OUT_ENABLED 1U -#define WCO_OUT_PORT GPIO_PRT0 -#define WCO_OUT_PORT_NUM 0U -#define WCO_OUT_PIN 1U -#define WCO_OUT_NUM 1U -#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG -#define WCO_OUT_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_1_HSIOM - #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM -#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define WCO_OUT_HAL_PORT_PIN P0_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define SWDIO_ENABLED 1U -#define SWDIO_PORT GPIO_PRT6 -#define SWDIO_PORT_NUM 6U -#define SWDIO_PIN 6U -#define SWDIO_NUM 6U -#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP -#define SWDIO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_6_HSIOM - #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM -#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define SWDIO_HAL_PORT_PIN P6_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP -#endif //defined (CY_USING_HAL) -#define SWCLK_ENABLED 1U -#define SWCLK_PORT GPIO_PRT6 -#define SWCLK_PORT_NUM 6U -#define SWCLK_PIN 7U -#define SWCLK_NUM 7U -#define SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN -#define SWCLK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_7_HSIOM - #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM -#define SWCLK_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define SWCLK_HAL_PORT_PIN P6_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN -#endif //defined (CY_USING_HAL) - -extern const cy_stc_gpio_pin_config_t WCO_IN_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t WCO_IN_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t WCO_OUT_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t WCO_OUT_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t SWDIO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t SWDIO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t SWCLK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t SWCLK_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_pins(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c deleted file mode 100644 index 315831c42c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ /dev/null @@ -1,31 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.c -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_routing.h" - -void init_cycfg_routing(void) -{ -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h deleted file mode 100644 index 6392359364..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ /dev/null @@ -1,47 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.h -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_ROUTING_H) -#define CYCFG_ROUTING_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -void init_cycfg_routing(void); -#define init_cycfg_connectivity() init_cycfg_routing() -#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN -#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS -#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c deleted file mode 100644 index 62e18c21c3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ /dev/null @@ -1,528 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.c -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_system.h" - -#define CY_CFG_SYSCLK_ECO_ERROR 1 -#define CY_CFG_SYSCLK_ALTHF_ERROR 2 -#define CY_CFG_SYSCLK_PLL_ERROR 3 -#define CY_CFG_SYSCLK_FLL_ERROR 4 -#define CY_CFG_SYSCLK_WCO_ERROR 5 -#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 -#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 -#define CY_CFG_SYSCLK_FLL_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL -#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_ILO_ENABLED 1 -#define CY_CFG_SYSCLK_IMO_ENABLED 1 -#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 -#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 -#define CY_CFG_SYSCLK_WCO_ENABLED 1 -#define CY_CFG_PWR_ENABLED 1 -#define CY_CFG_PWR_INIT 1 -#define CY_CFG_PWR_USING_PMIC 0 -#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 -#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP -#define CY_CFG_PWR_USING_ULP 0 - -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = -{ - .fllMult = 500U, - .refDiv = 20U, - .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, - .enableOutputDiv = true, - .lockTolerance = 10U, - .igain = 9U, - .pgain = 5U, - .settlingCount = 8U, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, - .cco_Freq = 355U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 1U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 4U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) - -__WEAK void cycfg_ClockStartupError(uint32_t error) -{ - (void)error; /* Suppress the compiler warning */ - while(1); -} -__STATIC_INLINE void Cy_SysClk_ClkBakInit() -{ - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkFastInit() -{ - Cy_SysClk_ClkFastSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_FllInit() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkHf0Init() -{ - Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); -} -__STATIC_INLINE void Cy_SysClk_IloInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -__STATIC_INLINE void Cy_SysClk_ClkLfInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkPath0Init() -{ - Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath1Init() -{ - Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath2Init() -{ - Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath3Init() -{ - Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath4Init() -{ - Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPeriInit() -{ - Cy_SysClk_ClkPeriSetDivider(1U); -} -__STATIC_INLINE void Cy_SysClk_ClkSlowInit() -{ - Cy_SysClk_ClkSlowSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_WcoInit() -{ - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); - } -} -__STATIC_INLINE void init_cycfg_power(void) -{ - /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ - #if (CY_CFG_PWR_VBACKUP_USING_VDDD) - if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) - { - Cy_SysLib_ResetBackupDomain(); - Cy_SysClk_IloDisable(); - Cy_SysClk_IloInit(); - } - #else /* Dedicated Supply */ - Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); - #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ - - /* Configure core regulator */ - #if CY_CFG_PWR_USING_LDO - Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); - Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); - #else - Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); - #endif /* CY_CFG_PWR_USING_LDO */ - /* Configure PMIC */ - Cy_SysPm_UnlockPmic(); - #if CY_CFG_PWR_USING_PMIC - Cy_SysPm_PmicEnableOutput(); - #else - Cy_SysPm_PmicDisableOutput(); - #endif /* CY_CFG_PWR_USING_PMIC */ -} - - -void init_cycfg_system(void) -{ - /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ - Cy_SysLib_SetWaitStates(false, 150UL); - #ifdef CY_CFG_PWR_ENABLED - #ifdef CY_CFG_PWR_INIT - init_cycfg_power(); - #else - #warning Power system will not be configured. Update power personality to v1.20 or later. - #endif /* CY_CFG_PWR_INIT */ - #endif /* CY_CFG_PWR_ENABLED */ - - /* Reset the core clock path to default and disable all the FLLs/PLLs */ - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkFastSetDivider(0U); - Cy_SysClk_ClkPeriSetDivider(1U); - Cy_SysClk_ClkSlowSetDivider(0U); - for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ - { - (void)Cy_SysClk_PllDisable(pll); - } - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - - if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && - (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) - { - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); - } - - Cy_SysClk_FllDisable(); - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); - #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); - #endif - - - /* Enable all source clocks */ - #ifdef CY_CFG_SYSCLK_PILO_ENABLED - Cy_SysClk_PiloInit(); - #endif - - #ifdef CY_CFG_SYSCLK_WCO_ENABLED - Cy_SysClk_WcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED - Cy_SysClk_ClkLfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED - Cy_SysClk_AltHfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ECO_ENABLED - Cy_SysClk_EcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED - Cy_SysClk_ExtClkInit(); - #endif - - /* Configure CPU clock dividers */ - #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED - Cy_SysClk_ClkFastInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED - Cy_SysClk_ClkPeriInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED - Cy_SysClk_ClkSlowInit(); - #endif - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ - Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); - #else - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure Path Clocks */ - #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED - Cy_SysClk_ClkPath0Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED - Cy_SysClk_ClkPath2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED - Cy_SysClk_ClkPath3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED - Cy_SysClk_ClkPath4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED - Cy_SysClk_ClkPath5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED - Cy_SysClk_ClkPath6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED - Cy_SysClk_ClkPath7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED - Cy_SysClk_ClkPath8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED - Cy_SysClk_ClkPath9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED - Cy_SysClk_ClkPath10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED - Cy_SysClk_ClkPath11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED - Cy_SysClk_ClkPath12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED - Cy_SysClk_ClkPath13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED - Cy_SysClk_ClkPath14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED - Cy_SysClk_ClkPath15Init(); - #endif - - /* Configure and enable FLL */ - #ifdef CY_CFG_SYSCLK_FLL_ENABLED - Cy_SysClk_FllInit(); - #endif - - Cy_SysClk_ClkHf0Init(); - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - /* Apply the ClkPath1 user setting */ - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure and enable PLLs */ - #ifdef CY_CFG_SYSCLK_PLL0_ENABLED - Cy_SysClk_Pll0Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL1_ENABLED - Cy_SysClk_Pll1Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL2_ENABLED - Cy_SysClk_Pll2Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL3_ENABLED - Cy_SysClk_Pll3Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL4_ENABLED - Cy_SysClk_Pll4Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL5_ENABLED - Cy_SysClk_Pll5Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL6_ENABLED - Cy_SysClk_Pll6Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL7_ENABLED - Cy_SysClk_Pll7Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL8_ENABLED - Cy_SysClk_Pll8Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL9_ENABLED - Cy_SysClk_Pll9Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL10_ENABLED - Cy_SysClk_Pll10Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL11_ENABLED - Cy_SysClk_Pll11Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL12_ENABLED - Cy_SysClk_Pll12Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL13_ENABLED - Cy_SysClk_Pll13Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL14_ENABLED - Cy_SysClk_Pll14Init(); - #endif - - /* Configure HF clocks */ - #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED - Cy_SysClk_ClkHf1Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED - Cy_SysClk_ClkHf2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED - Cy_SysClk_ClkHf3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED - Cy_SysClk_ClkHf4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED - Cy_SysClk_ClkHf5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED - Cy_SysClk_ClkHf6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED - Cy_SysClk_ClkHf7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED - Cy_SysClk_ClkHf8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED - Cy_SysClk_ClkHf9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED - Cy_SysClk_ClkHf10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED - Cy_SysClk_ClkHf11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED - Cy_SysClk_ClkHf12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED - Cy_SysClk_ClkHf13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED - Cy_SysClk_ClkHf14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED - Cy_SysClk_ClkHf15Init(); - #endif - - /* Configure miscellaneous clocks */ - #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED - Cy_SysClk_ClkTimerInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - Cy_SysClk_ClkAltSysTickInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED - Cy_SysClk_ClkPumpInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED - Cy_SysClk_ClkBakInit(); - #endif - - /* Configure default enabled clocks */ - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - Cy_SysClk_IloInit(); - #else - Cy_SysClk_IloDisable(); - #endif - - #ifndef CY_CFG_SYSCLK_IMO_ENABLED - #error the IMO must be enabled for proper chip operation - #endif - - #ifdef CY_CFG_SYSCLK_MFO_ENABLED - Cy_SysClk_MfoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED - Cy_SysClk_ClkMfInit(); - #endif - - /* Set accurate flash wait states */ - #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) - Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); - #endif - - /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ - SystemCoreClockUpdate(); - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h deleted file mode 100644 index 03bd80bbed..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ /dev/null @@ -1,102 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.h -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* cfg-backend-cli: 1.2.0.1478 -* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_SYSTEM_H) -#define CYCFG_SYSTEM_H - -#include "cycfg_notices.h" -#include "cy_sysclk.h" -#include "cy_ble_clk.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_gpio.h" -#include "cy_syspm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define cpuss_0_dap_0_ENABLED 1U -#define srss_0_clock_0_ENABLED 1U -#define srss_0_clock_0_bakclk_0_ENABLED 1U -#define srss_0_clock_0_fastclk_0_ENABLED 1U -#define srss_0_clock_0_fll_0_ENABLED 1U -#define srss_0_clock_0_hfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF0 0UL -#define srss_0_clock_0_ilo_0_ENABLED 1U -#define srss_0_clock_0_imo_0_ENABLED 1U -#define srss_0_clock_0_lfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 -#define srss_0_clock_0_pathmux_0_ENABLED 1U -#define srss_0_clock_0_pathmux_1_ENABLED 1U -#define srss_0_clock_0_pathmux_2_ENABLED 1U -#define srss_0_clock_0_pathmux_3_ENABLED 1U -#define srss_0_clock_0_pathmux_4_ENABLED 1U -#define srss_0_clock_0_periclk_0_ENABLED 1U -#define srss_0_clock_0_slowclk_0_ENABLED 1U -#define srss_0_clock_0_wco_0_ENABLED 1U -#define srss_0_power_0_ENABLED 1U -#define CY_CFG_PWR_MODE_LP 0x01UL -#define CY_CFG_PWR_MODE_ULP 0x02UL -#define CY_CFG_PWR_MODE_ACTIVE 0x04UL -#define CY_CFG_PWR_MODE_SLEEP 0x08UL -#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL -#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP -#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP -#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL -#define CY_CFG_PWR_USING_LDO 1 -#define CY_CFG_PWR_VDDA_MV 3300 -#define CY_CFG_PWR_VDDD_MV 3300 -#define CY_CFG_PWR_VBACKUP_MV 3300 -#define CY_CFG_PWR_VDD_NS_MV 3300 -#define CY_CFG_PWR_VDDIO0_MV 3300 -#define CY_CFG_PWR_VDDIO1_MV 3300 - -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_system(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list deleted file mode 100644 index 22e48eac70..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ /dev/null @@ -1,4 +0,0 @@ -[Device=CYBLE-416045-02] - -[Blocks] -# Nothing needs to be reserved for this board diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus deleted file mode 100644 index a1e0521c58..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ /dev/null @@ -1,208 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c deleted file mode 100644 index 4b7bb9588c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * mbed Microcontroller Library - * Copyright (c) 2017-2018 Future Electronics - * Copyright (c) 2019 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralNames.h" -#include "PeripheralPins.h" -#include "pinmap.h" - -#if DEVICE_SERIAL -//*** SERIAL *** -const PinMap PinMap_UART_RX[] = { - {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, - {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, - {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, - {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_TX[] = { - {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, - {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, - {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, - {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, - {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_RTS[] = { - {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, - {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, - {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, - {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, - {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, - {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, - {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_CTS[] = { - {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, - {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, - {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, - {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, - {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, - {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, - {NC, NC, 0} -}; -#endif // DEVICE_SERIAL - - -#if DEVICE_I2C -//*** I2C *** -const PinMap PinMap_I2C_SCL[] = { - {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, - {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, - {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)}, - {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, - {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, - {NC, NC, 0} -}; -const PinMap PinMap_I2C_SDA[] = { - {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, - {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, - {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)}, - {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, - {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, - {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, - {NC, NC, 0} -}; -#endif // DEVICE_I2C - -#if DEVICE_SPI -//*** SPI *** -const PinMap PinMap_SPI_MOSI[] = { - {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, - {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, - {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)}, - {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, - {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_MISO[] = { - {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, - {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, - {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)}, - {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, - {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, - {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SCLK[] = { - {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, - {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, - {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, - {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)}, - {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, - {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)}, - {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, - {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, - {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SSEL[] = { - {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, - {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, - {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, - {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)}, - {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, - {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)}, - {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, - {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, - {NC, NC, 0} -}; -#endif // DEVICE_SPI - -#if DEVICE_PWMOUT -//*** PWM *** -const PinMap PinMap_PWM_OUT[] = { - // 16-bit PWM outputs - {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, - {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, - {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, - {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, - {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, - {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, - {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, - {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, - {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, - {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, - {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, - {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, - {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, - {P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)}, - {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, - {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, - {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, - {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, - {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, - // 16-bit PWM inverted outputs - {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, - {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, - {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, - {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, - {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, - {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, - {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, - {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, - {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, - {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, - {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, - {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, - {P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)}, - {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, - {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, - {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, - {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, - // 32-bit PWM outputs - {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, - {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, - {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, - {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, - {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, - {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, - {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, - {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, - {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, - {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, - {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, - {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, - {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, - {P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)}, - {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, - {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, - {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, - {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, - {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, - // 32-bit PWM inverted outputs - {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, - {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, - {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, - {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, - {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, - {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, - {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, - {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, - {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, - {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, - {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, - {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, - {P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)}, - {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, - {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, - {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, - {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, - {NC, NC, 0} -}; -#endif // DEVICE_PWMOUT - -#if DEVICE_ANALOGIN -const PinMap PinMap_ADC[] = { - {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {NC, NC, 0} -}; -#endif // DEVICE_ANALOGIN - -#if DEVICE_ANALOGOUT -const PinMap PinMap_DAC[] = { - {P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {NC, NC, 0} -}; -#endif // DEVICE_ANALOGIN diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c deleted file mode 100644 index 851e751b7a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c +++ /dev/null @@ -1,128 +0,0 @@ -/***************************************************************************//** -* \file cybsp.c -* -* Description: -* Provides initialization code for starting up the hardware contained on the -* Cypress board. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "cy_syspm.h" -#include "cy_sysclk.h" -#include "cybsp.h" -#if defined(CY_USING_HAL) -#include "cyhal_hwmgr.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ -#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER - #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) -#endif - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -static cyhal_sdio_t sdio_obj; - -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) -{ - return &sdio_obj; -} -#endif - -/** - * Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - */ -static cy_rslt_t cybsp_register_sysclk_pm_callback(void) -{ - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, - .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER - }; - - if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) - { - result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; - } - return result; -} - -cy_rslt_t cybsp_init(void) -{ - /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ -#if defined(CY_USING_HAL) - cy_rslt_t result = cyhal_hwmgr_init(); -#else - cy_rslt_t result = CY_RSLT_SUCCESS; -#endif - -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) - init_cycfg_all(); -#endif - - if (CY_RSLT_SUCCESS == result) - { - result = cybsp_register_sysclk_pm_callback(); - } - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) - /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require - * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. - */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. - */ - result = cyhal_sdio_init( - &sdio_obj, - CYBSP_WIFI_SDIO_CMD, - CYBSP_WIFI_SDIO_CLK, - CYBSP_WIFI_SDIO_D0, - CYBSP_WIFI_SDIO_D1, - CYBSP_WIFI_SDIO_D2, - CYBSP_WIFI_SDIO_D3); - } -#endif /* defined(CYBSP_WIFI_CAPABLE) */ - - /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. - */ - return result; -} - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h deleted file mode 100644 index bb83a6b9a8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h +++ /dev/null @@ -1,76 +0,0 @@ -/***************************************************************************//** -* \file cybsp.h -* -* \brief -* Basic API for setting up boards containing a Cypress MCU. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#include "cy_result.h" -#include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -#include "cyhal_sdio.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_macros Macros -* \{ -*/ - -/** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) - -/** \} group_bsp_macros */ - -/** -* \addtogroup group_bsp_functions Functions -* \{ -*/ - -/** - * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is - * a problem initializing any hardware it returns an error code specific - * to the hardware module that had a problem. - */ -cy_rslt_t cybsp_init(void); - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -/** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. - * \note This function should only be called after cybsp_init(); - * \returns The initialized sdio object. - */ -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); -#endif /* defined(CYBSP_WIFI_CAPABLE) */ - -/** \} group_bsp_functions */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h deleted file mode 100644 index 2e02bdec7d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h +++ /dev/null @@ -1,155 +0,0 @@ -/***************************************************************************//** -* \file CY8CPROTO-063-BLE/cybsp_types.h -* -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-063-BLE kit. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#if defined(CY_USING_HAL) -#include "cyhal_pin_package.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_settings BSP Settings -* \{ -* -*
Peripheral Default HAL Settings:
-* | Resource | Parameter | Value | Remarks | -* | :------: | :-------: | :---: | :------ | -* | ADC | VREF | 1.2 V | | -* | ^ | Measurement type | Single Ended | | -* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | -* | ^ | Output range | 0x000 to 0x7FF | | -* | DAC | Reference source | VDDA | | -* | ^ | Input range | 0x000 to 0xFFF | | -* | ^ | Output range | 0 to VDDA | | -* | ^ | Output type | Unbuffered output | | -* | I2C | Role | Master | Configurable to slave mode through HAL function | -* | ^ | Data rate | 100 kbps | Configurable through HAL function | -* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | -* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| -* | SPI | Data rate | 100 kpbs | Configurable through HAL function | -* | ^ | Slave select polarity | Active low | | -* | UART | Flow control | No flow control | Configurable through HAL function | -* | ^ | Data format | 8N1 | Configurable through HAL function | -* | ^ | Baud rate | 115200 | Configurable through HAL function | -*/ -/** \} group_bsp_settings */ - -/** -* \addtogroup group_bsp_pin_state Pin States -* \{ -*/ - -/** Pin state for the LED on. */ -#define CYBSP_LED_STATE_ON (0U) -/** Pin state for the LED off. */ -#define CYBSP_LED_STATE_OFF (1U) - -/** Pin state for when a button is pressed. */ -#define CYBSP_BTN_PRESSED (0U) -/** Pin state for when a button is released. */ -#define CYBSP_BTN_OFF (1U) - -/** \} group_bsp_pin_state */ - -#if defined(CY_USING_HAL) - -/** -* \addtogroup group_bsp_pins Pin Mappings -* \{ -*/ - -/** -* \addtogroup group_bsp_pins_led LED Pins -* \{ -*/ - -/** LED 3; User LED1 (red) */ -#define CYBSP_LED3 (P6_3) -/** LED 4; User LED2 (green) */ -#define CYBSP_LED4 (P7_1) - -/** LED 3; User LED1 (red) */ -#define CYBSP_USER_LED1 (CYBSP_LED3) -/** LED 4; User LED2 (green) */ -#define CYBSP_USER_LED2 (CYBSP_LED4) -/** LED 3; User LED1 (red) */ -#define CYBSP_USER_LED (CYBSP_USER_LED1) - -/** \} group_bsp_pins_led */ - -/** -* \addtogroup group_bsp_pins_btn Button Pins -* \{ -*/ - -/** Switch 2; User Button 1 */ -#define CYBSP_SW2 (P0_4) - -/** Switch 2; User Button 1 */ -#define CYBSP_USER_BTN1 (CYBSP_SW2) -/** Switch 2; User Button 1 */ -#define CYBSP_USER_BTN (CYBSP_USER_BTN1) - -/** \} group_bsp_pins_btn */ - - -/** -* \addtogroup group_bsp_pins_comm Communication Pins -* \{ -*/ - -/** Pin: UART RX */ -#define CYBSP_UART_RX P5_0 -/** Pin: UART TX */ -#define CYBSP_UART_TX P5_1 - -/** Pin: UART RX */ -#define CYBSP_DEBUG_UART_RX P5_0 -/** Pin: UART TX */ -#define CYBSP_DEBUG_UART_TX P5_1 - -/** Pin: I2C SCL */ -#define CYBSP_I2C_SCL P6_4 -/** Pin: I2C SDA */ -#define CYBSP_I2C_SDA P6_5 - -/** Pin: SWDIO */ -#define CYBSP_SWDIO P6_6 -/** Pin: SWDCK */ -#define CYBSP_SWDCK P6_7 - -/** \} group_bsp_pins_comm */ - -/** \} group_bsp_pins */ - -#endif /* defined(CY_USING_HAL) */ - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct deleted file mode 100644 index 4ff5ccb454..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ /dev/null @@ -1,311 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) -{ - .cy_app_header +0 - { - * (.cy_app_header) - } - - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S deleted file mode 100644 index 09d6b4ccfe..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ /dev/null @@ -1,261 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm0plus.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD 0x0000000D ; NMI Handler located at ROM code - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External interrupts Description - DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 - DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 - DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 - DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 - DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 - DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 - DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 - DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 - DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 - DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 - DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 - DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 - DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 - DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 - DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 - DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 - DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 - DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 - DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 - DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 - DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 - DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 - DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 - DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 - DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 - DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 - DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 - DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 - DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 - DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 - DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 - DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - EXPORT __ramVectors - AREA RESET_RAM, READWRITE, NOINIT -__ramVectors SPACE __Vectors_Size - - - AREA |.text|, CODE, READONLY - - -; Weak function for startup customization -; -; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -; because this function is executed as the first instruction in the ResetHandler. -; The PDL is also not initialized to use the proper register offsets. -; The user of this function is responsible for initializing the PDL and resources before using them. -; -Cy_OnResetUser PROC - EXPORT Cy_OnResetUser [WEAK] - BX LR - ENDP - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - - ; Define strong function for startup customization - BL Cy_OnResetUser - - ; Copy vectors from ROM to RAM - LDR r1, =__Vectors - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -Vectors_Copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE Vectors_Copy - - ; Update Vector Table Offset Register. */ - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb 0xF - - LDR R0, =__main - BLX R0 - - ; Should never get here - B . - - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -Cy_SysLib_FaultHandler PROC - EXPORT Cy_SysLib_FaultHandler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - bl L_API_call -L_MSP - mrs r0, MSP -L_API_call - bl Cy_SysLib_FaultHandler - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT Default_Handler [WEAK] - EXPORT NvicMux0_IRQHandler [WEAK] - EXPORT NvicMux1_IRQHandler [WEAK] - EXPORT NvicMux2_IRQHandler [WEAK] - EXPORT NvicMux3_IRQHandler [WEAK] - EXPORT NvicMux4_IRQHandler [WEAK] - EXPORT NvicMux5_IRQHandler [WEAK] - EXPORT NvicMux6_IRQHandler [WEAK] - EXPORT NvicMux7_IRQHandler [WEAK] - EXPORT NvicMux8_IRQHandler [WEAK] - EXPORT NvicMux9_IRQHandler [WEAK] - EXPORT NvicMux10_IRQHandler [WEAK] - EXPORT NvicMux11_IRQHandler [WEAK] - EXPORT NvicMux12_IRQHandler [WEAK] - EXPORT NvicMux13_IRQHandler [WEAK] - EXPORT NvicMux14_IRQHandler [WEAK] - EXPORT NvicMux15_IRQHandler [WEAK] - EXPORT NvicMux16_IRQHandler [WEAK] - EXPORT NvicMux17_IRQHandler [WEAK] - EXPORT NvicMux18_IRQHandler [WEAK] - EXPORT NvicMux19_IRQHandler [WEAK] - EXPORT NvicMux20_IRQHandler [WEAK] - EXPORT NvicMux21_IRQHandler [WEAK] - EXPORT NvicMux22_IRQHandler [WEAK] - EXPORT NvicMux23_IRQHandler [WEAK] - EXPORT NvicMux24_IRQHandler [WEAK] - EXPORT NvicMux25_IRQHandler [WEAK] - EXPORT NvicMux26_IRQHandler [WEAK] - EXPORT NvicMux27_IRQHandler [WEAK] - EXPORT NvicMux28_IRQHandler [WEAK] - EXPORT NvicMux29_IRQHandler [WEAK] - EXPORT NvicMux30_IRQHandler [WEAK] - EXPORT NvicMux31_IRQHandler [WEAK] - -NvicMux0_IRQHandler -NvicMux1_IRQHandler -NvicMux2_IRQHandler -NvicMux3_IRQHandler -NvicMux4_IRQHandler -NvicMux5_IRQHandler -NvicMux6_IRQHandler -NvicMux7_IRQHandler -NvicMux8_IRQHandler -NvicMux9_IRQHandler -NvicMux10_IRQHandler -NvicMux11_IRQHandler -NvicMux12_IRQHandler -NvicMux13_IRQHandler -NvicMux14_IRQHandler -NvicMux15_IRQHandler -NvicMux16_IRQHandler -NvicMux17_IRQHandler -NvicMux18_IRQHandler -NvicMux19_IRQHandler -NvicMux20_IRQHandler -NvicMux21_IRQHandler -NvicMux22_IRQHandler -NvicMux23_IRQHandler -NvicMux24_IRQHandler -NvicMux25_IRQHandler -NvicMux26_IRQHandler -NvicMux27_IRQHandler -NvicMux28_IRQHandler -NvicMux29_IRQHandler -NvicMux30_IRQHandler -NvicMux31_IRQHandler - - B . - ENDP - - ALIGN - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld deleted file mode 100644 index a9d28573c6..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ /dev/null @@ -1,470 +0,0 @@ -/***************************************************************************//** -* \file cy8c6xx7_cm0plus.ld -* \version 2.70 -* -* Linker file for the GNU C compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location is fixed and starts at 0x10000000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) -ENTRY(Reset_Handler) - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_START -* is equal to MBED_ROM_START -*/ -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_SIZE -* is equal to MBED_ROM_SIZE -*/ -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -/* The size of the stack section at the end of CM0+ SRAM */ -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -/* Force symbol to be entered in the output file as an undefined symbol. Doing -* this may, for example, trigger linking of additional modules from standard -* libraries. You may list several symbols for each EXTERN, and you may use -* EXTERN multiple times. This command has the same effect as the -u command-line -* option. -*/ -EXTERN(Reset_Handler) - -/* The MEMORY section below describes the location and size of blocks of memory in the target. -* Use this section to specify the memory regions available for allocation. -*/ -MEMORY -{ - /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. - */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE - flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) - - /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ - em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ - - /* The following regions define device specific memory regions and must not be changed. */ - sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ - sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ - sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ - sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ - sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ - efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ - - -SECTIONS -{ - .cy_app_header : - { - KEEP(*(.cy_app_header)) - } > flash - - /* Cortex-M0+ application flash area */ - .text : - { - . = ALIGN(4); - __Vectors = . ; - KEEP(*(.vectors)) - . = ALIGN(4); - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - . = ALIGN(4); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* Read-only code (constants). */ - *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - - KEEP(*(.eh_frame*)) - } > flash - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - __exidx_start = .; - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Copy interrupt vectors from flash to RAM */ - LONG (__Vectors) /* From */ - LONG (__ram_vectors_start__) /* To */ - LONG (__Vectors_End - __Vectors) /* Size */ - - /* Copy data section to RAM */ - LONG (__etext) /* From */ - LONG (__data_start__) /* To */ - LONG (__data_end__ - __data_start__) /* Size */ - - __copy_table_end__ = .; - } > flash - - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > flash - - __etext = . ; - - - .ramVectors (NOLOAD) : ALIGN(8) - { - __ram_vectors_start__ = .; - KEEP(*(.ram_vectors)) - __ram_vectors_end__ = .; - } > ram - - - .data __ram_vectors_end__ : AT (__etext) - { - __data_start__ = .; - - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - - KEEP(*(.cy_ramfunc*)) - . = ALIGN(4); - - __data_end__ = .; - - } > ram - - - /* Place variables in the section that should not be initialized during the - * device startup. - */ - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } > ram - - - /* The uninitialized global or static variables are placed in this section. - * - * The NOLOAD attribute tells linker that .bss section does not consume - * any space in the image. The NOLOAD attribute changes the .bss type to - * NOBITS, and that makes linker to A) not allocate section in memory, and - * A) put information to clear the section with all zeros during application - * loading. - * - * Without the NOLOAD attribute, the .bss section might get PROGBITS type. - * This makes linker to A) allocate zeroed section in memory, and B) copy - * this section to RAM during application loading. - */ - .bss (NOLOAD): - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > ram - - - .heap (NOLOAD): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > ram - - - /* Public RAM */ - .cy_sharedmem (NOLOAD): - { - . = ALIGN(4); - KEEP(*(.cy_sharedmem)) - } > public_ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* Emulated EEPROM Flash area */ - .cy_em_eeprom : - { - KEEP(*(.cy_em_eeprom)) - } > em_eeprom - - - /* Supervisory Flash: User data */ - .cy_sflash_user_data : - { - KEEP(*(.cy_sflash_user_data)) - } > sflash_user_data - - - /* Supervisory Flash: Normal Access Restrictions (NAR) */ - .cy_sflash_nar : - { - KEEP(*(.cy_sflash_nar)) - } > sflash_nar - - - /* Supervisory Flash: Public Key */ - .cy_sflash_public_key : - { - KEEP(*(.cy_sflash_public_key)) - } > sflash_public_key - - - /* Supervisory Flash: Table of Content # 2 */ - .cy_toc_part2 : - { - KEEP(*(.cy_toc_part2)) - } > sflash_toc_2 - - - /* Supervisory Flash: Table of Content # 2 Copy */ - .cy_rtoc_part2 : - { - KEEP(*(.cy_rtoc_part2)) - } > sflash_rtoc_2 - - - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - - /* eFuse */ - .cy_efuse : - { - KEEP(*(.cy_efuse)) - } > efuse - - - /* These sections are used for additional metadata (silicon revision, - * Silicon/JTAG ID, etc.) storage. - */ - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE -} - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; -__cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -__cy_memory_2_start = 0x16000000; -__cy_memory_2_length = 0x8000; -__cy_memory_2_row_size = 0x200; - -/* XIP */ -__cy_memory_3_start = 0x18000000; -__cy_memory_3_length = 0x08000000; -__cy_memory_3_row_size = 0x200; - -/* eFuse */ -__cy_memory_4_start = 0x90700000; -__cy_memory_4_length = 0x100000; -__cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S deleted file mode 100644 index b46556a8a7..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S +++ /dev/null @@ -1,399 +0,0 @@ -/**************************************************************************//** - * @file startup_psoc6_01_cm0plus.S - * @brief CMSIS Core Device Startup File for - * ARMCM0plus Device Series - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* Address of the NMI handler */ - #define CY_NMI_HANLDER_ADDR 0x0000000D - - /* The CPU VTOR register */ - #define CY_CPU_VTOR_ADDR 0xE000ED08 - - /* Copy flash vectors and data section to RAM */ - #define __STARTUP_COPY_MULTIPLE - - /* Clear single BSS section */ - #define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long CY_NMI_HANLDER_ADDR /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts Description */ - .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ - .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ - .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ - .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ - .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ - .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ - .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ - .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ - .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ - .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ - .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ - .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ - .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ - .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ - .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ - .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ - .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ - .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ - .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ - .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ - .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ - .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ - .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ - .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ - .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ - .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ - .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ - .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ - .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ - .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ - .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ - .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ - - .size __Vectors, . - __Vectors - .equ __VectorsSize, . - __Vectors - - .section .ram_vectors - .align 2 - .globl __ramVectors -__ramVectors: - .space __VectorsSize - .size __ramVectors, . - __ramVectors - - - .text - .thumb - .thumb_func - .align 2 - - /* - * Device startup customization - * - * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) - * because this function is executed as the first instruction in the ResetHandler. - * The PDL is also not initialized to use the proper register offsets. - * The user of this function is responsible for initializing the PDL and resources before using them. - */ - .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser - .type Cy_OnResetUser, %function - -Cy_OnResetUser: - bx lr - .size Cy_OnResetUser, . - Cy_OnResetUser - .endfunc - - /* Reset handler */ - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - bl Cy_OnResetUser - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .L_loop1_done - -.L_loop1: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 - -.L_loop1_done: -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 - - subs r2, r1 - ble .L_loop3_done - -.L_loop3: - subs r2, #4 - str r0, [r1, r2] - bgt .L_loop3 -.L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - /* Update Vector Table Offset Register. */ - ldr r0, =__ramVectors - ldr r1, =CY_CPU_VTOR_ADDR - str r0, [r1] - dsb 0xF - - bl _start - - /* Should never get here */ - b . - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - .weak Cy_SysLib_FaultHandler - .type Cy_SysLib_FaultHandler, %function - -Cy_SysLib_FaultHandler: - b . - .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler - .type Fault_Handler, %function - -Fault_Handler: - /* Storing LR content for Creator call stack trace */ - push {LR} - movs r0, #4 - mov r1, LR - tst r0, r1 - beq .L_MSP - mrs r0, PSP - b .L_API_call -.L_MSP: - mrs r0, MSP -.L_API_call: - /* Compensation of stack pointer address due to pushing 4 bytes of LR */ - adds r0, r0, #4 - bl Cy_SysLib_FaultHandler - b . - .size Fault_Handler, . - Fault_Handler - -.macro def_fault_Handler fault_handler_name - .weak \fault_handler_name - .set \fault_handler_name, Fault_Handler - .endm - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - - def_fault_Handler HardFault_Handler - - def_irq_handler SVC_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ - def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ - def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ - def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ - def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ - def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ - def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ - def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ - def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ - def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ - def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ - def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ - def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ - def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ - def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ - def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ - def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ - def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ - def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ - def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ - def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ - def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ - def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ - def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ - def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ - def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ - def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ - def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ - def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ - def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ - def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ - def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ - - .end - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf deleted file mode 100644 index 3a0414efa3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ /dev/null @@ -1,287 +0,0 @@ -/***************************************************************************//** -* \file cy8c6xx7_cm0plus.icf -* \version 2.70 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_START - * is equal to MBED_ROM_START - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x80000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_SIZE - * is equal to MBED_ROM_SIZE - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00010000; -} - -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { - define symbol MBED_PUBLIC_RAM_SIZE = 0x200; -} -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - - if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x0400; - } else { - define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; - } -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; - -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} - -if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { - define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); -} - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); -/* Public RAM */ -define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application */ -".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; -place in IROM1_region { block RO }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { readwrite section .cy_ramfunc }; -place at end of IRAM1_region { block HSTACK }; - -/* Public RAM */ -place at start of IRAM2_region { section .cy_sharedmem }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_header, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00100000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S deleted file mode 100644 index e926966cf7..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S +++ /dev/null @@ -1,413 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm0plus.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device Series -; * @version V5.00 -; * @date 08. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec_ram:DATA:NOROOT(2) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN __iar_data_init3 - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - PUBLIC __ramVectors - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD 0x0000000D ; NMI_Handler is defined in ROM code - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External interrupts Description - DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 - DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 - DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 - DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 - DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 - DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 - DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 - DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 - DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 - DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 - DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 - DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 - DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 - DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 - DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 - DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 - DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 - DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 - DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 - DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 - DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 - DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 - DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 - DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 - DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 - DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 - DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 - DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 - DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 - DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 - DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 - DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - SECTION .intvec_ram:DATA:REORDER:NOROOT(2) -__ramVectors - DS32 __Vectors_Size - - - THUMB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default handlers -;; - PUBWEAK Default_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Default_Handler - B Default_Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Weak function for startup customization -;; -;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -;; because this function is executed as the first instruction in the ResetHandler. -;; The PDL is also not initialized to use the proper register offsets. -;; The user of this function is responsible for initializing the PDL and resources before using them. -;; - PUBWEAK Cy_OnResetUser - SECTION .text:CODE:REORDER:NOROOT(2) -Cy_OnResetUser - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Define strong version to return zero for -;; __iar_program_start to skip data sections -;; initialization. -;; - PUBLIC __low_level_init - SECTION .text:CODE:REORDER:NOROOT(2) -__low_level_init - MOVS R0, #0 - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - ; Define strong function for startup customization - LDR R0, =Cy_OnResetUser - BLX R0 - - ; Copy vectors from ROM to RAM - LDR r1, =__vector_table - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -intvec_copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE intvec_copy - - ; Update Vector Table Offset Register - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb - - LDR R0, =__iar_program_start - BLX R0 - -; Should never get here -Cy_Main_Exited - B Cy_Main_Exited - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK Cy_SysLib_FaultHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Cy_SysLib_FaultHandler - B Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - IMPORT Cy_SysLib_FaultHandler - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - b L_API_call -L_MSP - mrs r0, MSP -L_API_call - ; Storing LR content for Creator call stack trace - push {LR} - bl Cy_SysLib_FaultHandler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - ; External interrupts - PUBWEAK NvicMux0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux0_IRQHandler - B NvicMux0_IRQHandler - - PUBWEAK NvicMux1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux1_IRQHandler - B NvicMux1_IRQHandler - - PUBWEAK NvicMux2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux2_IRQHandler - B NvicMux2_IRQHandler - - PUBWEAK NvicMux3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux3_IRQHandler - B NvicMux3_IRQHandler - - PUBWEAK NvicMux4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux4_IRQHandler - B NvicMux4_IRQHandler - - PUBWEAK NvicMux5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux5_IRQHandler - B NvicMux5_IRQHandler - - PUBWEAK NvicMux6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux6_IRQHandler - B NvicMux6_IRQHandler - - PUBWEAK NvicMux7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux7_IRQHandler - B NvicMux7_IRQHandler - - PUBWEAK NvicMux8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux8_IRQHandler - B NvicMux8_IRQHandler - - PUBWEAK NvicMux9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux9_IRQHandler - B NvicMux9_IRQHandler - - PUBWEAK NvicMux10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux10_IRQHandler - B NvicMux10_IRQHandler - - PUBWEAK NvicMux11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux11_IRQHandler - B NvicMux11_IRQHandler - - PUBWEAK NvicMux12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux12_IRQHandler - B NvicMux12_IRQHandler - - PUBWEAK NvicMux13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux13_IRQHandler - B NvicMux13_IRQHandler - - PUBWEAK NvicMux14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux14_IRQHandler - B NvicMux14_IRQHandler - - PUBWEAK NvicMux15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux15_IRQHandler - B NvicMux15_IRQHandler - - PUBWEAK NvicMux16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux16_IRQHandler - B NvicMux16_IRQHandler - - PUBWEAK NvicMux17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux17_IRQHandler - B NvicMux17_IRQHandler - - PUBWEAK NvicMux18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux18_IRQHandler - B NvicMux18_IRQHandler - - PUBWEAK NvicMux19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux19_IRQHandler - B NvicMux19_IRQHandler - - PUBWEAK NvicMux20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux20_IRQHandler - B NvicMux20_IRQHandler - - PUBWEAK NvicMux21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux21_IRQHandler - B NvicMux21_IRQHandler - - PUBWEAK NvicMux22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux22_IRQHandler - B NvicMux22_IRQHandler - - PUBWEAK NvicMux23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux23_IRQHandler - B NvicMux23_IRQHandler - - PUBWEAK NvicMux24_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux24_IRQHandler - B NvicMux24_IRQHandler - - PUBWEAK NvicMux25_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux25_IRQHandler - B NvicMux25_IRQHandler - - PUBWEAK NvicMux26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux26_IRQHandler - B NvicMux26_IRQHandler - - PUBWEAK NvicMux27_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux27_IRQHandler - B NvicMux27_IRQHandler - - PUBWEAK NvicMux28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux28_IRQHandler - B NvicMux28_IRQHandler - - PUBWEAK NvicMux29_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux29_IRQHandler - B NvicMux29_IRQHandler - - PUBWEAK NvicMux30_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux30_IRQHandler - B NvicMux30_IRQHandler - - PUBWEAK NvicMux31_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux31_IRQHandler - B NvicMux31_IRQHandler - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c deleted file mode 100644 index 18cc197563..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ /dev/null @@ -1,526 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm0plus.c -* \version 2.70 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_sysclk.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default SlowClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -uint32_t cy_BleEcoClockFreqHz = 0UL; - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1M_THRESHOLD (1000000u) - -uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - -uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - - -/******************************************************************************* -* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() -*******************************************************************************/ -#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) -#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) -#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* -* Initializes the system: -* - Restores FLL registers to the default state. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - - Cy_SystemInit(); - SystemCoreClockUpdate(); - - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - /* Allocate and initialize semaphores for the system operations. */ - CY_SECTION(".cy_sharedmem") - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 - }; - - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - - if (0UL != locHf0Clock) - { - cy_Hfclk0FreqHz = locHf0Clock; - cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); - SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); - - /* Sets clock frequency for Delay API */ - cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; - } -} - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/******************************************************************************* -* Function Name: Cy_SysGetCM4Status -****************************************************************************//** -* -* Returns the Cortex-M4 core power mode. -* -* \return \ref group_system_config_cm4_status_macro -* -*******************************************************************************/ -uint32_t Cy_SysGetCM4Status(void) -{ - uint32_t regValue; - - /* Get current power mode */ - regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; - - return (regValue); -} - - -/******************************************************************************* -* Function Name: Cy_SysEnableCM4 -****************************************************************************//** -* -* Sets vector table base address and enables the Cortex-M4 core. -* -* \note If the CPU is already enabled, it is reset and then enabled. -* -* \param vectorTableOffset The offset of the vector table base address from -* memory address 0x00000000. The offset should be multiple to 1024 bytes. -* -*******************************************************************************/ -void Cy_SysEnableCM4(uint32_t vectorTableOffset) -{ - uint32_t regValue; - uint32_t interruptState; - uint32_t cpuState; - - CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); - - interruptState = Cy_SysLib_EnterCriticalSection(); - - cpuState = Cy_SysGetCM4Status(); - if (CY_SYS_CM4_STATUS_ENABLED == cpuState) - { - Cy_SysResetCM4(); - } - - CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_ENABLED; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysDisableCM4 -****************************************************************************//** -* -* Disables the Cortex-M4 core and waits for the mode to take the effect. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the -* CPU. -* -*******************************************************************************/ -void Cy_SysDisableCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_DISABLED; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysRetainCM4 -****************************************************************************//** -* -* Retains the Cortex-M4 core and exists without waiting for the mode to take -* effect. -* -* \note The retained mode can be entered only from the enabled mode. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. -* -*******************************************************************************/ -void Cy_SysRetainCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_RETAINED; - CPUSS->CM4_PWR_CTL = regValue; - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysResetCM4 -****************************************************************************//** -* -* Resets the Cortex-M4 core and waits for the mode to take the effect. -* -* \note The reset mode can not be entered from the retained mode. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. -* -*******************************************************************************/ -void Cy_SysResetCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_RESET; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} -#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm0 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm0(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct deleted file mode 100644 index 0f7f5fe0df..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ /dev/null @@ -1,311 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -; The size of the Cortex-M0+ application flash image -#define FLASH_CM0P_SIZE 0x2000 - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00045800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash image area -LR_IROM MBED_ROM_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S deleted file mode 100644 index fa2247ebe9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ /dev/null @@ -1,638 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD 0x0000000D ; NMI Handler located at ROM code - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) - DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 - DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 - DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 - DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 - DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 - DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 - DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 - DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 - DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 - DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 - DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 - DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 - DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 - DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 - DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 - DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt - DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - EXPORT __ramVectors - AREA RESET_RAM, READWRITE, NOINIT -__ramVectors SPACE __Vectors_Size - - - AREA |.text|, CODE, READONLY - - -; Weak function for startup customization -; -; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -; because this function is executed as the first instruction in the ResetHandler. -; The PDL is also not initialized to use the proper register offsets. -; The user of this function is responsible for initializing the PDL and resources before using them. -; -Cy_OnResetUser PROC - EXPORT Cy_OnResetUser [WEAK] - BX LR - ENDP - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT Cy_SystemInitFpuEnable - IMPORT __main - - ; Define strong function for startup customization - BL Cy_OnResetUser - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__Vectors - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -Vectors_Copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE Vectors_Copy - - ; Update Vector Table Offset Register. */ - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb 0xF - - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - - LDR R0, =__main - BLX R0 - - ; Should never get here - B . - - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -Cy_SysLib_FaultHandler PROC - EXPORT Cy_SysLib_FaultHandler [WEAK] - B . - ENDP -HardFault_Wrapper\ - PROC - EXPORT HardFault_Wrapper [WEAK] - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - bl L_API_call -L_MSP - mrs r0, MSP -L_API_call - bl Cy_SysLib_FaultHandler - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B HardFault_Wrapper - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT Default_Handler [WEAK] - EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] - EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] - EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] - EXPORT lpcomp_interrupt_IRQHandler [WEAK] - EXPORT scb_8_interrupt_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] - EXPORT srss_interrupt_backup_IRQHandler [WEAK] - EXPORT srss_interrupt_IRQHandler [WEAK] - EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] - EXPORT bless_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] - EXPORT scb_0_interrupt_IRQHandler [WEAK] - EXPORT scb_1_interrupt_IRQHandler [WEAK] - EXPORT scb_2_interrupt_IRQHandler [WEAK] - EXPORT scb_3_interrupt_IRQHandler [WEAK] - EXPORT scb_4_interrupt_IRQHandler [WEAK] - EXPORT scb_5_interrupt_IRQHandler [WEAK] - EXPORT scb_6_interrupt_IRQHandler [WEAK] - EXPORT scb_7_interrupt_IRQHandler [WEAK] - EXPORT csd_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] - EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] - EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] - EXPORT udb_interrupts_0_IRQHandler [WEAK] - EXPORT udb_interrupts_1_IRQHandler [WEAK] - EXPORT udb_interrupts_2_IRQHandler [WEAK] - EXPORT udb_interrupts_3_IRQHandler [WEAK] - EXPORT udb_interrupts_4_IRQHandler [WEAK] - EXPORT udb_interrupts_5_IRQHandler [WEAK] - EXPORT udb_interrupts_6_IRQHandler [WEAK] - EXPORT udb_interrupts_7_IRQHandler [WEAK] - EXPORT udb_interrupts_8_IRQHandler [WEAK] - EXPORT udb_interrupts_9_IRQHandler [WEAK] - EXPORT udb_interrupts_10_IRQHandler [WEAK] - EXPORT udb_interrupts_11_IRQHandler [WEAK] - EXPORT udb_interrupts_12_IRQHandler [WEAK] - EXPORT udb_interrupts_13_IRQHandler [WEAK] - EXPORT udb_interrupts_14_IRQHandler [WEAK] - EXPORT udb_interrupts_15_IRQHandler [WEAK] - EXPORT pass_interrupt_sar_IRQHandler [WEAK] - EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] - EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] - EXPORT profile_interrupt_IRQHandler [WEAK] - EXPORT smif_interrupt_IRQHandler [WEAK] - EXPORT usb_interrupt_hi_IRQHandler [WEAK] - EXPORT usb_interrupt_med_IRQHandler [WEAK] - EXPORT usb_interrupt_lo_IRQHandler [WEAK] - EXPORT pass_interrupt_dacs_IRQHandler [WEAK] - -ioss_interrupts_gpio_0_IRQHandler -ioss_interrupts_gpio_1_IRQHandler -ioss_interrupts_gpio_2_IRQHandler -ioss_interrupts_gpio_3_IRQHandler -ioss_interrupts_gpio_4_IRQHandler -ioss_interrupts_gpio_5_IRQHandler -ioss_interrupts_gpio_6_IRQHandler -ioss_interrupts_gpio_7_IRQHandler -ioss_interrupts_gpio_8_IRQHandler -ioss_interrupts_gpio_9_IRQHandler -ioss_interrupts_gpio_10_IRQHandler -ioss_interrupts_gpio_11_IRQHandler -ioss_interrupts_gpio_12_IRQHandler -ioss_interrupts_gpio_13_IRQHandler -ioss_interrupts_gpio_14_IRQHandler -ioss_interrupt_gpio_IRQHandler -ioss_interrupt_vdd_IRQHandler -lpcomp_interrupt_IRQHandler -scb_8_interrupt_IRQHandler -srss_interrupt_mcwdt_0_IRQHandler -srss_interrupt_mcwdt_1_IRQHandler -srss_interrupt_backup_IRQHandler -srss_interrupt_IRQHandler -pass_interrupt_ctbs_IRQHandler -bless_interrupt_IRQHandler -cpuss_interrupts_ipc_0_IRQHandler -cpuss_interrupts_ipc_1_IRQHandler -cpuss_interrupts_ipc_2_IRQHandler -cpuss_interrupts_ipc_3_IRQHandler -cpuss_interrupts_ipc_4_IRQHandler -cpuss_interrupts_ipc_5_IRQHandler -cpuss_interrupts_ipc_6_IRQHandler -cpuss_interrupts_ipc_7_IRQHandler -cpuss_interrupts_ipc_8_IRQHandler -cpuss_interrupts_ipc_9_IRQHandler -cpuss_interrupts_ipc_10_IRQHandler -cpuss_interrupts_ipc_11_IRQHandler -cpuss_interrupts_ipc_12_IRQHandler -cpuss_interrupts_ipc_13_IRQHandler -cpuss_interrupts_ipc_14_IRQHandler -cpuss_interrupts_ipc_15_IRQHandler -scb_0_interrupt_IRQHandler -scb_1_interrupt_IRQHandler -scb_2_interrupt_IRQHandler -scb_3_interrupt_IRQHandler -scb_4_interrupt_IRQHandler -scb_5_interrupt_IRQHandler -scb_6_interrupt_IRQHandler -scb_7_interrupt_IRQHandler -csd_interrupt_IRQHandler -cpuss_interrupts_dw0_0_IRQHandler -cpuss_interrupts_dw0_1_IRQHandler -cpuss_interrupts_dw0_2_IRQHandler -cpuss_interrupts_dw0_3_IRQHandler -cpuss_interrupts_dw0_4_IRQHandler -cpuss_interrupts_dw0_5_IRQHandler -cpuss_interrupts_dw0_6_IRQHandler -cpuss_interrupts_dw0_7_IRQHandler -cpuss_interrupts_dw0_8_IRQHandler -cpuss_interrupts_dw0_9_IRQHandler -cpuss_interrupts_dw0_10_IRQHandler -cpuss_interrupts_dw0_11_IRQHandler -cpuss_interrupts_dw0_12_IRQHandler -cpuss_interrupts_dw0_13_IRQHandler -cpuss_interrupts_dw0_14_IRQHandler -cpuss_interrupts_dw0_15_IRQHandler -cpuss_interrupts_dw1_0_IRQHandler -cpuss_interrupts_dw1_1_IRQHandler -cpuss_interrupts_dw1_2_IRQHandler -cpuss_interrupts_dw1_3_IRQHandler -cpuss_interrupts_dw1_4_IRQHandler -cpuss_interrupts_dw1_5_IRQHandler -cpuss_interrupts_dw1_6_IRQHandler -cpuss_interrupts_dw1_7_IRQHandler -cpuss_interrupts_dw1_8_IRQHandler -cpuss_interrupts_dw1_9_IRQHandler -cpuss_interrupts_dw1_10_IRQHandler -cpuss_interrupts_dw1_11_IRQHandler -cpuss_interrupts_dw1_12_IRQHandler -cpuss_interrupts_dw1_13_IRQHandler -cpuss_interrupts_dw1_14_IRQHandler -cpuss_interrupts_dw1_15_IRQHandler -cpuss_interrupts_fault_0_IRQHandler -cpuss_interrupts_fault_1_IRQHandler -cpuss_interrupt_crypto_IRQHandler -cpuss_interrupt_fm_IRQHandler -cpuss_interrupts_cm0_cti_0_IRQHandler -cpuss_interrupts_cm0_cti_1_IRQHandler -cpuss_interrupts_cm4_cti_0_IRQHandler -cpuss_interrupts_cm4_cti_1_IRQHandler -tcpwm_0_interrupts_0_IRQHandler -tcpwm_0_interrupts_1_IRQHandler -tcpwm_0_interrupts_2_IRQHandler -tcpwm_0_interrupts_3_IRQHandler -tcpwm_0_interrupts_4_IRQHandler -tcpwm_0_interrupts_5_IRQHandler -tcpwm_0_interrupts_6_IRQHandler -tcpwm_0_interrupts_7_IRQHandler -tcpwm_1_interrupts_0_IRQHandler -tcpwm_1_interrupts_1_IRQHandler -tcpwm_1_interrupts_2_IRQHandler -tcpwm_1_interrupts_3_IRQHandler -tcpwm_1_interrupts_4_IRQHandler -tcpwm_1_interrupts_5_IRQHandler -tcpwm_1_interrupts_6_IRQHandler -tcpwm_1_interrupts_7_IRQHandler -tcpwm_1_interrupts_8_IRQHandler -tcpwm_1_interrupts_9_IRQHandler -tcpwm_1_interrupts_10_IRQHandler -tcpwm_1_interrupts_11_IRQHandler -tcpwm_1_interrupts_12_IRQHandler -tcpwm_1_interrupts_13_IRQHandler -tcpwm_1_interrupts_14_IRQHandler -tcpwm_1_interrupts_15_IRQHandler -tcpwm_1_interrupts_16_IRQHandler -tcpwm_1_interrupts_17_IRQHandler -tcpwm_1_interrupts_18_IRQHandler -tcpwm_1_interrupts_19_IRQHandler -tcpwm_1_interrupts_20_IRQHandler -tcpwm_1_interrupts_21_IRQHandler -tcpwm_1_interrupts_22_IRQHandler -tcpwm_1_interrupts_23_IRQHandler -udb_interrupts_0_IRQHandler -udb_interrupts_1_IRQHandler -udb_interrupts_2_IRQHandler -udb_interrupts_3_IRQHandler -udb_interrupts_4_IRQHandler -udb_interrupts_5_IRQHandler -udb_interrupts_6_IRQHandler -udb_interrupts_7_IRQHandler -udb_interrupts_8_IRQHandler -udb_interrupts_9_IRQHandler -udb_interrupts_10_IRQHandler -udb_interrupts_11_IRQHandler -udb_interrupts_12_IRQHandler -udb_interrupts_13_IRQHandler -udb_interrupts_14_IRQHandler -udb_interrupts_15_IRQHandler -pass_interrupt_sar_IRQHandler -audioss_interrupt_i2s_IRQHandler -audioss_interrupt_pdm_IRQHandler -profile_interrupt_IRQHandler -smif_interrupt_IRQHandler -usb_interrupt_hi_IRQHandler -usb_interrupt_med_IRQHandler -usb_interrupt_lo_IRQHandler -pass_interrupt_dacs_IRQHandler - - B . - ENDP - - ALIGN - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld deleted file mode 100644 index 9be3c4aa3b..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ /dev/null @@ -1,461 +0,0 @@ -/***************************************************************************//** -* \file cy8c6xx7_cm4_dual.ld -* \version 2.70 -* -* Linker file for the GNU C compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location is fixed and starts at 0x10000000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) -ENTRY(Reset_Handler) - -/* The size of the Cortex-M0+ application image at the start of FLASH */ -FLASH_CM0P_SIZE = 0x2000; - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00045800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* The size of the stack section at the end of CM4 SRAM */ -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Force symbol to be entered in the output file as an undefined symbol. Doing -* this may, for example, trigger linking of additional modules from standard -* libraries. You may list several symbols for each EXTERN, and you may use -* EXTERN multiple times. This command has the same effect as the -u command-line -* option. -*/ -EXTERN(Reset_Handler) - -/* The MEMORY section below describes the location and size of blocks of memory in the target. -* Use this section to specify the memory regions available for allocation. -*/ -MEMORY -{ - /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. - */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE - flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - - /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ - em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ - - /* The following regions define device specific memory regions and must not be changed. */ - sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ - sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ - sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ - sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ - sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ - efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ - - -SECTIONS -{ - /* Cortex-M0+ application flash image area */ - .cy_m0p_image ORIGIN(cm0p_image) : - { - . = ALIGN(4); - __cy_m0p_code_start = . ; - KEEP(*(.cy_m0p_image)) - __cy_m0p_code_end = . ; - } > cm0p_image - - /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : - { - . = ALIGN(4); - __Vectors = . ; - KEEP(*(.vectors)) - . = ALIGN(4); - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - . = ALIGN(4); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* Read-only code (constants). */ - *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - - KEEP(*(.eh_frame*)) - } > flash - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - __exidx_start = .; - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Copy interrupt vectors from flash to RAM */ - LONG (__Vectors) /* From */ - LONG (__ram_vectors_start__) /* To */ - LONG (__Vectors_End - __Vectors) /* Size */ - - /* Copy data section to RAM */ - LONG (__etext) /* From */ - LONG (__data_start__) /* To */ - LONG (__data_end__ - __data_start__) /* Size */ - - __copy_table_end__ = .; - } > flash - - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > flash - - __etext = . ; - - - .ramVectors (NOLOAD) : ALIGN(8) - { - __ram_vectors_start__ = .; - KEEP(*(.ram_vectors)) - __ram_vectors_end__ = .; - } > ram - - - .data __ram_vectors_end__ : AT (__etext) - { - __data_start__ = .; - - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - - KEEP(*(.cy_ramfunc*)) - . = ALIGN(4); - - __data_end__ = .; - - } > ram - - - /* Place variables in the section that should not be initialized during the - * device startup. - */ - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } > ram - - - /* The uninitialized global or static variables are placed in this section. - * - * The NOLOAD attribute tells linker that .bss section does not consume - * any space in the image. The NOLOAD attribute changes the .bss type to - * NOBITS, and that makes linker to A) not allocate section in memory, and - * A) put information to clear the section with all zeros during application - * loading. - * - * Without the NOLOAD attribute, the .bss section might get PROGBITS type. - * This makes linker to A) allocate zeroed section in memory, and B) copy - * this section to RAM during application loading. - */ - .bss (NOLOAD): - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > ram - - - .heap (NOLOAD): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* Used for the digital signature of the secure application and the Bootloader SDK application. - * The size of the section depends on the required data size. */ - .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : - { - KEEP(*(.cy_app_signature)) - } > flash - - - /* Emulated EEPROM Flash area */ - .cy_em_eeprom : - { - KEEP(*(.cy_em_eeprom)) - } > em_eeprom - - - /* Supervisory Flash: User data */ - .cy_sflash_user_data : - { - KEEP(*(.cy_sflash_user_data)) - } > sflash_user_data - - - /* Supervisory Flash: Normal Access Restrictions (NAR) */ - .cy_sflash_nar : - { - KEEP(*(.cy_sflash_nar)) - } > sflash_nar - - - /* Supervisory Flash: Public Key */ - .cy_sflash_public_key : - { - KEEP(*(.cy_sflash_public_key)) - } > sflash_public_key - - - /* Supervisory Flash: Table of Content # 2 */ - .cy_toc_part2 : - { - KEEP(*(.cy_toc_part2)) - } > sflash_toc_2 - - - /* Supervisory Flash: Table of Content # 2 Copy */ - .cy_rtoc_part2 : - { - KEEP(*(.cy_rtoc_part2)) - } > sflash_rtoc_2 - - - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - - /* eFuse */ - .cy_efuse : - { - KEEP(*(.cy_efuse)) - } > efuse - - - /* These sections are used for additional metadata (silicon revision, - * Silicon/JTAG ID, etc.) storage. - */ - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE -} - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; -__cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -__cy_memory_2_start = 0x16000000; -__cy_memory_2_length = 0x8000; -__cy_memory_2_row_size = 0x200; - -/* XIP */ -__cy_memory_3_start = 0x18000000; -__cy_memory_3_length = 0x08000000; -__cy_memory_3_row_size = 0x200; - -/* eFuse */ -__cy_memory_4_start = 0x90700000; -__cy_memory_4_length = 0x100000; -__cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S deleted file mode 100644 index 3c2f44d1e0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S +++ /dev/null @@ -1,631 +0,0 @@ -/**************************************************************************//** - * @file startup_psoc6_01_cm4.S - * @brief CMSIS Core Device Startup File for - * ARMCM4 Device Series - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* Address of the NMI handler */ - #define CY_NMI_HANLDER_ADDR 0x0000000D - - /* The CPU VTOR register */ - #define CY_CPU_VTOR_ADDR 0xE000ED08 - - /* Copy flash vectors and data section to RAM */ - #define __STARTUP_COPY_MULTIPLE - - /* Clear single BSS section */ - #define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long CY_NMI_HANLDER_ADDR /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts Description */ - .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ - .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ - .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ - .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ - .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ - .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ - .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ - .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ - .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ - .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ - .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ - .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ - .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ - .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ - .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ - .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ - .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ - .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ - .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ - .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ - .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ - .long usb_interrupt_med_IRQHandler /* USB Interrupt */ - .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ - .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ - - - .size __Vectors, . - __Vectors - .equ __VectorsSize, . - __Vectors - - .section .ram_vectors - .align 2 - .globl __ramVectors -__ramVectors: - .space __VectorsSize - .size __ramVectors, . - __ramVectors - - - .text - .thumb - .thumb_func - .align 2 - - /* - * Device startup customization - * - * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) - * because this function is executed as the first instruction in the ResetHandler. - * The PDL is also not initialized to use the proper register offsets. - * The user of this function is responsible for initializing the PDL and resources before using them. - */ - .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser - .type Cy_OnResetUser, %function - -Cy_OnResetUser: - bx lr - .size Cy_OnResetUser, . - Cy_OnResetUser - .endfunc - - /* Reset handler */ - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - bl Cy_OnResetUser - cpsid i - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - /* Update Vector Table Offset Register. */ - ldr r0, =__ramVectors - ldr r1, =CY_CPU_VTOR_ADDR - str r0, [r1] - dsb 0xF - - /* Enable the FPU if used */ - bl Cy_SystemInitFpuEnable - - bl _start - - /* Should never get here */ - b . - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function - -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - - .weak Cy_SysLib_FaultHandler - .type Cy_SysLib_FaultHandler, %function - -Cy_SysLib_FaultHandler: - b . - .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler - .type Fault_Handler, %function - -Fault_Handler: - /* Storing LR content for Creator call stack trace */ - push {LR} - movs r0, #4 - mov r1, LR - tst r0, r1 - beq .L_MSP - mrs r0, PSP - b .L_API_call -.L_MSP: - mrs r0, MSP -.L_API_call: - /* Compensation of stack pointer address due to pushing 4 bytes of LR */ - adds r0, r0, #4 - bl Cy_SysLib_FaultHandler - b . - .size Fault_Handler, . - Fault_Handler - -.macro def_fault_Handler fault_handler_name - .weak \fault_handler_name - .set \fault_handler_name, Fault_Handler - .endm - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - - def_fault_Handler HardFault_Handler - def_fault_Handler MemManage_Handler - def_fault_Handler BusFault_Handler - def_fault_Handler UsageFault_Handler - - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ - def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ - def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ - def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ - def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ - def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ - def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ - def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ - def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ - def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ - def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ - def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ - def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ - def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ - def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ - def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ - def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ - def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ - def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ - def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ - def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ - def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ - - .end - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf deleted file mode 100644 index b405a8b603..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ /dev/null @@ -1,286 +0,0 @@ -/***************************************************************************//** -* \file cy8c6xx7_cm4_dual.icf -* \version 2.70 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/* The size of the Cortex-M0+ application image */ -define symbol FLASH_CM0P_SIZE = 0x2000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. In case if MBED_APP_START address is - * customized by the bootloader config, the application image should not - * include CM0p prebuilt image. - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x00100000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08002000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00045800; -} - -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - - if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x0400; - } else { - define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; - } -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); -/* Flash */ -define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); - -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; - -define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application image */ -place at start of IROM0_region { block CM0P_RO }; - -/* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { block HEAP}; -place at end of IRAM1_region { block CSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_m0p_image, - section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00100000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S deleted file mode 100644 index f4ca47b457..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ /dev/null @@ -1,1137 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 08. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec_ram:DATA:NOROOT(2) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN Cy_SystemInitFpuEnable - EXTERN __iar_data_init3 - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - PUBLIC __ramVectors - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD 0x0000000D ; NMI_Handler is defined in ROM code - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) - DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 - DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 - DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 - DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 - DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 - DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 - DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 - DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 - DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 - DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 - DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 - DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 - DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 - DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 - DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 - DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt - DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - SECTION .intvec_ram:DATA:REORDER:NOROOT(2) -__ramVectors - DS32 __Vectors_Size - - - THUMB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default handlers -;; - PUBWEAK Default_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Default_Handler - B Default_Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Weak function for startup customization -;; -;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -;; because this function is executed as the first instruction in the ResetHandler. -;; The PDL is also not initialized to use the proper register offsets. -;; The user of this function is responsible for initializing the PDL and resources before using them. -;; - PUBWEAK Cy_OnResetUser - SECTION .text:CODE:REORDER:NOROOT(2) -Cy_OnResetUser - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Define strong version to return zero for -;; __iar_program_start to skip data sections -;; initialization. -;; - PUBLIC __low_level_init - SECTION .text:CODE:REORDER:NOROOT(2) -__low_level_init - MOVS R0, #0 - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - ; Define strong function for startup customization - LDR R0, =Cy_OnResetUser - BLX R0 - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__vector_table - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -intvec_copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE intvec_copy - - ; Update Vector Table Offset Register - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb - - ; Initialize data sections - LDR R0, =__iar_data_init3 - BLX R0 - - LDR R0, =SystemInit - BLX R0 - - LDR R0, =__iar_program_start - BLX R0 - -; Should never get here -Cy_Main_Exited - B Cy_Main_Exited - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK Cy_SysLib_FaultHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Cy_SysLib_FaultHandler - B Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Wrapper - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Wrapper - IMPORT Cy_SysLib_FaultHandler - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - b L_API_call -L_MSP - mrs r0, MSP -L_API_call - ; Storing LR content for Creator call stack trace - push {LR} - bl Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Wrapper - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B HardFault_Wrapper - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B HardFault_Wrapper - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B HardFault_Wrapper - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - ; External interrupts - PUBWEAK ioss_interrupts_gpio_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_0_IRQHandler - B ioss_interrupts_gpio_0_IRQHandler - - PUBWEAK ioss_interrupts_gpio_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_1_IRQHandler - B ioss_interrupts_gpio_1_IRQHandler - - PUBWEAK ioss_interrupts_gpio_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_2_IRQHandler - B ioss_interrupts_gpio_2_IRQHandler - - PUBWEAK ioss_interrupts_gpio_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_3_IRQHandler - B ioss_interrupts_gpio_3_IRQHandler - - PUBWEAK ioss_interrupts_gpio_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_4_IRQHandler - B ioss_interrupts_gpio_4_IRQHandler - - PUBWEAK ioss_interrupts_gpio_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_5_IRQHandler - B ioss_interrupts_gpio_5_IRQHandler - - PUBWEAK ioss_interrupts_gpio_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_6_IRQHandler - B ioss_interrupts_gpio_6_IRQHandler - - PUBWEAK ioss_interrupts_gpio_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_7_IRQHandler - B ioss_interrupts_gpio_7_IRQHandler - - PUBWEAK ioss_interrupts_gpio_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_8_IRQHandler - B ioss_interrupts_gpio_8_IRQHandler - - PUBWEAK ioss_interrupts_gpio_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_9_IRQHandler - B ioss_interrupts_gpio_9_IRQHandler - - PUBWEAK ioss_interrupts_gpio_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_10_IRQHandler - B ioss_interrupts_gpio_10_IRQHandler - - PUBWEAK ioss_interrupts_gpio_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_11_IRQHandler - B ioss_interrupts_gpio_11_IRQHandler - - PUBWEAK ioss_interrupts_gpio_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_12_IRQHandler - B ioss_interrupts_gpio_12_IRQHandler - - PUBWEAK ioss_interrupts_gpio_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_13_IRQHandler - B ioss_interrupts_gpio_13_IRQHandler - - PUBWEAK ioss_interrupts_gpio_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_14_IRQHandler - B ioss_interrupts_gpio_14_IRQHandler - - PUBWEAK ioss_interrupt_gpio_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_gpio_IRQHandler - B ioss_interrupt_gpio_IRQHandler - - PUBWEAK ioss_interrupt_vdd_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_vdd_IRQHandler - B ioss_interrupt_vdd_IRQHandler - - PUBWEAK lpcomp_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -lpcomp_interrupt_IRQHandler - B lpcomp_interrupt_IRQHandler - - PUBWEAK scb_8_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_8_interrupt_IRQHandler - B scb_8_interrupt_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_0_IRQHandler - B srss_interrupt_mcwdt_0_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_1_IRQHandler - B srss_interrupt_mcwdt_1_IRQHandler - - PUBWEAK srss_interrupt_backup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_backup_IRQHandler - B srss_interrupt_backup_IRQHandler - - PUBWEAK srss_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_IRQHandler - B srss_interrupt_IRQHandler - - PUBWEAK pass_interrupt_ctbs_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_ctbs_IRQHandler - B pass_interrupt_ctbs_IRQHandler - - PUBWEAK bless_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -bless_interrupt_IRQHandler - B bless_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_0_IRQHandler - B cpuss_interrupts_ipc_0_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_1_IRQHandler - B cpuss_interrupts_ipc_1_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_2_IRQHandler - B cpuss_interrupts_ipc_2_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_3_IRQHandler - B cpuss_interrupts_ipc_3_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_4_IRQHandler - B cpuss_interrupts_ipc_4_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_5_IRQHandler - B cpuss_interrupts_ipc_5_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_6_IRQHandler - B cpuss_interrupts_ipc_6_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_7_IRQHandler - B cpuss_interrupts_ipc_7_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_8_IRQHandler - B cpuss_interrupts_ipc_8_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_9_IRQHandler - B cpuss_interrupts_ipc_9_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_10_IRQHandler - B cpuss_interrupts_ipc_10_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_11_IRQHandler - B cpuss_interrupts_ipc_11_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_12_IRQHandler - B cpuss_interrupts_ipc_12_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_13_IRQHandler - B cpuss_interrupts_ipc_13_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_14_IRQHandler - B cpuss_interrupts_ipc_14_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_15_IRQHandler - B cpuss_interrupts_ipc_15_IRQHandler - - PUBWEAK scb_0_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_0_interrupt_IRQHandler - B scb_0_interrupt_IRQHandler - - PUBWEAK scb_1_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_1_interrupt_IRQHandler - B scb_1_interrupt_IRQHandler - - PUBWEAK scb_2_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_2_interrupt_IRQHandler - B scb_2_interrupt_IRQHandler - - PUBWEAK scb_3_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_3_interrupt_IRQHandler - B scb_3_interrupt_IRQHandler - - PUBWEAK scb_4_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_4_interrupt_IRQHandler - B scb_4_interrupt_IRQHandler - - PUBWEAK scb_5_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_5_interrupt_IRQHandler - B scb_5_interrupt_IRQHandler - - PUBWEAK scb_6_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_6_interrupt_IRQHandler - B scb_6_interrupt_IRQHandler - - PUBWEAK scb_7_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_7_interrupt_IRQHandler - B scb_7_interrupt_IRQHandler - - PUBWEAK csd_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -csd_interrupt_IRQHandler - B csd_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_0_IRQHandler - B cpuss_interrupts_dw0_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_1_IRQHandler - B cpuss_interrupts_dw0_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_2_IRQHandler - B cpuss_interrupts_dw0_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_3_IRQHandler - B cpuss_interrupts_dw0_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_4_IRQHandler - B cpuss_interrupts_dw0_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_5_IRQHandler - B cpuss_interrupts_dw0_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_6_IRQHandler - B cpuss_interrupts_dw0_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_7_IRQHandler - B cpuss_interrupts_dw0_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_8_IRQHandler - B cpuss_interrupts_dw0_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_9_IRQHandler - B cpuss_interrupts_dw0_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_10_IRQHandler - B cpuss_interrupts_dw0_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_11_IRQHandler - B cpuss_interrupts_dw0_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_12_IRQHandler - B cpuss_interrupts_dw0_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_13_IRQHandler - B cpuss_interrupts_dw0_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_14_IRQHandler - B cpuss_interrupts_dw0_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_15_IRQHandler - B cpuss_interrupts_dw0_15_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_0_IRQHandler - B cpuss_interrupts_dw1_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_1_IRQHandler - B cpuss_interrupts_dw1_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_2_IRQHandler - B cpuss_interrupts_dw1_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_3_IRQHandler - B cpuss_interrupts_dw1_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_4_IRQHandler - B cpuss_interrupts_dw1_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_5_IRQHandler - B cpuss_interrupts_dw1_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_6_IRQHandler - B cpuss_interrupts_dw1_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_7_IRQHandler - B cpuss_interrupts_dw1_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_8_IRQHandler - B cpuss_interrupts_dw1_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_9_IRQHandler - B cpuss_interrupts_dw1_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_10_IRQHandler - B cpuss_interrupts_dw1_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_11_IRQHandler - B cpuss_interrupts_dw1_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_12_IRQHandler - B cpuss_interrupts_dw1_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_13_IRQHandler - B cpuss_interrupts_dw1_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_14_IRQHandler - B cpuss_interrupts_dw1_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_15_IRQHandler - B cpuss_interrupts_dw1_15_IRQHandler - - PUBWEAK cpuss_interrupts_fault_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_0_IRQHandler - B cpuss_interrupts_fault_0_IRQHandler - - PUBWEAK cpuss_interrupts_fault_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_1_IRQHandler - B cpuss_interrupts_fault_1_IRQHandler - - PUBWEAK cpuss_interrupt_crypto_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_crypto_IRQHandler - B cpuss_interrupt_crypto_IRQHandler - - PUBWEAK cpuss_interrupt_fm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_fm_IRQHandler - B cpuss_interrupt_fm_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_0_IRQHandler - B cpuss_interrupts_cm0_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_1_IRQHandler - B cpuss_interrupts_cm0_cti_1_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_0_IRQHandler - B cpuss_interrupts_cm4_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_1_IRQHandler - B cpuss_interrupts_cm4_cti_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_0_IRQHandler - B tcpwm_0_interrupts_0_IRQHandler - - PUBWEAK tcpwm_0_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_1_IRQHandler - B tcpwm_0_interrupts_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_2_IRQHandler - B tcpwm_0_interrupts_2_IRQHandler - - PUBWEAK tcpwm_0_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_3_IRQHandler - B tcpwm_0_interrupts_3_IRQHandler - - PUBWEAK tcpwm_0_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_4_IRQHandler - B tcpwm_0_interrupts_4_IRQHandler - - PUBWEAK tcpwm_0_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_5_IRQHandler - B tcpwm_0_interrupts_5_IRQHandler - - PUBWEAK tcpwm_0_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_6_IRQHandler - B tcpwm_0_interrupts_6_IRQHandler - - PUBWEAK tcpwm_0_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_7_IRQHandler - B tcpwm_0_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_0_IRQHandler - B tcpwm_1_interrupts_0_IRQHandler - - PUBWEAK tcpwm_1_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_1_IRQHandler - B tcpwm_1_interrupts_1_IRQHandler - - PUBWEAK tcpwm_1_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_2_IRQHandler - B tcpwm_1_interrupts_2_IRQHandler - - PUBWEAK tcpwm_1_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_3_IRQHandler - B tcpwm_1_interrupts_3_IRQHandler - - PUBWEAK tcpwm_1_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_4_IRQHandler - B tcpwm_1_interrupts_4_IRQHandler - - PUBWEAK tcpwm_1_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_5_IRQHandler - B tcpwm_1_interrupts_5_IRQHandler - - PUBWEAK tcpwm_1_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_6_IRQHandler - B tcpwm_1_interrupts_6_IRQHandler - - PUBWEAK tcpwm_1_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_7_IRQHandler - B tcpwm_1_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_8_IRQHandler - B tcpwm_1_interrupts_8_IRQHandler - - PUBWEAK tcpwm_1_interrupts_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_9_IRQHandler - B tcpwm_1_interrupts_9_IRQHandler - - PUBWEAK tcpwm_1_interrupts_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_10_IRQHandler - B tcpwm_1_interrupts_10_IRQHandler - - PUBWEAK tcpwm_1_interrupts_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_11_IRQHandler - B tcpwm_1_interrupts_11_IRQHandler - - PUBWEAK tcpwm_1_interrupts_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_12_IRQHandler - B tcpwm_1_interrupts_12_IRQHandler - - PUBWEAK tcpwm_1_interrupts_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_13_IRQHandler - B tcpwm_1_interrupts_13_IRQHandler - - PUBWEAK tcpwm_1_interrupts_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_14_IRQHandler - B tcpwm_1_interrupts_14_IRQHandler - - PUBWEAK tcpwm_1_interrupts_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_15_IRQHandler - B tcpwm_1_interrupts_15_IRQHandler - - PUBWEAK tcpwm_1_interrupts_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_16_IRQHandler - B tcpwm_1_interrupts_16_IRQHandler - - PUBWEAK tcpwm_1_interrupts_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_17_IRQHandler - B tcpwm_1_interrupts_17_IRQHandler - - PUBWEAK tcpwm_1_interrupts_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_18_IRQHandler - B tcpwm_1_interrupts_18_IRQHandler - - PUBWEAK tcpwm_1_interrupts_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_19_IRQHandler - B tcpwm_1_interrupts_19_IRQHandler - - PUBWEAK tcpwm_1_interrupts_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_20_IRQHandler - B tcpwm_1_interrupts_20_IRQHandler - - PUBWEAK tcpwm_1_interrupts_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_21_IRQHandler - B tcpwm_1_interrupts_21_IRQHandler - - PUBWEAK tcpwm_1_interrupts_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_22_IRQHandler - B tcpwm_1_interrupts_22_IRQHandler - - PUBWEAK tcpwm_1_interrupts_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_23_IRQHandler - B tcpwm_1_interrupts_23_IRQHandler - - PUBWEAK udb_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_0_IRQHandler - B udb_interrupts_0_IRQHandler - - PUBWEAK udb_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_1_IRQHandler - B udb_interrupts_1_IRQHandler - - PUBWEAK udb_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_2_IRQHandler - B udb_interrupts_2_IRQHandler - - PUBWEAK udb_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_3_IRQHandler - B udb_interrupts_3_IRQHandler - - PUBWEAK udb_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_4_IRQHandler - B udb_interrupts_4_IRQHandler - - PUBWEAK udb_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_5_IRQHandler - B udb_interrupts_5_IRQHandler - - PUBWEAK udb_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_6_IRQHandler - B udb_interrupts_6_IRQHandler - - PUBWEAK udb_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_7_IRQHandler - B udb_interrupts_7_IRQHandler - - PUBWEAK udb_interrupts_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_8_IRQHandler - B udb_interrupts_8_IRQHandler - - PUBWEAK udb_interrupts_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_9_IRQHandler - B udb_interrupts_9_IRQHandler - - PUBWEAK udb_interrupts_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_10_IRQHandler - B udb_interrupts_10_IRQHandler - - PUBWEAK udb_interrupts_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_11_IRQHandler - B udb_interrupts_11_IRQHandler - - PUBWEAK udb_interrupts_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_12_IRQHandler - B udb_interrupts_12_IRQHandler - - PUBWEAK udb_interrupts_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_13_IRQHandler - B udb_interrupts_13_IRQHandler - - PUBWEAK udb_interrupts_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_14_IRQHandler - B udb_interrupts_14_IRQHandler - - PUBWEAK udb_interrupts_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_15_IRQHandler - B udb_interrupts_15_IRQHandler - - PUBWEAK pass_interrupt_sar_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_sar_IRQHandler - B pass_interrupt_sar_IRQHandler - - PUBWEAK audioss_interrupt_i2s_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_interrupt_i2s_IRQHandler - B audioss_interrupt_i2s_IRQHandler - - PUBWEAK audioss_interrupt_pdm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_interrupt_pdm_IRQHandler - B audioss_interrupt_pdm_IRQHandler - - PUBWEAK profile_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -profile_interrupt_IRQHandler - B profile_interrupt_IRQHandler - - PUBWEAK smif_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -smif_interrupt_IRQHandler - B smif_interrupt_IRQHandler - - PUBWEAK usb_interrupt_hi_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_hi_IRQHandler - B usb_interrupt_hi_IRQHandler - - PUBWEAK usb_interrupt_med_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_med_IRQHandler - B usb_interrupt_med_IRQHandler - - PUBWEAK usb_interrupt_lo_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_lo_IRQHandler - B usb_interrupt_lo_IRQHandler - - PUBWEAK pass_interrupt_dacs_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_dacs_IRQHandler - B pass_interrupt_dacs_IRQHandler - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c deleted file mode 100644 index 7800d6b2ef..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c +++ /dev/null @@ -1,390 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm4.c -* \version 2.70 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_sysclk.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default FastClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -uint32_t cy_BleEcoClockFreqHz = 0UL; - -/* SCB->CPACR */ -#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - -/* IPC_STRUCT7->DATA configuration */ -#define CY_STARTUP_CM0_DP_STATE (0x2uL) -#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1M_THRESHOLD (1000000u) - -uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - -uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* \cond -* Initializes the system: -* - Restores FLL registers to the default state for single core devices. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* \endcond -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - - Cy_SystemInit(); - SystemCoreClockUpdate(); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << - CY_STARTUP_IPC7_DP_OFFSET); - - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Allocate and initialize semaphores for the system operations. */ - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - #else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); - #endif /* (__CM0P_PRESENT) */ -#else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); -#endif /* __CM0P_PRESENT */ - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 - }; - - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - - if (0UL != locHf0Clock) - { - cy_Hfclk0FreqHz = locHf0Clock; - cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); - SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - - /* Sets clock frequency for Delay API */ - cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; - } -} - - -/******************************************************************************* -* Function Name: Cy_SystemInitFpuEnable -****************************************************************************//** -* -* Enables the FPU if it is used. The function is called from the startup file. -* -*******************************************************************************/ -void Cy_SystemInitFpuEnable(void) -{ - #if defined (__FPU_USED) && (__FPU_USED == 1U) - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; - __DSB(); - __ISB(); - Cy_SysLib_ExitCriticalSection(interruptState); - #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ -} - - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm4 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm4(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h deleted file mode 100644 index 8dd97ffb7a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h +++ /dev/null @@ -1,658 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6.h -* \version 2.70 -* -* \brief Device system header file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - - -#ifndef _SYSTEM_PSOC6_H_ -#define _SYSTEM_PSOC6_H_ - -/** -* \addtogroup group_system_config -* \{ -* Provides device startup, system configuration, and linker script files. -* The system startup provides the followings features: -* - See \ref group_system_config_device_initialization for the: -* * \ref group_system_config_dual_core_device_initialization -* * \ref group_system_config_single_core_device_initialization -* - \ref group_system_config_device_memory_definition -* - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps -* - \ref group_system_config_default_handlers -* - \ref group_system_config_device_vector_table -* - \ref group_system_config_cm4_functions -* -* \section group_system_config_configuration Configuration Considerations -* -* \subsection group_system_config_device_memory_definition Device Memory Definition -* The flash and RAM allocation for each CPU is defined by the linker scripts. -* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. -* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. -* For Single-Core devices the system reserves additional 80 bytes of RAM. -* Using the reserved memory area for other purposes will lead to unexpected behavior. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see warnings during the build process. To eliminate build -* warnings in your project, you can simply comment out or remove the relevant -* code in the linker file. -* -* ARM GCC\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 -* \endcode -* - 'xx_cm4_dual.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* ARM MDK\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see the warnings during the build process: -* L6314W (no section matches pattern) and/or L6329W -* (pattern only matches removed unused sections). In your project, you can -* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -* the linker. You can also comment out or remove the relevant code in the linker -* file. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 -* \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* IAR\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; -* \endcode -* - 'xx_cm4_dual.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* \subsection group_system_config_device_initialization Device Initialization -* After a power-on-reset (POR), the boot process is handled by the boot code -* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot -* code passes the control to the Cortex-M0+ startup code located in flash. -* -* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices -* The Cortex-M0+ startup code performs the device initialization by a call to -* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled -* by default. Enable the core using the \ref Cy_SysEnableCM4() function. -* See \ref group_system_config_cm4_functions for more details. -* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. -* The function has a separate implementation on each core. -* Both function implementations unlock and disable the WDT. -* Therefore enable the WDT after both cores have been initialized. -* -* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices -* The Cortex-M0+ core is not user-accessible on these devices. In this case the -* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. -* -* \subsection group_system_config_heap_stack_config Heap and Stack Configuration -* There are two ways to adjust heap and stack configurations: -* -# Editing source code files -* -# Specifying via command line -* -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. -* -* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* Change the heap and stack sizes by modifying the following lines:\n -* \code .equ Stack_Size, 0x00001000 \endcode -* \code .equ Heap_Size, 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode -* -* \subsubsection group_system_config_heap_stack_config_iar IAR -* - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', -* where 'xx' is the device family, and 'yy' is the target CPU; for example, -* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the -* linker (including quotation marks):\n -* \code --define_symbol __STACK_SIZE=0x000000400 \endcode -* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode -* -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* -* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition -* The default interrupt handler functions are defined as weak functions to a dummy -* handler in the startup file. The naming convention for the interrupt handler names -* is \_IRQHandler. A default interrupt handler can be overwritten in -* user code by defining the handler function using the same name. For example: -* \code -* void scb_0_interrupt_IRQHandler(void) -*{ -* ... -*} -* \endcode -* -* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM -* This process uses memory sections defined in the linker script. The startup -* code actually defines the contents of the vector table and performs the copy. -* \subsubsection group_system_config_device_vector_table_gcc ARM GCC -* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. -* It defines sections and locations in memory.\n -* Copy interrupt vectors from flash to RAM: \n -* From: \code LONG (__Vectors) \endcode -* To: \code LONG (__ram_vectors_start__) \endcode -* Size: \code LONG (__Vectors_End - __Vectors) \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table -* (RESET_RAM) shall be first in the RAM section.\n -* RESET_RAM represents the vector table. It is defined in the assembler startup -* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \subsubsection group_system_config_device_vector_table_iar IAR -* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* This file defines the .intvec_ram section and its location. -* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* -* \section group_system_config_MISRA MISRA Compliance -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
-* -* \section group_system_config_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.Provided support for SysPM driver updates.
Updated the linker scripts.Reserved FLASH area for the MCU boot headers.
Added System Pipe initialization for all devices. Improved PDL usability according to user experience.
Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. -* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. Defect fixing.
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n -* Removed $Sub$$main symbol for ARM MDK compiler. -* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n -* Added note about WDT disabling by SystemInit() function. -* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. -* Single core device support. -*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n -* Renamed 'wflash' memory region to 'em_eeprom'. -* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
-* -* -* \defgroup group_system_config_macro Macro -* \{ -* \defgroup group_system_config_system_macro System -* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status -* \defgroup group_system_config_user_settings_macro User Settings -* \} -* \defgroup group_system_config_functions Functions -* \{ -* \defgroup group_system_config_system_functions System -* \defgroup group_system_config_cm4_functions Cortex-M4 Control -* \} -* \defgroup group_system_config_globals Global Variables -* -* \} -*/ - -/** -* \addtogroup group_system_config_system_functions -* \{ -* \details -* The following system functions implement CMSIS Core functions. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* \} -*/ - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************************* -* Include files -*******************************************************************************/ -#include - - -/******************************************************************************* -* Global preprocessor symbols/macros ('define') -*******************************************************************************/ -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) - #define CY_SYSTEM_CPU_CM0P 1UL -#else - #define CY_SYSTEM_CPU_CM0P 0UL -#endif - - -/******************************************************************************* -* -* START OF USER SETTINGS HERE -* =========================== -* -* All lines with '<<<' can be set by user. -* -*******************************************************************************/ - -/** -* \addtogroup group_system_config_user_settings_macro -* \{ -*/ - - -/***************************************************************************//** -* \brief Start address of the Cortex-M4 application ([address]UL) -* (USER SETTING) -*******************************************************************************/ -#if !defined (CY_CORTEX_M4_APPL_ADDR) - #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ -#endif /* (CY_CORTEX_M4_APPL_ADDR) */ - - -/***************************************************************************//** -* \brief IPC Semaphores allocation ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ - - -/***************************************************************************//** -* \brief IPC Pipe definitions ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ - - -/******************************************************************************* -* -* END OF USER SETTINGS HERE -* ========================= -* -*******************************************************************************/ - -/** \} group_system_config_user_settings_macro */ - - -/** -* \addtogroup group_system_config_system_macro -* \{ -*/ - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M0+ startup driver identifier */ - #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - -#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M4 startup driver identifier */ - #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ - -/** \} group_system_config_system_macro */ - - -/** -* \addtogroup group_system_config_system_functions -* \{ -*/ -extern void SystemInit(void); - -extern void SystemCoreClockUpdate(void); -/** \} group_system_config_system_functions */ - - -/** -* \addtogroup group_system_config_cm4_functions -* \{ -*/ -extern uint32_t Cy_SysGetCM4Status(void); -extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); -extern void Cy_SysDisableCM4(void); -extern void Cy_SysRetainCM4(void); -extern void Cy_SysResetCM4(void); -/** \} group_system_config_cm4_functions */ - - -/** \cond */ -extern void Default_Handler (void); - -void Cy_SysIpcPipeIsrCm0(void); -void Cy_SysIpcPipeIsrCm4(void); - -extern void Cy_SystemInit(void); -extern void Cy_SystemInitFpuEnable(void); - -extern uint32_t cy_delayFreqKhz; -extern uint8_t cy_delayFreqMhz; -extern uint32_t cy_delay32kMs; -/** \endcond */ - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/** -* \addtogroup group_system_config_cm4_status_macro -* \{ -*/ -#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ -#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ -#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ -#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ -/** \} group_system_config_cm4_status_macro */ - -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - - -/******************************************************************************* -* IPC Configuration -* ========================= -*******************************************************************************/ -/* IPC CY_PIPE default configuration */ -#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) - -#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ - -#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) - - -/******************************************************************************/ -/* - * The System pipe configuration defines the IPC channel number, interrupt - * number, and the pipe interrupt mask for the endpoint. - * - * The format of the endPoint configuration - * Bits[31:16] Interrupt Mask - * Bits[15:8 ] IPC interrupt - * Bits[ 7:0 ] IPC channel - */ - -/* System Pipe addresses */ -/* CyPipe defines */ - -#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) - -#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) - -/******************************************************************************/ - - -/** \addtogroup group_system_config_globals -* \{ -*/ - -extern uint32_t SystemCoreClock; -extern uint32_t cy_BleEcoClockFreqHz; -extern uint32_t cy_Hfclk0FreqHz; -extern uint32_t cy_PeriClkFreqHz; - -/** \} group_system_config_globals */ - - - -/** \cond INTERNAL */ -/******************************************************************************* -* Backward compatibility macros. The following code is DEPRECATED and must -* not be used in new projects -*******************************************************************************/ - -/* BWC defines for functions related to enter/exit critical section */ -#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection -#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection -#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) -#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) -#define cy_delayFreqHz (SystemCoreClock) - -/** \endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_PSOC6_H_ */ - - -/* [] END OF FILE */ diff --git a/targets/targets.json b/targets/targets.json index 77d7aa4dd3..4df9929d28 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8864,38 +8864,6 @@ ], "bootloader_supported": false }, - "CY8CPROTO_063_BLE": { - "inherits": [ - "MCU_PSOC6_M4" - ], - "components_remove": [ - "QSPIF" - ], - "device_has_remove": [ - "USBDEVICE", - "QSPI" - ], - "extra_labels_add": [ - "PSOC6_01", - "MXCRYPTO_01" - ], - "macros_add": [ - "CYBLE_416045_02" - ], - "device_name": "CYBLE-416045-02", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x00045800", - "detect_code": [ - "1904" - ], - "sectors": [ - [ - 268443648, - 512 - ] - ], - "bootloader_supported": false - }, "CY8CPROTO_064_SB": { "inherits": [ "MCU_PSOC6_M4"