From 84dc7f82d55267fee3565c9c802fa0dc4956af1c Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 15 Dec 2017 10:09:20 +0100 Subject: [PATCH 001/118] STM32F1: Add Flash API support --- .../TARGET_STM32F1/common_objects.h | 7 + targets/TARGET_STM/TARGET_STM32F1/flash_api.c | 226 ++++++++++++++++++ targets/targets.json | 2 +- 3 files changed, 234 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F1/flash_api.c diff --git a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h index 3bd078970c..d57c6128f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h @@ -124,6 +124,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #include "gpio_object.h" #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c new file mode 100644 index 0000000000..1a5f335181 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c @@ -0,0 +1,226 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "mbed_assert.h" +#include "cmsis.h" + +#ifndef FLASH_SIZE +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) +#endif + +// Minimum number of bytes to be programmed at a time +#define MIN_PROG_SIZE (4U) + +/** Initialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +/** Uninitialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Falsh */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + uint32_t PAGEError = 0; + FLASH_EraseInitTypeDef EraseInitStruct; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + // Clear Flash status register's flags + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_OPTVERR); + + /* MBED HAL erases 1 sector at a time */ + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.PageAddress = address; + EraseInitStruct.NbPages = 1; + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; +} + +/** Program one page starting at defined address + * + * The page should be at page boundary, should not cross multiple sectors. + * This function does not do any check for address alignments or if size + * is aligned to a page size. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t flash_program_page(flash_t *obj, uint32_t address, + const uint8_t *data, uint32_t size) +{ + uint32_t StartAddress = 0; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if ((size % MIN_PROG_SIZE) != 0) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Program the user Flash area word by word */ + StartAddress = address; + + /* HW needs an aligned address to program flash, which data parameter doesn't ensure */ + if ((uint32_t) data % 4 != 0) { + + volatile uint32_t data32; + while (address < (StartAddress + size) && (status == 0)) { + for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) { + *(((uint8_t *) &data32) + i) = *(data + i); + } + + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } else { /* case where data is aligned, so let's avoid any copy */ + while ((address < (StartAddress + size)) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } + + flash_lock(); + + return status; +} + +/** Get sector size + * + * @param obj The flash object + * @param address The sector starting address + * @return The size of a sector (in our case considering 1 sector = 1 page) + */ +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return MBED_FLASH_INVALID_SIZE; + } else { + return FLASH_PAGE_SIZE; + } +} + +/** Get page size + * + * @param obj The flash object + * @param address The page starting address + * @return The size of a page (in our case the minimum programmable size) + */ +uint32_t flash_get_page_size(const flash_t *obj) +{ + return MIN_PROG_SIZE; +} + +/** Get start address for the flash region + * + * @param obj The flash object + * @return The start address for the flash region + */ +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +/** Get the flash region size + * + * @param obj The flash object + * @return The flash region size + */ +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +#endif diff --git a/targets/targets.json b/targets/targets.json index dfd17df2b5..54aa84a9e6 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -881,7 +881,7 @@ } }, "detect_code": ["0700"], - "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F103RB" }, From 39d38eb245f72c7ea6f5e514ab851161098e199f Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 15 Dec 2017 11:11:35 +0100 Subject: [PATCH 002/118] STM32F0: Add Flash API support --- .../TARGET_STM32F0/common_objects.h | 7 + targets/TARGET_STM/TARGET_STM32F0/flash_api.c | 226 ++++++++++++++++++ targets/targets.json | 6 +- 3 files changed, 236 insertions(+), 3 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F0/flash_api.c diff --git a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h index c6ebc7bd02..fee640796f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h @@ -136,6 +136,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c new file mode 100644 index 0000000000..27e42a3c1b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c @@ -0,0 +1,226 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "mbed_assert.h" +#include "cmsis.h" + +#ifndef FLASH_SIZE +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) +#endif + +// Minimum number of bytes to be programmed at a time +#define MIN_PROG_SIZE (4U) + +/** Initialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +/** Uninitialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Falsh */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + uint32_t PAGEError = 0; + FLASH_EraseInitTypeDef EraseInitStruct; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + // Clear Flash status register's flags + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + /* MBED HAL erases 1 sector at a time */ + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.PageAddress = address; + EraseInitStruct.NbPages = 1; + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; +} + +/** Program one page starting at defined address + * + * The page should be at page boundary, should not cross multiple sectors. + * This function does not do any check for address alignments or if size + * is aligned to a page size. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t flash_program_page(flash_t *obj, uint32_t address, + const uint8_t *data, uint32_t size) +{ + uint32_t StartAddress = 0; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if ((size % MIN_PROG_SIZE) != 0) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Program the user Flash area word by word */ + StartAddress = address; + + /* HW needs an aligned address to program flash, which data parameter doesn't ensure */ + if ((uint32_t) data % 4 != 0) { + + volatile uint32_t data32; + while (address < (StartAddress + size) && (status == 0)) { + for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) { + *(((uint8_t *) &data32) + i) = *(data + i); + } + + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } else { /* case where data is aligned, so let's avoid any copy */ + while ((address < (StartAddress + size)) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } + + flash_lock(); + + return status; +} + +/** Get sector size + * + * @param obj The flash object + * @param address The sector starting address + * @return The size of a sector (in our case considering 1 sector = 1 page) + */ +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return MBED_FLASH_INVALID_SIZE; + } else { + return FLASH_PAGE_SIZE; + } +} + +/** Get page size + * + * @param obj The flash object + * @param address The page starting address + * @return The size of a page (in our case the minimum programmable size) + */ +uint32_t flash_get_page_size(const flash_t *obj) +{ + return MIN_PROG_SIZE; +} + +/** Get start address for the flash region + * + * @param obj The flash object + * @return The start address for the flash region + */ +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +/** Get the flash region size + * + * @param obj The flash object + * @return The flash region size + */ +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +#endif diff --git a/targets/targets.json b/targets/targets.json index 54aa84a9e6..a80d2ed758 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -823,7 +823,7 @@ }, "detect_code": ["0755"], "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], - "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F070RB" }, @@ -841,7 +841,7 @@ }, "detect_code": ["0730"], "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F072RB" }, @@ -859,7 +859,7 @@ }, "detect_code": ["0750"], "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F091RC" }, From 8589a21f44ddd5d3b11484dbbc992dda3afef248 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 18 Dec 2017 15:28:41 +0100 Subject: [PATCH 003/118] STM32F0: Remove flash functions doc --- targets/TARGET_STM/TARGET_STM32F0/flash_api.c | 81 ++++--------------- 1 file changed, 15 insertions(+), 66 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c index 27e42a3c1b..9a2d7c4c8e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c @@ -28,29 +28,9 @@ // Minimum number of bytes to be programmed at a time #define MIN_PROG_SIZE (4U) -/** Initialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_init(flash_t *obj) -{ - return 0; -} - -/** Uninitialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_free(flash_t *obj) -{ - return 0; -} - static int32_t flash_unlock(void) { - /* Allow Access to Flash control registers and user Falsh */ + /* Allow Access to Flash control registers and user Flash */ if (HAL_FLASH_Unlock()) { return -1; } else { @@ -69,13 +49,16 @@ static int32_t flash_lock(void) } } -/** Erase one sector starting at defined address - * - * The address should be at sector boundary. This function does not do any check for address alignments - * @param obj The flash object - * @param address The sector starting address - * @return 0 for success, -1 for error - */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + int32_t flash_erase_sector(flash_t *obj, uint32_t address) { uint32_t PAGEError = 0; @@ -113,19 +96,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return status; } -/** Program one page starting at defined address - * - * The page should be at page boundary, should not cross multiple sectors. - * This function does not do any check for address alignments or if size - * is aligned to a page size. - * @param obj The flash object - * @param address The sector starting address - * @param data The data buffer to be programmed - * @param size The number of bytes to program - * @return 0 for success, -1 for error - */ -int32_t flash_program_page(flash_t *obj, uint32_t address, - const uint8_t *data, uint32_t size) +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) { uint32_t StartAddress = 0; int32_t status = 0; @@ -177,13 +148,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return status; } -/** Get sector size - * - * @param obj The flash object - * @param address The sector starting address - * @return The size of a sector (in our case considering 1 sector = 1 page) - */ -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { return MBED_FLASH_INVALID_SIZE; @@ -192,33 +157,17 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) } } -/** Get page size - * - * @param obj The flash object - * @param address The page starting address - * @return The size of a page (in our case the minimum programmable size) - */ uint32_t flash_get_page_size(const flash_t *obj) { return MIN_PROG_SIZE; } -/** Get start address for the flash region - * - * @param obj The flash object - * @return The start address for the flash region - */ -uint32_t flash_get_start_address(const flash_t *obj) +uint32_t flash_get_start_address(const flash_t *obj) { return FLASH_BASE; } -/** Get the flash region size - * - * @param obj The flash object - * @return The flash region size - */ -uint32_t flash_get_size(const flash_t *obj) +uint32_t flash_get_size(const flash_t *obj) { return FLASH_SIZE; } From c71e50ea8c2cb772ff42f88127d957e212fa7ad0 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 18 Dec 2017 15:31:56 +0100 Subject: [PATCH 004/118] STM32F1: Remove flash functions doc --- targets/TARGET_STM/TARGET_STM32F1/flash_api.c | 81 ++++--------------- 1 file changed, 15 insertions(+), 66 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c index 1a5f335181..46c6040ae4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c @@ -28,29 +28,9 @@ // Minimum number of bytes to be programmed at a time #define MIN_PROG_SIZE (4U) -/** Initialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_init(flash_t *obj) -{ - return 0; -} - -/** Uninitialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_free(flash_t *obj) -{ - return 0; -} - static int32_t flash_unlock(void) { - /* Allow Access to Flash control registers and user Falsh */ + /* Allow Access to Flash control registers and user Flash */ if (HAL_FLASH_Unlock()) { return -1; } else { @@ -69,13 +49,16 @@ static int32_t flash_lock(void) } } -/** Erase one sector starting at defined address - * - * The address should be at sector boundary. This function does not do any check for address alignments - * @param obj The flash object - * @param address The sector starting address - * @return 0 for success, -1 for error - */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + int32_t flash_erase_sector(flash_t *obj, uint32_t address) { uint32_t PAGEError = 0; @@ -113,19 +96,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return status; } -/** Program one page starting at defined address - * - * The page should be at page boundary, should not cross multiple sectors. - * This function does not do any check for address alignments or if size - * is aligned to a page size. - * @param obj The flash object - * @param address The sector starting address - * @param data The data buffer to be programmed - * @param size The number of bytes to program - * @return 0 for success, -1 for error - */ -int32_t flash_program_page(flash_t *obj, uint32_t address, - const uint8_t *data, uint32_t size) +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) { uint32_t StartAddress = 0; int32_t status = 0; @@ -177,13 +148,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return status; } -/** Get sector size - * - * @param obj The flash object - * @param address The sector starting address - * @return The size of a sector (in our case considering 1 sector = 1 page) - */ -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { return MBED_FLASH_INVALID_SIZE; @@ -192,33 +157,17 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) } } -/** Get page size - * - * @param obj The flash object - * @param address The page starting address - * @return The size of a page (in our case the minimum programmable size) - */ uint32_t flash_get_page_size(const flash_t *obj) { return MIN_PROG_SIZE; } -/** Get start address for the flash region - * - * @param obj The flash object - * @return The start address for the flash region - */ -uint32_t flash_get_start_address(const flash_t *obj) +uint32_t flash_get_start_address(const flash_t *obj) { return FLASH_BASE; } -/** Get the flash region size - * - * @param obj The flash object - * @return The flash region size - */ -uint32_t flash_get_size(const flash_t *obj) +uint32_t flash_get_size(const flash_t *obj) { return FLASH_SIZE; } From 3d2894df822f05c8da4e466e3c3d72da117656f9 Mon Sep 17 00:00:00 2001 From: amq Date: Wed, 25 Oct 2017 10:40:10 +0200 Subject: [PATCH 005/118] Add missing device_name for targets with bootloader --- targets/targets.json | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index a80d2ed758..85b1af66ca 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2906,6 +2906,7 @@ "macros_add": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], + "device_name": "EFM32PG12B500F1024GL125", "public": false, "bootloader_supported": true }, @@ -2958,6 +2959,7 @@ "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], + "device_name": "EFR32MG12P332F1024GL125", "public": false, "bootloader_supported": true }, From 3dc3201d26c0c2688fd419caf2c53ced37511580 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mika=20Lepp=C3=A4nen?= Date: Fri, 3 Nov 2017 15:54:22 +0200 Subject: [PATCH 006/118] Tests for wifi emac interface --- TESTS/network/emac/README.md | 28 ++ TESTS/network/emac/emac_ctp.cpp | 143 ++++++ TESTS/network/emac/emac_ctp.h | 31 ++ TESTS/network/emac/emac_initialize.h | 24 + TESTS/network/emac/emac_membuf.cpp | 83 ++++ TESTS/network/emac/emac_membuf.h | 24 + TESTS/network/emac/emac_test_broadcast.cpp | 73 +++ TESTS/network/emac/emac_test_initialize.cpp | 140 ++++++ TESTS/network/emac/emac_test_unicast.cpp | 67 +++ .../emac/emac_test_unicast_frame_len.cpp | 72 +++ TESTS/network/emac/emac_tests.h | 26 ++ TESTS/network/emac/emac_util.cpp | 436 ++++++++++++++++++ TESTS/network/emac/emac_util.h | 93 ++++ TESTS/network/emac/main.cpp | 71 +++ TESTS/network/emac/template_mbed_app.txt | 32 ++ 15 files changed, 1343 insertions(+) create mode 100644 TESTS/network/emac/README.md create mode 100644 TESTS/network/emac/emac_ctp.cpp create mode 100644 TESTS/network/emac/emac_ctp.h create mode 100644 TESTS/network/emac/emac_initialize.h create mode 100644 TESTS/network/emac/emac_membuf.cpp create mode 100644 TESTS/network/emac/emac_membuf.h create mode 100644 TESTS/network/emac/emac_test_broadcast.cpp create mode 100644 TESTS/network/emac/emac_test_initialize.cpp create mode 100644 TESTS/network/emac/emac_test_unicast.cpp create mode 100644 TESTS/network/emac/emac_test_unicast_frame_len.cpp create mode 100644 TESTS/network/emac/emac_tests.h create mode 100644 TESTS/network/emac/emac_util.cpp create mode 100644 TESTS/network/emac/emac_util.h create mode 100644 TESTS/network/emac/main.cpp create mode 100644 TESTS/network/emac/template_mbed_app.txt diff --git a/TESTS/network/emac/README.md b/TESTS/network/emac/README.md new file mode 100644 index 0000000000..610f7a7c42 --- /dev/null +++ b/TESTS/network/emac/README.md @@ -0,0 +1,28 @@ +# Description + +This document describes how to run EMAC tests. The EMAC test cases are made using Ethernet Configuration Testing Protocol (CTP). To run the tests, one device in the Ethernet segment needs to be configured to be a CTP echo server. The devices running the test cases, use the echo server to forward the CTP Ethernet frames back. + +# Configuring CTP echo server + +A device can be configured to be a CTP echo server by enabling `echo-server` setting in the test environment's application `json` file. When device is configured to be a CTP echo server, it starts to forward CTP messages automatically after power up and will continue forwarding until power down. + +# Test cases + +## EMAC interface initialise + +Initializes EMAC interface driver. + +For WLAN installs test case so that it can intercept incoming Ethernet messages from the WLAN driver. Incoming CTP frames are handed by the test case and other frames are forwarded to the LWIP stack. + +## EMAC interface broadcast + +Sends three 100 byte CTP broadcast messages, waits for three seconds and sends three 50 byte CTP broadcast messages. Listens for the CTP echo server responses and stores the addresses of the echo servers if replies are received. The test case will pass if there are no responses from echo server, but further test cases will be skipped. + +## EMAC interface unicast + +Sends three CTP unicast messages to the CTP echo server. Verifies that all are replied. + +## EMAC interface unicast frame length + +Sends CTP unicast messages with Ethernet message length from 100 bytes to maximum. Verifies that all are replied. + diff --git a/TESTS/network/emac/emac_ctp.cpp b/TESTS/network/emac/emac_ctp.cpp new file mode 100644 index 0000000000..308f29f988 --- /dev/null +++ b/TESTS/network/emac/emac_ctp.cpp @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "mbed.h" + +#include "lwip/opt.h" /* ETH_PAD_SIZE */ + +#include "emac_stack_mem.h" +#include "emac_api.h" + +#include "emac_tests.h" +#include "emac_ctp.h" + +#include "emac_initialize.h" +#include "emac_util.h" +#include "emac_membuf.h" + +using namespace utest::v1; + +// Unique identifier for message +static int receipt_number = 0; + +static int emac_if_ctp_header_build(unsigned char *eth_frame, const unsigned char *dest_addr, const unsigned char *origin_addr, const unsigned char *forward_addr) +{ + memcpy(ð_frame[0], dest_addr, 6); + memcpy(ð_frame[6], origin_addr, 6); + + eth_frame[12] = 0x90; /* loop back */ + eth_frame[13] = 0x00; + + eth_frame[14] = 0x00; /* skip count */ + eth_frame[15] = 0x00; + + eth_frame[16] = 0x02; /* function, forward */ + eth_frame[17] = 0x00; + + memcpy(ð_frame[18], forward_addr, 6); + + eth_frame[24] = 0x01; /* function, reply */ + eth_frame[25] = 0x00; + + receipt_number++; + + eth_frame[26] = receipt_number; /* receipt number */ + eth_frame[27] = receipt_number >> 8; + + return receipt_number; +} + +ctp_function emac_if_ctp_header_handle(unsigned char *eth_input_frame, unsigned char *eth_output_frame, unsigned char *origin_addr, int *receipt_number) +{ + if (eth_input_frame[12] != 0x90 || eth_input_frame[13] != 0x00) { + return CTP_NONE; + } + + int skip_count = eth_input_frame[15] << 8 | eth_input_frame[14]; + unsigned char *ethernet_ptr = ð_input_frame[16] + skip_count; + + int function = ethernet_ptr[1] << 8 | ethernet_ptr[0]; + ethernet_ptr += 2; + + // Forward + if (function == 0x0002) { + memcpy(eth_output_frame, eth_input_frame, ETH_FRAME_HEADER_LEN); + // Update skip count + skip_count += 8; + eth_output_frame[14] = skip_count; + eth_output_frame[15] = skip_count >> 8; + // Set forward address to destination address + memcpy(ð_output_frame[0], ethernet_ptr, 6); + // Copy own address to origin + memcpy(ð_output_frame[6], origin_addr, 6); + return CTP_FORWARD; + // reply + } else if (function == 0x0001) { + *receipt_number = ethernet_ptr[1] << 8 | ethernet_ptr[0]; + return CTP_REPLY; + } + + return CTP_NONE; +} + +void emac_if_ctp_msg_build(int eth_frame_len, const unsigned char *dest_addr, const unsigned char *origin_addr, const unsigned char *forward_addr) +{ + if (eth_frame_len < ETH_FRAME_HEADER_LEN) { + eth_frame_len = ETH_FRAME_HEADER_LEN; + } + + printf("message sent %x:%x:%x:%x:%x:%x\r\n\r\n", dest_addr[0], dest_addr[1], dest_addr[2], dest_addr[3], dest_addr[4], dest_addr[5]); + + int outgoing_msg_index = emac_if_add_outgoing_msg(eth_frame_len); + + if (outgoing_msg_index < 0) { + SET_ERROR_FLAGS(OUT_OF_MSG_DATA); + return; + } + + emac_stack_mem_chain_t *mem_chain_p = emac_stack_mem_alloc(0, eth_frame_len + ETH_PAD_SIZE, 0); + + if (!mem_chain_p) { + SET_ERROR_FLAGS(NO_FREE_MEM_BUF); + emac_if_free_outgoing_msg(outgoing_msg_index); + return; + } + + if (memcmp(dest_addr, eth_mac_broadcast_addr, 6) == 0) { + emac_if_set_outgoing_msg_flags(outgoing_msg_index, BROADCAST); + } + + unsigned char eth_output_frame_data[ETH_FRAME_HEADER_LEN]; + int receipt_number = emac_if_ctp_header_build(eth_output_frame_data, dest_addr, origin_addr, forward_addr); + emac_if_set_outgoing_msg_receipt_num(outgoing_msg_index, receipt_number); + + emac_if_memory_buffer_write(mem_chain_p, eth_output_frame_data, true); + + //emac_if->ops.link_out(hw_driver, mem_chain_p); + emac_if_get()->ops.link_out(emac_if_get(), mem_chain_p); + + emac_stack_mem_free(0, mem_chain_p); +} + +#endif + diff --git a/TESTS/network/emac/emac_ctp.h b/TESTS/network/emac/emac_ctp.h new file mode 100644 index 0000000000..97c18e6a91 --- /dev/null +++ b/TESTS/network/emac/emac_ctp.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_CTP_H +#define EMAC_CTP_H + +enum ctp_function { + CTP_NONE, + CTP_FORWARD, + CTP_REPLY +}; + +ctp_function emac_if_ctp_header_handle(unsigned char *eth_input_frame, unsigned char *eth_output_frame, unsigned char *origin_addr, int *receipt_number); +void emac_if_ctp_msg_build(int eth_frame_len, const unsigned char *dest_addr, const unsigned char *origin_addr, const unsigned char *forward_addr); +void emac_if_ctp_reply_handle(int lenght, int invalid_data_index); + +#endif /* EMAC_CTP_H */ diff --git a/TESTS/network/emac/emac_initialize.h b/TESTS/network/emac/emac_initialize.h new file mode 100644 index 0000000000..307b7c47f6 --- /dev/null +++ b/TESTS/network/emac/emac_initialize.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_INITIALIZE_H +#define EMAC_INITIALIZE_H + +uint8_t *emac_if_get_hw_addr(void); +emac_interface_t *emac_if_get(void); + +#endif /* EMAC_INITIALIZE_H */ diff --git a/TESTS/network/emac/emac_membuf.cpp b/TESTS/network/emac/emac_membuf.cpp new file mode 100644 index 0000000000..1b5f31d685 --- /dev/null +++ b/TESTS/network/emac/emac_membuf.cpp @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "lwip/opt.h" /* ETH_PAD_SIZE */ + +#include "emac_api.h" +#include "emac_stack_mem.h" + +#include "emac_membuf.h" +#include "emac_util.h" + +int emac_if_memory_buffer_read(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame) +{ + int eth_frame_index = 0; + int invalid_data_index = 0; + int index = ETH_PAD_SIZE; + + for (emac_stack_mem_t *mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p); mem_p != NULL; mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p)) { + unsigned char *buf_payload = (unsigned char *) emac_stack_mem_ptr(0, mem_p); + int buf_payload_len = emac_stack_mem_len(0, mem_p); + + for (; index < buf_payload_len; index++) { + if (eth_frame_index < ETH_FRAME_HEADER_LEN) { + eth_frame[eth_frame_index] = buf_payload[index]; + } else { + if (buf_payload[index] != (uint8_t) eth_frame_index) { + invalid_data_index = eth_frame_index; + break; + } + } + eth_frame_index++; + } + index = 0; + } + + return invalid_data_index; +} + +void emac_if_memory_buffer_write(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame, bool write_data) +{ + int eth_frame_index = 0; + int index = ETH_PAD_SIZE; + + for (emac_stack_mem_t *mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p); mem_p != NULL; mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p)) { + unsigned char *buf_payload = (unsigned char *) emac_stack_mem_ptr(0, mem_p); + int buf_payload_len = emac_stack_mem_len(0, mem_p); + + for (; index < buf_payload_len; index++) { + if (eth_frame_index < ETH_FRAME_HEADER_LEN) { + buf_payload[index] = eth_frame[eth_frame_index]; + } else if (write_data) { + buf_payload[index] = (char) eth_frame_index; + } else { + break; + } + eth_frame_index++; + } + index = 0; + } +} + +#endif diff --git a/TESTS/network/emac/emac_membuf.h b/TESTS/network/emac/emac_membuf.h new file mode 100644 index 0000000000..b02f0692c3 --- /dev/null +++ b/TESTS/network/emac/emac_membuf.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_MEMBUF_H +#define EMAC_MEMBUF_H + +int emac_if_memory_buffer_read(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame); +void emac_if_memory_buffer_write(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame, bool write_data); + +#endif /* EMAC_MEMBUF_H */ diff --git a/TESTS/network/emac/emac_test_broadcast.cpp b/TESTS/network/emac/emac_test_broadcast.cpp new file mode 100644 index 0000000000..1b5588cf5d --- /dev/null +++ b/TESTS/network/emac/emac_test_broadcast.cpp @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "emac_tests.h" +#include "emac_util.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +void test_emac_broadcast_cb(void) +{ + emac_if_validate_outgoing_msg(); + + static int counter = 0; + + // Send three broadcast + if (counter < 3) { + emac_if_ctp_msg_build(100, eth_mac_broadcast_addr, emac_if_get_own_addr(), emac_if_get_own_addr()); + counter++; + } else if (counter < 6) { + counter++; + } else if (counter < 9) { + emac_if_ctp_msg_build(50, eth_mac_broadcast_addr, emac_if_get_own_addr(), emac_if_get_own_addr()); + counter++; + } else if (counter < 12) { + counter++; + } else if (counter == 12) { + emac_if_reset_outgoing_msg(); + // ignore errors since just probing + RESET_ERROR_FLAGS; +#if MBED_CONF_APP_ECHO_SERVER + printf("echo server started successfully\r\n\r\n"); + counter = 255; +#else + worker_loop_end(); +#endif + } +} + +void test_emac_broadcast(void) +{ + RESET_ERROR_FLAGS; + SET_TRACE_LEVEL(TRACE_ETH_FRAMES | TRACE_SUCCESS | TRACE_FAILURE); + + worker_loop_start(test_emac_broadcast_cb, 10 * SECOND_TO_MS); + + PRINT_ERROR_FLAGS; + TEST_ASSERT_FALSE(ERROR_FLAGS); + RESET_OUTGOING_MSG_DATA; +} + +#endif diff --git a/TESTS/network/emac/emac_test_initialize.cpp b/TESTS/network/emac/emac_test_initialize.cpp new file mode 100644 index 0000000000..64cd5f907e --- /dev/null +++ b/TESTS/network/emac/emac_test_initialize.cpp @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "inttypes.h" + +#if MBED_CONF_APP_TEST_WIFI +#ifdef TARGET_UBLOX_EVK_ODIN_W2 +#include "wifi_emac_api.h" +#include "OdinWiFiInterface.h" +#endif +#ifdef TARGET_REALTEK_RTL8195AM +#include "rtw_emac.h" +#include "RTWInterface.h" +#endif +#endif + +#include "emac_api.h" +#include "emac_tests.h" +#include "emac_util.h" + +using namespace utest::v1; + +static unsigned char eth_mac_addr[ETH_MAC_ADDR_LEN]; + +static char emac_if_link_state_change_cb_data[] = "link_state_change_cb_data"; +static char emac_if_link_input_cb_data[] = "link_input_cb_data"; + +static bool emac_if_init(void); + +void test_emac_initialize() +{ +#if MBED_CONF_APP_TEST_WIFI + static WiFiInterface *wifi; + +#ifdef TARGET_UBLOX_EVK_ODIN_W2 + wifi = new OdinWiFiInterface; +#endif +#ifdef TARGET_REALTEK_RTL8195AM + wifi = new RTWInterface; +#endif + +#if MBED_CONF_APP_WIFI_SCAN + WiFiAccessPoint ap[30]; + + int size = wifi->scan(ap, 30); + + for (int i=0; iset_credentials(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, MBED_CONF_APP_WIFI_SECURITY); + wifi->connect(); + + const char *ip_addr = wifi->get_ip_address(); + printf("connected IP %s\r\n\r\n", ip_addr); +#endif + + TEST_ASSERT(emac_if_init()); +} + +unsigned char *emac_if_get_hw_addr(void) +{ + return ð_mac_addr[0]; +} + +emac_interface_t *emac_if_get(void) +{ +#if MBED_CONF_APP_TEST_WIFI +#ifdef TARGET_UBLOX_EVK_ODIN_W2 + return wifi_emac_get_interface(); +#endif +#ifdef TARGET_REALTEK_RTL8195AM + return wlan_emac_init_interface(); +#endif +#else + return 0; +#endif +} + +static bool emac_if_init(void) +{ + emac_interface_t *emac_if = emac_if_get(); + + emac_if->ops.set_link_input_cb(emac_if, emac_if_link_input_cb, emac_if_link_input_cb_data); + emac_if->ops.set_link_state_cb(emac_if, emac_if_link_state_change_cb, emac_if_link_state_change_cb_data); + + int hwaddr_len = emac_if->ops.get_hwaddr_size(emac_if); + printf("emac hwaddr length %i\r\n\r\n", hwaddr_len); + + if (hwaddr_len == 6) { + emac_if->ops.get_hwaddr(emac_if, eth_mac_addr); + printf("emac hwaddr %x:%x:%x:%x:%x:%x\r\n\r\n", eth_mac_addr[0],eth_mac_addr[1],eth_mac_addr[2],eth_mac_addr[3],eth_mac_addr[4],eth_mac_addr[5]); + } + + int mtu = emac_if->ops.get_mtu_size(emac_if); + printf("emac mtu %i\r\n\r\n", mtu); + + char hw_name[11]; + emac_if->ops.get_ifname(emac_if, hw_name, 10); + printf("emac if name %s\r\n\r\n", hw_name); + + if (!emac_if->ops.power_up(emac_if)) { + return false; + } + + return true; +} + +#endif diff --git a/TESTS/network/emac/emac_test_unicast.cpp b/TESTS/network/emac/emac_test_unicast.cpp new file mode 100644 index 0000000000..ee4088c647 --- /dev/null +++ b/TESTS/network/emac/emac_test_unicast.cpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "emac_tests.h" +#include "emac_util.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +void test_emac_unicast_cb(void) +{ + emac_if_validate_outgoing_msg(); + + static uint8_t counter = 0; + + // Send three unicast + if (counter < 3) { + emac_if_ctp_msg_build(100, emac_if_get_echo_server_addr(0), emac_if_get_own_addr(), emac_if_get_own_addr()); + } + + // End test + if (counter > 10) { + worker_loop_end(); + + if (emac_if_count_outgoing_msg() != 0) { + SET_ERROR_FLAGS(TEST_FAILED); + } + } + counter++; +} + +void test_emac_unicast() +{ + RESET_ERROR_FLAGS; + SET_TRACE_LEVEL(TRACE_ETH_FRAMES | TRACE_SUCCESS | TRACE_FAILURE); + + if (emac_if_count_echo_server_addr()) { + worker_loop_start(test_emac_unicast_cb, 1 * SECOND_TO_MS); + } + + PRINT_ERROR_FLAGS; + TEST_ASSERT_FALSE(ERROR_FLAGS); + RESET_OUTGOING_MSG_DATA; +} + +#endif diff --git a/TESTS/network/emac/emac_test_unicast_frame_len.cpp b/TESTS/network/emac/emac_test_unicast_frame_len.cpp new file mode 100644 index 0000000000..96aed45d13 --- /dev/null +++ b/TESTS/network/emac/emac_test_unicast_frame_len.cpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "emac_tests.h" +#include "emac_util.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +void test_emac_unicast_frame_len_cb(void) +{ + emac_if_validate_outgoing_msg(); + + static uint32_t counter = 0; + + // Send unicast to echo server + if (counter < 16) { + static uint32_t msg_len = 0; + + emac_if_ctp_msg_build(msg_len, emac_if_get_echo_server_addr(0), emac_if_get_own_addr(), emac_if_get_own_addr()); + + msg_len += 100; + + if (msg_len > 1514) { + msg_len = 1514; + } + } + + if (counter > 18) { + if (emac_if_count_outgoing_msg() == 0) { + worker_loop_end(); + } + } + counter++; +} + +void test_emac_unicast_frame_len() +{ + RESET_ERROR_FLAGS; + SET_TRACE_LEVEL(TRACE_SUCCESS | TRACE_FAILURE); + + if (emac_if_count_echo_server_addr()) { + worker_loop_start(test_emac_unicast_frame_len_cb, 1 * SECOND_TO_MS); + } + + PRINT_ERROR_FLAGS; + TEST_ASSERT_FALSE(ERROR_FLAGS); + RESET_OUTGOING_MSG_DATA; +} + +#endif diff --git a/TESTS/network/emac/emac_tests.h b/TESTS/network/emac/emac_tests.h new file mode 100644 index 0000000000..edd0679cce --- /dev/null +++ b/TESTS/network/emac/emac_tests.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_TESTS_H +#define EMAC_TESTS_H + +void test_emac_initialize(); +void test_emac_broadcast(); +void test_emac_unicast(); +void test_emac_unicast_frame_len(); + +#endif /* EMAC_TESTS_H */ diff --git a/TESTS/network/emac/emac_util.cpp b/TESTS/network/emac/emac_util.cpp new file mode 100644 index 0000000000..920bd6407a --- /dev/null +++ b/TESTS/network/emac/emac_util.cpp @@ -0,0 +1,436 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +extern "C" { // netif input +#include "tcpip.h" +} + +#include "emac_api.h" +#include "emac_stack_mem.h" + +#include "emac_tests.h" +#include "emac_initialize.h" +#include "emac_util.h" +#include "emac_membuf.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +typedef struct { + int length; + int receipt_number; + unsigned short flags; + unsigned short lifetime; +} outgoing_msg_t; + +#define ECHO_SERVER_COUNT 5 + +#define OUTGOING_MSG_COUNT 100 + +// Event flags +#define LINK_UP 0x01 +#define LINK_DOWN 0x02 + +// Hook to lwip input function +extern struct netif *netif_list; + +// Broadcast address +const unsigned char eth_mac_broadcast_addr[ETH_MAC_ADDR_LEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + +// Event queue +static EventQueue worker_loop_event_queue; +static void worker_loop_event_cb(int event); +static Event worker_loop_event(&worker_loop_event_queue, worker_loop_event_cb); +static void link_input_event_cb(emac_stack_mem_chain_t *mem_chain_p); +static Event link_input_event(&worker_loop_event_queue, link_input_event_cb); + +// Found echo server addresses +static unsigned char eth_mac_echo_server_addr[ECHO_SERVER_COUNT][ETH_MAC_ADDR_LEN]; +static int etc_mac_echo_server_free_index = 0; + +// Outgoing messages +static outgoing_msg_t outgoing_msgs[OUTGOING_MSG_COUNT]; + +static unsigned int trace_level = 0; +static unsigned int error_flags = 0; +static unsigned int no_response_cnt = 0; + +int emac_if_find_outgoing_msg(int receipt_number) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length && outgoing_msgs[i].receipt_number == receipt_number) { + return i; + } + } + return -1; +} + +void emac_if_free_outgoing_msg(int index) +{ + outgoing_msgs[index].length = 0; +} + +int emac_if_count_outgoing_msg(void) +{ + int count = 0; + + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + count++; + } + } + + return count; +} + +void emac_if_reset_outgoing_msg(void) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + outgoing_msgs[i].length = 0; + } + } +} + +int emac_if_add_outgoing_msg(int length) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (!outgoing_msgs[i].length) { + outgoing_msgs[i].receipt_number = 0; + outgoing_msgs[i].length = length; + outgoing_msgs[i].flags = 0; + outgoing_msgs[i].lifetime = 10; + return i; + } + } + return -1; +} + +void emac_if_set_outgoing_msg_receipt_num(int index, int receipt_number) +{ + outgoing_msgs[index].receipt_number = receipt_number; +} + +void emac_if_set_outgoing_msg_flags(int index, int flags) +{ + outgoing_msgs[index].flags |= flags; +} + +void emac_if_timeout_outgoing_msg(void) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + if (outgoing_msgs[i].lifetime) { + outgoing_msgs[i].lifetime--; + if (outgoing_msgs[i].lifetime == 0) { + SET_ERROR_FLAGS(NO_RESPONSE); + } + } + } + } +} + +void emac_if_validate_outgoing_msg(void) +{ + static char broadcast_resp_count = 0; + + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + + if (outgoing_msgs[i].flags & RESPONSE_RECEIVED) { + + int failure = outgoing_msgs[i].flags & (INVALID_LENGHT | INVALID_DATA); + + if (failure) { + SET_ERROR_FLAGS(MSG_VALID_ERROR); + } + + if (!(outgoing_msgs[i].flags & PRINTED)) { + if ((trace_level & TRACE_SUCCESS) || ((trace_level & TRACE_FAILURE) && failure)) { + printf("response: receipt number %i %s %s %s\r\n\r\n", outgoing_msgs[i].receipt_number, + outgoing_msgs[i].flags & INVALID_LENGHT ? "LENGTH INVALID" : "LENGTH OK", + outgoing_msgs[i].flags & INVALID_DATA ? "DATA INVALID" : "DATA OK", + outgoing_msgs[i].flags & BROADCAST ? "BROADCAST" : "UNICAST"); + outgoing_msgs[i].flags |= PRINTED; + } + } + + if (outgoing_msgs[i].flags & BROADCAST) { + outgoing_msgs[i].lifetime = 2; + broadcast_resp_count++; + if (broadcast_resp_count > 5) { + emac_if_free_outgoing_msg(i); + } + } else { + emac_if_free_outgoing_msg(i); + } + } + + if (!outgoing_msgs[i].lifetime) { + if (!(outgoing_msgs[i].flags & RESPONSE_RECEIVED) && (trace_level & TRACE_FAILURE)) { + printf("NO RESPONSE: receipt number %i\r\n\r\n", outgoing_msgs[i].receipt_number); + } + emac_if_free_outgoing_msg(i); + } + } + } +} + +void emac_if_update_reply_to_outgoing_msg(int receipt_number, int lenght, int invalid_data_index) +{ + int32_t outgoing_msg_index = emac_if_find_outgoing_msg(receipt_number); + + if (outgoing_msg_index >= 0) { + outgoing_msgs[outgoing_msg_index].flags |= RESPONSE_RECEIVED; + +#if MBED_CONF_APP_TEST_ETHERNET + if (outgoing_msgs[outgoing_msg_index].length < ETH_FRAME_MIN_LEN) { + if (lenght != ETH_FRAME_MIN_LEN) { + outgoing_msgs[outgoing_msg_index].flags |= INVALID_LENGHT; + } + } else { +#endif + if (outgoing_msgs[outgoing_msg_index].length != lenght) { + outgoing_msgs[outgoing_msg_index].flags |= INVALID_LENGHT; + } +#if MBED_CONF_APP_TEST_ETHERNET + } +#endif + if (invalid_data_index && invalid_data_index < outgoing_msgs[outgoing_msg_index].length) { + outgoing_msgs[outgoing_msg_index].flags |= INVALID_DATA; + } + } +} + +void emac_if_add_echo_server_addr(unsigned char *addr) +{ + if (etc_mac_echo_server_free_index == ECHO_SERVER_COUNT) { + return; + } + + for (int i = 0; i < etc_mac_echo_server_free_index; i++) { + if (memcmp(ð_mac_echo_server_addr[i][0], addr, ETH_MAC_ADDR_LEN) == 0) { + return; + } + } + + memcpy(ð_mac_echo_server_addr[etc_mac_echo_server_free_index][0], addr, ETH_MAC_ADDR_LEN); + etc_mac_echo_server_free_index++; +} + +int emac_if_count_echo_server_addr(void) +{ + return etc_mac_echo_server_free_index; +} + +unsigned char *emac_if_get_echo_server_addr(int index) +{ + if (index < etc_mac_echo_server_free_index) { + return ð_mac_echo_server_addr[index][0]; + } + + return 0; +} + +void emac_if_set_error_flags(unsigned int error_flags_value) +{ + error_flags |= error_flags_value; + + if (error_flags_value & NO_RESPONSE) { + no_response_cnt++; + } +} + +unsigned int emac_if_get_error_flags(void) +{ + int error_flags_value = error_flags; + + // Indicate no response error only if more than three messages are lost + if (error_flags_value & NO_RESPONSE) { + if (no_response_cnt < 3) { + error_flags_value &= ~NO_RESPONSE; + } + } + + return error_flags_value; +} + +void emac_if_reset_error_flags(void) +{ + error_flags = 0; + no_response_cnt = 0; +} + +void emac_if_print_error_flags(void) +{ + int error_flags_value = emac_if_get_error_flags(); + + char no_resp_message[50]; + if (error_flags_value & NO_RESPONSE) { + snprintf(no_resp_message, 50, "no response from echo server, counter: %i", no_response_cnt); + } else if (no_response_cnt > 0) { + printf("no response from echo server, counter: %i\r\n\r\n", no_response_cnt); + } + + printf("test result: %s%s%s%s%s%s\r\n\r\n", + error_flags_value ? "Test FAILED, reason: ": "PASS", + error_flags_value & TEST_FAILED ? "test failed ": "", + error_flags_value & MSG_VALID_ERROR ? "message content validation error ": "", + error_flags_value & OUT_OF_MSG_DATA ? "out of message validation data storage ": "", + error_flags_value & NO_FREE_MEM_BUF ? "no free memory buffers ": "", + error_flags_value & NO_RESPONSE ? no_resp_message: ""); +} + +void emac_if_set_trace_level(char trace_level_value) +{ + trace_level = trace_level_value; +} + +void emac_if_trace_to_ascii_hex_dump(const char *prefix, int len, unsigned char *data) +{ + int line_len = 0; + + for (int i = 0; i < len; i++) { + if ((line_len % 14) == 0) { + if (line_len != 0) { + printf("\r\n"); + } + printf("%s %06x", prefix, line_len); + } + line_len++; + printf(" %02x", data[i]); + } + printf("\r\n\r\n"); +} + +void emac_if_link_state_change_cb(void *data, bool up) +{ + if (up) { + worker_loop_event.post(LINK_UP); + } else { + worker_loop_event.post(LINK_DOWN); + } +} + +void emac_if_link_input_cb(void *data, emac_stack_mem_chain_t *mem_chain_p) +{ + link_input_event.post(mem_chain_p); +} + +static void link_input_event_cb(emac_stack_mem_chain_t *mem_chain_p) +{ + int lenght = emac_stack_mem_len(0, mem_chain_p); + + if (lenght >= ETH_FRAME_HEADER_LEN) { + // Ethernet input frame + unsigned char eth_input_frame_data[ETH_FRAME_HEADER_LEN]; + memset(eth_input_frame_data, 0, ETH_FRAME_HEADER_LEN); + + int invalid_data_index = emac_if_memory_buffer_read(mem_chain_p, eth_input_frame_data); + + if (eth_input_frame_data[12] == 0x90 && eth_input_frame_data[13] == 0x00) { + unsigned char eth_output_frame_data[ETH_FRAME_HEADER_LEN]; + int receipt_number; + + ctp_function function = emac_if_ctp_header_handle(eth_input_frame_data, eth_output_frame_data, emac_if_get_hw_addr(), &receipt_number); + + if (function == CTP_REPLY) { + emac_if_update_reply_to_outgoing_msg(receipt_number, lenght, invalid_data_index); +#if MBED_CONF_APP_ECHO_SERVER + // Echoes only if configured as echo server + } else if (function == CTP_FORWARD) { + emac_if_memory_buffer_write(mem_chain_p, eth_output_frame_data, false); + emac_if_get()->ops.link_out(emac_if_get(), mem_chain_p); +#endif + } + + emac_if_add_echo_server_addr(ð_input_frame_data[6]); + + emac_stack_mem_free(0, mem_chain_p); + + if (trace_level & TRACE_ETH_FRAMES) { + printf("LEN %i\r\n\r\n", lenght); + const char trace_type[] = "INP>"; + emac_if_trace_to_ascii_hex_dump(trace_type, ETH_FRAME_HEADER_LEN, eth_input_frame_data); + } + return; + } + } + + // Forward other than CTP frames to lwip + struct netif *netif; + + /* loop through netif's */ + netif = netif_list; + if (netif != NULL) { + struct pbuf *p = (struct pbuf *)mem_chain_p; + + /* pass all packets to ethernet_input, which decides what packets it supports */ + if (netif->input(p, netif) != ERR_OK) { + emac_stack_mem_free(0, mem_chain_p); + } + } else { + emac_stack_mem_free(0, mem_chain_p); + } +} + +void worker_loop_start(void (*test_step_cb_fnc)(void), int timeout) +{ + int test_step_cb_timer = worker_loop_event_queue.call_every(timeout, test_step_cb_fnc); + int timeout_outgoing_msg_timer = worker_loop_event_queue.call_every(1000, emac_if_timeout_outgoing_msg); + +#if MBED_CONF_APP_ECHO_SERVER + worker_loop_event_queue.dispatch_forever(); +#else + worker_loop_event_queue.dispatch(600 * SECOND_TO_MS); +#endif + + worker_loop_event_queue.cancel(test_step_cb_timer); + worker_loop_event_queue.cancel(timeout_outgoing_msg_timer); + + worker_loop_event_queue.dispatch(5); +} + +static void worker_loop_event_cb(int event) +{ + if (event == LINK_UP) { + printf("cable connected\r\n\r\n"); + } + + if (event == LINK_DOWN) { + printf("cable disconnected\r\n\r\n"); + } +} + +void worker_loop_end(void) +{ + worker_loop_event_queue.break_dispatch(); +} + +unsigned char *emac_if_get_own_addr(void) +{ + return (emac_if_get_hw_addr()); +} + +#endif diff --git a/TESTS/network/emac/emac_util.h b/TESTS/network/emac/emac_util.h new file mode 100644 index 0000000000..59fc8506b0 --- /dev/null +++ b/TESTS/network/emac/emac_util.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_UTIL_H +#define EMAC_UTIL_H + +#define SECOND_TO_US 1000000 +#define SECOND_TO_MS 1000 +#define MS_TO_US 1000 + +extern const unsigned char eth_mac_broadcast_addr[]; + +// Trace flags +#define TRACE_ETH_FRAMES 0x01 +#define TRACE_SUCCESS 0x02 +#define TRACE_FAILURE 0x04 +#define SET_TRACE_LEVEL(level) emac_if_set_trace_level(level) + +// Message validation flags +#define BROADCAST 0x01 +#define RESPONSE_RECEIVED 0x02 +#define INVALID_LENGHT 0x04 +#define INVALID_DATA 0x08 +#define PRINTED 0x10 + +#define RESET_OUTGOING_MSG_DATA emac_if_reset_outgoing_msg() + +// General error flags +#define TEST_FAILED 0x01 +#define MSG_VALID_ERROR 0x02 +#define OUT_OF_MSG_DATA 0x04 +#define NO_FREE_MEM_BUF 0x08 +#define NO_RESPONSE 0x10 + +#define ERROR_FLAGS emac_if_get_error_flags() +#define RESET_ERROR_FLAGS emac_if_reset_error_flags() +#define PRINT_ERROR_FLAGS emac_if_print_error_flags() +#define SET_ERROR_FLAGS(flags) emac_if_set_error_flags(flags) + +#define ETH_FRAME_HEADER_LEN 28 +#define ETH_FRAME_MIN_LEN 60 +#define ETH_MAC_ADDR_LEN 6 + +int emac_if_find_outgoing_msg(int receipt_number); +void emac_if_free_outgoing_msg(int index); +int emac_if_count_outgoing_msg(void); +void emac_if_reset_outgoing_msg(void); +int emac_if_add_outgoing_msg(int length); +void emac_if_timeout_outgoing_msg(void); +void emac_if_validate_outgoing_msg(void); +void emac_if_set_outgoing_msg_receipt_num(int index, int receipt_number); +void emac_if_set_outgoing_msg_flags(int index, int flags); + +void emac_if_add_echo_server_addr(unsigned char *addr); +int emac_if_count_echo_server_addr(void); +unsigned char *emac_if_get_echo_server_addr(int index); + +void emac_if_set_error_flags(unsigned int error_flags_value); +unsigned int emac_if_get_error_flags(void); +void emac_if_reset_error_flags(void); +void emac_if_print_error_flags(void); + +void emac_if_set_trace_level(char trace_level_value); + +void emac_if_trace_to_ascii_hex_dump(const char *prefix, int len, char *data); + +void emac_if_link_state_change_cb(void *data, bool up); + +unsigned char *emac_if_get_own_addr(void); + +extern void emac_if_link_input_cb(void *data, void *mem_chain_p); +extern void emac_if_link_state_change_cb(void *data, bool up); + +void worker_loop_start(void (*test_step_cb_fnc)(void), int timeout); +void worker_loop_end(void); + +void emac_if_init_main_thread(void); + +#endif /* EMAC_UTIL_H */ diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp new file mode 100644 index 0000000000..454bb69353 --- /dev/null +++ b/TESTS/network/emac/main.cpp @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !defined(MBED_CONF_APP_TEST_WIFI) || \ + !defined(MBED_CONF_APP_TEST_ETHERNET) || \ + !defined(MBED_CONF_APP_ECHO_SERVER) || \ + !defined(MBED_CONF_APP_WIFI_SCAN) || \ + !defined(MBED_CONF_APP_WIFI_SSID ) || \ + !defined(MBED_CONF_APP_WIFI_SECURITY) || \ + !defined(MBED_CONF_APP_WIFI_PASSWORD) +#error [NOT_SUPPORTED] Requires parameters from mbed_app.json +#endif + +#if !MBED_CONF_APP_TEST_WIFI && !MBED_CONF_APP_TEST_ETHERNET +#error [NOT_SUPPORTED] Either wifi or ethernet testing need to be enabled +#endif +#if MBED_CONF_APP_TEST_WIFI +#if !defined(TARGET_UBLOX_EVK_ODIN_W2) && !defined(TARGET_REALTEK_RTL8195AM) +#error [NOT_SUPPORTED] Tests are valid only for UBLOX_EVK_ODIN_W2 and REALTEK_RTL8195AM +#endif +#endif +#if MBED_CONF_APP_TEST_ETHERNET +#error [NOT_SUPPORTED] Ethernet testing not supported +#endif + +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest.h" + +#include "emac_tests.h" +#include "emac_util.h" + +using namespace utest::v1; + +// Test setup +utest::v1::status_t test_setup(const size_t number_of_cases) { +#if !MBED_CONF_APP_ECHO_SERVER + GREENTEA_SETUP(600, "default_auto"); +#endif + return verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("EMAC interface initialize", test_emac_initialize), + Case("EMAC interface broadcast", test_emac_broadcast), + Case("EMAC interface unicast", test_emac_unicast), + Case("EMAC interface unicast frame length", test_emac_unicast_frame_len), + Case("EMAC interface broadcast (run again)", test_emac_broadcast) +}; + +Specification specification(test_setup, cases); + +int main() +{ + return !Harness::run(specification); +} + diff --git a/TESTS/network/emac/template_mbed_app.txt b/TESTS/network/emac/template_mbed_app.txt new file mode 100644 index 0000000000..ce8b8076e0 --- /dev/null +++ b/TESTS/network/emac/template_mbed_app.txt @@ -0,0 +1,32 @@ +{ + "config": { + "test-ethernet": { + "help": "Enable ethernet testing", + "value": 0 + }, + "test-wifi": { + "help": "Enable wifi testing", + "value": 1 + }, + "echo-server": { + "help": "Build test to be echo server", + "value": 0 + }, + "wifi-scan": { + "help": "Scan and list access points", + "value": 0 + }, + "wifi-ssid": { + "help": "WiFi SSID for network", + "value": "\"SSID\"" + }, + "wifi-security": { + "help": "WiFi Security", + "value": "NSAPI_SECURITY_WPA_WPA2" + }, + "wifi-password": { + "help": "WiFi Password", + "value": "\"PASSWORD\"" + } + } +} From c841e4065d7f7982b80a6baeab409d86f53ef6f0 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 21 Nov 2017 15:13:48 +0100 Subject: [PATCH 007/118] STM32 UART init update - serial_init, serial_free and serial_baud function moved from serial_device.c (specific to each STM32 family) to serial_api.c (common STM32 file) - default baudrate value was hardcoded to 9600 - Value is set now to MBED_CONF_PLATFORM_STDIO_BAUD_RATE for STDIO - Value is set now to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE for other use - UART init will not be stopped before calling serial_baud function --- .../TARGET_STM/TARGET_STM32F0/serial_device.c | 230 +---------- .../TARGET_STM/TARGET_STM32F1/serial_device.c | 123 +----- .../TARGET_STM/TARGET_STM32F2/serial_device.c | 212 +--------- .../TARGET_STM/TARGET_STM32F3/serial_device.c | 182 +-------- .../TARGET_STM/TARGET_STM32F4/serial_device.c | 253 +----------- .../TARGET_STM/TARGET_STM32F7/serial_device.c | 203 +--------- .../TARGET_STM/TARGET_STM32L0/serial_device.c | 173 +------- .../TARGET_STM/TARGET_STM32L1/serial_device.c | 154 +------- .../TARGET_STM/TARGET_STM32L4/serial_device.c | 187 +-------- targets/TARGET_STM/serial_api.c | 372 +++++++++++++++++- targets/TARGET_STM/serial_api_hal.h | 11 +- 11 files changed, 462 insertions(+), 1638 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 36023d28e7..37ee8a3a4c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,234 +27,26 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#if defined (TARGET_STM32F091RC) - #define UART_NUM (8) +#if defined (TARGET_STM32F031K6) + #define UART_NUM (1 #elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) || defined (TARGET_STM32F042K6) #define UART_NUM (2) -#elif defined (TARGET_STM32F031K6) - #define UART_NUM (1) -#else +#elif defined (TARGET_STM32F070RB) || defined (TARGET_STM32F072RB) #define UART_NUM (4) +#else + #define UART_NUM (8) // max value (TARGET_STM32F091RC) #endif -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - -#if defined USART2_BASE - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } -#endif - -#if defined USART3_BASE - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } -#endif - -#if defined USART4_BASE - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif - -#if defined USART5_BASE - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - -#if defined USART6_BASE - if (obj_s->uart == UART_6) { - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - } -#endif - -#if defined USART7_BASE - if (obj_s->uart == UART_7) { - __HAL_RCC_USART7_FORCE_RESET(); - __HAL_RCC_USART7_RELEASE_RESET(); - __HAL_RCC_USART7_CLK_ENABLE(); - obj_s->index = 6; - } -#endif - -#if defined USART8_BASE - if (obj_s->uart == UART_8) { - __HAL_RCC_USART8_FORCE_RESET(); - __HAL_RCC_USART8_RELEASE_RESET(); - __HAL_RCC_USART8_CLK_ENABLE(); - obj_s->index = 7; - } -#endif - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } - -#if defined(USART2_BASE) - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } -#endif - -#if defined USART3_BASE - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - } -#endif - -#if defined USART4_BASE - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_DISABLE(); - } -#endif - -#if defined USART5_BASE - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_DISABLE(); - } -#endif - -#if defined USART6_BASE - if (obj_s->uart == UART_6) { - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_DISABLE(); - } -#endif - -#if defined USART7_BASE - if (obj_s->uart == UART_7) { - __HAL_RCC_USART7_FORCE_RESET(); - __HAL_RCC_USART7_RELEASE_RESET(); - __HAL_RCC_USART7_CLK_DISABLE(); - } -#endif - -#if defined USART8_BASE - if (obj_s->uart == UART_8) { - __HAL_RCC_USART8_FORCE_RESET(); - __HAL_RCC_USART8_RELEASE_RESET(); - __HAL_RCC_USART8_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -884,7 +676,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -943,6 +735,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c index 8c9cf38f21..b0747f4d50 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,129 +27,18 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include -#include "PeripheralPins.h" +#include "serial_api_hal.h" #define UART_NUM (3) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } - - // Configure UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -687,7 +576,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -746,6 +635,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c index 7f23897175..cc74ffb45e 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,216 +27,18 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#define UART_NUM (8) +#define UART_NUM (6) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - switch (obj_s->uart) { - case UART_1: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - break; - - case UART_2: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - break; - -#if defined(USART3_BASE) - case UART_3: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - break; -#endif -#if defined(USART6_BASE) - case UART_6: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - break; -#endif -#if defined(UART7_BASE) - case UART_7: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_ENABLE(); - obj_s->index = 6; - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_ENABLE(); - obj_s->index = 7; - break; -#endif - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - switch (obj_s->index) { - case 0: - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - break; - - case 1: - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - break; - -#if defined(USART3_BASE) - case 2: - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - break; -#endif -#if defined(UART4_BASE) - case 3: - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - break; -#endif -#if defined(UART5_BASE) - case 4: - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - break; -#endif -#if defined(USART6_BASE) - case 5: - __USART6_FORCE_RESET(); - __USART6_RELEASE_RESET(); - __USART6_CLK_DISABLE(); - break; -#endif -#if defined(UART7_BASE) - case 6: - __UART7_FORCE_RESET(); - __UART7_RELEASE_RESET(); - __UART7_CLK_DISABLE(); - break; -#endif -#if defined(UART8_BASE) - case 7: - __UART8_FORCE_RESET(); - __UART8_RELEASE_RESET(); - __UART8_CLK_DISABLE(); - break; -#endif - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -865,7 +667,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -924,6 +726,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c index b1f2de8ca0..13ba2eaa7a 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,179 +27,21 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#define UART_NUM (5) +#if defined (TARGET_STM32F302x8) || defined (TARGET_STM32F303x8) || defined (TARGET_STM32F334x8) + #define UART_NUM (3) +#else + #define UART_NUM (5) // max value +#endif -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; -uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock + switch to SystemClock - if (obj_s->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_ENABLE(); -#if defined(RCC_USART1CLKSOURCE_SYSCLK) - __HAL_RCC_USART1_CONFIG(RCC_USART1CLKSOURCE_SYSCLK); -#endif - obj_s->index = 0; - } -#if defined(USART2_BASE) - if (obj_s->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_ENABLE(); -#if defined(RCC_USART2CLKSOURCE_SYSCLK) - __HAL_RCC_USART2_CONFIG(RCC_USART2CLKSOURCE_SYSCLK); -#endif - obj_s->index = 1; - } -#endif -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_ENABLE(); -#if defined(RCC_USART3CLKSOURCE_SYSCLK) - __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK); -#endif - obj_s->index = 2; - } -#endif -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_ENABLE(); -#if defined(RCC_UART4CLKSOURCE_SYSCLK) - __HAL_RCC_UART4_CONFIG(RCC_UART4CLKSOURCE_SYSCLK); -#endif - obj_s->index = 3; - } -#endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __UART5_CLK_ENABLE(); -#if defined(RCC_UART5CLKSOURCE_SYSCLK) - __HAL_RCC_UART5_CONFIG(RCC_UART5CLKSOURCE_SYSCLK); -#endif - obj_s->index = 4; - } -#endif - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj_s->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } -#endif -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - } -#endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} +static uart_irq_handler irq_handler; /****************************************************************************** * INTERRUPTS HANDLING @@ -785,7 +627,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -844,6 +686,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c index 02a3811ccd..2c3970143d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,242 +28,29 @@ ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" - #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#define UART_NUM (10) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +#if defined (TARGET_STM32F401xC) || defined (TARGET_STM32F401xE) || defined (TARGET_STM32F410xB) || defined (TARGET_STM32F411xE) + #define UART_NUM (3) +#elif defined (TARGET_STM32F412xG) + #define UART_NUM (4) +#elif defined (TARGET_STM32F407xG) || defined (TARGET_STM32F446xE) + #define UART_NUM (6) +#elif defined (TARGET_STM32F429xI) || defined (TARGET_STM32F439xI) || defined (TARGET_STM32F437xG) || defined (TARGET_STM32F469xI) + #define UART_NUM (8) +#elif defined (TARGET_STM32F413xH) + #define UART_NUM (10) +#else + #define UART_NUM (10) // max value +#endif + +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - switch (obj_s->uart) { - case UART_1: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - break; - - case UART_2: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - break; -#if defined(USART3_BASE) - case UART_3: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - break; -#endif -#if defined(USART6_BASE) - case UART_6: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - break; -#endif -#if defined(UART7_BASE) - case UART_7: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_ENABLE(); - obj_s->index = 6; - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_ENABLE(); - obj_s->index = 7; - break; -#endif -#if defined(UART9_BASE) - case UART_9: - __HAL_RCC_UART9_FORCE_RESET(); - __HAL_RCC_UART9_RELEASE_RESET(); - __HAL_RCC_UART9_CLK_ENABLE(); - obj_s->index = 8; - break; -#endif -#if defined(UART10_BASE) - case UART_10: - __HAL_RCC_UART10_FORCE_RESET(); - __HAL_RCC_UART10_RELEASE_RESET(); - __HAL_RCC_UART10_CLK_ENABLE(); - obj_s->index = 9; - break; -#endif - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - switch (obj_s->index) { - case 0: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - break; - case 1: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - break; -#if defined(USART3_BASE) - case 2: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - break; -#endif -#if defined(UART4_BASE) - case 3: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_DISABLE(); - break; -#endif -#if defined(UART5_BASE) - case 4: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_DISABLE(); - break; -#endif -#if defined(USART6_BASE) - case 5: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_DISABLE(); - break; -#endif -#if defined(UART7_BASE) - case 6: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_DISABLE(); - break; -#endif -#if defined(UART8_BASE) - case 7: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_DISABLE(); - break; -#endif -#if defined(UART9_BASE) - case 8: - __HAL_RCC_UART9_FORCE_RESET(); - __HAL_RCC_UART9_RELEASE_RESET(); - __HAL_RCC_UART9_CLK_DISABLE(); - break; -#endif -#if defined(UART10_BASE) - case 9: - __HAL_RCC_UART10_FORCE_RESET(); - __HAL_RCC_UART10_RELEASE_RESET(); - __HAL_RCC_UART10_CLK_DISABLE(); - break; -#endif - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -927,7 +714,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -986,6 +773,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c index a4bece1815..9723a8a526 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,208 +27,17 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" #define UART_NUM (8) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - switch (obj_s->uart) { - case UART_1: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - break; - - case UART_2: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - break; -#if defined(USART3_BASE) - case UART_3: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - break; -#endif - case UART_6: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - break; -#if defined(UART7_BASE) - case UART_7: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_ENABLE(); - obj_s->index = 6; - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_ENABLE(); - obj_s->index = 7; - break; -#endif - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - switch (obj_s->uart) { - case UART_1: - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - break; - case UART_2: - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - break; -#if defined(USART3_BASE) - case UART_3: - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - break; -#endif - case UART_6: - __USART6_FORCE_RESET(); - __USART6_RELEASE_RESET(); - __USART6_CLK_DISABLE(); - break; -#if defined(UART7_BASE) - case UART_7: - __UART7_FORCE_RESET(); - __UART7_RELEASE_RESET(); - __UART7_CLK_DISABLE(); - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __UART8_FORCE_RESET(); - __UART8_RELEASE_RESET(); - __UART8_CLK_DISABLE(); - break; -#endif - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -854,7 +663,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -913,6 +722,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c index 74107fd42f..33123140ed 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,171 +27,24 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#define UART_NUM (5) +#if defined (TARGET_STM32L011K4) || defined (TARGET_STM32L031K6) + #define UART_NUM (2) +#elif defined (TARGET_STM32L053x8) + #define UART_NUM (3) +#else + #define UART_NUM (5) +#endif -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable UART clock -#if defined(USART1_BASE) - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } -#endif - - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_ENABLE(); - obj_s->index = 2; - } - -#if defined(USART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif - -#if defined(USART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock -#if defined(USART1_BASE) - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } -#endif - - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } - - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_DISABLE(); - } - -#if defined(USART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_DISABLE(); - } -#endif - -#if defined(USART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -761,7 +614,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -820,6 +673,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c index bcf53156b0..797979dd89 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,160 +27,18 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include -#include "PeripheralPins.h" +#include "serial_api_hal.h" #define UART_NUM (5) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - - // Configure UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj_s->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - if (obj_s->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - } -#endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -752,7 +610,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -811,6 +669,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index 4a9bfbf530..916f9d45f6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,187 +27,22 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include -#include "PeripheralPins.h" +#include "serial_api_hal.h" -#define UART_NUM (6) +#if defined (TARGET_STM32L432xC) + #define UART_NUM (3) +#else + #define UART_NUM (6) // max value +#endif -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } -#endif - -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif - -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - -#if defined(LPUART1_BASE) - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_ENABLE(); - obj_s->index = 5; - } -#endif - - // Configure UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } - - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } - -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - } -#endif - -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_DISABLE(); - } -#endif - -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_DISABLE(); - } -#endif - -#if defined(LPUART1_BASE) - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -806,7 +641,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -865,6 +700,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index 5d6167b61e..9f022e2cca 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,15 +27,369 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "mbed_error.h" -#include "serial_api.h" -#include "serial_api_hal.h" -#include "PeripheralPins.h" #if DEVICE_SERIAL -void init_uart(serial_t *obj) +#include "serial_api_hal.h" + +int stdio_uart_inited = 0; // used in platform/mbed_board.c and platform/mbed_retarget.cpp +serial_t stdio_uart; + +extern UART_HandleTypeDef uart_handlers[]; +extern uint32_t serial_irq_ids[]; + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + struct serial_s *obj_s = SERIAL_S(obj); + int IndexNumber = 0; + + // Determine the UART to use (UART_1, UART_2, ...) + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object + obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT(obj_s->uart != (UARTName)NC); + + // Enable USART clock +#if defined(USART1_BASE) + if (obj_s->uart == UART_1) { + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); + __HAL_RCC_USART1_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined (USART2_BASE) + if (obj_s->uart == UART_2) { + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); + __HAL_RCC_USART2_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART3_BASE) + if (obj_s->uart == UART_3) { + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); + __HAL_RCC_USART3_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_UART4_FORCE_RESET(); + __HAL_RCC_UART4_RELEASE_RESET(); + __HAL_RCC_UART4_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_USART4_FORCE_RESET(); + __HAL_RCC_USART4_RELEASE_RESET(); + __HAL_RCC_USART4_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_UART5_FORCE_RESET(); + __HAL_RCC_UART5_RELEASE_RESET(); + __HAL_RCC_UART5_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_USART5_FORCE_RESET(); + __HAL_RCC_USART5_RELEASE_RESET(); + __HAL_RCC_USART5_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART6_BASE) + if (obj_s->uart == UART_6) { + __HAL_RCC_USART6_FORCE_RESET(); + __HAL_RCC_USART6_RELEASE_RESET(); + __HAL_RCC_USART6_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_UART7_FORCE_RESET(); + __HAL_RCC_UART7_RELEASE_RESET(); + __HAL_RCC_UART7_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_USART7_FORCE_RESET(); + __HAL_RCC_USART7_RELEASE_RESET(); + __HAL_RCC_USART7_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_UART8_FORCE_RESET(); + __HAL_RCC_UART8_RELEASE_RESET(); + __HAL_RCC_UART8_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_USART8_FORCE_RESET(); + __HAL_RCC_USART8_RELEASE_RESET(); + __HAL_RCC_USART8_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART9_BASE) + if (obj_s->uart == UART_9) { + __HAL_RCC_UART9_FORCE_RESET(); + __HAL_RCC_UART9_RELEASE_RESET(); + __HAL_RCC_UART9_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART10_BASE) + if (obj_s->uart == UART_10) { + __HAL_RCC_UART10_FORCE_RESET(); + __HAL_RCC_UART10_RELEASE_RESET(); + __HAL_RCC_UART10_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + + +#if defined(LPUART1_BASE) + if (obj_s->uart == LPUART_1) { + __HAL_RCC_LPUART1_FORCE_RESET(); + __HAL_RCC_LPUART1_RELEASE_RESET(); + __HAL_RCC_LPUART1_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + + // Configure UART pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + // Configure UART + obj_s->baudrate = 9600; // baudrate default value + if (obj_s->uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + obj_s->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json +#endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */ + } + else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + obj_s->baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json +#endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */ + } + obj_s->databits = UART_WORDLENGTH_8B; + obj_s->stopbits = UART_STOPBITS_1; + obj_s->parity = UART_PARITY_NONE; + +#if DEVICE_SERIAL_FC + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; +#endif + + obj_s->pin_tx = tx; + obj_s->pin_rx = rx; + + init_uart(obj); /* init_uart will be called again in serial_baud function, so don't worry if init_uart returns HAL_ERROR */ + + // For stdio management + if (obj_s->uart == STDIO_UART) { // STDIO_UART defined in PeripheralNames.h + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + struct serial_s *obj_s = SERIAL_S(obj); + + // Reset UART and disable clock +#if defined(USART1_BASE) + if (obj_s->uart == UART_1) { + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); + __HAL_RCC_USART1_CLK_DISABLE(); + } +#endif + +#if defined(USART2_BASE) + if (obj_s->uart == UART_2) { + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); + __HAL_RCC_USART2_CLK_DISABLE(); + } +#endif + +#if defined(USART3_BASE) + if (obj_s->uart == UART_3) { + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); + __HAL_RCC_USART3_CLK_DISABLE(); + } +#endif + +#if defined(UART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_UART4_FORCE_RESET(); + __HAL_RCC_UART4_RELEASE_RESET(); + __HAL_RCC_UART4_CLK_DISABLE(); + } +#endif + +#if defined(USART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_USART4_FORCE_RESET(); + __HAL_RCC_USART4_RELEASE_RESET(); + __HAL_RCC_USART4_CLK_DISABLE(); + } +#endif + +#if defined(UART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_UART5_FORCE_RESET(); + __HAL_RCC_UART5_RELEASE_RESET(); + __HAL_RCC_UART5_CLK_DISABLE(); + } +#endif + +#if defined(USART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_USART5_FORCE_RESET(); + __HAL_RCC_USART5_RELEASE_RESET(); + __HAL_RCC_USART5_CLK_DISABLE(); + } +#endif + +#if defined(USART6_BASE) + if (obj_s->uart == UART_6) { + __HAL_RCC_USART6_FORCE_RESET(); + __HAL_RCC_USART6_RELEASE_RESET(); + __HAL_RCC_USART6_CLK_DISABLE(); + } +#endif + +#if defined(UART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_UART7_FORCE_RESET(); + __HAL_RCC_UART7_RELEASE_RESET(); + __HAL_RCC_UART7_CLK_DISABLE(); + } +#endif + +#if defined(USART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_USART7_FORCE_RESET(); + __HAL_RCC_USART7_RELEASE_RESET(); + __HAL_RCC_USART7_CLK_DISABLE(); + } +#endif + +#if defined(UART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_UART8_FORCE_RESET(); + __HAL_RCC_UART8_RELEASE_RESET(); + __HAL_RCC_UART8_CLK_DISABLE(); + } +#endif + +#if defined(USART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_USART8_FORCE_RESET(); + __HAL_RCC_USART8_RELEASE_RESET(); + __HAL_RCC_USART8_CLK_DISABLE(); + } +#endif + +#if defined(UART9_BASE) + if (obj_s->uart == UART_9) { + __HAL_RCC_UART9_FORCE_RESET(); + __HAL_RCC_UART9_RELEASE_RESET(); + __HAL_RCC_UART9_CLK_DISABLE(); + } +#endif + +#if defined(UART10_BASE) + if (obj_s->uart == UART_10) { + __HAL_RCC_UART10_FORCE_RESET(); + __HAL_RCC_UART10_RELEASE_RESET(); + __HAL_RCC_UART10_CLK_DISABLE(); + } +#endif + +#if defined(LPUART1_BASE) + if (obj_s->uart == LPUART_1) { + __HAL_RCC_LPUART1_FORCE_RESET(); + __HAL_RCC_LPUART1_RELEASE_RESET(); + __HAL_RCC_LPUART1_CLK_DISABLE(); + } +#endif + + // Configure GPIOs + pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + + serial_irq_ids[obj_s->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + struct serial_s *obj_s = SERIAL_S(obj); + + obj_s->baudrate = baudrate; + if (init_uart(obj) != HAL_OK) { + debug("Cannot initialize UART with baud rate %u\n", baudrate); + /* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */ + } +} + +HAL_StatusTypeDef init_uart(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; @@ -64,9 +418,7 @@ void init_uart(serial_t *obj) huart->Init.Mode = UART_MODE_TX_RX; } - if (HAL_UART_Init(huart) != HAL_OK) { - error("Cannot initialize UART\n"); - } + return HAL_UART_Init(huart); } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) diff --git a/targets/TARGET_STM/serial_api_hal.h b/targets/TARGET_STM/serial_api_hal.h index e4a1892f52..b1fd7fcea1 100644 --- a/targets/TARGET_STM/serial_api_hal.h +++ b/targets/TARGET_STM/serial_api_hal.h @@ -32,7 +32,14 @@ #define MBED_SERIAL_API_HAL_H #include "serial_api.h" +#include +#include "mbed_assert.h" +#include "mbed_debug.h" +#include "mbed_error.h" +// #include "cmsis.h" +// #include "pinmap.h" +#include "PeripheralPins.h" #ifdef __cplusplus extern "C" { @@ -47,14 +54,12 @@ extern "C" { #define SERIAL_S(obj) (obj) #endif -extern UART_HandleTypeDef uart_handlers[]; - /** Initialize and configure the UART peripheral * * @param obj The serial object containing the configuration */ -void init_uart(serial_t *obj); +HAL_StatusTypeDef init_uart(serial_t *obj); #ifdef __cplusplus } From fba156a35a44a85a76480133b97711e8bd3f9cd1 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 23 Nov 2017 14:52:35 +0100 Subject: [PATCH 008/118] STM32 LPUART : update clock source depending on expected baudrate --- targets/TARGET_STM/serial_api.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index 9f022e2cca..89914d7bae 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -384,8 +384,32 @@ void serial_baud(serial_t *obj, int baudrate) obj_s->baudrate = baudrate; if (init_uart(obj) != HAL_OK) { - debug("Cannot initialize UART with baud rate %u\n", baudrate); + +#if defined(LPUART1_BASE) /* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */ + if (obj_s->uart == LPUART_1) { + /* Try to change LPUART clock source */ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if (baudrate == 9600) { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + if (init_uart(obj) == HAL_OK){ + return; + } + } + else { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + if (init_uart(obj) == HAL_OK){ + return; + } + } + } +#endif /* LPUART1_BASE */ + + debug("Cannot initialize UART with baud rate %u\n", baudrate); } } From 02b5e52b23fdc2a17cf5630573427c9e5f8ae0c9 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 24 Nov 2017 13:39:33 +0100 Subject: [PATCH 009/118] STM32 uart: update after code review --- targets/TARGET_STM/TARGET_STM32F0/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32F4/serial_device.c | 4 +--- targets/TARGET_STM/serial_api_hal.h | 2 -- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 37ee8a3a4c..2ea47faeb3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -33,7 +33,7 @@ #include "serial_api_hal.h" #if defined (TARGET_STM32F031K6) - #define UART_NUM (1 + #define UART_NUM (1) #elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) || defined (TARGET_STM32F042K6) #define UART_NUM (2) #elif defined (TARGET_STM32F070RB) || defined (TARGET_STM32F072RB) diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c index 2c3970143d..09e326fac7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c @@ -40,10 +40,8 @@ #define UART_NUM (6) #elif defined (TARGET_STM32F429xI) || defined (TARGET_STM32F439xI) || defined (TARGET_STM32F437xG) || defined (TARGET_STM32F469xI) #define UART_NUM (8) -#elif defined (TARGET_STM32F413xH) - #define UART_NUM (10) #else - #define UART_NUM (10) // max value + #define UART_NUM (10) // max value // TARGET_STM32F413xH #endif uint32_t serial_irq_ids[UART_NUM] = {0}; diff --git a/targets/TARGET_STM/serial_api_hal.h b/targets/TARGET_STM/serial_api_hal.h index b1fd7fcea1..c5cea54e0b 100644 --- a/targets/TARGET_STM/serial_api_hal.h +++ b/targets/TARGET_STM/serial_api_hal.h @@ -37,8 +37,6 @@ #include "mbed_debug.h" #include "mbed_error.h" -// #include "cmsis.h" -// #include "pinmap.h" #include "PeripheralPins.h" #ifdef __cplusplus From 22a7801c7e3d076f0a6266954770003bd5164c75 Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Tue, 28 Nov 2017 09:26:29 +0100 Subject: [PATCH 010/118] current critical section implementation makes possible that interrupt signals are lost. It was observed at last for tests-api-spi ci-test-shield's test. This patch introduce usage of sdk5 origin implementation in which sd_nvic_critical_region_enter/exit is calling each time critical region is enter/exit. This fixes the issue. --- .../TARGET_NRF5/nordic_critical.c | 36 +++---------------- 1 file changed, 5 insertions(+), 31 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c index 4f94263196..866cb10fbc 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c @@ -15,43 +15,17 @@ * limitations under the License. */ -#include // uint32_t, UINT32_MAX -#include // uint32_t, UINT32_MAX -#include "cmsis.h" -#include "nrf_soc.h" -#include "nrf_sdm.h" -#include "nrf_nvic.h" +#include +#include "app_util_platform.h" -static uint8_t _sd_state = 0; -static volatile uint32_t _entry_count = 0; +static uint8_t nordic_cr_nested = 0; void core_util_critical_section_enter() { - // if a critical section has already been entered, just update the counter - if (_entry_count) { - ++_entry_count; - return; - } - - // in this path, a critical section has never been entered - // routine of SD V11 work even if the softdevice is not active - sd_nvic_critical_region_enter(&_sd_state); - - assert(_entry_count == 0); // entry count should always be equal to 0 at this point - ++_entry_count; + app_util_critical_region_enter(&nordic_cr_nested); } void core_util_critical_section_exit() { - assert(_entry_count > 0); - --_entry_count; - - // If their is other segments which have entered the critical section, just leave - if (_entry_count) { - return; - } - - // This is the last segment of the critical section, state should be restored as before entering - // the critical section - sd_nvic_critical_region_exit(_sd_state); + app_util_critical_region_exit(nordic_cr_nested); } From db31ab08e43693e5745b803ceddcb968a197fa48 Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Fri, 22 Dec 2017 16:03:54 +0100 Subject: [PATCH 011/118] Implementation of critical section primitives which can be called from diferent contexts. Orginal nordic critical primitives must been called in pairs from exacly the same function. As mbed hal call it in separate methods, so they are not suitable here. --- .../TARGET_NRF5/nordic_critical.c | 77 ++++++++++++++++++- 1 file changed, 74 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c index 866cb10fbc..e3a1938164 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c @@ -18,14 +18,85 @@ #include #include "app_util_platform.h" -static uint8_t nordic_cr_nested = 0; +#if defined(SOFTDEVICE_PRESENT) +static volatile uint32_t nordic_cr_nested = 0; + +static void nordic_nvic_critical_region_enter(void); +static void nordic_nvic_critical_region_exit(void); +#endif void core_util_critical_section_enter() { - app_util_critical_region_enter(&nordic_cr_nested); +#ifdef NRF52 + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + nordic_nvic_critical_region_enter(); +#else + app_util_disable_irq(); +#endif } void core_util_critical_section_exit() { - app_util_critical_region_exit(nordic_cr_nested); +#ifdef NRF52 + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + nordic_nvic_critical_region_exit(); +#else + app_util_enable_irq(); +#endif } + +#if defined(SOFTDEVICE_PRESENT) +/**@brief Enters critical region. + * + * @post Application interrupts will be disabled. + * @sa nordic_nvic_critical_region_exit + */ +static inline void nordic_nvic_critical_region_enter(void) +{ + int was_masked = __sd_nvic_irq_disable(); + + if (nordic_cr_nested == 0) { + nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); + NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; +#ifdef NRF52 + nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); + NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; +#endif + } + + nordic_cr_nested++; + + if (!was_masked) { + __sd_nvic_irq_enable(); + } +} + +/**@brief Exit critical region. + * + * @pre Application has entered a critical region using ::nordic_nvic_critical_region_enter. + * @post If not in a nested critical region, the application interrupts will restored to the state before ::nordic_nvic_critical_region_enter was called. + */ +static inline void nordic_nvic_critical_region_exit(void) +{ + nordic_cr_nested--; + + if (nordic_cr_nested == 0) { + int was_masked = __sd_nvic_irq_disable(); + NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; +#ifdef NRF52 + NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; +#endif + if (!was_masked) { + __sd_nvic_irq_enable(); + } + } +} +#endif From 5982972ba5039022ebc36eb094739e3ebaf72d50 Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Tue, 28 Nov 2017 13:35:52 +0100 Subject: [PATCH 012/118] Enable tickless for nRF52840 --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 85b1af66ca..798f175c60 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3233,7 +3233,7 @@ "MCU_NRF52840": { "inherits": ["Target"], "core": "Cortex-M4F", - "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], + "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"], "device_has": ["STCLK_OFF_DURING_SLEEP"], "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"], "OUTPUT_EXT": "hex", From bb2028828f4dfacce45cadb0c5e2f0f5f6f5c6d1 Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Wed, 6 Dec 2017 14:32:10 +0100 Subject: [PATCH 013/118] mem_trace tests refactoring --- TESTS/mbed_drivers/mem_trace/main.cpp | 277 +++++++++++++++++++------- 1 file changed, 209 insertions(+), 68 deletions(-) diff --git a/TESTS/mbed_drivers/mem_trace/main.cpp b/TESTS/mbed_drivers/mem_trace/main.cpp index 5b10b45a62..286be0377b 100644 --- a/TESTS/mbed_drivers/mem_trace/main.cpp +++ b/TESTS/mbed_drivers/mem_trace/main.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -28,15 +28,27 @@ #error [NOT_SUPPORTED] test not supported #endif -using namespace utest::v1; +using utest::v1::Case; + /******************************************************************************/ /* Helper functions and data structures */ /******************************************************************************/ +#define THREAD_STACK_SIZE 384 +#define NUM_TEST_THREADS 3 + +template +class TestThread : public Thread { + uint8_t stack[STACK_SIZE]; +public: + TestThread() : Thread(PRIORITY, STACK_SIZE, stack) { } +}; + // This structure keeps data about the various memory allocation operations, // as traced by 'test_trace_cb' below. #define TEST_MAX_MEMORY_OPS 10 + // Trace results for all possible operations typedef struct { uint8_t op; @@ -58,24 +70,28 @@ typedef struct { } free_info; }; } mem_trace_data_t; + // Memory operation statistics typedef struct { mem_trace_data_t op_data[TEST_MAX_MEMORY_OPS]; uint32_t total_ops; bool invalid_op, overflow; } stats_t; + static stats_t stats; + // Clear all the memory statistics -static void test_clear_stats() { +static void test_clear_stats() +{ memset(&stats, 0, sizeof(stats)); } // Memory tracer callback that records each operation in "stats" (above) -extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) { +extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) +{ va_list va; mem_trace_data_t *pmem = stats.op_data + stats.total_ops; - if (stats.total_ops >= TEST_MAX_MEMORY_OPS) { stats.overflow = true; return; @@ -110,180 +126,305 @@ extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) { } // Generic sanity checks for the tracer -static void check_sanity(uint32_t expected_ops) { +static void check_sanity(uint32_t expected_ops) +{ TEST_ASSERT_FALSE(stats.overflow); TEST_ASSERT_FALSE(stats.invalid_op); - TEST_ASSERT_EQUAL_UINT32(stats.total_ops, expected_ops); + TEST_ASSERT_EQUAL_UINT32(expected_ops, stats.total_ops); } // Check a "malloc" operation -static void check_malloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_size) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_MALLOC); - TEST_ASSERT_EQUAL_PTR(p->res, expected_res); - TEST_ASSERT_EQUAL_UINT32(p->malloc_info.arg_size, expected_arg_size); +static void check_malloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_size) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_MALLOC, p->op); + TEST_ASSERT_EQUAL_PTR(expected_res, p->res); + TEST_ASSERT_EQUAL_UINT32(expected_arg_size, p->malloc_info.arg_size); } // Check a "free" operation -static void check_free_op(const mem_trace_data_t *p, void *expected_arg_ptr) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_FREE); - TEST_ASSERT_EQUAL_PTR(p->free_info.arg_ptr, expected_arg_ptr); +static void check_free_op(const mem_trace_data_t *p, void *expected_arg_ptr) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_FREE, p->op); + TEST_ASSERT_EQUAL_PTR(expected_arg_ptr, p->free_info.arg_ptr); } // Check a "realloc" operation -static void check_realloc_op(const mem_trace_data_t *p, void *expected_res, void *expected_arg_ptr, size_t expected_arg_size) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_REALLOC); - TEST_ASSERT_EQUAL_PTR(p->res, expected_res); - TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_ptr, expected_arg_ptr); - TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_size, expected_arg_size); +static void check_realloc_op(const mem_trace_data_t *p, void *expected_res, void *expected_arg_ptr, size_t expected_arg_size) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_REALLOC, p->op); + TEST_ASSERT_EQUAL_PTR(expected_res, p->res); + TEST_ASSERT_EQUAL_UINT32(expected_arg_ptr, p->realloc_info.arg_ptr); + TEST_ASSERT_EQUAL_UINT32(expected_arg_size, p->realloc_info.arg_size); } // Check a "calloc" operation -static void check_calloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_nmemb, size_t expected_arg_size) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_CALLOC); - TEST_ASSERT_EQUAL_PTR(p->res, expected_res); - TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_nmemb, expected_arg_nmemb); - TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_size, expected_arg_size); +static void check_calloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_nmemb, size_t expected_arg_size) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_CALLOC, p->op); + TEST_ASSERT_EQUAL_PTR(expected_res, p->res); + TEST_ASSERT_EQUAL_UINT32(expected_arg_nmemb, p->calloc_info.arg_nmemb); + TEST_ASSERT_EQUAL_UINT32(expected_arg_size, p->calloc_info.arg_size); } -/******************************************************************************/ -/* Tests */ -/******************************************************************************/ +// Memory tracer callback to test thread safety +extern "C" void test_trace_cb_multithread(uint8_t op, void *res, void *caller, ...) +{ + volatile static int trace_guard = 0; + trace_guard++; + TEST_ASSERT_TRUE_MESSAGE(trace_guard == 1, "Race condition occurred !!!!"); + trace_guard--; +} -// Allocate a single buffer, then free it. Check that tracing matches the operations. -static void test_case_single_malloc_free() { +// Thread function +void malloc_free(volatile bool *thread_continue) +{ + const size_t block_size = 126; + + while(*thread_continue) { + void *p = malloc(block_size); + TEST_ASSERT_NOT_EQUAL(p, NULL); + free(p); + } +} + + +/** Test single malloc/free tracing + * + * Given a memory trace mechanism + * When perform single memory allocation/deallocation using malloc/free + * Then tracing matches the operations + * + */ +static void test_case_single_malloc_free() +{ + const uint32_t num_op = 2; const size_t block_size = 126; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a single memory block void *p = malloc(block_size); TEST_ASSERT_NOT_EQUAL(p, NULL); + // Free the memory block free(p); + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(2); - check_malloc_op(pmem ++, p, block_size); + check_sanity(num_op); + check_malloc_op(pmem++, p, block_size); check_free_op(pmem, p); } -// Test all memory operations (malloc, realloc, free, calloc) -static void test_case_all_memory_ops() { + +/** Test all memory operations (malloc, realloc, free, calloc) tracing + * + * Given a memory trace mechanism + * When perform all memory operations + * Then tracing matches the operations + * + */ +static void test_case_all_memory_ops() +{ + const uint32_t num_op = 5; const size_t malloc_size = 40, realloc_size = 80, nmemb = 25, size = 10; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a single memory block, the realloc it void *p_malloc = malloc(malloc_size); TEST_ASSERT_NOT_EQUAL(p_malloc, NULL); void *p_realloc = realloc(p_malloc, realloc_size); TEST_ASSERT_NOT_EQUAL(p_realloc, NULL); + // Use calloc() now void *p_calloc = calloc(nmemb, size); - //TEST_ASSERT_NOT_EQUAL(p_calloc, NULL); + TEST_ASSERT_NOT_EQUAL(p_calloc, NULL); + // Free the realloc() pointer first, then the calloc() one free(p_realloc); free(p_calloc); + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(6); - check_malloc_op(pmem ++, p_malloc, malloc_size); - check_realloc_op(pmem ++, p_realloc, p_malloc, realloc_size); - // calloc() calls malloc() internally - check_malloc_op(pmem ++, p_calloc, nmemb * size); - check_calloc_op(pmem ++, p_calloc, nmemb, size); - check_free_op(pmem ++, p_realloc); + check_sanity(num_op); + check_malloc_op(pmem++, p_malloc, malloc_size); + check_realloc_op(pmem++, p_realloc, p_malloc, realloc_size); + check_calloc_op(pmem++, p_calloc, nmemb, size); + check_free_op(pmem++, p_realloc); check_free_op(pmem, p_calloc); } -// Test that tracing is off when using a NULL callback -static void test_case_trace_off() { + +/** Test that tracing is off when using a NULL callback + * + * Given a memory trace mechanism + * When tracing is turned off + * Then performed memory operations doesn't report any tracing + * + */ +static void test_case_trace_off() +{ + const uint32_t num_op = 0; const size_t malloc_size = 10; test_clear_stats(); // We don't want any tracing mbed_mem_trace_set_callback(NULL); + // Allocate a buffer and free it void *p_malloc = malloc(malloc_size); TEST_ASSERT_NOT_EQUAL(p_malloc, NULL); free(p_malloc); + // Check that we didn't trace anything - check_sanity(0); + check_sanity(num_op); } -// Test partial tracing (start tracing, stop tracing, restart later) -static void test_case_partial_trace() { + +/** Test partial tracing + * + * Given a memory trace mechanism + * When perform memory operations while tracing is on then off and on again + * Then tracing report only part of operations + * + */ +static void test_case_partial_trace() +{ + const uint32_t num_op = 2; const size_t malloc_size_1 = 20, malloc_size_2 = 30; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); + // Start tracing mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a buffer void *p_malloc_1 = malloc(malloc_size_1); TEST_ASSERT_NOT_EQUAL(p_malloc_1, NULL); + // Disable tracing before freeing the first buffer mbed_mem_trace_set_callback(NULL); free(p_malloc_1); + // Allocate another buffer (still not traced) void *p_malloc_2 = malloc(malloc_size_2); TEST_ASSERT_NOT_EQUAL(p_malloc_2, NULL); + // Re-enable tracing mbed_mem_trace_set_callback(test_trace_cb); + // And free the second buffer (this operation should be tracer) free(p_malloc_2); + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(2); - check_malloc_op(pmem ++, p_malloc_1, malloc_size_1); + check_sanity(num_op); + check_malloc_op(pmem++, p_malloc_1, malloc_size_1); check_free_op(pmem, p_malloc_2); } -// Test new/delete tracing -static void test_case_new_delete() { + +/** Test new/delete tracing + * + * Given a memory trace mechanism + * When memory allocation/deallocation is performed using new/delete + * Then tracing matches the operations + * + */ +static void test_case_new_delete() +{ + const uint32_t num_op = 4; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); + // Start tracing mbed_mem_trace_set_callback(test_trace_cb); + // Test new, new[], delete and delete[] int *p_int = new int; int *p_int_array = new int[10]; delete p_int; delete[] p_int_array; + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(4); - check_malloc_op(pmem ++, p_int, sizeof(int)); - check_malloc_op(pmem ++, p_int_array, 10 * sizeof(int)); - check_free_op(pmem ++, p_int); - check_free_op(pmem ++, p_int_array); + check_sanity(num_op); + check_malloc_op(pmem++, p_int, sizeof(int)); + check_malloc_op(pmem++, p_int_array, 10 * sizeof(int)); + check_free_op(pmem++, p_int); + check_free_op(pmem, p_int_array); } -static Case cases[] = { - Case("single malloc/free", test_case_single_malloc_free), - Case("all memory operations", test_case_all_memory_ops), - Case("trace off", test_case_trace_off), - Case("partial trace", test_case_partial_trace), - Case("test new/delete", test_case_new_delete) + +/** Test tracing thread safety + * + * Given a memory trace mechanism and multiple threads are started in parallel + * When each of the threads perform memory allocation/deallocation (thus uses memory trace mechanisms) + * Then tracing is protected against simultaneous multithreaded access + * + */ +static void test_case_multithread_malloc_free() +{ + const uint32_t wait_time_us = 10000; + volatile bool threads_continue; + TestThread threads[NUM_TEST_THREADS]; + + mbed_mem_trace_set_callback(test_trace_cb_multithread); + + threads_continue = true; + for (int i = 0; i < NUM_TEST_THREADS; i++) { + threads[i].start(callback(malloc_free, &threads_continue)); + } + + Thread::wait(wait_time_us); + threads_continue = false; + + for (int i = 0; i < NUM_TEST_THREADS; i++) { + threads[i].join(); + } + + mbed_mem_trace_set_callback(NULL); +} + + + +static Case cases[] = +{ + Case("Test single malloc/free trace", test_case_single_malloc_free), + Case("Test all memory operations trace", test_case_all_memory_ops), + Case("Test trace off", test_case_trace_off), + Case("Test partial trace", test_case_partial_trace), + Case("Test new/delete trace", test_case_new_delete), + Case("Test multithreaded trace", test_case_multithread_malloc_free) }; -static status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(20, "default_auto"); - return greentea_test_setup_handler(number_of_cases); +static utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(15, "default_auto"); + return utest::v1::greentea_test_setup_handler(number_of_cases); } -static Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); +static utest::v1::Specification specification(greentea_test_setup, cases, utest::v1::greentea_test_teardown_handler); -int main() { +int main() +{ // Disable stdout buffering to prevent any unwanted allocations setvbuf(stdout, NULL, _IONBF, 0); - Harness::run(specification); -} + return !utest::v1::Harness::run(specification); +} From 3d90822ed281a6eeac1fd1174971fc050ce1dceb Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 12 Dec 2017 16:52:32 +0100 Subject: [PATCH 014/118] STM32F3: add Flash api --- .../TARGET_STM32F3/common_objects.h | 7 + targets/TARGET_STM/TARGET_STM32F3/flash_api.c | 173 ++++++++++++++++++ 2 files changed, 180 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32F3/flash_api.c diff --git a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h index ba731890ce..590b60d94c 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h @@ -132,6 +132,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #include "gpio_object.h" #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c new file mode 100644 index 0000000000..459294d045 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -0,0 +1,173 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "mbed_assert.h" +#include "cmsis.h" + +#define NUM_PAGES_IN_SECTOR (1U) +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Falsh */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + uint32_t PAGEError = 0; + FLASH_EraseInitTypeDef EraseInitStruct; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR); + /* MBED HAL erases 1 sector at a time */ + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.PageAddress = address; + EraseInitStruct.NbPages = NUM_PAGES_IN_SECTOR; + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; + +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, + const uint8_t *data, uint32_t size) +{ + uint32_t StartAddress = 0; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if ((size % 4) != 0) { + /* F3 flash devices can only be programmed 32bits/4 bytes at a time */ + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Program the user Flash area word by word */ + StartAddress = address; + + /* HW needs an aligned address to program flash, which data + * parameters doesn't ensure */ + if ((uint32_t) data % 4 != 0) { + volatile uint32_t data32; + while (address < (StartAddress + size) && (status == 0)) { + for (uint8_t i =0; i < 4; i++) { + *(((uint8_t *) &data32) + i) = *(data + i); + } + + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) { + address = address + 4; + data = data + 4; + } else { + status = -1; + } + } + } else { /* case where data is aligned, so let's avoid any copy */ + while ((address < (StartAddress + size)) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + address = address + 4; + data = data + 4; + } else { + status = -1; + } + } + } + + flash_lock(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return MBED_FLASH_INVALID_SIZE; + } else { + return (NUM_PAGES_IN_SECTOR * FLASH_PAGE_SIZE); + } +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + /* Page size is the minimum programmable size, which is 4 bytes */ + return 4; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +#endif From a9a4cdd64d099838920ef4fa030b6ecd89a363a4 Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 12 Dec 2017 17:09:22 +0100 Subject: [PATCH 015/118] STM32F303xE: add FLASH support in targets.json --- targets/targets.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 798f175c60..86fde468d4 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -959,7 +959,7 @@ } }, "detect_code": ["0745"], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F303RE" }, @@ -976,7 +976,7 @@ } }, "detect_code": ["0747"], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F303ZE" }, From 349056ca48685f317a105b9a2018154ec30ea799 Mon Sep 17 00:00:00 2001 From: bcostm Date: Wed, 13 Dec 2017 09:59:49 +0100 Subject: [PATCH 016/118] STM32F3: flash_api typos --- targets/TARGET_STM/TARGET_STM32F3/flash_api.c | 84 +++++++++++++++---- 1 file changed, 68 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c index 459294d045..9827f94507 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -21,14 +21,28 @@ #include "mbed_assert.h" #include "cmsis.h" -#define NUM_PAGES_IN_SECTOR (1U) -#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) +#ifndef FLASH_SIZE +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) +#endif +// Minimum number of bytes to be programmed at a time +#define MIN_PROG_SIZE (4U) + +/** Initialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ int32_t flash_init(flash_t *obj) { return 0; } +/** Uninitialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ int32_t flash_free(flash_t *obj) { return 0; @@ -55,6 +69,13 @@ static int32_t flash_lock(void) } } +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ int32_t flash_erase_sector(flash_t *obj, uint32_t address) { uint32_t PAGEError = 0; @@ -70,11 +91,12 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) } __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR); + /* MBED HAL erases 1 sector at a time */ /* Fill EraseInit structure*/ EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; EraseInitStruct.PageAddress = address; - EraseInitStruct.NbPages = NUM_PAGES_IN_SECTOR; + EraseInitStruct.NbPages = 1; /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code @@ -88,9 +110,19 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) flash_lock(); return status; - } +/** Program one page starting at defined address + * + * The page should be at page boundary, should not cross multiple sectors. + * This function does not do any check for address alignments or if size + * is aligned to a page size. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) { @@ -101,8 +133,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return -1; } - if ((size % 4) != 0) { - /* F3 flash devices can only be programmed 32bits/4 bytes at a time */ + if ((size % MIN_PROG_SIZE) != 0) { return -1; } @@ -113,18 +144,18 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, /* Program the user Flash area word by word */ StartAddress = address; - /* HW needs an aligned address to program flash, which data - * parameters doesn't ensure */ + /* HW needs an aligned address to program flash, which data parameter doesn't ensure */ if ((uint32_t) data % 4 != 0) { + volatile uint32_t data32; while (address < (StartAddress + size) && (status == 0)) { - for (uint8_t i =0; i < 4; i++) { + for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) { *(((uint8_t *) &data32) + i) = *(data + i); } if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) { - address = address + 4; - data = data + 4; + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; } else { status = -1; } @@ -132,8 +163,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, } else { /* case where data is aligned, so let's avoid any copy */ while ((address < (StartAddress + size)) && (status == 0)) { if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { - address = address + 4; - data = data + 4; + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; } else { status = -1; } @@ -145,26 +176,47 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return status; } +/** Get sector size + * + * @param obj The flash object + * @param address The sector starting address + * @return The size of a sector (in our case considering 1 sector = 1 page) + */ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { return MBED_FLASH_INVALID_SIZE; } else { - return (NUM_PAGES_IN_SECTOR * FLASH_PAGE_SIZE); + return FLASH_PAGE_SIZE; } } +/** Get page size + * + * @param obj The flash object + * @param address The page starting address + * @return The size of a page (in our case the minimum programmable size) + */ uint32_t flash_get_page_size(const flash_t *obj) { - /* Page size is the minimum programmable size, which is 4 bytes */ - return 4; + return MIN_PROG_SIZE; } +/** Get start address for the flash region + * + * @param obj The flash object + * @return The start address for the flash region + */ uint32_t flash_get_start_address(const flash_t *obj) { return FLASH_BASE; } +/** Get the flash region size + * + * @param obj The flash object + * @return The flash region size + */ uint32_t flash_get_size(const flash_t *obj) { return FLASH_SIZE; From 5dbc668298d9ebf1c83ed1ba8c61e43af9a12935 Mon Sep 17 00:00:00 2001 From: bcostm Date: Wed, 13 Dec 2017 10:10:30 +0100 Subject: [PATCH 017/118] STM32F3: reset PGERR flash flag --- targets/TARGET_STM/TARGET_STM32F3/flash_api.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c index 9827f94507..27e42a3c1b 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -90,7 +90,8 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return -1; } - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR); + // Clear Flash status register's flags + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); /* MBED HAL erases 1 sector at a time */ /* Fill EraseInit structure*/ From eaf7077a9c741b3db1f717df6f4acc9a3ac1a613 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 18 Dec 2017 10:21:53 +0100 Subject: [PATCH 018/118] STM32F3: Remove flash functions doc + typos --- targets/TARGET_STM/TARGET_STM32F3/flash_api.c | 81 ++++--------------- 1 file changed, 15 insertions(+), 66 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c index 27e42a3c1b..9a2d7c4c8e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -28,29 +28,9 @@ // Minimum number of bytes to be programmed at a time #define MIN_PROG_SIZE (4U) -/** Initialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_init(flash_t *obj) -{ - return 0; -} - -/** Uninitialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_free(flash_t *obj) -{ - return 0; -} - static int32_t flash_unlock(void) { - /* Allow Access to Flash control registers and user Falsh */ + /* Allow Access to Flash control registers and user Flash */ if (HAL_FLASH_Unlock()) { return -1; } else { @@ -69,13 +49,16 @@ static int32_t flash_lock(void) } } -/** Erase one sector starting at defined address - * - * The address should be at sector boundary. This function does not do any check for address alignments - * @param obj The flash object - * @param address The sector starting address - * @return 0 for success, -1 for error - */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + int32_t flash_erase_sector(flash_t *obj, uint32_t address) { uint32_t PAGEError = 0; @@ -113,19 +96,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return status; } -/** Program one page starting at defined address - * - * The page should be at page boundary, should not cross multiple sectors. - * This function does not do any check for address alignments or if size - * is aligned to a page size. - * @param obj The flash object - * @param address The sector starting address - * @param data The data buffer to be programmed - * @param size The number of bytes to program - * @return 0 for success, -1 for error - */ -int32_t flash_program_page(flash_t *obj, uint32_t address, - const uint8_t *data, uint32_t size) +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) { uint32_t StartAddress = 0; int32_t status = 0; @@ -177,13 +148,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return status; } -/** Get sector size - * - * @param obj The flash object - * @param address The sector starting address - * @return The size of a sector (in our case considering 1 sector = 1 page) - */ -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { return MBED_FLASH_INVALID_SIZE; @@ -192,33 +157,17 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) } } -/** Get page size - * - * @param obj The flash object - * @param address The page starting address - * @return The size of a page (in our case the minimum programmable size) - */ uint32_t flash_get_page_size(const flash_t *obj) { return MIN_PROG_SIZE; } -/** Get start address for the flash region - * - * @param obj The flash object - * @return The start address for the flash region - */ -uint32_t flash_get_start_address(const flash_t *obj) +uint32_t flash_get_start_address(const flash_t *obj) { return FLASH_BASE; } -/** Get the flash region size - * - * @param obj The flash object - * @return The flash region size - */ -uint32_t flash_get_size(const flash_t *obj) +uint32_t flash_get_size(const flash_t *obj) { return FLASH_SIZE; } From 37cc8a2876fb598c298a594a79911dbb5a84e103 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Wed, 13 Dec 2017 16:04:33 +1100 Subject: [PATCH 019/118] Cleared data structures in analogin_init(); Set buffer for 1 sample in analogin_read_u16. Before it assumes the buffer is set outside by the higher layer. Now it's temporarily located on the stack since only the ADC value is returned. --- .../TARGET_ADUCM3029/api/analogin_api.c | 17 +++++++++++++---- .../TARGET_ADUCM4050/api/analogin_api.c | 12 ++++++++++-- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c index 91905d61bd..621c8b2038 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c @@ -47,7 +47,6 @@ #include "pinmap.h" #include "PeripheralPins.h" - #ifdef __cplusplus extern "C" { #endif @@ -80,7 +79,10 @@ void analogin_init(analogin_t *obj, PinName pin) ADCName peripheral; uint32_t function, channel; - peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral + memset(obj, 0, sizeof(analogin_t) ); + memset( DeviceMemory, 0, sizeof( DeviceMemory ) ); + + peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral MBED_ASSERT(peripheral != (ADCName)NC); /* verify read function */ @@ -142,6 +144,7 @@ void analogin_init(analogin_t *obj, PinName pin) /* Set the acquisition time. (Application need to change it based on the impedence) */ adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles); + } /** Read the input voltage, represented as a float in the range [0.0, 1.0] @@ -165,6 +168,11 @@ uint16_t analogin_read_u16(analogin_t *obj) { ADI_ADC_HANDLE hDevice = obj->hDevice; ADI_ADC_BUFFER *pAdcBuffer; + uint32_t ADCsample; + + obj->UserBuffer.pDataBuffer = &ADCsample; + obj->UserBuffer.nNumConversionPasses = 1; + obj->UserBuffer.nBuffSize = 1; /* Submit the buffer to the driver */ adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer); @@ -178,8 +186,9 @@ uint16_t analogin_read_u16(analogin_t *obj) return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); } -/* Retrieve te active channel correspondoing to the input pin */ -static uint32_t adi_pin2channel(PinName pin) { +/* Retrieve the active channel corresponding to the input pin */ +static uint32_t adi_pin2channel(PinName pin) +{ uint32_t activech; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c index baa96a694e..621c8b2038 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -79,7 +79,10 @@ void analogin_init(analogin_t *obj, PinName pin) ADCName peripheral; uint32_t function, channel; - peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral + memset(obj, 0, sizeof(analogin_t) ); + memset( DeviceMemory, 0, sizeof( DeviceMemory ) ); + + peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral MBED_ASSERT(peripheral != (ADCName)NC); /* verify read function */ @@ -165,6 +168,11 @@ uint16_t analogin_read_u16(analogin_t *obj) { ADI_ADC_HANDLE hDevice = obj->hDevice; ADI_ADC_BUFFER *pAdcBuffer; + uint32_t ADCsample; + + obj->UserBuffer.pDataBuffer = &ADCsample; + obj->UserBuffer.nNumConversionPasses = 1; + obj->UserBuffer.nBuffSize = 1; /* Submit the buffer to the driver */ adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer); @@ -178,7 +186,7 @@ uint16_t analogin_read_u16(analogin_t *obj) return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); } -/* Retrieve te active channel correspondoing to the input pin */ +/* Retrieve the active channel corresponding to the input pin */ static uint32_t adi_pin2channel(PinName pin) { From 8a2a182bfeab1760088043f4a63fd5eef9f46bde Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 20 Dec 2017 14:35:00 +0100 Subject: [PATCH 020/118] lp_timer test : add a minimum delta value --- TESTS/mbed_drivers/lp_timer/main.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/TESTS/mbed_drivers/lp_timer/main.cpp b/TESTS/mbed_drivers/lp_timer/main.cpp index bf3f09639e..a7232149a3 100644 --- a/TESTS/mbed_drivers/lp_timer/main.cpp +++ b/TESTS/mbed_drivers/lp_timer/main.cpp @@ -51,13 +51,17 @@ extern uint32_t SystemCoreClock; * For K64F DELTA = (80000 / 120000000) * 1000000 = 666[us] * For NUCLEO_F070RB DELTA = (80000 / 48000000) * 1000000 = 1666[us] * For NRF51_DK DELTA = (80000 / 16000000) * 1000000 = 5000[us] + * + * As low power timer cannot be too much accurate, this DELTA should not be more precise than 500us, + * which corresponds to a maximum CPU clock around 130MHz */ #define US_PER_SEC 1000000 #define US_PER_MSEC 1000 #define TOLERANCE_FACTOR 80000.0f #define US_FACTOR 1000000.0f +#define CLOCK_MAX 130000000 -static const int delta_sys_clk_us = ((int) (TOLERANCE_FACTOR / (float) SystemCoreClock * US_FACTOR)); +static const int delta_sys_clk_us = (SystemCoreClock < CLOCK_MAX? ((int) (TOLERANCE_FACTOR / (float) SystemCoreClock * US_FACTOR)):((int) (TOLERANCE_FACTOR / (float) CLOCK_MAX * US_FACTOR))); /* When test performs time measurement using Timer in sequence, then measurement error accumulates * in the successive attempts. */ From 2ead50c32565493a97149cc21bc08d0b9e6e2280 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Wed, 20 Dec 2017 18:52:04 +0000 Subject: [PATCH 021/118] Adding MTB ublox ODIN W2 --- .../stm32f4_eth_conf.c | 61 +++++ .../stm32f4_eth_init.c | 143 +++++++++++ .../TARGET_MTB_UBLOX_ODIN_W2/PinNames.h | 238 ++++++++++++++++++ targets/targets.json | 19 ++ 4 files changed, 461 insertions(+) create mode 100644 features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c create mode 100644 features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c new file mode 100644 index 0000000000..d5b3414f4c --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32f4xx_hal.h" + +void _eth_config_mac(ETH_HandleTypeDef *heth) +{ + ETH_MACInitTypeDef macconf = + { + .Watchdog = ETH_WATCHDOG_ENABLE, + .Jabber = ETH_JABBER_ENABLE, + .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, + .CarrierSense = ETH_CARRIERSENCE_ENABLE, + .ReceiveOwn = ETH_RECEIVEOWN_ENABLE, + .LoopbackMode = ETH_LOOPBACKMODE_DISABLE, + .ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE, + .RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE, + .AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE, + .BackOffLimit = ETH_BACKOFFLIMIT_10, + .DeferralCheck = ETH_DEFFERRALCHECK_DISABLE, + .ReceiveAll = ETH_RECEIVEAll_DISABLE, + .SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE, + .PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL, + .BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE, + .DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL, + .PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE, + .MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter + .UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT, + .HashTableHigh = 0x0U, + .HashTableLow = 0x0U, + .PauseTime = 0x0U, + .ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE, + .PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4, + .UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, + .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE, + .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, + .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, + .VLANTagIdentifier = 0x0U + }; + + if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } else { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + + (void) HAL_ETH_ConfigMAC(heth, &macconf); +} \ No newline at end of file diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c new file mode 100644 index 0000000000..bb6b7448c4 --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c @@ -0,0 +1,143 @@ +#include +#include "stm32f4xx_hal.h" +#include "mbed_toolchain.h" + +#define C029_OTP_START_ADDRESS (0x1FFF7800U) +#define C029_OTP_END_ADDRESS (C029_OTP_START_ADDRESS + (16*32)) +#define C029_MAC_ETHERNET_ID (3) + +typedef MBED_PACKED(struct) C029_OTP_Header { + uint8_t id; + uint8_t len; + uint8_t data[]; +} C029_OTP_Header; + +static int _macRetrieved = 0; +static char _macAddr[6] = { 0x02, 0x02, 0xF7, 0xF0, 0x00, 0x00 }; + +static C029_OTP_Header *increment(C029_OTP_Header *pTemp) +{ + uint8_t len = 0; + uint8_t id = 0; + uint8_t *p = (uint8_t*)pTemp; + + memcpy((void*)&id, (void*)pTemp, 1); + + if (id == 0xFF){ + p++; + } else { + p++; + memcpy((void*)&len, (void*)p++, 1); + p += len; + } + return (C029_OTP_Header*)p; +} + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStructure; + if (heth->Instance == ETH) { + + /* Enable GPIOs clocks */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + /* Configure PA1, PA2 and PA7 */ + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_PULLUP; + GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7; + GPIO_InitStructure.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pin = GPIO_PIN_1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure PB13 */ + GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure PC1, PC4 and PC5 */ + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Enable the Ethernet global Interrupt */ + HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + + /* Enable ETHERNET clock */ + __HAL_RCC_ETH_CLK_ENABLE(); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if (heth->Instance == ETH) { + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); + + /* Disable the Ethernet global Interrupt */ + NVIC_DisableIRQ(ETH_IRQn); + } +} + +uint8_t mbed_otp_mac_address(char *mac) +{ + C029_OTP_Header *pFound = NULL; + C029_OTP_Header *pTemp = (C029_OTP_Header*)C029_OTP_START_ADDRESS; + C029_OTP_Header temp; + + if (_macRetrieved == 0) { + while ((pTemp >= (C029_OTP_Header*)C029_OTP_START_ADDRESS) && (pTemp < (C029_OTP_Header*)C029_OTP_END_ADDRESS)){ + memcpy((void*)&temp, (void*)pTemp, sizeof(temp)); + if (temp.id == C029_MAC_ETHERNET_ID){ + pFound = pTemp; + break; + } + pTemp = increment(pTemp); + } + if (pFound != NULL) { + memcpy(_macAddr, pFound->data, 6); + _macRetrieved = 1; + } + } + memcpy(mac, _macAddr, 6); + + return 1; +} \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h new file mode 100644 index 0000000000..a2e7f25c44 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h @@ -0,0 +1,238 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, + PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + + PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, + PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, + PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, + + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, + PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, + PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, + PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, + + PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, + PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, + PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, + PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, + + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, + PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, + PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, + PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, + + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, + PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, + PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, + PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, + + PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, + PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, + PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, + PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, + + PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, + PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, + PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, + PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + + // Not connected + NC = (int)0xFFFFFFFF, + + // Module Pins + // PortA + P_A1 = NC, + P_A2 = NC, + P_A3 = NC, + P_A4 = NC, + P_A5 = PC_2, // UART-DTR + P_A6 = PF_2, // Switch-0 + P_A7 = PE_0, // Red, Mode + P_A8 = PB_6, // Green, Switch-1 + P_A9 = PB_8, // Blue + P_A10 = PA_11, // UART-CTS + P_A11 = PA_9, // UART-TXD + P_A12 = PA_12, // UART-RTS + P_A13 = PA_10, // UART-RXD + P_A14 = PD_9, // GPIO-0 + P_A15 = PD_8, // GPIO-1 + P_A16 = PD_11, // GPIO-2 + P_A17 = PD_12, // GPIO-3 + P_A18 = PA_3, // UART-DSR + // PortB + P_B1 = NC, + P_B2 = NC, + P_B3 = NC, + P_B4 = NC, + P_B5 = NC, + P_B6 = NC, + P_B7 = NC, + P_B8 = NC, + // PortC + P_C1 = NC, + P_C2 = NC, + P_C3 = NC, + P_C4 = NC, + P_C5 = PG_4, // SPI-IRQ + P_C6 = PE_13, // SPI-MISO + P_C7 = NC, + P_C8 = PE_12, // Res + P_C9 = NC, + P_C10 = PE_14, // SPI-MOSI + P_C11 = PE_11, // SPI-CS0 + P_C12 = PE_9, // Res + P_C13 = PF_6, // GPIO-4 + P_C14 = PC_1, // RMII-MDC + P_C15 = PA_2, // RMII-MDIO + P_C16 = PF_7, // GPIO-7 + P_C17 = PF_1, // I2C-SCL + P_C18 = PF_0, // I2C-SDA + // PortD + P_D1 = PB_12, // RMII-TXD0 + P_D2 = PB_13, // RMII-TXD1 + P_D3 = PB_11, // RMII-TXEN + P_D4 = PA_7, // RMII-CRSDV + P_D5 = PC_4, // RMII-RXD0 + P_D6 = PC_5, // RMII-RXD1 + P_D7 = NC, + P_D8 = PA_1, // RMII-REFCLK + // TestPads + P_TP5 = PB_4, // NTRST + P_TP7 = PA_13, // TMS SWDIO + P_TP8 = PA_15, // TDI + P_TP9 = PA_14, // TCK SWCLK + P_TP10 = PB_3, // TDO + //P_TP11, // BOOT0 + + // Internal + LED1 = PD_9, + LED2 = PA_12, + LED3 = PD_8, + LED4 = PA_11, + LED5 = PC_2, + LED6 = PA_3, + LED7 = PF_6, + LED_RED = PE_0, + LED_GREEN = PB_6, + LED_BLUE = PB_8, + SW1 = PF_2, + SW2 = PG_4, + + // Standardized button names + BUTTON1 = SW1, + BUTTON2 = SW2, + + I2C_SDA = PF_0, + I2C_SCL = PF_1, + + SPI0_MOSI = PE_14, + SPI0_MISO = PE_13, + SPI0_SCK = PE_12, + SPI0_CS = PE_11, + SPI1_CS = PE_9, + + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_CS, + + // DAPLink + USBRX = MBED_CONF_TARGET_USB_RX, + USBTX = MBED_CONF_TARGET_USB_TX, + SWDIO = PA_15, + SWCLK = PA_14, + NTRST = PB_4, + + // MTB Aliases + // Left side (top view) + TGT_SWDIO = SWDIO, + TGT_SWCLK = SWCLK, + TGT_RESET = NTRST, + TG_TX = USBTX, + TG_RX = USBRX, + TX1 = P_A15, + RX1 = P_A14, + SDA1 = P_C18, + SCL1 = P_C17, + MOSI1 = P_C10, + MISO1 = P_C6, + SCK1 = SPI_SCK, + GP0 = BUTTON1, + GP1 = SPI_CS, + AIN0 = P_C13, + AIN1 = P_A18, + AIN2 = P_A5, + + //Right side (top view) + GND = NC, + GP10 = NC, + RTS = NC, + CTS = NC, + GP7 = P_C12, + GP6 = P_A12, + GP5 = P_A10, + GP4 = P_A17, + TX2 = NC, + RX2 = NC, + SDA2 = NC, + SCL2 = NC, + MOSI2 = NC, + MISO2 = NC, + SCK2 = NC, + GP3 = P_A16, + GP2 = P_C5, + PWM2 = LED_GREEN, + PWM1 = LED_BLUE, + PWM0 = LED_RED, + + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/targets.json b/targets/targets.json index 86fde468d4..ca11e7e011 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1835,6 +1835,25 @@ } } }, + "MTB_UBLOX_ODIN_W2": { + "inherits": ["MODULE_UBLOX_ODIN_W2"], + "release_versions": ["5"], + "config": { + "usb_tx": { + "help": "Value PA_11", + "value": "PA_11" + }, + "usb_rx": { + "help": "Value PA_13", + "value": "PA_13" + }, + "stdio_uart": { + "help": "Value: UART_1", + "value": "UART_1", + "macro_name": "STDIO_UART" + } + } + }, "UBLOX_C030": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], From 0c132c57de66cff27915a1a2353ca956ebc6459e Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Thu, 21 Dec 2017 15:38:58 +0000 Subject: [PATCH 022/118] Fixing indentation --- .../TARGET_MTB_UBLOX_ODIN_W2/PinNames.h | 73 +++++++++---------- 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h index a2e7f25c44..ed2efe8318 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h @@ -183,51 +183,50 @@ typedef enum { USBRX = MBED_CONF_TARGET_USB_RX, USBTX = MBED_CONF_TARGET_USB_TX, SWDIO = PA_15, - SWCLK = PA_14, + SWCLK = PA_14, NTRST = PB_4, // MTB Aliases // Left side (top view) TGT_SWDIO = SWDIO, TGT_SWCLK = SWCLK, - TGT_RESET = NTRST, - TG_TX = USBTX, - TG_RX = USBRX, - TX1 = P_A15, - RX1 = P_A14, - SDA1 = P_C18, - SCL1 = P_C17, - MOSI1 = P_C10, - MISO1 = P_C6, - SCK1 = SPI_SCK, - GP0 = BUTTON1, - GP1 = SPI_CS, - AIN0 = P_C13, - AIN1 = P_A18, - AIN2 = P_A5, + TGT_RESET = NTRST, + TG_TX = USBTX, + TG_RX = USBRX, + TX1 = P_A15, + RX1 = P_A14, + SDA1 = P_C18, + SCL1 = P_C17, + MOSI1 = P_C10, + MISO1 = P_C6, + SCK1 = SPI_SCK, + GP0 = BUTTON1, + GP1 = SPI_CS, + AIN0 = P_C13, + AIN1 = P_A18, + AIN2 = P_A5, //Right side (top view) - GND = NC, - GP10 = NC, - RTS = NC, - CTS = NC, - GP7 = P_C12, - GP6 = P_A12, - GP5 = P_A10, - GP4 = P_A17, - TX2 = NC, - RX2 = NC, - SDA2 = NC, - SCL2 = NC, - MOSI2 = NC, - MISO2 = NC, - SCK2 = NC, - GP3 = P_A16, - GP2 = P_C5, - PWM2 = LED_GREEN, - PWM1 = LED_BLUE, - PWM0 = LED_RED, - + GND = NC, + GP10 = NC, + RTS = NC, + CTS = NC, + GP7 = P_C12, + GP6 = P_A12, + GP5 = P_A10, + GP4 = P_A17, + TX2 = NC, + RX2 = NC, + SDA2 = NC, + SCL2 = NC, + MOSI2 = NC, + MISO2 = NC, + SCK2 = NC, + GP3 = P_A16, + GP2 = P_C5, + PWM2 = LED_GREEN, + PWM1 = LED_BLUE, + PWM0 = LED_RED, } PinName; From 9c07a11a1b3e66ee38b6e2ded03f5527758b2956 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Thu, 21 Dec 2017 16:14:00 +0000 Subject: [PATCH 023/118] Add new line to EOF --- .../TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c index d5b3414f4c..56f754a4f4 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c @@ -58,4 +58,4 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) } (void) HAL_ETH_ConfigMAC(heth, &macconf); -} \ No newline at end of file +} From de0db5290374c15b524f08b09484f0fdac75f731 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Fri, 22 Dec 2017 13:54:22 +0000 Subject: [PATCH 024/118] Adding license info --- .../TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c index bb6b7448c4..9baf012f2a 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c @@ -1,3 +1,19 @@ +/* Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include #include "stm32f4xx_hal.h" #include "mbed_toolchain.h" From 5894775398e15058c526b81f37de7044458b2c9a Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 09:39:41 +0800 Subject: [PATCH 025/118] Remove debug code in AES alternative --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 43 ++----------------- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 9 +--- 2 files changed, 5 insertions(+), 47 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 0aeeb0286b..b256c729af 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -40,8 +40,6 @@ -#define mbedtls_trace(...) //printf(__VA_ARGS__) - /* Implementation that should never be optimized out by the compiler */ static void mbedtls_zeroize( void *v, size_t n ) { volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; @@ -59,13 +57,6 @@ extern volatile int g_AES_done; MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; -static void dumpHex(const unsigned char au8Data[], int len) -{ - int j; - for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]); - mbedtls_trace("\r\n"); -} - static void swapInitVector(unsigned char iv[16]) { unsigned int* piv; @@ -123,8 +114,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) { int i =-1; - - mbedtls_trace("=== %s \r\n", __FUNCTION__); memset( ctx, 0, sizeof( mbedtls_aes_context ) ); ctx->swapType = AES_IN_OUT_SWAP; @@ -143,13 +132,11 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) NVIC_EnableIRQ(CRPT_IRQn); AES_ENABLE_INT(); - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, (int)ctx->channel); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) { - - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,(int)ctx->channel); + if( ctx == NULL ) return; @@ -167,8 +154,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, { unsigned int i; - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex(key,keybits/8); switch( keybits ) { @@ -210,8 +195,6 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, { int ret; - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex((uint8_t *)key,keybits/8); /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) @@ -231,8 +214,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, unsigned char* pIn; unsigned char* pOut; -// mbedtls_trace("=== %s \r\n", __FUNCTION__); - dumpHex(input,16); AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); @@ -257,7 +238,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, while (!g_AES_done); if( pOut != output ) memcpy(output, au8OutputData, dataSize); - dumpHex(output,16); } @@ -268,13 +248,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) -{ - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - +{ ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, 16); - } #endif /* MBEDTLS_AES_ENCRYPT_ALT */ @@ -286,13 +262,8 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, 16); - - } #endif /* MBEDTLS_AES_DECRYPT_ALT */ @@ -304,9 +275,6 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - ctx->opMode = AES_MODE_ECB; if( mode == MBEDTLS_AES_ENCRYPT ) mbedtls_aes_encrypt( ctx, input, output ); @@ -331,7 +299,7 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, unsigned char temp[16]; int length = len; int blockChainLen; - mbedtls_trace("=== %s [0x%x]\r\n", __FUNCTION__,length); + if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); @@ -388,7 +356,7 @@ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, int c; size_t n = *iv_off; unsigned char iv_tmp[16]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); + if( mode == MBEDTLS_AES_DECRYPT ) { while( length-- ) @@ -448,7 +416,6 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, int remLen=0; int ivLen; - mbedtls_trace("=== %s \r\n", __FUNCTION__); // proceed: start with partial block by ECB mode first if( n !=0 ) { @@ -520,7 +487,6 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, unsigned char c; unsigned char ov[17]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); while( length-- ) { memcpy( ov, iv, 16 ); @@ -556,7 +522,6 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, int c, i; size_t n = *nc_off; - mbedtls_trace("=== %s \r\n", __FUNCTION__); while( length-- ) { if( n == 0 ) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index f0fec3122a..8d16e333be 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -53,15 +53,8 @@ typedef struct uint32_t channel; uint32_t swapType; uint32_t *iv; - unsigned char prv_iv[16]; -#if 1 + unsigned char prv_iv[16]; uint32_t buf[8]; -/* For comparsion with software AES for correctness */ -#else - uint32_t buf[68]; /*!< unaligned data */ - int nr; /*!< number of rounds */ - uint32_t *rk; /*!< AES round keys */ -#endif } mbedtls_aes_context; From d174e850cad50d078d867d7f6510f966b12502ae Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 09:46:34 +0800 Subject: [PATCH 026/118] Remove other unnecessary AES alternative macro definitions As MBEDTLS_AES_ALT is defined, alternative implementations for all AES functions should be defined. --- .../TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h | 4 ---- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 8 -------- 2 files changed, 12 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h index 22396dfea2..1043cab9fd 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h @@ -23,9 +23,5 @@ #define MBEDTLS_SHA512_ALT #define MBEDTLS_AES_ALT -#define MBEDTLS_AES_SETKEY_ENC_ALT -#define MBEDTLS_AES_SETKEY_DEC_ALT -#define MBEDTLS_AES_ENCRYPT_ALT -#define MBEDTLS_AES_DECRYPT_ALT #endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index b256c729af..d61c2d20af 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -148,7 +148,6 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ) /* * AES key schedule (encryption) */ -#if defined(MBEDTLS_AES_SETKEY_ENC_ALT) int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits ) { @@ -184,12 +183,10 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, return( 0 ); } -#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */ /* * AES key schedule (decryption) */ -#if defined(MBEDTLS_AES_SETKEY_DEC_ALT) int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits ) { @@ -204,7 +201,6 @@ exit: return( ret ); } -#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, @@ -244,7 +240,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* * AES-ECB block encryption */ -#if defined(MBEDTLS_AES_ENCRYPT_ALT) void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) @@ -252,12 +247,10 @@ void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, 16); } -#endif /* MBEDTLS_AES_ENCRYPT_ALT */ /* * AES-ECB block decryption */ -#if defined(MBEDTLS_AES_DECRYPT_ALT) void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) @@ -265,7 +258,6 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, 16); } -#endif /* MBEDTLS_AES_DECRYPT_ALT */ /* * AES-ECB block encryption/decryption From d1dab259ab97ad96d998a4e4f74c8075d141da19 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 10:31:16 +0800 Subject: [PATCH 027/118] Remove unnecessary MBEDTLS_CONFIG_FILE check from AES/DES/SHA alternative 1. aes.h/des.h/sha1.h/sha256.h/sha512.h includes config.h before aes_alt.h/des_alt.h/sha1_alt.h/sha256_alt.h/sha512_alt.h. 2. aes_alt.h/des_alt.h/sha1_alt.h/sha256_alt.h/sha512_alt.h should not be included in any other location. 3. Just include aes.h/des.h/sha1.h/sha256.h/sha512.h in aes_alt.c/des_alt.c/sha1_alt.c/sha256_alt.c/sha512_alt.c. --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 8 +------- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 6 ------ .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 8 +------- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.h | 6 ------ .../TARGET_M480/des/des_alt_sw.c | 8 +------- .../TARGET_M480/des/des_alt_sw.h | 6 ------ .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c | 7 +------ .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h | 6 ------ .../TARGET_M480/sha/sha1_alt_sw.c | 9 +-------- .../TARGET_M480/sha/sha1_alt_sw.h | 6 ------ .../TARGET_M480/sha/sha256_alt.c | 7 +------ .../TARGET_M480/sha/sha256_alt.h | 6 ------ .../TARGET_M480/sha/sha256_alt_sw.c | 8 +------- .../TARGET_M480/sha/sha256_alt_sw.h | 6 ------ .../TARGET_M480/sha/sha512_alt.c | 7 +------ .../TARGET_M480/sha/sha512_alt.h | 6 ------ .../TARGET_M480/sha/sha512_alt_sw.c | 8 +------- .../TARGET_M480/sha/sha512_alt_sw.h | 6 ------ .../TARGET_M480/sha/sha_alt_hw.c | 20 +++---------------- .../TARGET_M480/sha/sha_alt_hw.h | 6 ------ 20 files changed, 12 insertions(+), 138 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index d61c2d20af..035a69b059 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -21,19 +21,13 @@ * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/aes.h" #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) #include -#include "mbedtls/aes.h" - #include "M480.h" #include "mbed_toolchain.h" #include "mbed_assert.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index 8d16e333be..c50048a624 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -23,12 +23,6 @@ #ifndef MBEDTLS_AES_ALT_H #define MBEDTLS_AES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index e4e9fd4023..d4389607c1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -14,18 +14,12 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include -#include "mbedtls/des.h" -#include "des_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "mbed_toolchain.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h index b783889d53..58ead66cb9 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h @@ -17,12 +17,6 @@ #ifndef MBEDTLS_DES_ALT_H #define MBEDTLS_DES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c index 1e51151c86..301a5476c1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c @@ -25,17 +25,11 @@ * http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) -#include "mbedtls/des.h" - #include /* Implementation that should never be optimized out by the compiler */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h index d42aa2ba05..9910ce59a7 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h @@ -23,12 +23,6 @@ #ifndef MBEDTLS_DES_ALT_SW_H #define MBEDTLS_DES_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index de6ff01415..1e7a6a1276 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -14,16 +14,11 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h index 6cf738a1bb..94972b54f6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h @@ -16,12 +16,6 @@ #ifndef MBEDTLS_SHA1_ALT_H #define MBEDTLS_SHA1_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c index cc7ff7f074..a8a3679c95 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c @@ -24,17 +24,10 @@ * http://www.itl.nist.gov/fipspubs/fip180-1.htm */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) - -#include "mbedtls/sha1.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h index 9d138abb8a..9f7c210b5d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h @@ -23,12 +23,6 @@ #ifndef MBEDTLS_SHA1_ALT_SW_H #define MBEDTLS_SHA1_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index de337ac525..20f2c79ac6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -14,16 +14,11 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h index 23a156ddd7..494c501caf 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h @@ -16,12 +16,6 @@ #ifndef MBEDTLS_SHA256_ALT_H #define MBEDTLS_SHA256_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c index 2062643335..7c7ec543ba 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c @@ -24,17 +24,11 @@ * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "mbedtls/sha256.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h index c1b72ea8f7..0a33d3fe98 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h @@ -23,12 +23,6 @@ #ifndef MBEDTLS_SHA256_ALT_SW_H #define MBEDTLS_SHA256_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index 365d172b54..9761a1c674 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -14,16 +14,11 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) -#include "sha512_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h index 67ecb0f589..15681f0826 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h @@ -16,12 +16,6 @@ #ifndef MBEDTLS_SHA512_ALT_H #define MBEDTLS_SHA512_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c index 1f8387445c..5b204ccb5e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c @@ -24,17 +24,11 @@ * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) -#include "mbedtls/sha512.h" - #if defined(_MSC_VER) || defined(__WATCOMC__) #define UL64(x) x##ui64 #else diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h index cbdd9b4962..a461977bf6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h @@ -23,12 +23,6 @@ #ifndef MBEDTLS_SHA512_ALT_SW_H #define MBEDTLS_SHA512_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index 3b5c65793a..53e46abfae 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -14,28 +14,14 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) -#if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" -#endif /* MBEDTLS_SHA1_ALT */ - -#if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" -#endif /* MBEDTLS_SHA256_ALT */ - -#if defined(MBEDTLS_SHA512_ALT) -#include "sha512_alt.h" -#endif /* MBEDTLS_SHA512_ALT */ - #include "nu_bitutil.h" #include "mbed_assert.h" #include "crypto-misc.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h index 527a38e657..0ab92e57ce 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h @@ -16,12 +16,6 @@ #ifndef MBEDTLS_SHA_ALT_HW_H #define MBEDTLS_SHA_ALT_HW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) From e7d85cd56cf19ddbb0a136262d7a13817903ecac Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 11:46:16 +0800 Subject: [PATCH 028/118] Fix DES alternative function not thread-safe --- .../targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index d4389607c1..12f8720987 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -24,11 +24,6 @@ #include "nu_bitutil.h" #include "mbed_toolchain.h" -// Must be a multiple of 64-bit block size -#define MAXSIZE_DMABUF (8 * 5) -static uint8_t dmabuf_in[MAXSIZE_DMABUF] MBED_ALIGN(4); -static uint8_t dmabuf_out[MAXSIZE_DMABUF] MBED_ALIGN(4); - static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output); @@ -341,6 +336,11 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S const unsigned char *in_pos = input; unsigned char *out_pos = output; + // Must be a multiple of 64-bit block size + #define MAXSIZE_DMABUF (8 * 5) + MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; + MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; + while (rmn) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; From ca8ac443c645f4c77c3fb3765f283ea026d17106 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 13:09:55 +0800 Subject: [PATCH 029/118] Remove debug code in AES alternative --- .../TARGET_NUC472/aes/aes_alt.c | 29 ------------------- .../TARGET_NUC472/aes/aes_alt.h | 11 ++----- 2 files changed, 2 insertions(+), 38 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index a86c0cb9e3..7f1cd8d56a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -38,11 +38,6 @@ #include "mbed_toolchain.h" #include "mbed_assert.h" -//static int aes_init_done = 0; - - -#define mbedtls_trace(...) //printf(__VA_ARGS__) - /* Implementation that should never be optimized out by the compiler */ static void mbedtls_zeroize( void *v, size_t n ) { volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; @@ -60,12 +55,6 @@ extern volatile int g_AES_done; static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); -static void dumpHex(const unsigned char au8Data[], int len) -{ - int j; - for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]); - mbedtls_trace("\r\n"); -} static void swapInitVector(unsigned char iv[16]) { @@ -121,7 +110,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) // sw_mbedtls_aes_init(ctx); // return; - mbedtls_trace("=== %s \r\n", __FUNCTION__); memset( ctx, 0, sizeof( mbedtls_aes_context ) ); ctx->swapType = AES_IN_OUT_SWAP; @@ -141,13 +129,11 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) NVIC_EnableIRQ(CRPT_IRQn); AES_ENABLE_INT(); - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, (int)ctx->channel); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) { - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,(int)ctx->channel); if( ctx == NULL ) return; @@ -173,8 +159,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, { unsigned int i; - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex(key,keybits/8); switch( keybits ) { @@ -216,8 +200,6 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, { int ret; - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex((uint8_t *)key,keybits/8); /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) @@ -237,8 +219,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, unsigned char* pIn; unsigned char* pOut; -// mbedtls_trace("=== %s \r\n", __FUNCTION__); - dumpHex(input,16); AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); @@ -263,7 +243,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, while (!g_AES_done); if( pOut != output ) memcpy(output, au8OutputData, dataSize); - dumpHex(output,16); } @@ -276,7 +255,6 @@ void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, unsigned char output[16] ) { - mbedtls_trace("=== %s \r\n", __FUNCTION__); ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, 16); @@ -293,7 +271,6 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, unsigned char output[16] ) { - mbedtls_trace("=== %s \r\n", __FUNCTION__); ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, 16); @@ -311,7 +288,6 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, unsigned char output[16] ) { - mbedtls_trace("=== %s \r\n", __FUNCTION__); ctx->opMode = AES_MODE_ECB; if( mode == MBEDTLS_AES_ENCRYPT ) @@ -337,7 +313,6 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, unsigned char temp[16]; int length = len; int blockChainLen; - mbedtls_trace("=== %s [0x%x]\r\n", __FUNCTION__,length); if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); @@ -394,7 +369,6 @@ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, int c; size_t n = *iv_off; unsigned char iv_tmp[16]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); if( mode == MBEDTLS_AES_DECRYPT ) { while( length-- ) @@ -454,7 +428,6 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, int remLen=0; int ivLen; - mbedtls_trace("=== %s \r\n", __FUNCTION__); // proceed: start with partial block by ECB mode first if( n !=0 ) { @@ -526,7 +499,6 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, unsigned char c; unsigned char ov[17]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); while( length-- ) { memcpy( ov, iv, 16 ); @@ -562,7 +534,6 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, int c, i; size_t n = *nc_off; - mbedtls_trace("=== %s \r\n", __FUNCTION__); while( length-- ) { if( n == 0 ) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index d46ef6d16e..a657fce6fa 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -54,15 +54,8 @@ typedef struct uint32_t channel; uint32_t swapType; uint32_t *iv; - unsigned char prv_iv[16]; -#if 1 - uint32_t buf[8]; -/* For comparsion with software AES for correctness */ -#else - uint32_t buf[68]; /*!< unaligned data */ - int nr; /*!< number of rounds */ - uint32_t *rk; /*!< AES round keys */ -#endif + unsigned char prv_iv[16]; + uint32_t buf[8]; } mbedtls_aes_context; From 70c50f2cb1fed95cc059424e4f3279309d36aadb Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 13:17:56 +0800 Subject: [PATCH 030/118] Remove other unnecessary AES alternative macro definitions As MBEDTLS_AES_ALT is defined, alternative implementations for all AES functions should be defined. --- .../TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h | 4 ---- .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 8 -------- 2 files changed, 12 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h index 7f0f6c8142..3a4009a23b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h @@ -22,9 +22,5 @@ #define MBEDTLS_SHA256_ALT #define MBEDTLS_AES_ALT -#define MBEDTLS_AES_SETKEY_ENC_ALT -#define MBEDTLS_AES_SETKEY_DEC_ALT -#define MBEDTLS_AES_ENCRYPT_ALT -#define MBEDTLS_AES_DECRYPT_ALT #endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 7f1cd8d56a..0cbcc875ec 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -153,7 +153,6 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ) /* * AES key schedule (encryption) */ -#if defined(MBEDTLS_AES_SETKEY_ENC_ALT) int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits ) { @@ -189,12 +188,10 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, return( 0 ); } -#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */ /* * AES key schedule (decryption) */ -#if defined(MBEDTLS_AES_SETKEY_DEC_ALT) int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits ) { @@ -209,7 +206,6 @@ exit: return( ret ); } -#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, @@ -249,7 +245,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* * AES-ECB block encryption */ -#if defined(MBEDTLS_AES_ENCRYPT_ALT) void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) @@ -260,12 +255,10 @@ void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, __nvt_aes_crypt(ctx, input, output, 16); } -#endif /* MBEDTLS_AES_ENCRYPT_ALT */ /* * AES-ECB block decryption */ -#if defined(MBEDTLS_AES_DECRYPT_ALT) void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) @@ -277,7 +270,6 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, } -#endif /* MBEDTLS_AES_DECRYPT_ALT */ /* * AES-ECB block encryption/decryption From 1b82cbdc9144af452d30dd8e5c643c50b66efd94 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 13:36:23 +0800 Subject: [PATCH 031/118] Remove unnecessary MBEDTLS_CONFIG_FILE check from AES/DES/SHA alternative 1. aes.h/des.h/sha1.h/sha256.h/sha512.h includes config.h before aes_alt.h/des_alt.h/sha1_alt.h/sha256_alt.h/sha512_alt.h. 2. aes_alt.h/des_alt.h/sha1_alt.h/sha256_alt.h/sha512_alt.h should not be included in any other location. 3. Just include aes.h/des.h/sha1.h/sha256.h/sha512.h in aes_alt.c/des_alt.c/sha1_alt.c/sha256_alt.c/sha512_alt.c. --- .../TARGET_NUC472/aes/aes_alt.c | 9 +-------- .../TARGET_NUC472/aes/aes_alt.h | 6 +----- .../TARGET_NUC472/des/des_alt.c | 8 +------- .../TARGET_NUC472/des/des_alt.h | 7 +------ .../TARGET_NUC472/des/des_alt_sw.c | 8 +------- .../TARGET_NUC472/des/des_alt_sw.h | 6 +----- .../TARGET_NUC472/sha/sha1_alt.c | 7 +------ .../TARGET_NUC472/sha/sha1_alt.h | 6 +----- .../TARGET_NUC472/sha/sha1_alt_sw.c | 8 +------- .../TARGET_NUC472/sha/sha1_alt_sw.h | 6 +----- .../TARGET_NUC472/sha/sha256_alt.c | 7 +------ .../TARGET_NUC472/sha/sha256_alt.h | 6 +----- .../TARGET_NUC472/sha/sha256_alt_sw.c | 8 +------- .../TARGET_NUC472/sha/sha256_alt_sw.h | 6 +----- .../TARGET_NUC472/sha/sha_alt_hw.c | 20 +++---------------- .../TARGET_NUC472/sha/sha_alt_hw.h | 8 +------- 16 files changed, 18 insertions(+), 108 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 0cbcc875ec..6eee0297b0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -21,19 +21,12 @@ * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/aes.h" #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) #include - -#include "mbedtls/aes.h" - #include "NUC472_442.h" #include "mbed_toolchain.h" #include "mbed_assert.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index a657fce6fa..31567043df 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -24,11 +24,7 @@ #ifndef MBEDTLS_AES_ALT_H #define MBEDTLS_AES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/aes.h" #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index e4e9fd4023..d4389607c1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -14,18 +14,12 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include -#include "mbedtls/des.h" -#include "des_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "mbed_toolchain.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h index b783889d53..3e00c3be6d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h @@ -17,18 +17,13 @@ #ifndef MBEDTLS_DES_ALT_H #define MBEDTLS_DES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include #include -#include "des.h" #include "des_alt_sw.h" #ifdef __cplusplus diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c index 1e51151c86..301a5476c1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c @@ -25,17 +25,11 @@ * http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) -#include "mbedtls/des.h" - #include /* Implementation that should never be optimized out by the compiler */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h index d42aa2ba05..a255170af0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h @@ -23,11 +23,7 @@ #ifndef MBEDTLS_DES_ALT_SW_H #define MBEDTLS_DES_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index de6ff01415..1e7a6a1276 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -14,16 +14,11 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h index 6cf738a1bb..9d6db507f4 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h @@ -16,11 +16,7 @@ #ifndef MBEDTLS_SHA1_ALT_H #define MBEDTLS_SHA1_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c index 230c872465..f511214993 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c @@ -24,17 +24,11 @@ * http://www.itl.nist.gov/fipspubs/fip180-1.htm */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) -#include "mbedtls/sha1.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h index 9d138abb8a..4dbb609fe8 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h @@ -23,11 +23,7 @@ #ifndef MBEDTLS_SHA1_ALT_SW_H #define MBEDTLS_SHA1_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index e5fd727e2a..acdcbb95a4 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -14,16 +14,11 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h index 23a156ddd7..2e336f760b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h @@ -16,11 +16,7 @@ #ifndef MBEDTLS_SHA256_ALT_H #define MBEDTLS_SHA256_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c index 3ac2b61317..5116e69258 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c @@ -24,17 +24,11 @@ * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "mbedtls/sha256.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h index c1b72ea8f7..d43d2e402a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h @@ -23,11 +23,7 @@ #ifndef MBEDTLS_SHA256_ALT_SW_H #define MBEDTLS_SHA256_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index b34bcd7f87..d1304b5b54 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -14,28 +14,14 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) -#if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" -#endif /* MBEDTLS_SHA1_ALT */ - -#if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" -#endif /* MBEDTLS_SHA256_ALT */ - -#if defined(MBEDTLS_SHA512_ALT) -#include "sha512_alt.h" -#endif /* MBEDTLS_SHA512_ALT */ - #include "nu_bitutil.h" #include "mbed_assert.h" #include "crypto-misc.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h index 6ee7da14df..ae539b01de 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h @@ -16,12 +16,6 @@ #ifndef MBEDTLS_SHA_ALT_HW_H #define MBEDTLS_SHA_ALT_HW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - #if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) @@ -89,4 +83,4 @@ void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char dat #endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */ #endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */ -#endif /* sha_alt.h */ +#endif /* sha_alt_hw.h */ From 02ab1a05b0453c5fa94d9341fcb72834e766701f Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 13:40:07 +0800 Subject: [PATCH 032/118] Fix DES alternative function not thread-safe --- .../targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index d4389607c1..12f8720987 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -24,11 +24,6 @@ #include "nu_bitutil.h" #include "mbed_toolchain.h" -// Must be a multiple of 64-bit block size -#define MAXSIZE_DMABUF (8 * 5) -static uint8_t dmabuf_in[MAXSIZE_DMABUF] MBED_ALIGN(4); -static uint8_t dmabuf_out[MAXSIZE_DMABUF] MBED_ALIGN(4); - static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output); @@ -341,6 +336,11 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S const unsigned char *in_pos = input; unsigned char *out_pos = output; + // Must be a multiple of 64-bit block size + #define MAXSIZE_DMABUF (8 * 5) + MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; + MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; + while (rmn) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; From 646136c59f24aec254871e4e65cdf287f9dcb5f0 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 14:14:59 +0800 Subject: [PATCH 033/118] Refine coding style --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 446 +++++++++--------- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 59 ++- .../TARGET_NUVOTON/TARGET_M480/crypto-misc.c | 7 +- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 152 +++--- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.h | 44 +- .../TARGET_M480/des/des_alt_sw.c | 211 ++++----- .../TARGET_M480/des/des_alt_sw.h | 44 +- .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c | 21 +- .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h | 3 +- .../TARGET_M480/sha/sha1_alt_sw.c | 21 +- .../TARGET_M480/sha/sha1_alt_sw.h | 5 +- .../TARGET_M480/sha/sha256_alt.c | 25 +- .../TARGET_M480/sha/sha256_alt.h | 5 +- .../TARGET_M480/sha/sha256_alt_sw.c | 53 +-- .../TARGET_M480/sha/sha256_alt_sw.h | 7 +- .../TARGET_M480/sha/sha512_alt.c | 25 +- .../TARGET_M480/sha/sha512_alt.h | 5 +- .../TARGET_M480/sha/sha512_alt_sw.c | 76 ++- .../TARGET_M480/sha/sha512_alt_sw.h | 7 +- .../TARGET_M480/sha/sha_alt_hw.c | 164 ++++--- .../TARGET_M480/sha/sha_alt_hw.h | 15 +- 21 files changed, 651 insertions(+), 744 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 035a69b059..c42ea5990c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -35,8 +35,10 @@ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } @@ -46,29 +48,28 @@ static uint32_t au32MyAESIV[4] = { extern volatile int g_AES_done; -// Must be a multiple of 16 bytes block size +// Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; static void swapInitVector(unsigned char iv[16]) { - unsigned int* piv; - int i; - // iv SWAP - piv = (unsigned int*)iv; - for( i=0; i< 4; i++) - { - *piv = (((*piv) & 0x000000FF) << 24) | - (((*piv) & 0x0000FF00) << 8) | - (((*piv) & 0x00FF0000) >> 8) | - (((*piv) & 0xFF000000) >> 24); - piv++; - } -} + unsigned int* piv; + int i; + // iv SWAP + piv = (unsigned int*)iv; + for( i=0; i< 4; i++) { + *piv = (((*piv) & 0x000000FF) << 24) | + (((*piv) & 0x0000FF00) << 8) | + (((*piv) & 0x00FF0000) >> 8) | + (((*piv) & 0xFF000000) >> 24); + piv++; + } +} -/* IRQHandler: To share CRYPTO_IRQHandler() with TRNG & other crypto IPs - For ex: +/* IRQHandler: To share CRYPTO_IRQHandler() with TRNG & other crypto IPs + For ex: volatile void CRYPTO_IRQHandler() { ... @@ -77,47 +78,44 @@ static void swapInitVector(unsigned char iv[16]) AES_CLR_INT_FLAG(); } ... - } + } */ /* AES available channel 0~3 */ -static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00}; // 0: idle, 1: busy +static unsigned char channel_flag[4]= {0x00,0x00,0x00,0x00}; // 0: idle, 1: busy static int channel_alloc() { - int i; - for(i=0; i< (int)sizeof(channel_flag); i++) - { - if( channel_flag[i] == 0x00 ) - { - channel_flag[i] = 0x01; - return i; - } - } - return(-1); + int i; + for(i=0; i< (int)sizeof(channel_flag); i++) { + if( channel_flag[i] == 0x00 ) { + channel_flag[i] = 0x01; + return i; + } + } + return(-1); } static void channel_free(int i) { - if( i >=0 && i < (int)sizeof(channel_flag) ) + if( i >=0 && i < (int)sizeof(channel_flag) ) channel_flag[i] = 0x00; } void mbedtls_aes_init( mbedtls_aes_context *ctx ) { - int i =-1; + int i =-1; memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - + ctx->swapType = AES_IN_OUT_SWAP; - while( (i = channel_alloc()) < 0 ) - { + while( (i = channel_alloc()) < 0 ) { mbed_assert_internal("No available AES channel", __FILE__, __LINE__); } ctx->channel = i; ctx->iv = au32MyAESIV; - + /* Unlock protected registers */ SYS_UnlockReg(); CLK_EnableModuleClock(CRPT_MODULE); @@ -125,16 +123,16 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) SYS_LockReg(); NVIC_EnableIRQ(CRPT_IRQn); - AES_ENABLE_INT(); + AES_ENABLE_INT(); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) { - + if( ctx == NULL ) return; - + channel_free(ctx->channel); mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); } @@ -143,35 +141,34 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ) * AES key schedule (encryption) */ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { unsigned int i; - - switch( keybits ) - { - case 128: - ctx->keySize = AES_KEY_SIZE_128; - break; - case 192: - ctx->keySize = AES_KEY_SIZE_192; - break; - case 256: - ctx->keySize = AES_KEY_SIZE_256; - break; - default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + + switch( keybits ) { + case 128: + ctx->keySize = AES_KEY_SIZE_128; + break; + case 192: + ctx->keySize = AES_KEY_SIZE_192; + break; + case 256: + ctx->keySize = AES_KEY_SIZE_256; + break; + default : + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); } - // key swap - for( i = 0; i < ( keybits >> 5 ); i++ ) - { - ctx->buf[i] = (*(key+i*4) << 24) | - (*(key+1+i*4) << 16) | - (*(key+2+i*4) << 8) | - (*(key+3+i*4) ); - } + // key swap + for( i = 0; i < ( keybits >> 5 ); i++ ) { + ctx->buf[i] = (*(key+i*4) << 24) | + (*(key+1+i*4) << 16) | + (*(key+2+i*4) << 8) | + (*(key+3+i*4) ); + } AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); @@ -182,14 +179,14 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, * AES key schedule (decryption) */ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { int ret; - - + + /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) - goto exit; + goto exit; exit: @@ -198,30 +195,28 @@ exit: static void __nvt_aes_crypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16], int dataSize) + const unsigned char input[16], + unsigned char output[16], int dataSize) { - unsigned char* pIn; - unsigned char* pOut; + unsigned char* pIn; + unsigned char* pOut; + - AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); - if( ((uint32_t)input) & 0x03 ) - { - memcpy(au8InputData, input, dataSize); - pIn = au8InputData; - }else{ - pIn = (unsigned char*)input; + if( ((uint32_t)input) & 0x03 ) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } else { + pIn = (unsigned char*)input; + } + if( (((uint32_t)output) & 0x03) || (dataSize%4)) { // HW CFB output byte count must be multiple of word + pOut = au8OutputData; + } else { + pOut = output; } - if( (((uint32_t)output) & 0x03) || (dataSize%4)) // HW CFB output byte count must be multiple of word - { - pOut = au8OutputData; - } else { - pOut = output; - } - AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); + AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); g_AES_done = 0; AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT); @@ -237,9 +232,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) -{ - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, 16); +{ + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, 16); } /* @@ -249,24 +244,24 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, 16); + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, 16); } /* * AES-ECB block encryption/decryption */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ) + int mode, + const unsigned char input[16], + unsigned char output[16] ) { - ctx->opMode = AES_MODE_ECB; + ctx->opMode = AES_MODE_ECB; if( mode == MBEDTLS_AES_ENCRYPT ) mbedtls_aes_encrypt( ctx, input, output ); else mbedtls_aes_decrypt( ctx, input, output ); - + return( 0 ); } @@ -276,50 +271,47 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * AES-CBC buffer encryption/decryption */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t len, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t len, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { unsigned char temp[16]; int length = len; - int blockChainLen; + int blockChainLen; if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); + if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { + blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); } else { - blockChainLen = length; - } - - while( length > 0 ) - { - ctx->opMode = AES_MODE_CBC; - swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; + blockChainLen = length; + } + + while( length > 0 ) { + ctx->opMode = AES_MODE_CBC; + swapInitVector(iv); // iv SWAP + ctx->iv = (uint32_t *)iv; + + if( mode == MBEDTLS_AES_ENCRYPT ) { + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, blockChainLen); +// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() + memcpy( iv, output+blockChainLen-16, 16 ); + } else { + memcpy( temp, input+blockChainLen-16, 16 ); + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, blockChainLen); +// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() + memcpy( iv, temp, 16 ); + } + length -= blockChainLen; + input += blockChainLen; + output += blockChainLen; + if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - if( mode == MBEDTLS_AES_ENCRYPT ) - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, output+blockChainLen-16, 16 ); - }else{ - memcpy( temp, input+blockChainLen-16, 16 ); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, temp, 16 ); - } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } return( 0 ); @@ -332,50 +324,43 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, */ /* Support partial block encryption/decryption */ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { int c; size_t n = *iv_off; - unsigned char iv_tmp[16]; + unsigned char iv_tmp[16]; - if( mode == MBEDTLS_AES_DECRYPT ) - { - while( length-- ) - { + if( mode == MBEDTLS_AES_DECRYPT ) { + while( length-- ) { if( n == 0) mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - + else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode + memcpy(iv_tmp, iv, n); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); + memcpy(iv, iv_tmp, n); + } + c = *input++; *output++ = (unsigned char)( c ^ iv[n] ); iv[n] = (unsigned char) c; n = ( n + 1 ) & 0x0F; } - } - else - { - while( length-- ) - { + } else { + while( length-- ) { if( n == 0 ) mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - + else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode + memcpy(iv_tmp, iv, n); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); + memcpy(iv, iv_tmp, n); + } + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); n = ( n + 1 ) & 0x0F; @@ -388,75 +373,70 @@ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, } int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t len, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t len, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { - size_t n = *iv_off; + size_t n = *iv_off; unsigned char temp[16]; - int length=len; - int blockChainLen; - int remLen=0; - int ivLen; - - - // proceed: start with partial block by ECB mode first - if( n !=0 ) { - __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n , iv_off, iv, input, output); - input += (16 - n); - output += (16 - n); - length -= (16 - n); - } - - // For address or byte count non-word alignment, go through reserved DMA buffer. - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) // Must reserved DMA buffer for each block - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else if(length%4) { // Need reserved DMA buffer once for last chain - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); - } else { // Not need reserved DMA buffer - blockChainLen = length; - } - - // proceed: start with block alignment - while( length > 0 ) - { + int length=len; + int blockChainLen; + int remLen=0; + int ivLen; - ctx->opMode = AES_MODE_CFB; - swapInitVector(iv); // iv SWAP - - ctx->iv = (uint32_t *)iv; - remLen = blockChainLen%16; - ivLen = (( remLen > 0) ? remLen: 16 ); - - if( mode == MBEDTLS_AES_DECRYPT ) - { - memcpy(temp, input+blockChainLen - ivLen, ivLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16 , 16); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy(iv,temp, ivLen); - } - else - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16 , 16); - memcpy(iv,output+blockChainLen-ivLen,ivLen); - } - length -= blockChainLen; + // proceed: start with partial block by ECB mode first + if( n !=0 ) { + __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n, iv_off, iv, input, output); + input += (16 - n); + output += (16 - n); + length -= (16 - n); + } + + // For address or byte count non-word alignment, go through reserved DMA buffer. + if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { // Must reserved DMA buffer for each block + blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); + } else if(length%4) { // Need reserved DMA buffer once for last chain + blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); + } else { // Not need reserved DMA buffer + blockChainLen = length; + } + + // proceed: start with block alignment + while( length > 0 ) { + + ctx->opMode = AES_MODE_CFB; + + swapInitVector(iv); // iv SWAP + + ctx->iv = (uint32_t *)iv; + remLen = blockChainLen%16; + ivLen = (( remLen > 0) ? remLen: 16 ); + + if( mode == MBEDTLS_AES_DECRYPT ) { + memcpy(temp, input+blockChainLen - ivLen, ivLen); + if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16, 16); + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, blockChainLen); + memcpy(iv,temp, ivLen); + } else { + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, blockChainLen); + if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16, 16); + memcpy(iv,output+blockChainLen-ivLen,ivLen); + } + length -= blockChainLen; input += blockChainLen; output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } - + if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain + } + *iv_off = remLen; - return( 0 ); + return( 0 ); } @@ -464,17 +444,16 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, * AES-CFB8 buffer encryption/decryption */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { unsigned char c; unsigned char ov[17]; - while( length-- ) - { + while( length-- ) { memcpy( ov, iv, 16 ); mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); @@ -498,18 +477,17 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * AES-CTR buffer encryption/decryption */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ) + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) { int c, i; size_t n = *nc_off; - while( length-- ) - { + while( length-- ) { if( n == 0 ) { mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index c50048a624..788921bae7 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -39,8 +39,7 @@ extern "C" { * - to simplify key expansion in the 256-bit case by * generating an extra round key */ -typedef struct -{ +typedef struct { uint32_t keySize; uint32_t encDec; uint32_t opMode; @@ -48,7 +47,7 @@ typedef struct uint32_t swapType; uint32_t *iv; unsigned char prv_iv[16]; - uint32_t buf[8]; + uint32_t buf[8]; } mbedtls_aes_context; @@ -76,7 +75,7 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ); * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES key schedule (decryption) @@ -88,7 +87,7 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES-ECB block encryption/decryption @@ -101,9 +100,9 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ); + int mode, + const unsigned char input[16], + unsigned char output[16] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -129,11 +128,11 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) @@ -163,12 +162,12 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); /** * \brief AES-CFB8 buffer encryption/decryption. @@ -195,11 +194,11 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /*MBEDTLS_CIPHER_MODE_CFB */ #if defined(MBEDTLS_CIPHER_MODE_CTR) @@ -226,12 +225,12 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ); + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CTR */ /** diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c index 7f6646f40b..c5d49bb0dd 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c @@ -30,7 +30,7 @@ void crypto_init(void) return; } crypto_inited = 1; - + CLK_EnableModuleClock(CRPT_MODULE); } @@ -48,11 +48,10 @@ int crypto_sha_acquire(void) if (crypto_sha_avail) { crypto_sha_avail = 0; return 1; - } - else { + } else { return 0; } - + } void crypto_sha_release(void) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 12f8720987..cb7effa7bd 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -24,8 +24,8 @@ #include "nu_bitutil.h" #include "mbed_toolchain.h" -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output); +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output); void mbedtls_des_init(mbedtls_des_context *ctx) { @@ -58,15 +58,16 @@ void mbedtls_des3_free( mbedtls_des3_context *ctx ) } static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; + 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, + 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, + 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, + 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, + 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, + 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, + 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, + 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, + 254 + }; void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE]) { @@ -114,8 +115,7 @@ int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SI #define WEAK_KEY_COUNT 16 -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ +static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, @@ -157,7 +157,7 @@ int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MB memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE); - + return 0; } @@ -180,7 +180,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * Triple-DES key schedule (112-bit, encryption) */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 1; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -196,7 +196,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (112-bit, decryption) */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 0; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -212,7 +212,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, encryption) */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 1; // Keying option 1: All three keys are independent. @@ -228,7 +228,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, decryption) */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 0; // Keying option 1: All three keys are independent. @@ -244,8 +244,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * DES-ECB block encryption/decryption */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, DES_MODE_ECB, 8, iv, input, output); @@ -256,11 +256,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * DES-CBC buffer encryption/decryption */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, DES_MODE_CBC, length, iv, input, output); } @@ -270,8 +270,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * 3DES-ECB block encryption/decryption */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, TDES_MODE_ECB, 8, iv, input, output); @@ -282,11 +282,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * 3DES-CBC buffer encryption/decryption */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, TDES_MODE_CBC, length, iv, input, output); } @@ -294,24 +294,23 @@ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output) +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output) { if (length % 8) { return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } - + // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | - tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); + tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); // Keying option 1: All three keys are independent. // Keying option 2: K1 and K2 are independent, and K3 = K1. - // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. + // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. if (keyopt == 1) { CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk; - } - else { + } else { CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; } @@ -331,72 +330,71 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S *tdes_key ++ = val; val = nu_get32_be(key[2] + 4); *tdes_key ++ = val; - + uint32_t rmn = length; const unsigned char *in_pos = input; unsigned char *out_pos = output; - + // Must be a multiple of 64-bit block size - #define MAXSIZE_DMABUF (8 * 5) +#define MAXSIZE_DMABUF (8 * 5) MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; while (rmn) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; - + uint32_t ivh, ivl; ivh = nu_get32_be(iv); ivl = nu_get32_be(iv + 4); TDES_SetInitVect(0, ivh, ivl); - + memcpy(dmabuf_in, in_pos, data_len); - + TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - + // Start enc/dec. // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting. CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); - + memcpy(out_pos, dmabuf_out, data_len); in_pos += data_len; out_pos += data_len; rmn -= data_len; - + // Update IV for next block enc/dec in next function call switch (tdes_opmode) { - case DES_MODE_OFB: - case TDES_MODE_OFB: { - // OFB: IV (enc/dec) = output block XOR input block - uint32_t lbh, lbl; - // Last block of input data - lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); - lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); - // Last block of output data - ivh = nu_get32_be(dmabuf_out + 4); - ivl = nu_get32_be(dmabuf_out + 0); - ivh = ivh ^ lbh; - ivl = ivl ^ lbl; - nu_set32_be(iv + 4, ivh); - nu_set32_be(iv, ivl); - break; - } - case DES_MODE_CBC: - case DES_MODE_CFB: - case TDES_MODE_CBC: - case TDES_MODE_CFB: { - // CBC/CFB: IV (enc) = output block - // IV (dec) = input block - if (enc) { - memcpy(iv, dmabuf_out + data_len - 8, 8); - } - else { - memcpy(iv, dmabuf_in + data_len - 8, 8); - } + case DES_MODE_OFB: + case TDES_MODE_OFB: { + // OFB: IV (enc/dec) = output block XOR input block + uint32_t lbh, lbl; + // Last block of input data + lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); + lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); + // Last block of output data + ivh = nu_get32_be(dmabuf_out + 4); + ivl = nu_get32_be(dmabuf_out + 0); + ivh = ivh ^ lbh; + ivl = ivl ^ lbl; + nu_set32_be(iv + 4, ivh); + nu_set32_be(iv, ivl); + break; + } + case DES_MODE_CBC: + case DES_MODE_CFB: + case TDES_MODE_CBC: + case TDES_MODE_CFB: { + // CBC/CFB: IV (enc) = output block + // IV (dec) = input block + if (enc) { + memcpy(iv, dmabuf_out + data_len - 8, 8); + } else { + memcpy(iv, dmabuf_in + data_len - 8, 8); } } + } } - + return 0; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h index 58ead66cb9..3165ba81d0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h @@ -13,7 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #ifndef MBEDTLS_DES_ALT_H #define MBEDTLS_DES_ALT_H @@ -32,8 +32,7 @@ extern "C" { /** * \brief DES context structure */ -typedef struct -{ +typedef struct { int enc; /*!< 0: dec, 1: enc */ uint16_t keyopt; uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ @@ -43,8 +42,7 @@ mbedtls_des_context; /** * \brief Triple-DES context structure */ -typedef struct -{ +typedef struct { int enc; /*!< 0: dec, 1: enc */ uint16_t keyopt; uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ @@ -139,7 +137,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * \return 0 */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (112-bit, decryption) @@ -150,7 +148,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (168-bit, encryption) @@ -161,7 +159,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief Triple-DES key schedule (168-bit, decryption) @@ -172,7 +170,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief DES-ECB block encryption/decryption @@ -184,8 +182,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * \return 0 if successful */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -207,11 +205,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * \param output buffer holding the output data */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -224,8 +222,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * \return 0 if successful */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -249,11 +247,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c index 301a5476c1..d3968b464b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c @@ -33,8 +33,10 @@ #include /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } /* @@ -63,8 +65,7 @@ static void mbedtls_zeroize( void *v, size_t n ) { /* * Expanded DES S-boxes */ -static const uint32_t SB1[64] = -{ +static const uint32_t SB1[64] = { 0x01010400, 0x00000000, 0x00010000, 0x01010404, 0x01010004, 0x00010404, 0x00000004, 0x00010000, 0x00000400, 0x01010400, 0x01010404, 0x00000400, @@ -83,8 +84,7 @@ static const uint32_t SB1[64] = 0x00010004, 0x00010400, 0x00000000, 0x01010004 }; -static const uint32_t SB2[64] = -{ +static const uint32_t SB2[64] = { 0x80108020, 0x80008000, 0x00008000, 0x00108020, 0x00100000, 0x00000020, 0x80100020, 0x80008020, 0x80000020, 0x80108020, 0x80108000, 0x80000000, @@ -103,8 +103,7 @@ static const uint32_t SB2[64] = 0x80000000, 0x80100020, 0x80108020, 0x00108000 }; -static const uint32_t SB3[64] = -{ +static const uint32_t SB3[64] = { 0x00000208, 0x08020200, 0x00000000, 0x08020008, 0x08000200, 0x00000000, 0x00020208, 0x08000200, 0x00020008, 0x08000008, 0x08000008, 0x00020000, @@ -123,8 +122,7 @@ static const uint32_t SB3[64] = 0x00020208, 0x00000008, 0x08020008, 0x00020200 }; -static const uint32_t SB4[64] = -{ +static const uint32_t SB4[64] = { 0x00802001, 0x00002081, 0x00002081, 0x00000080, 0x00802080, 0x00800081, 0x00800001, 0x00002001, 0x00000000, 0x00802000, 0x00802000, 0x00802081, @@ -143,8 +141,7 @@ static const uint32_t SB4[64] = 0x00000080, 0x00800000, 0x00002000, 0x00802080 }; -static const uint32_t SB5[64] = -{ +static const uint32_t SB5[64] = { 0x00000100, 0x02080100, 0x02080000, 0x42000100, 0x00080000, 0x00000100, 0x40000000, 0x02080000, 0x40080100, 0x00080000, 0x02000100, 0x40080100, @@ -163,8 +160,7 @@ static const uint32_t SB5[64] = 0x00000000, 0x40080000, 0x02080100, 0x40000100 }; -static const uint32_t SB6[64] = -{ +static const uint32_t SB6[64] = { 0x20000010, 0x20400000, 0x00004000, 0x20404010, 0x20400000, 0x00000010, 0x20404010, 0x00400000, 0x20004000, 0x00404010, 0x00400000, 0x20000010, @@ -183,8 +179,7 @@ static const uint32_t SB6[64] = 0x20404000, 0x20000000, 0x00400010, 0x20004010 }; -static const uint32_t SB7[64] = -{ +static const uint32_t SB7[64] = { 0x00200000, 0x04200002, 0x04000802, 0x00000000, 0x00000800, 0x04000802, 0x00200802, 0x04200800, 0x04200802, 0x00200000, 0x00000000, 0x04000002, @@ -203,8 +198,7 @@ static const uint32_t SB7[64] = 0x04000002, 0x04000800, 0x00000800, 0x00200002 }; -static const uint32_t SB8[64] = -{ +static const uint32_t SB8[64] = { 0x10001040, 0x00001000, 0x00040000, 0x10041040, 0x10000000, 0x10001040, 0x00000040, 0x10000000, 0x00040040, 0x10040000, 0x10041040, 0x00041000, @@ -226,16 +220,14 @@ static const uint32_t SB8[64] = /* * PC1: left and right halves bit-swap */ -static const uint32_t LHs[16] = -{ +static const uint32_t LHs[16] = { 0x00000000, 0x00000001, 0x00000100, 0x00000101, 0x00010000, 0x00010001, 0x00010100, 0x00010101, 0x01000000, 0x01000001, 0x01000100, 0x01000101, 0x01010000, 0x01010001, 0x01010100, 0x01010101 }; -static const uint32_t RHs[16] = -{ +static const uint32_t RHs[16] = { 0x00000000, 0x01000000, 0x00010000, 0x01010000, 0x00000100, 0x01000100, 0x00010100, 0x01010100, 0x00000001, 0x01000001, 0x00010001, 0x01010001, @@ -317,15 +309,16 @@ void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ) } static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; + 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, + 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, + 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, + 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, + 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, + 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, + 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, + 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, + 254 + }; void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ) { @@ -372,8 +365,7 @@ int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY #define WEAK_KEY_COUNT 16 -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ +static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, @@ -415,18 +407,22 @@ void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KE /* * Permuted Choice 1 */ - T = ((Y >> 4) ^ X) & 0x0F0F0F0F; X ^= T; Y ^= (T << 4); - T = ((Y ) ^ X) & 0x10101010; X ^= T; Y ^= (T ); + T = ((Y >> 4) ^ X) & 0x0F0F0F0F; + X ^= T; + Y ^= (T << 4); + T = ((Y ) ^ X) & 0x10101010; + X ^= T; + Y ^= (T ); X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2) - | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) - | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) - | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); + | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) + | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) + | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2) - | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) - | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) - | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); + | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) + | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) + | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); X &= 0x0FFFFFFF; Y &= 0x0FFFFFFF; @@ -434,42 +430,38 @@ void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KE /* * calculate subkeys */ - for( i = 0; i < 16; i++ ) - { - if( i < 2 || i == 8 || i == 15 ) - { + for( i = 0; i < 16; i++ ) { + if( i < 2 || i == 8 || i == 15 ) { X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF; Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF; - } - else - { + } else { X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF; Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF; } *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000) - | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) - | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) - | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) - | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) - | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) - | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) - | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) - | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) - | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) - | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); + | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) + | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) + | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) + | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) + | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) + | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) + | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) + | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) + | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) + | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000) - | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) - | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) - | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) - | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) - | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) - | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) - | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) - | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) - | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) - | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); + | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) + | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) + | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) + | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) + | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) + | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) + | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) + | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) + | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) + | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); } } @@ -492,8 +484,7 @@ int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char mbedtls_des_setkey( ctx->sk, key ); - for( i = 0; i < 16; i += 2 ) - { + for( i = 0; i < 16; i += 2 ) { SWAP( ctx->sk[i ], ctx->sk[30 - i] ); SWAP( ctx->sk[i + 1], ctx->sk[31 - i] ); } @@ -510,8 +501,7 @@ static void des3_set2key( uint32_t esk[96], mbedtls_des_setkey( esk, key ); mbedtls_des_setkey( dsk + 32, key + 8 ); - for( i = 0; i < 32; i += 2 ) - { + for( i = 0; i < 32; i += 2 ) { dsk[i ] = esk[30 - i]; dsk[i + 1] = esk[31 - i]; @@ -530,7 +520,7 @@ static void des3_set2key( uint32_t esk[96], * Triple-DES key schedule (112-bit, encryption) */ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { uint32_t sk[96]; @@ -544,7 +534,7 @@ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, * Triple-DES key schedule (112-bit, decryption) */ int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { uint32_t sk[96]; @@ -564,8 +554,7 @@ static void des3_set3key( uint32_t esk[96], mbedtls_des_setkey( dsk + 32, key + 8 ); mbedtls_des_setkey( esk + 64, key + 16 ); - for( i = 0; i < 32; i += 2 ) - { + for( i = 0; i < 32; i += 2 ) { dsk[i ] = esk[94 - i]; dsk[i + 1] = esk[95 - i]; @@ -581,7 +570,7 @@ static void des3_set3key( uint32_t esk[96], * Triple-DES key schedule (168-bit, encryption) */ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { uint32_t sk[96]; @@ -595,7 +584,7 @@ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, * Triple-DES key schedule (168-bit, decryption) */ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { uint32_t sk[96]; @@ -609,8 +598,8 @@ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, * DES-ECB block encryption/decryption */ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { int i; uint32_t X, Y, T, *SK; @@ -622,8 +611,7 @@ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, DES_IP( X, Y ); - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( Y, X ); DES_ROUND( X, Y ); } @@ -641,11 +629,11 @@ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, * DES-CBC buffer encryption/decryption */ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { int i; unsigned char temp[8]; @@ -653,10 +641,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, if( length % 8 ) return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { + if( mode == MBEDTLS_DES_ENCRYPT ) { + while( length > 0 ) { for( i = 0; i < 8; i++ ) output[i] = (unsigned char)( input[i] ^ iv[i] ); @@ -667,11 +653,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, output += 8; length -= 8; } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { + } else { /* MBEDTLS_DES_DECRYPT */ + while( length > 0 ) { memcpy( temp, input, 8 ); mbedtls_des_sw_crypt_ecb( ctx, input, output ); @@ -694,8 +677,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, * 3DES-ECB block encryption/decryption */ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { int i; uint32_t X, Y, T, *SK; @@ -707,20 +690,17 @@ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, DES_IP( X, Y ); - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( Y, X ); DES_ROUND( X, Y ); } - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( X, Y ); DES_ROUND( Y, X ); } - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( Y, X ); DES_ROUND( X, Y ); } @@ -738,11 +718,11 @@ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, * 3DES-CBC buffer encryption/decryption */ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { int i; unsigned char temp[8]; @@ -750,10 +730,8 @@ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, if( length % 8 ) return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { + if( mode == MBEDTLS_DES_ENCRYPT ) { + while( length > 0 ) { for( i = 0; i < 8; i++ ) output[i] = (unsigned char)( input[i] ^ iv[i] ); @@ -764,11 +742,8 @@ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, output += 8; length -= 8; } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { + } else { /* MBEDTLS_DES_DECRYPT */ + while( length > 0 ) { memcpy( temp, input, 8 ); mbedtls_des3_sw_crypt_ecb( ctx, input, output ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h index 9910ce59a7..36ef2f28d9 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h @@ -36,8 +36,7 @@ extern "C" { /** * \brief DES context structure */ -typedef struct -{ +typedef struct { uint32_t sk[32]; /*!< DES subkeys */ } mbedtls_des_sw_context; @@ -45,8 +44,7 @@ mbedtls_des_sw_context; /** * \brief Triple-DES context structure */ -typedef struct -{ +typedef struct { uint32_t sk[96]; /*!< 3DES subkeys */ } mbedtls_des3_sw_context; @@ -139,7 +137,7 @@ int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char * \return 0 */ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (112-bit, decryption) @@ -150,7 +148,7 @@ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, * \return 0 */ int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (168-bit, encryption) @@ -161,7 +159,7 @@ int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, * \return 0 */ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief Triple-DES key schedule (168-bit, decryption) @@ -172,7 +170,7 @@ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, * \return 0 */ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief DES-ECB block encryption/decryption @@ -184,8 +182,8 @@ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, * \return 0 if successful */ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -207,11 +205,11 @@ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, * \param output buffer holding the output data */ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -224,8 +222,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, * \return 0 if successful */ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -249,11 +247,11 @@ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH */ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -265,7 +263,7 @@ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, * \param key Base key */ void mbedtls_des_sw_setkey( uint32_t SK[32], - const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); #ifdef __cplusplus } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index 1e7a6a1276..5ef56e9040 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -28,8 +28,7 @@ void mbedtls_sha1_init(mbedtls_sha1_context *ctx) if (crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha1_hw_init(&ctx->hw_ctx); - } - else { + } else { ctx->ishw = 0; mbedtls_sha1_sw_init(&ctx->sw_ctx); } @@ -44,8 +43,7 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) if (ctx->ishw) { mbedtls_sha1_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else { mbedtls_sha1_sw_free(&ctx->sw_ctx); } } @@ -73,8 +71,7 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -87,8 +84,7 @@ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) { if (ctx->ishw) { mbedtls_sha1_hw_starts(&ctx->hw_ctx); - } - else { + } else { mbedtls_sha1_sw_starts(&ctx->sw_ctx); } } @@ -100,8 +96,7 @@ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, { if (ctx->ishw) { mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else { mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -113,8 +108,7 @@ void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20]) { if (ctx->ishw) { mbedtls_sha1_hw_finish(&ctx->hw_ctx, output); - } - else { + } else { mbedtls_sha1_sw_finish(&ctx->sw_ctx, output); } } @@ -123,8 +117,7 @@ void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64 { if (ctx->ishw) { mbedtls_sha1_hw_process(&ctx->hw_ctx, data); - } - else { + } else { mbedtls_sha1_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h index 94972b54f6..9c0a92f368 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h @@ -31,8 +31,7 @@ struct mbedtls_sha1_context_s; /** * \brief SHA-1 context structure */ -typedef struct mbedtls_sha1_context_s -{ +typedef struct mbedtls_sha1_context_s { int ishw; crypto_sha_context hw_ctx; mbedtls_sha1_sw_context sw_ctx; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c index a8a3679c95..759823b2cc 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c @@ -39,8 +39,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } /* @@ -80,7 +82,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ) } void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ) + const mbedtls_sha1_sw_context *src ) { *dst = *src; } @@ -276,8 +278,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha1_sw_process( ctx, ctx->buffer ); input += fill; @@ -285,8 +286,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha1_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -296,9 +296,8 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha1_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha1_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -314,7 +313,7 @@ void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[ unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h index 9f7c210b5d..416779ed3c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h @@ -36,8 +36,7 @@ extern "C" { /** * \brief SHA-1 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[5]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -65,7 +64,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ); + const mbedtls_sha1_sw_context *src ); /** * \brief SHA-1 context setup diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index 20f2c79ac6..4c95a206cc 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -28,8 +28,7 @@ void mbedtls_sha256_init(mbedtls_sha256_context *ctx) if (crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha256_hw_init(&ctx->hw_ctx); - } - else { + } else { ctx->ishw = 0; mbedtls_sha256_sw_init(&ctx->sw_ctx); } @@ -44,14 +43,13 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) if (ctx->ishw) { mbedtls_sha256_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else { mbedtls_sha256_sw_free(&ctx->sw_ctx); } } void mbedtls_sha256_clone(mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src) + const mbedtls_sha256_context *src) { if (src->ishw) { // Clone S/W ctx from H/W ctx @@ -74,8 +72,7 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -85,11 +82,10 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, * SHA-256 context setup */ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) -{ +{ if (ctx->ishw) { mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224); - } - else { + } else { mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224); } } @@ -101,8 +97,7 @@ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *inp { if (ctx->ishw) { mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else { mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -114,8 +109,7 @@ void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32] { if (ctx->ishw) { mbedtls_sha256_hw_finish(&ctx->hw_ctx, output); - } - else { + } else { mbedtls_sha256_sw_finish(&ctx->sw_ctx, output); } } @@ -124,8 +118,7 @@ void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char dat { if (ctx->ishw) { mbedtls_sha256_hw_process(&ctx->hw_ctx, data); - } - else { + } else { mbedtls_sha256_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h index 494c501caf..c23c7eae5e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h @@ -31,8 +31,7 @@ struct mbedtls_sha256_context_s; /** * \brief SHA-256 context structure */ -typedef struct mbedtls_sha256_context_s -{ +typedef struct mbedtls_sha256_context_s { int ishw; crypto_sha_context hw_ctx; mbedtls_sha256_sw_context sw_ctx; @@ -78,7 +77,7 @@ void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c index 7c7ec543ba..771c998eef 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c @@ -43,8 +43,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; + while( n-- ) *p++ = 0; } /* @@ -84,7 +86,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ) } void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ) + const mbedtls_sha256_sw_context *src ) { *dst = *src; } @@ -97,8 +99,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->total[0] = 0; ctx->total[1] = 0; - if( is224 == 0 ) - { + if( is224 == 0 ) { /* SHA-256 */ ctx->state[0] = 0x6A09E667; ctx->state[1] = 0xBB67AE85; @@ -108,9 +109,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->state[5] = 0x9B05688C; ctx->state[6] = 0x1F83D9AB; ctx->state[7] = 0x5BE0CD19; - } - else - { + } else { /* SHA-224 */ ctx->state[0] = 0xC1059ED8; ctx->state[1] = 0x367CD507; @@ -125,8 +124,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->is224 = is224; } -static const uint32_t K[] = -{ +static const uint32_t K[] = { 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5, 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5, 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3, @@ -180,8 +178,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c A[i] = ctx->state[i]; #if defined(MBEDTLS_SHA256_SMALLER) - for( i = 0; i < 64; i++ ) - { + for( i = 0; i < 64; i++ ) { if( i < 16 ) GET_UINT32_BE( W[i], data, 4 * i ); else @@ -189,15 +186,21 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] ); - temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3]; - A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1; + temp1 = A[7]; + A[7] = A[6]; + A[6] = A[5]; + A[5] = A[4]; + A[4] = A[3]; + A[3] = A[2]; + A[2] = A[1]; + A[1] = A[0]; + A[0] = temp1; } #else /* MBEDTLS_SHA256_SMALLER */ for( i = 0; i < 16; i++ ) GET_UINT32_BE( W[i], data, 4 * i ); - for( i = 0; i < 16; i += 8 ) - { + for( i = 0; i < 16; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] ); @@ -208,8 +211,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] ); } - for( i = 16; i < 64; i += 8 ) - { + for( i = 16; i < 64; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] ); @@ -229,7 +231,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c * SHA-256 process buffer */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ) + size_t ilen ) { size_t fill; uint32_t left; @@ -246,8 +248,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha256_sw_process( ctx, ctx->buffer ); input += fill; @@ -255,8 +256,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha256_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -266,9 +266,8 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha256_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha256_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -284,7 +283,7 @@ void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char out unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h index 0a33d3fe98..c10b08144e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h @@ -36,8 +36,7 @@ extern "C" { /** * \brief SHA-256 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[8]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -66,7 +65,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ); + const mbedtls_sha256_sw_context *src ); /** * \brief SHA-256 context setup @@ -84,7 +83,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index 9761a1c674..a36fc2b680 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -28,8 +28,7 @@ void mbedtls_sha512_init(mbedtls_sha512_context *ctx) if (crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha512_hw_init(&ctx->hw_ctx); - } - else { + } else { ctx->ishw = 0; mbedtls_sha512_sw_init(&ctx->sw_ctx); } @@ -44,14 +43,13 @@ void mbedtls_sha512_free(mbedtls_sha512_context *ctx) if (ctx->ishw) { mbedtls_sha512_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else { mbedtls_sha512_sw_free(&ctx->sw_ctx); } } void mbedtls_sha512_clone(mbedtls_sha512_context *dst, - const mbedtls_sha512_context *src) + const mbedtls_sha512_context *src) { if (src->ishw) { // Clone S/W ctx from H/W ctx @@ -75,8 +73,7 @@ void mbedtls_sha512_clone(mbedtls_sha512_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha512_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -86,11 +83,10 @@ void mbedtls_sha512_clone(mbedtls_sha512_context *dst, * SHA-512 context setup */ void mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384) -{ +{ if (ctx->ishw) { mbedtls_sha512_hw_starts(&ctx->hw_ctx, is384); - } - else { + } else { mbedtls_sha512_sw_starts(&ctx->sw_ctx, is384); } } @@ -102,8 +98,7 @@ void mbedtls_sha512_update(mbedtls_sha512_context *ctx, const unsigned char *inp { if (ctx->ishw) { mbedtls_sha512_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else { mbedtls_sha512_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -115,8 +110,7 @@ void mbedtls_sha512_finish(mbedtls_sha512_context *ctx, unsigned char output[64] { if (ctx->ishw) { mbedtls_sha512_hw_finish(&ctx->hw_ctx, output); - } - else { + } else { mbedtls_sha512_sw_finish(&ctx->sw_ctx, output); } } @@ -125,8 +119,7 @@ void mbedtls_sha512_process(mbedtls_sha512_context *ctx, const unsigned char dat { if (ctx->ishw) { mbedtls_sha512_hw_process(&ctx->hw_ctx, data); - } - else { + } else { mbedtls_sha512_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h index 15681f0826..1d85833d46 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h @@ -31,8 +31,7 @@ struct mbedtls_sha512_context_s; /** * \brief SHA-512 context structure */ -typedef struct mbedtls_sha512_context_s -{ +typedef struct mbedtls_sha512_context_s { int ishw; crypto_sha_context hw_ctx; mbedtls_sha512_sw_context sw_ctx; @@ -78,7 +77,7 @@ void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, int is384 ); * \param ilen length of the input data */ void mbedtls_sha512_update( mbedtls_sha512_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-512 final digest diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c index 5b204ccb5e..7dfce4ff85 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c @@ -30,9 +30,9 @@ #if defined(MBEDTLS_SHA512_ALT) #if defined(_MSC_VER) || defined(__WATCOMC__) - #define UL64(x) x##ui64 +#define UL64(x) x##ui64 #else - #define UL64(x) x##ULL +#define UL64(x) x##ULL #endif #include @@ -50,8 +50,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; + while( n-- ) *p++ = 0; } /* @@ -99,7 +101,7 @@ void mbedtls_sha512_sw_free( mbedtls_sha512_sw_context *ctx ) } void mbedtls_sha512_sw_clone( mbedtls_sha512_sw_context *dst, - const mbedtls_sha512_sw_context *src ) + const mbedtls_sha512_sw_context *src ) { *dst = *src; } @@ -112,8 +114,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ) ctx->total[0] = 0; ctx->total[1] = 0; - if( is384 == 0 ) - { + if( is384 == 0 ) { /* SHA-512 */ ctx->state[0] = UL64(0x6A09E667F3BCC908); ctx->state[1] = UL64(0xBB67AE8584CAA73B); @@ -123,9 +124,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ) ctx->state[5] = UL64(0x9B05688C2B3E6C1F); ctx->state[6] = UL64(0x1F83D9ABFB41BD6B); ctx->state[7] = UL64(0x5BE0CD19137E2179); - } - else - { + } else { /* SHA-384 */ ctx->state[0] = UL64(0xCBBB9D5DC1059ED8); ctx->state[1] = UL64(0x629A292A367CD507); @@ -145,8 +144,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ) /* * Round constants */ -static const uint64_t K[80] = -{ +static const uint64_t K[80] = { UL64(0x428A2F98D728AE22), UL64(0x7137449123EF65CD), UL64(0xB5C0FBCFEC4D3B2F), UL64(0xE9B5DBA58189DBBC), UL64(0x3956C25BF348B538), UL64(0x59F111F1B605D019), @@ -214,13 +212,11 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c d += temp1; h = temp1 + temp2; \ } - for( i = 0; i < 16; i++ ) - { + for( i = 0; i < 16; i++ ) { GET_UINT64_BE( W[i], data, i << 3 ); } - for( ; i < 80; i++ ) - { + for( ; i < 80; i++ ) { W[i] = S1(W[i - 2]) + W[i - 7] + S0(W[i - 15]) + W[i - 16]; } @@ -235,18 +231,24 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c H = ctx->state[7]; i = 0; - do - { - P( A, B, C, D, E, F, G, H, W[i], K[i] ); i++; - P( H, A, B, C, D, E, F, G, W[i], K[i] ); i++; - P( G, H, A, B, C, D, E, F, W[i], K[i] ); i++; - P( F, G, H, A, B, C, D, E, W[i], K[i] ); i++; - P( E, F, G, H, A, B, C, D, W[i], K[i] ); i++; - P( D, E, F, G, H, A, B, C, W[i], K[i] ); i++; - P( C, D, E, F, G, H, A, B, W[i], K[i] ); i++; - P( B, C, D, E, F, G, H, A, W[i], K[i] ); i++; - } - while( i < 80 ); + do { + P( A, B, C, D, E, F, G, H, W[i], K[i] ); + i++; + P( H, A, B, C, D, E, F, G, W[i], K[i] ); + i++; + P( G, H, A, B, C, D, E, F, W[i], K[i] ); + i++; + P( F, G, H, A, B, C, D, E, W[i], K[i] ); + i++; + P( E, F, G, H, A, B, C, D, W[i], K[i] ); + i++; + P( D, E, F, G, H, A, B, C, W[i], K[i] ); + i++; + P( C, D, E, F, G, H, A, B, W[i], K[i] ); + i++; + P( B, C, D, E, F, G, H, A, W[i], K[i] ); + i++; + } while( i < 80 ); ctx->state[0] += A; ctx->state[1] += B; @@ -263,7 +265,7 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c * SHA-512 process buffer */ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned char *input, - size_t ilen ) + size_t ilen ) { size_t fill; unsigned int left; @@ -279,8 +281,7 @@ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned ch if( ctx->total[0] < (uint64_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha512_sw_process( ctx, ctx->buffer ); input += fill; @@ -288,8 +289,7 @@ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned ch left = 0; } - while( ilen >= 128 ) - { + while( ilen >= 128 ) { mbedtls_sha512_sw_process( ctx, input ); input += 128; ilen -= 128; @@ -299,9 +299,8 @@ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned ch memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha512_padding[128] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha512_padding[128] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -321,7 +320,7 @@ void mbedtls_sha512_sw_finish( mbedtls_sha512_sw_context *ctx, unsigned char out unsigned char msglen[16]; high = ( ctx->total[0] >> 61 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT64_BE( high, msglen, 0 ); @@ -340,8 +339,7 @@ void mbedtls_sha512_sw_finish( mbedtls_sha512_sw_context *ctx, unsigned char out PUT_UINT64_BE( ctx->state[4], output, 32 ); PUT_UINT64_BE( ctx->state[5], output, 40 ); - if( ctx->is384 == 0 ) - { + if( ctx->is384 == 0 ) { PUT_UINT64_BE( ctx->state[6], output, 48 ); PUT_UINT64_BE( ctx->state[7], output, 56 ); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h index a461977bf6..485d01105b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h @@ -36,8 +36,7 @@ extern "C" { /** * \brief SHA-512 context structure */ -typedef struct -{ +typedef struct { uint64_t total[2]; /*!< number of bytes processed */ uint64_t state[8]; /*!< intermediate digest state */ unsigned char buffer[128]; /*!< data block being processed */ @@ -66,7 +65,7 @@ void mbedtls_sha512_sw_free( mbedtls_sha512_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha512_sw_clone( mbedtls_sha512_sw_context *dst, - const mbedtls_sha512_sw_context *src ); + const mbedtls_sha512_sw_context *src ); /** * \brief SHA-512 context setup @@ -84,7 +83,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ); * \param ilen length of the input data */ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-512 final digest diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index 53e46abfae..521165383a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -53,7 +53,7 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) } void mbedtls_sha1_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) + const crypto_sha_context *src) { *dst = *src; } @@ -62,17 +62,17 @@ void mbedtls_sha1_hw_starts(crypto_sha_context *ctx) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; ctx->blocksize_mask = 0x3F; SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP, 0); - + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; - + return; } @@ -88,12 +88,11 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, 20); - + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha1_sw_context ctx_sw; - + mbedtls_sha1_sw_init(&ctx_sw); mbedtls_sha1_sw_starts(&ctx_sw); mbedtls_sha1_sw_finish(&ctx_sw, output); @@ -128,7 +127,7 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) } void mbedtls_sha256_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) + const crypto_sha_context *src) { *dst = *src; } @@ -137,7 +136,7 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; @@ -145,10 +144,10 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) ctx->is224_384 = is224; SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP, 0); - + // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; - + return; } @@ -164,12 +163,11 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224_384 ? 28 : 32); - + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha256_sw_context ctx_sw; - + mbedtls_sha256_sw_init(&ctx_sw); mbedtls_sha256_sw_starts(&ctx_sw, ctx->is224_384); mbedtls_sha256_sw_finish(&ctx_sw, output); @@ -205,7 +203,7 @@ void mbedtls_sha512_hw_free(crypto_sha_context *ctx) } void mbedtls_sha512_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) + const crypto_sha_context *src) { *dst = *src; } @@ -214,7 +212,7 @@ void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 128; @@ -222,10 +220,10 @@ void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384) ctx->is224_384 = is384; SHA_Open(is384 ? SHA_MODE_SHA384 : SHA_MODE_SHA512, SHA_NO_SWAP, 0); - + // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; - + return; } @@ -241,12 +239,11 @@ void mbedtls_sha512_hw_finish(crypto_sha_context *ctx, unsigned char output[64]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224_384 ? 48 : 64); - + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha512_sw_context ctx_sw; - + mbedtls_sha512_sw_init(&ctx_sw); mbedtls_sha512_sw_starts(&ctx_sw, ctx->is224_384); mbedtls_sha512_sw_finish(&ctx_sw, output); @@ -270,7 +267,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size if (ilen == 0) { return; } - + size_t fill = ctx->blocksize - ctx->buffer_left; ctx->total += (uint32_t) ilen; @@ -285,7 +282,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size ctx->buffer_left = 0; } } - + while (ilen > ctx->blocksize) { crypto_sha_update_nobuf(ctx, input, ctx->blocksize, 0); input += ctx->blocksize; @@ -304,17 +301,17 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input // 1. Last block which may be incomplete // 2. Non-last block which is complete MBED_ASSERT(islast || ilen == ctx->blocksize); - + const unsigned char *in_pos = input; int rmn = ilen; uint32_t sha_ctl_start = (CRPT->HMAC_CTL & ~(CRPT_HMAC_CTL_DMALAST_Msk | CRPT_HMAC_CTL_DMAEN_Msk | CRPT_HMAC_CTL_HMACEN_Msk)) | CRPT_HMAC_CTL_START_Msk; uint32_t sha_opmode = (CRPT->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; uint32_t DGST0_old = 0, DGST1_old = 0, DGST2_old = 0, DGST3_old = 0, DGST4_old = 0, DGST5_old = 0, DGST6_old = 0, DGST7_old = 0, - DGST8_old = 0, DGST9_old = 0, DGST10_old = 0, DGST11_old = 0, DGST12_old = 0, DGST13_old = 0, DGST14_old = 0, DGST15_old = 0; - + DGST8_old = 0, DGST9_old = 0, DGST10_old = 0, DGST11_old = 0, DGST12_old = 0, DGST13_old = 0, DGST14_old = 0, DGST15_old = 0; + while (rmn > 0) { CRPT->HMAC_CTL = sha_ctl_start; - + uint32_t data = nu_get32_be(in_pos); if (rmn <= 4) { // Last word of a (in)complete block if (islast) { @@ -324,82 +321,79 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input } CRPT->HMAC_DMACNT = lastblock_size; CRPT->HMAC_CTL = sha_ctl_start | CRPT_HMAC_CTL_DMALAST_Msk; - } - else { + } else { switch (sha_opmode) { - case SHA_MODE_SHA512: - DGST15_old = CRPT->HMAC_DGST[15]; - DGST14_old = CRPT->HMAC_DGST[14]; - DGST13_old = CRPT->HMAC_DGST[13]; - DGST12_old = CRPT->HMAC_DGST[12]; - case SHA_MODE_SHA384: - DGST11_old = CRPT->HMAC_DGST[11]; - DGST10_old = CRPT->HMAC_DGST[10]; - DGST9_old = CRPT->HMAC_DGST[9]; - DGST8_old = CRPT->HMAC_DGST[8]; - case SHA_MODE_SHA256: - DGST7_old = CRPT->HMAC_DGST[7]; - case SHA_MODE_SHA224: - DGST5_old = CRPT->HMAC_DGST[5]; - DGST6_old = CRPT->HMAC_DGST[6]; - case SHA_MODE_SHA1: - DGST0_old = CRPT->HMAC_DGST[0]; - DGST1_old = CRPT->HMAC_DGST[1]; - DGST2_old = CRPT->HMAC_DGST[2]; - DGST3_old = CRPT->HMAC_DGST[3]; - DGST4_old = CRPT->HMAC_DGST[4]; + case SHA_MODE_SHA512: + DGST15_old = CRPT->HMAC_DGST[15]; + DGST14_old = CRPT->HMAC_DGST[14]; + DGST13_old = CRPT->HMAC_DGST[13]; + DGST12_old = CRPT->HMAC_DGST[12]; + case SHA_MODE_SHA384: + DGST11_old = CRPT->HMAC_DGST[11]; + DGST10_old = CRPT->HMAC_DGST[10]; + DGST9_old = CRPT->HMAC_DGST[9]; + DGST8_old = CRPT->HMAC_DGST[8]; + case SHA_MODE_SHA256: + DGST7_old = CRPT->HMAC_DGST[7]; + case SHA_MODE_SHA224: + DGST5_old = CRPT->HMAC_DGST[5]; + DGST6_old = CRPT->HMAC_DGST[6]; + case SHA_MODE_SHA1: + DGST0_old = CRPT->HMAC_DGST[0]; + DGST1_old = CRPT->HMAC_DGST[1]; + DGST2_old = CRPT->HMAC_DGST[2]; + DGST3_old = CRPT->HMAC_DGST[3]; + DGST4_old = CRPT->HMAC_DGST[4]; } CRPT->HMAC_CTL = sha_ctl_start; } - } - else { // Non-last word of a complete block + } else { // Non-last word of a complete block CRPT->HMAC_CTL = sha_ctl_start; } while (! (CRPT->HMAC_STS & CRPT_HMAC_STS_DATINREQ_Msk)); CRPT->HMAC_DATIN = data; - + in_pos += 4; rmn -= 4; } - + if (islast) { // Finish of last block while (CRPT->HMAC_STS & CRPT_HMAC_STS_BUSY_Msk); - } - else { // Finish of non-last block + } else { // Finish of non-last block // No H/W flag to indicate finish of non-last block process. // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement. int isfinish = 0; while (! isfinish) { switch (sha_opmode) { - case SHA_MODE_SHA512: - if (DGST12_old != CRPT->HMAC_DGST[12] || DGST13_old != CRPT->HMAC_DGST[13] || DGST14_old != CRPT->HMAC_DGST[14] || + case SHA_MODE_SHA512: + if (DGST12_old != CRPT->HMAC_DGST[12] || DGST13_old != CRPT->HMAC_DGST[13] || DGST14_old != CRPT->HMAC_DGST[14] || DGST15_old != CRPT->HMAC_DGST[15]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA384: - if (DGST8_old != CRPT->HMAC_DGST[8] || DGST9_old != CRPT->HMAC_DGST[9] || DGST10_old != CRPT->HMAC_DGST[10] || + isfinish = 1; + break; + } + case SHA_MODE_SHA384: + if (DGST8_old != CRPT->HMAC_DGST[8] || DGST9_old != CRPT->HMAC_DGST[9] || DGST10_old != CRPT->HMAC_DGST[10] || DGST11_old != CRPT->HMAC_DGST[11]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA256: - if (DGST7_old != CRPT->HMAC_DGST[7]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA224: - if (DGST5_old != CRPT->HMAC_DGST[5] || DGST6_old != CRPT->HMAC_DGST[6]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA1: - if (DGST0_old != CRPT->HMAC_DGST[0] || DGST1_old != CRPT->HMAC_DGST[1] || DGST2_old != CRPT->HMAC_DGST[2] || + isfinish = 1; + break; + } + case SHA_MODE_SHA256: + if (DGST7_old != CRPT->HMAC_DGST[7]) { + isfinish = 1; + break; + } + case SHA_MODE_SHA224: + if (DGST5_old != CRPT->HMAC_DGST[5] || DGST6_old != CRPT->HMAC_DGST[6]) { + isfinish = 1; + break; + } + case SHA_MODE_SHA1: + if (DGST0_old != CRPT->HMAC_DGST[0] || DGST1_old != CRPT->HMAC_DGST[1] || DGST2_old != CRPT->HMAC_DGST[2] || DGST3_old != CRPT->HMAC_DGST[3] || DGST4_old != CRPT->HMAC_DGST[4]) { - isfinish = 1; - break; - } + isfinish = 1; + break; + } } } } @@ -410,7 +404,7 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen) uint32_t *in_pos = (uint32_t *) &CRPT->HMAC_DGST[0]; unsigned char *out_pos = output; uint32_t rmn = olen; - + while (rmn) { uint32_t val = *in_pos ++; nu_set32_be(out_pos, val); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h index 0ab92e57ce..bc833c2e5d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h @@ -29,14 +29,13 @@ extern "C" { /** * \brief SHA context structure */ -typedef struct -{ +typedef struct { uint32_t total; /*!< number of bytes processed */ unsigned char buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ uint16_t buffer_left; uint16_t blocksize; /*!< block size */ uint32_t blocksize_mask; /*!< block size mask */ - + int is224_384; /*!< 0 => SHA-256/SHA-512, else SHA-224/384 */ } crypto_sha_context; @@ -51,7 +50,7 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); void mbedtls_sha1_hw_free( crypto_sha_context *ctx ); void mbedtls_sha1_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); + const crypto_sha_context *src ); void mbedtls_sha1_hw_starts( crypto_sha_context *ctx ); void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ); @@ -66,10 +65,10 @@ void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[ void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); void mbedtls_sha256_hw_free( crypto_sha_context *ctx ); void mbedtls_sha256_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); + const crypto_sha_context *src ); void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 ); void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] ); void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); @@ -82,10 +81,10 @@ void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char dat void mbedtls_sha512_hw_init( crypto_sha_context *ctx ); void mbedtls_sha512_hw_free( crypto_sha_context *ctx ); void mbedtls_sha512_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); + const crypto_sha_context *src ); void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384 ); void mbedtls_sha512_hw_update( crypto_sha_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); void mbedtls_sha512_hw_finish( crypto_sha_context *ctx, unsigned char output[64] ); void mbedtls_sha512_hw_process( crypto_sha_context *ctx, const unsigned char data[128] ); From cb8b449c464cac34aa579be217df4350a2fe71d1 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 17 Aug 2017 14:26:15 +0800 Subject: [PATCH 034/118] Refine coding style --- .../TARGET_NUC472/aes/aes_alt.c | 462 +++++++++--------- .../TARGET_NUC472/aes/aes_alt.h | 59 ++- .../TARGET_NUC472/crypto-misc.c | 7 +- .../TARGET_NUC472/des/des_alt.c | 152 +++--- .../TARGET_NUC472/des/des_alt.h | 44 +- .../TARGET_NUC472/des/des_alt_sw.c | 211 ++++---- .../TARGET_NUC472/des/des_alt_sw.h | 44 +- .../TARGET_NUC472/sha/sha1_alt.c | 21 +- .../TARGET_NUC472/sha/sha1_alt.h | 3 +- .../TARGET_NUC472/sha/sha1_alt_sw.c | 21 +- .../TARGET_NUC472/sha/sha1_alt_sw.h | 5 +- .../TARGET_NUC472/sha/sha256_alt.c | 25 +- .../TARGET_NUC472/sha/sha256_alt.h | 5 +- .../TARGET_NUC472/sha/sha256_alt_sw.c | 53 +- .../TARGET_NUC472/sha/sha256_alt_sw.h | 7 +- .../TARGET_NUC472/sha/sha_alt_hw.c | 107 ++-- .../TARGET_NUC472/sha/sha_alt_hw.h | 11 +- 17 files changed, 578 insertions(+), 659 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 6eee0297b0..389bcb7659 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -32,8 +32,10 @@ #include "mbed_assert.h" /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } @@ -43,7 +45,7 @@ static uint32_t au32MyAESIV[4] = { extern volatile int g_AES_done; -// Must be a multiple of 16 bytes block size +// Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); @@ -51,19 +53,18 @@ static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); static void swapInitVector(unsigned char iv[16]) { - unsigned int* piv; - int i; - // iv SWAP - piv = (unsigned int*)iv; - for( i=0; i< 4; i++) - { - *piv = (((*piv) & 0x000000FF) << 24) | - (((*piv) & 0x0000FF00) << 8) | - (((*piv) & 0x00FF0000) >> 8) | - (((*piv) & 0xFF000000) >> 24); - piv++; - } -} + unsigned int* piv; + int i; + // iv SWAP + piv = (unsigned int*)iv; + for( i=0; i< 4; i++) { + *piv = (((*piv) & 0x000000FF) << 24) | + (((*piv) & 0x0000FF00) << 8) | + (((*piv) & 0x00FF0000) >> 8) | + (((*piv) & 0xFF000000) >> 24); + piv++; + } +} //volatile void CRYPTO_IRQHandler() //{ @@ -74,54 +75,51 @@ static void swapInitVector(unsigned char iv[16]) //} // AES available channel 0~3 -static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00}; // 0: idle, 1: busy +static unsigned char channel_flag[4]= {0x00,0x00,0x00,0x00}; // 0: idle, 1: busy static int channel_alloc() { - int i; - for(i=0; i< (int)sizeof(channel_flag); i++) - { - if( channel_flag[i] == 0x00 ) - { - channel_flag[i] = 0x01; - return i; - } - } - return(-1); + int i; + for(i=0; i< (int)sizeof(channel_flag); i++) { + if( channel_flag[i] == 0x00 ) { + channel_flag[i] = 0x01; + return i; + } + } + return(-1); } static void channel_free(int i) { - if( i >=0 && i < (int)sizeof(channel_flag) ) - channel_flag[i] = 0x00; + if( i >=0 && i < (int)sizeof(channel_flag) ) + channel_flag[i] = 0x00; } void mbedtls_aes_init( mbedtls_aes_context *ctx ) { - int i =-1; + int i =-1; + +// sw_mbedtls_aes_init(ctx); +// return; -// sw_mbedtls_aes_init(ctx); -// return; - memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - + ctx->swapType = AES_IN_OUT_SWAP; - while( (i = channel_alloc()) < 0 ) - { - mbed_assert_internal("No available AES channel", __FILE__, __LINE__); - //osDelay(300); + while( (i = channel_alloc()) < 0 ) { + mbed_assert_internal("No available AES channel", __FILE__, __LINE__); + //osDelay(300); } ctx->channel = i; ctx->iv = au32MyAESIV; - + /* Unlock protected registers */ SYS_UnlockReg(); - CLK_EnableModuleClock(CRPT_MODULE); + CLK_EnableModuleClock(CRPT_MODULE); /* Lock protected registers */ SYS_LockReg(); NVIC_EnableIRQ(CRPT_IRQn); - AES_ENABLE_INT(); + AES_ENABLE_INT(); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) @@ -138,8 +136,8 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ) // SYS_LockReg(); // NVIC_DisableIRQ(CRPT_IRQn); -// AES_DISABLE_INT(); - channel_free(ctx->channel); +// AES_DISABLE_INT(); + channel_free(ctx->channel); mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); } @@ -147,35 +145,34 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ) * AES key schedule (encryption) */ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { unsigned int i; - - switch( keybits ) - { - case 128: - ctx->keySize = AES_KEY_SIZE_128; - break; - case 192: - ctx->keySize = AES_KEY_SIZE_192; - break; - case 256: - ctx->keySize = AES_KEY_SIZE_256; - break; - default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + + switch( keybits ) { + case 128: + ctx->keySize = AES_KEY_SIZE_128; + break; + case 192: + ctx->keySize = AES_KEY_SIZE_192; + break; + case 256: + ctx->keySize = AES_KEY_SIZE_256; + break; + default : + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); } - // key swap - for( i = 0; i < ( keybits >> 5 ); i++ ) - { - ctx->buf[i] = (*(key+i*4) << 24) | - (*(key+1+i*4) << 16) | - (*(key+2+i*4) << 8) | - (*(key+3+i*4) ); - } + // key swap + for( i = 0; i < ( keybits >> 5 ); i++ ) { + ctx->buf[i] = (*(key+i*4) << 24) | + (*(key+1+i*4) << 16) | + (*(key+2+i*4) << 8) | + (*(key+3+i*4) ); + } AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); @@ -186,14 +183,14 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, * AES key schedule (decryption) */ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { int ret; - - + + /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) - goto exit; + goto exit; exit: @@ -202,30 +199,28 @@ exit: static void __nvt_aes_crypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16], int dataSize) + const unsigned char input[16], + unsigned char output[16], int dataSize) { - unsigned char* pIn; - unsigned char* pOut; + unsigned char* pIn; + unsigned char* pOut; + - AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); - if( ((uint32_t)input) & 0x03 ) - { - memcpy(au8InputData, input, dataSize); - pIn = au8InputData; - }else{ - pIn = (unsigned char*)input; + if( ((uint32_t)input) & 0x03 ) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } else { + pIn = (unsigned char*)input; + } + if( (((uint32_t)output) & 0x03) || (dataSize%4)) { // HW CFB output byte count must be multiple of word + pOut = au8OutputData; + } else { + pOut = output; } - if( (((uint32_t)output) & 0x03) || (dataSize%4)) // HW CFB output byte count must be multiple of word - { - pOut = au8OutputData; - } else { - pOut = output; - } - AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); + AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); g_AES_done = 0; AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT); @@ -243,10 +238,10 @@ void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, unsigned char output[16] ) { - - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, 16); - + + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, 16); + } /* @@ -256,10 +251,10 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, 16); + + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, 16); } @@ -268,18 +263,18 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, * AES-ECB block encryption/decryption */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ) + int mode, + const unsigned char input[16], + unsigned char output[16] ) { - - - ctx->opMode = AES_MODE_ECB; + + + ctx->opMode = AES_MODE_ECB; if( mode == MBEDTLS_AES_ENCRYPT ) mbedtls_aes_encrypt( ctx, input, output ); else mbedtls_aes_decrypt( ctx, input, output ); - + return( 0 ); } @@ -289,49 +284,46 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * AES-CBC buffer encryption/decryption */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t len, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t len, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { unsigned char temp[16]; int length = len; - int blockChainLen; + int blockChainLen; if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); + if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { + blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); } else { - blockChainLen = length; - } - - while( length > 0 ) - { - ctx->opMode = AES_MODE_CBC; - swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; + blockChainLen = length; + } + + while( length > 0 ) { + ctx->opMode = AES_MODE_CBC; + swapInitVector(iv); // iv SWAP + ctx->iv = (uint32_t *)iv; + + if( mode == MBEDTLS_AES_ENCRYPT ) { + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, blockChainLen); +// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() + memcpy( iv, output+blockChainLen-16, 16 ); + } else { + memcpy( temp, input+blockChainLen-16, 16 ); + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, blockChainLen); +// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() + memcpy( iv, temp, 16 ); + } + length -= blockChainLen; + input += blockChainLen; + output += blockChainLen; + if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - if( mode == MBEDTLS_AES_ENCRYPT ) - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, output+blockChainLen-16, 16 ); - }else{ - memcpy( temp, input+blockChainLen-16, 16 ); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, temp, 16 ); - } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } return( 0 ); @@ -344,49 +336,42 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, */ /* Support partial block encryption/decryption */ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { int c; size_t n = *iv_off; - unsigned char iv_tmp[16]; - if( mode == MBEDTLS_AES_DECRYPT ) - { - while( length-- ) - { + unsigned char iv_tmp[16]; + if( mode == MBEDTLS_AES_DECRYPT ) { + while( length-- ) { if( n == 0) mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - + else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode + memcpy(iv_tmp, iv, n); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); + memcpy(iv, iv_tmp, n); + } + c = *input++; *output++ = (unsigned char)( c ^ iv[n] ); iv[n] = (unsigned char) c; n = ( n + 1 ) & 0x0F; } - } - else - { - while( length-- ) - { + } else { + while( length-- ) { if( n == 0 ) mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - + else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode + memcpy(iv_tmp, iv, n); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); + memcpy(iv, iv_tmp, n); + } + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); n = ( n + 1 ) & 0x0F; @@ -399,75 +384,70 @@ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, } int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t len, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t len, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { - size_t n = *iv_off; + size_t n = *iv_off; unsigned char temp[16]; - int length=len; - int blockChainLen; - int remLen=0; - int ivLen; - - - // proceed: start with partial block by ECB mode first - if( n !=0 ) { - __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n , iv_off, iv, input, output); - input += (16 - n); - output += (16 - n); - length -= (16 - n); - } - - // For address or byte count non-word alignment, go through reserved DMA buffer. - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) // Must reserved DMA buffer for each block - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else if(length%4) { // Need reserved DMA buffer once for last chain - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); - } else { // Not need reserved DMA buffer - blockChainLen = length; - } - - // proceed: start with block alignment - while( length > 0 ) - { + int length=len; + int blockChainLen; + int remLen=0; + int ivLen; - ctx->opMode = AES_MODE_CFB; - swapInitVector(iv); // iv SWAP - - ctx->iv = (uint32_t *)iv; - remLen = blockChainLen%16; - ivLen = (( remLen > 0) ? remLen: 16 ); - - if( mode == MBEDTLS_AES_DECRYPT ) - { - memcpy(temp, input+blockChainLen - ivLen, ivLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16 , 16); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy(iv,temp, ivLen); - } - else - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16 , 16); - memcpy(iv,output+blockChainLen-ivLen,ivLen); - } - length -= blockChainLen; + // proceed: start with partial block by ECB mode first + if( n !=0 ) { + __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n, iv_off, iv, input, output); + input += (16 - n); + output += (16 - n); + length -= (16 - n); + } + + // For address or byte count non-word alignment, go through reserved DMA buffer. + if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { // Must reserved DMA buffer for each block + blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); + } else if(length%4) { // Need reserved DMA buffer once for last chain + blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); + } else { // Not need reserved DMA buffer + blockChainLen = length; + } + + // proceed: start with block alignment + while( length > 0 ) { + + ctx->opMode = AES_MODE_CFB; + + swapInitVector(iv); // iv SWAP + + ctx->iv = (uint32_t *)iv; + remLen = blockChainLen%16; + ivLen = (( remLen > 0) ? remLen: 16 ); + + if( mode == MBEDTLS_AES_DECRYPT ) { + memcpy(temp, input+blockChainLen - ivLen, ivLen); + if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16, 16); + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, blockChainLen); + memcpy(iv,temp, ivLen); + } else { + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, blockChainLen); + if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16, 16); + memcpy(iv,output+blockChainLen-ivLen,ivLen); + } + length -= blockChainLen; input += blockChainLen; output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } - + if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain + } + *iv_off = remLen; - return( 0 ); + return( 0 ); } @@ -475,17 +455,16 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, * AES-CFB8 buffer encryption/decryption */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { unsigned char c; unsigned char ov[17]; - while( length-- ) - { + while( length-- ) { memcpy( ov, iv, 16 ); mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); @@ -509,18 +488,17 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * AES-CTR buffer encryption/decryption */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ) + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) { int c, i; size_t n = *nc_off; - while( length-- ) - { + while( length-- ) { if( n == 0 ) { mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index 31567043df..8b98e73ef0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -42,8 +42,7 @@ extern "C" { * - to simplify key expansion in the 256-bit case by * generating an extra round key */ -typedef struct -{ +typedef struct { uint32_t keySize; uint32_t encDec; uint32_t opMode; @@ -51,7 +50,7 @@ typedef struct uint32_t swapType; uint32_t *iv; unsigned char prv_iv[16]; - uint32_t buf[8]; + uint32_t buf[8]; } mbedtls_aes_context; @@ -79,7 +78,7 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ); * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES key schedule (decryption) @@ -91,7 +90,7 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES-ECB block encryption/decryption @@ -104,9 +103,9 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ); + int mode, + const unsigned char input[16], + unsigned char output[16] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -132,11 +131,11 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) @@ -166,12 +165,12 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); /** * \brief AES-CFB8 buffer encryption/decryption. @@ -198,11 +197,11 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /*MBEDTLS_CIPHER_MODE_CFB */ #if defined(MBEDTLS_CIPHER_MODE_CTR) @@ -229,12 +228,12 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ); + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CTR */ /** diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c index 7f6646f40b..c5d49bb0dd 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c @@ -30,7 +30,7 @@ void crypto_init(void) return; } crypto_inited = 1; - + CLK_EnableModuleClock(CRPT_MODULE); } @@ -48,11 +48,10 @@ int crypto_sha_acquire(void) if (crypto_sha_avail) { crypto_sha_avail = 0; return 1; - } - else { + } else { return 0; } - + } void crypto_sha_release(void) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 12f8720987..cb7effa7bd 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -24,8 +24,8 @@ #include "nu_bitutil.h" #include "mbed_toolchain.h" -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output); +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output); void mbedtls_des_init(mbedtls_des_context *ctx) { @@ -58,15 +58,16 @@ void mbedtls_des3_free( mbedtls_des3_context *ctx ) } static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; + 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, + 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, + 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, + 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, + 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, + 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, + 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, + 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, + 254 + }; void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE]) { @@ -114,8 +115,7 @@ int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SI #define WEAK_KEY_COUNT 16 -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ +static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, @@ -157,7 +157,7 @@ int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MB memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE); - + return 0; } @@ -180,7 +180,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * Triple-DES key schedule (112-bit, encryption) */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 1; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -196,7 +196,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (112-bit, decryption) */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 0; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -212,7 +212,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, encryption) */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 1; // Keying option 1: All three keys are independent. @@ -228,7 +228,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, decryption) */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 0; // Keying option 1: All three keys are independent. @@ -244,8 +244,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * DES-ECB block encryption/decryption */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, DES_MODE_ECB, 8, iv, input, output); @@ -256,11 +256,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * DES-CBC buffer encryption/decryption */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, DES_MODE_CBC, length, iv, input, output); } @@ -270,8 +270,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * 3DES-ECB block encryption/decryption */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, TDES_MODE_ECB, 8, iv, input, output); @@ -282,11 +282,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * 3DES-CBC buffer encryption/decryption */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, TDES_MODE_CBC, length, iv, input, output); } @@ -294,24 +294,23 @@ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output) +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output) { if (length % 8) { return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } - + // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | - tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); + tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); // Keying option 1: All three keys are independent. // Keying option 2: K1 and K2 are independent, and K3 = K1. - // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. + // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. if (keyopt == 1) { CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk; - } - else { + } else { CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; } @@ -331,72 +330,71 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S *tdes_key ++ = val; val = nu_get32_be(key[2] + 4); *tdes_key ++ = val; - + uint32_t rmn = length; const unsigned char *in_pos = input; unsigned char *out_pos = output; - + // Must be a multiple of 64-bit block size - #define MAXSIZE_DMABUF (8 * 5) +#define MAXSIZE_DMABUF (8 * 5) MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; while (rmn) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; - + uint32_t ivh, ivl; ivh = nu_get32_be(iv); ivl = nu_get32_be(iv + 4); TDES_SetInitVect(0, ivh, ivl); - + memcpy(dmabuf_in, in_pos, data_len); - + TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - + // Start enc/dec. // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting. CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); - + memcpy(out_pos, dmabuf_out, data_len); in_pos += data_len; out_pos += data_len; rmn -= data_len; - + // Update IV for next block enc/dec in next function call switch (tdes_opmode) { - case DES_MODE_OFB: - case TDES_MODE_OFB: { - // OFB: IV (enc/dec) = output block XOR input block - uint32_t lbh, lbl; - // Last block of input data - lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); - lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); - // Last block of output data - ivh = nu_get32_be(dmabuf_out + 4); - ivl = nu_get32_be(dmabuf_out + 0); - ivh = ivh ^ lbh; - ivl = ivl ^ lbl; - nu_set32_be(iv + 4, ivh); - nu_set32_be(iv, ivl); - break; - } - case DES_MODE_CBC: - case DES_MODE_CFB: - case TDES_MODE_CBC: - case TDES_MODE_CFB: { - // CBC/CFB: IV (enc) = output block - // IV (dec) = input block - if (enc) { - memcpy(iv, dmabuf_out + data_len - 8, 8); - } - else { - memcpy(iv, dmabuf_in + data_len - 8, 8); - } + case DES_MODE_OFB: + case TDES_MODE_OFB: { + // OFB: IV (enc/dec) = output block XOR input block + uint32_t lbh, lbl; + // Last block of input data + lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); + lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); + // Last block of output data + ivh = nu_get32_be(dmabuf_out + 4); + ivl = nu_get32_be(dmabuf_out + 0); + ivh = ivh ^ lbh; + ivl = ivl ^ lbl; + nu_set32_be(iv + 4, ivh); + nu_set32_be(iv, ivl); + break; + } + case DES_MODE_CBC: + case DES_MODE_CFB: + case TDES_MODE_CBC: + case TDES_MODE_CFB: { + // CBC/CFB: IV (enc) = output block + // IV (dec) = input block + if (enc) { + memcpy(iv, dmabuf_out + data_len - 8, 8); + } else { + memcpy(iv, dmabuf_in + data_len - 8, 8); } } + } } - + return 0; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h index 3e00c3be6d..054a9f0b78 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h @@ -13,7 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #ifndef MBEDTLS_DES_ALT_H #define MBEDTLS_DES_ALT_H @@ -33,8 +33,7 @@ extern "C" { /** * \brief DES context structure */ -typedef struct -{ +typedef struct { int enc; /*!< 0: dec, 1: enc */ uint16_t keyopt; uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ @@ -44,8 +43,7 @@ mbedtls_des_context; /** * \brief Triple-DES context structure */ -typedef struct -{ +typedef struct { int enc; /*!< 0: dec, 1: enc */ uint16_t keyopt; uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ @@ -140,7 +138,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * \return 0 */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (112-bit, decryption) @@ -151,7 +149,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (168-bit, encryption) @@ -162,7 +160,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief Triple-DES key schedule (168-bit, decryption) @@ -173,7 +171,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief DES-ECB block encryption/decryption @@ -185,8 +183,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * \return 0 if successful */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -208,11 +206,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * \param output buffer holding the output data */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -225,8 +223,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * \return 0 if successful */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -250,11 +248,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c index 301a5476c1..d3968b464b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c @@ -33,8 +33,10 @@ #include /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } /* @@ -63,8 +65,7 @@ static void mbedtls_zeroize( void *v, size_t n ) { /* * Expanded DES S-boxes */ -static const uint32_t SB1[64] = -{ +static const uint32_t SB1[64] = { 0x01010400, 0x00000000, 0x00010000, 0x01010404, 0x01010004, 0x00010404, 0x00000004, 0x00010000, 0x00000400, 0x01010400, 0x01010404, 0x00000400, @@ -83,8 +84,7 @@ static const uint32_t SB1[64] = 0x00010004, 0x00010400, 0x00000000, 0x01010004 }; -static const uint32_t SB2[64] = -{ +static const uint32_t SB2[64] = { 0x80108020, 0x80008000, 0x00008000, 0x00108020, 0x00100000, 0x00000020, 0x80100020, 0x80008020, 0x80000020, 0x80108020, 0x80108000, 0x80000000, @@ -103,8 +103,7 @@ static const uint32_t SB2[64] = 0x80000000, 0x80100020, 0x80108020, 0x00108000 }; -static const uint32_t SB3[64] = -{ +static const uint32_t SB3[64] = { 0x00000208, 0x08020200, 0x00000000, 0x08020008, 0x08000200, 0x00000000, 0x00020208, 0x08000200, 0x00020008, 0x08000008, 0x08000008, 0x00020000, @@ -123,8 +122,7 @@ static const uint32_t SB3[64] = 0x00020208, 0x00000008, 0x08020008, 0x00020200 }; -static const uint32_t SB4[64] = -{ +static const uint32_t SB4[64] = { 0x00802001, 0x00002081, 0x00002081, 0x00000080, 0x00802080, 0x00800081, 0x00800001, 0x00002001, 0x00000000, 0x00802000, 0x00802000, 0x00802081, @@ -143,8 +141,7 @@ static const uint32_t SB4[64] = 0x00000080, 0x00800000, 0x00002000, 0x00802080 }; -static const uint32_t SB5[64] = -{ +static const uint32_t SB5[64] = { 0x00000100, 0x02080100, 0x02080000, 0x42000100, 0x00080000, 0x00000100, 0x40000000, 0x02080000, 0x40080100, 0x00080000, 0x02000100, 0x40080100, @@ -163,8 +160,7 @@ static const uint32_t SB5[64] = 0x00000000, 0x40080000, 0x02080100, 0x40000100 }; -static const uint32_t SB6[64] = -{ +static const uint32_t SB6[64] = { 0x20000010, 0x20400000, 0x00004000, 0x20404010, 0x20400000, 0x00000010, 0x20404010, 0x00400000, 0x20004000, 0x00404010, 0x00400000, 0x20000010, @@ -183,8 +179,7 @@ static const uint32_t SB6[64] = 0x20404000, 0x20000000, 0x00400010, 0x20004010 }; -static const uint32_t SB7[64] = -{ +static const uint32_t SB7[64] = { 0x00200000, 0x04200002, 0x04000802, 0x00000000, 0x00000800, 0x04000802, 0x00200802, 0x04200800, 0x04200802, 0x00200000, 0x00000000, 0x04000002, @@ -203,8 +198,7 @@ static const uint32_t SB7[64] = 0x04000002, 0x04000800, 0x00000800, 0x00200002 }; -static const uint32_t SB8[64] = -{ +static const uint32_t SB8[64] = { 0x10001040, 0x00001000, 0x00040000, 0x10041040, 0x10000000, 0x10001040, 0x00000040, 0x10000000, 0x00040040, 0x10040000, 0x10041040, 0x00041000, @@ -226,16 +220,14 @@ static const uint32_t SB8[64] = /* * PC1: left and right halves bit-swap */ -static const uint32_t LHs[16] = -{ +static const uint32_t LHs[16] = { 0x00000000, 0x00000001, 0x00000100, 0x00000101, 0x00010000, 0x00010001, 0x00010100, 0x00010101, 0x01000000, 0x01000001, 0x01000100, 0x01000101, 0x01010000, 0x01010001, 0x01010100, 0x01010101 }; -static const uint32_t RHs[16] = -{ +static const uint32_t RHs[16] = { 0x00000000, 0x01000000, 0x00010000, 0x01010000, 0x00000100, 0x01000100, 0x00010100, 0x01010100, 0x00000001, 0x01000001, 0x00010001, 0x01010001, @@ -317,15 +309,16 @@ void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ) } static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; + 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, + 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, + 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, + 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, + 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, + 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, + 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, + 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, + 254 + }; void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ) { @@ -372,8 +365,7 @@ int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY #define WEAK_KEY_COUNT 16 -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ +static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, @@ -415,18 +407,22 @@ void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KE /* * Permuted Choice 1 */ - T = ((Y >> 4) ^ X) & 0x0F0F0F0F; X ^= T; Y ^= (T << 4); - T = ((Y ) ^ X) & 0x10101010; X ^= T; Y ^= (T ); + T = ((Y >> 4) ^ X) & 0x0F0F0F0F; + X ^= T; + Y ^= (T << 4); + T = ((Y ) ^ X) & 0x10101010; + X ^= T; + Y ^= (T ); X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2) - | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) - | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) - | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); + | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) + | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) + | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2) - | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) - | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) - | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); + | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) + | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) + | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); X &= 0x0FFFFFFF; Y &= 0x0FFFFFFF; @@ -434,42 +430,38 @@ void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KE /* * calculate subkeys */ - for( i = 0; i < 16; i++ ) - { - if( i < 2 || i == 8 || i == 15 ) - { + for( i = 0; i < 16; i++ ) { + if( i < 2 || i == 8 || i == 15 ) { X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF; Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF; - } - else - { + } else { X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF; Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF; } *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000) - | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) - | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) - | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) - | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) - | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) - | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) - | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) - | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) - | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) - | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); + | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) + | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) + | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) + | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) + | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) + | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) + | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) + | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) + | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) + | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000) - | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) - | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) - | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) - | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) - | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) - | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) - | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) - | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) - | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) - | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); + | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) + | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) + | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) + | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) + | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) + | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) + | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) + | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) + | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) + | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); } } @@ -492,8 +484,7 @@ int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char mbedtls_des_setkey( ctx->sk, key ); - for( i = 0; i < 16; i += 2 ) - { + for( i = 0; i < 16; i += 2 ) { SWAP( ctx->sk[i ], ctx->sk[30 - i] ); SWAP( ctx->sk[i + 1], ctx->sk[31 - i] ); } @@ -510,8 +501,7 @@ static void des3_set2key( uint32_t esk[96], mbedtls_des_setkey( esk, key ); mbedtls_des_setkey( dsk + 32, key + 8 ); - for( i = 0; i < 32; i += 2 ) - { + for( i = 0; i < 32; i += 2 ) { dsk[i ] = esk[30 - i]; dsk[i + 1] = esk[31 - i]; @@ -530,7 +520,7 @@ static void des3_set2key( uint32_t esk[96], * Triple-DES key schedule (112-bit, encryption) */ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { uint32_t sk[96]; @@ -544,7 +534,7 @@ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, * Triple-DES key schedule (112-bit, decryption) */ int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { uint32_t sk[96]; @@ -564,8 +554,7 @@ static void des3_set3key( uint32_t esk[96], mbedtls_des_setkey( dsk + 32, key + 8 ); mbedtls_des_setkey( esk + 64, key + 16 ); - for( i = 0; i < 32; i += 2 ) - { + for( i = 0; i < 32; i += 2 ) { dsk[i ] = esk[94 - i]; dsk[i + 1] = esk[95 - i]; @@ -581,7 +570,7 @@ static void des3_set3key( uint32_t esk[96], * Triple-DES key schedule (168-bit, encryption) */ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { uint32_t sk[96]; @@ -595,7 +584,7 @@ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, * Triple-DES key schedule (168-bit, decryption) */ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { uint32_t sk[96]; @@ -609,8 +598,8 @@ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, * DES-ECB block encryption/decryption */ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { int i; uint32_t X, Y, T, *SK; @@ -622,8 +611,7 @@ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, DES_IP( X, Y ); - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( Y, X ); DES_ROUND( X, Y ); } @@ -641,11 +629,11 @@ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, * DES-CBC buffer encryption/decryption */ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { int i; unsigned char temp[8]; @@ -653,10 +641,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, if( length % 8 ) return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { + if( mode == MBEDTLS_DES_ENCRYPT ) { + while( length > 0 ) { for( i = 0; i < 8; i++ ) output[i] = (unsigned char)( input[i] ^ iv[i] ); @@ -667,11 +653,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, output += 8; length -= 8; } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { + } else { /* MBEDTLS_DES_DECRYPT */ + while( length > 0 ) { memcpy( temp, input, 8 ); mbedtls_des_sw_crypt_ecb( ctx, input, output ); @@ -694,8 +677,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, * 3DES-ECB block encryption/decryption */ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { int i; uint32_t X, Y, T, *SK; @@ -707,20 +690,17 @@ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, DES_IP( X, Y ); - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( Y, X ); DES_ROUND( X, Y ); } - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( X, Y ); DES_ROUND( Y, X ); } - for( i = 0; i < 8; i++ ) - { + for( i = 0; i < 8; i++ ) { DES_ROUND( Y, X ); DES_ROUND( X, Y ); } @@ -738,11 +718,11 @@ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, * 3DES-CBC buffer encryption/decryption */ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { int i; unsigned char temp[8]; @@ -750,10 +730,8 @@ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, if( length % 8 ) return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { + if( mode == MBEDTLS_DES_ENCRYPT ) { + while( length > 0 ) { for( i = 0; i < 8; i++ ) output[i] = (unsigned char)( input[i] ^ iv[i] ); @@ -764,11 +742,8 @@ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, output += 8; length -= 8; } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { + } else { /* MBEDTLS_DES_DECRYPT */ + while( length > 0 ) { memcpy( temp, input, 8 ); mbedtls_des3_sw_crypt_ecb( ctx, input, output ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h index a255170af0..24d4b13a47 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h @@ -38,8 +38,7 @@ extern "C" { /** * \brief DES context structure */ -typedef struct -{ +typedef struct { uint32_t sk[32]; /*!< DES subkeys */ } mbedtls_des_sw_context; @@ -47,8 +46,7 @@ mbedtls_des_sw_context; /** * \brief Triple-DES context structure */ -typedef struct -{ +typedef struct { uint32_t sk[96]; /*!< 3DES subkeys */ } mbedtls_des3_sw_context; @@ -141,7 +139,7 @@ int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char * \return 0 */ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (112-bit, decryption) @@ -152,7 +150,7 @@ int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, * \return 0 */ int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (168-bit, encryption) @@ -163,7 +161,7 @@ int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, * \return 0 */ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief Triple-DES key schedule (168-bit, decryption) @@ -174,7 +172,7 @@ int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, * \return 0 */ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief DES-ECB block encryption/decryption @@ -186,8 +184,8 @@ int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, * \return 0 if successful */ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -209,11 +207,11 @@ int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, * \param output buffer holding the output data */ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -226,8 +224,8 @@ int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, * \return 0 if successful */ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -251,11 +249,11 @@ int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH */ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -267,7 +265,7 @@ int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, * \param key Base key */ void mbedtls_des_sw_setkey( uint32_t SK[32], - const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); #ifdef __cplusplus } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index 1e7a6a1276..5ef56e9040 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -28,8 +28,7 @@ void mbedtls_sha1_init(mbedtls_sha1_context *ctx) if (crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha1_hw_init(&ctx->hw_ctx); - } - else { + } else { ctx->ishw = 0; mbedtls_sha1_sw_init(&ctx->sw_ctx); } @@ -44,8 +43,7 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) if (ctx->ishw) { mbedtls_sha1_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else { mbedtls_sha1_sw_free(&ctx->sw_ctx); } } @@ -73,8 +71,7 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -87,8 +84,7 @@ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) { if (ctx->ishw) { mbedtls_sha1_hw_starts(&ctx->hw_ctx); - } - else { + } else { mbedtls_sha1_sw_starts(&ctx->sw_ctx); } } @@ -100,8 +96,7 @@ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, { if (ctx->ishw) { mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else { mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -113,8 +108,7 @@ void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20]) { if (ctx->ishw) { mbedtls_sha1_hw_finish(&ctx->hw_ctx, output); - } - else { + } else { mbedtls_sha1_sw_finish(&ctx->sw_ctx, output); } } @@ -123,8 +117,7 @@ void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64 { if (ctx->ishw) { mbedtls_sha1_hw_process(&ctx->hw_ctx, data); - } - else { + } else { mbedtls_sha1_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h index 9d6db507f4..9471b628ba 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h @@ -33,8 +33,7 @@ struct mbedtls_sha1_context_s; /** * \brief SHA-1 context structure */ -typedef struct mbedtls_sha1_context_s -{ +typedef struct mbedtls_sha1_context_s { int ishw; crypto_sha_context hw_ctx; mbedtls_sha1_sw_context sw_ctx; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c index f511214993..097b0e518f 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c @@ -40,8 +40,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } /* @@ -81,7 +83,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ) } void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ) + const mbedtls_sha1_sw_context *src ) { *dst = *src; } @@ -277,8 +279,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha1_sw_process( ctx, ctx->buffer ); input += fill; @@ -286,8 +287,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha1_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -297,9 +297,8 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha1_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha1_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -315,7 +314,7 @@ void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[ unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h index 4dbb609fe8..3be7272be6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h @@ -38,8 +38,7 @@ extern "C" { /** * \brief SHA-1 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[5]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -67,7 +66,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ); + const mbedtls_sha1_sw_context *src ); /** * \brief SHA-1 context setup diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index acdcbb95a4..965b026099 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -28,8 +28,7 @@ void mbedtls_sha256_init(mbedtls_sha256_context *ctx) if (crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha256_hw_init(&ctx->hw_ctx); - } - else { + } else { ctx->ishw = 0; mbedtls_sha256_sw_init(&ctx->sw_ctx); } @@ -44,14 +43,13 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) if (ctx->ishw) { mbedtls_sha256_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else { mbedtls_sha256_sw_free(&ctx->sw_ctx); } } void mbedtls_sha256_clone(mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src) + const mbedtls_sha256_context *src) { if (src->ishw) { // Clone S/W ctx from H/W ctx @@ -74,8 +72,7 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -85,11 +82,10 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, * SHA-256 context setup */ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) -{ +{ if (ctx->ishw) { mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224); - } - else { + } else { mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224); } } @@ -101,8 +97,7 @@ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *inp { if (ctx->ishw) { mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else { mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -114,8 +109,7 @@ void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32] { if (ctx->ishw) { mbedtls_sha256_hw_finish(&ctx->hw_ctx, output); - } - else { + } else { mbedtls_sha256_sw_finish(&ctx->sw_ctx, output); } } @@ -124,8 +118,7 @@ void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char dat { if (ctx->ishw) { mbedtls_sha256_hw_process(&ctx->hw_ctx, data); - } - else { + } else { mbedtls_sha256_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h index 2e336f760b..eedca82eea 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h @@ -33,8 +33,7 @@ struct mbedtls_sha256_context_s; /** * \brief SHA-256 context structure */ -typedef struct mbedtls_sha256_context_s -{ +typedef struct mbedtls_sha256_context_s { int ishw; crypto_sha_context hw_ctx; mbedtls_sha256_sw_context sw_ctx; @@ -80,7 +79,7 @@ void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c index 5116e69258..616a8400f6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c @@ -43,8 +43,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; + while( n-- ) *p++ = 0; } /* @@ -84,7 +86,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ) } void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ) + const mbedtls_sha256_sw_context *src ) { *dst = *src; } @@ -97,8 +99,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->total[0] = 0; ctx->total[1] = 0; - if( is224 == 0 ) - { + if( is224 == 0 ) { /* SHA-256 */ ctx->state[0] = 0x6A09E667; ctx->state[1] = 0xBB67AE85; @@ -108,9 +109,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->state[5] = 0x9B05688C; ctx->state[6] = 0x1F83D9AB; ctx->state[7] = 0x5BE0CD19; - } - else - { + } else { /* SHA-224 */ ctx->state[0] = 0xC1059ED8; ctx->state[1] = 0x367CD507; @@ -125,8 +124,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->is224 = is224; } -static const uint32_t K[] = -{ +static const uint32_t K[] = { 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5, 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5, 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3, @@ -180,8 +178,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c A[i] = ctx->state[i]; #if defined(MBEDTLS_SHA256_SMALLER) - for( i = 0; i < 64; i++ ) - { + for( i = 0; i < 64; i++ ) { if( i < 16 ) GET_UINT32_BE( W[i], data, 4 * i ); else @@ -189,15 +186,21 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] ); - temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3]; - A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1; + temp1 = A[7]; + A[7] = A[6]; + A[6] = A[5]; + A[5] = A[4]; + A[4] = A[3]; + A[3] = A[2]; + A[2] = A[1]; + A[1] = A[0]; + A[0] = temp1; } #else /* MBEDTLS_SHA256_SMALLER */ for( i = 0; i < 16; i++ ) GET_UINT32_BE( W[i], data, 4 * i ); - for( i = 0; i < 16; i += 8 ) - { + for( i = 0; i < 16; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] ); @@ -208,8 +211,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] ); } - for( i = 16; i < 64; i += 8 ) - { + for( i = 16; i < 64; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] ); @@ -229,7 +231,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c * SHA-256 process buffer */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ) + size_t ilen ) { size_t fill; uint32_t left; @@ -246,8 +248,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha256_sw_process( ctx, ctx->buffer ); input += fill; @@ -255,8 +256,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha256_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -266,9 +266,8 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha256_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha256_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -284,7 +283,7 @@ void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char out unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h index d43d2e402a..feb75a3604 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h @@ -38,8 +38,7 @@ extern "C" { /** * \brief SHA-256 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[8]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -68,7 +67,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ); + const mbedtls_sha256_sw_context *src ); /** * \brief SHA-256 context setup @@ -86,7 +85,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index d1304b5b54..a653cd7a96 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -53,7 +53,7 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) } void mbedtls_sha1_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) + const crypto_sha_context *src) { *dst = *src; } @@ -62,17 +62,17 @@ void mbedtls_sha1_hw_starts(crypto_sha_context *ctx) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; ctx->blocksize_mask = 0x3F; SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP); - + // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk; - + return; } @@ -88,12 +88,11 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, 20); - + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha1_sw_context ctx_sw; - + mbedtls_sha1_sw_init(&ctx_sw); mbedtls_sha1_sw_starts(&ctx_sw); mbedtls_sha1_sw_finish(&ctx_sw, output); @@ -128,7 +127,7 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) } void mbedtls_sha256_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) + const crypto_sha_context *src) { *dst = *src; } @@ -137,7 +136,7 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; @@ -145,10 +144,10 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) ctx->is224 = is224; SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP); - + // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk; - + return; } @@ -164,12 +163,11 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224 ? 28 : 32); - + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha256_sw_context ctx_sw; - + mbedtls_sha256_sw_init(&ctx_sw); mbedtls_sha256_sw_starts(&ctx_sw, ctx->is224); mbedtls_sha256_sw_finish(&ctx_sw, output); @@ -193,7 +191,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size if (ilen == 0) { return; } - + size_t fill = ctx->blocksize - ctx->buffer_left; ctx->total += (uint32_t) ilen; @@ -208,7 +206,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size ctx->buffer_left = 0; } } - + while (ilen > ctx->blocksize) { crypto_sha_update_nobuf(ctx, input, ctx->blocksize, 0); input += ctx->blocksize; @@ -227,16 +225,16 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input // 1. Last block which may be incomplete // 2. Non-last block which is complete MBED_ASSERT(islast || ilen == ctx->blocksize); - + const unsigned char *in_pos = input; int rmn = ilen; uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk; uint32_t sha_opmode = (CRPT->SHA_CTL & CRPT_SHA_CTL_OPMODE_Msk) >> CRPT_SHA_CTL_OPMODE_Pos; uint32_t DGST0_old, DGST1_old, DGST2_old, DGST3_old, DGST4_old, DGST5_old, DGST6_old, DGST7_old; - + while (rmn > 0) { CRPT->SHA_CTL = sha_ctl_start; - + uint32_t data = nu_get32_be(in_pos); if (rmn <= 4) { // Last word of a (in)complete block if (islast) { @@ -246,60 +244,57 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input } CRPT->SHA_DMACNT = lastblock_size; CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk; - } - else { + } else { switch (sha_opmode) { - case SHA_MODE_SHA256: - DGST7_old = CRPT->SHA_DGST7; - case SHA_MODE_SHA224: - DGST5_old = CRPT->SHA_DGST5; - DGST6_old = CRPT->SHA_DGST6; - case SHA_MODE_SHA1: - DGST0_old = CRPT->SHA_DGST0; - DGST1_old = CRPT->SHA_DGST1; - DGST2_old = CRPT->SHA_DGST2; - DGST3_old = CRPT->SHA_DGST3; - DGST4_old = CRPT->SHA_DGST4; + case SHA_MODE_SHA256: + DGST7_old = CRPT->SHA_DGST7; + case SHA_MODE_SHA224: + DGST5_old = CRPT->SHA_DGST5; + DGST6_old = CRPT->SHA_DGST6; + case SHA_MODE_SHA1: + DGST0_old = CRPT->SHA_DGST0; + DGST1_old = CRPT->SHA_DGST1; + DGST2_old = CRPT->SHA_DGST2; + DGST3_old = CRPT->SHA_DGST3; + DGST4_old = CRPT->SHA_DGST4; } CRPT->SHA_CTL = sha_ctl_start; } - } - else { // Non-last word of a complete block + } else { // Non-last word of a complete block CRPT->SHA_CTL = sha_ctl_start; } while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk)); CRPT->SHA_DATIN = data; - + in_pos += 4; rmn -= 4; } - + if (islast) { // Finish of last block while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk); - } - else { // Finish of non-last block + } else { // Finish of non-last block // No H/W flag to indicate finish of non-last block process. // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement. int isfinish = 0; while (! isfinish) { switch (sha_opmode) { - case SHA_MODE_SHA256: - if (DGST7_old != CRPT->SHA_DGST7) { - isfinish = 1; - break; - } - case SHA_MODE_SHA224: - if (DGST5_old != CRPT->SHA_DGST5 || DGST6_old != CRPT->SHA_DGST6) { - isfinish = 1; - break; - } - case SHA_MODE_SHA1: - if (DGST0_old != CRPT->SHA_DGST0 || DGST1_old != CRPT->SHA_DGST1 || DGST2_old != CRPT->SHA_DGST2 || + case SHA_MODE_SHA256: + if (DGST7_old != CRPT->SHA_DGST7) { + isfinish = 1; + break; + } + case SHA_MODE_SHA224: + if (DGST5_old != CRPT->SHA_DGST5 || DGST6_old != CRPT->SHA_DGST6) { + isfinish = 1; + break; + } + case SHA_MODE_SHA1: + if (DGST0_old != CRPT->SHA_DGST0 || DGST1_old != CRPT->SHA_DGST1 || DGST2_old != CRPT->SHA_DGST2 || DGST3_old != CRPT->SHA_DGST3 || DGST4_old != CRPT->SHA_DGST4) { - isfinish = 1; - break; - } + isfinish = 1; + break; + } } } } @@ -310,7 +305,7 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen) uint32_t *in_pos = (uint32_t *) &CRPT->SHA_DGST0; unsigned char *out_pos = output; uint32_t rmn = olen; - + while (rmn) { uint32_t val = *in_pos ++; nu_set32_be(out_pos, val); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h index ae539b01de..b43ac43e46 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h @@ -29,14 +29,13 @@ extern "C" { /** * \brief SHA context structure */ -typedef struct -{ +typedef struct { uint32_t total; /*!< number of bytes processed */ unsigned char buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ uint16_t buffer_left; uint16_t blocksize; /*!< block size */ uint32_t blocksize_mask; /*!< block size mask */ - + int is224; /*!< 0 => SHA-256, else SHA-224 */ } crypto_sha_context; @@ -51,7 +50,7 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); void mbedtls_sha1_hw_free( crypto_sha_context *ctx ); void mbedtls_sha1_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); + const crypto_sha_context *src ); void mbedtls_sha1_hw_starts( crypto_sha_context *ctx ); void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ); @@ -66,10 +65,10 @@ void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[ void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); void mbedtls_sha256_hw_free( crypto_sha_context *ctx ); void mbedtls_sha256_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); + const crypto_sha_context *src ); void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 ); void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] ); void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); From 5cd3b98cf10bc66e939fcee26e50561f56f6ac00 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Fri, 18 Aug 2017 11:17:44 +0800 Subject: [PATCH 035/118] Fix AES alternative function not thread-safe --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 15 +++++---------- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 2 +- .../TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 18 ++++++------------ .../TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h | 2 +- 4 files changed, 13 insertions(+), 24 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index c42ea5990c..e11c9431a0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -41,17 +41,10 @@ static void mbedtls_zeroize( void *v, size_t n ) while( n-- ) *p++ = 0; } - -static uint32_t au32MyAESIV[4] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}; - extern volatile int g_AES_done; // Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) -MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; -MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; static void swapInitVector(unsigned char iv[16]) { @@ -114,7 +107,7 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) mbed_assert_internal("No available AES channel", __FILE__, __LINE__); } ctx->channel = i; - ctx->iv = au32MyAESIV; + memset(ctx->iv, 0, sizeof (ctx->iv)); /* Unlock protected registers */ SYS_UnlockReg(); @@ -201,6 +194,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, unsigned char* pIn; unsigned char* pOut; + MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; + MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); @@ -293,7 +288,7 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, while( length > 0 ) { ctx->opMode = AES_MODE_CBC; swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; + memcpy(ctx->iv, iv, 16); if( mode == MBEDTLS_AES_ENCRYPT ) { ctx->encDec = 1; @@ -412,7 +407,7 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; + memcpy(ctx->iv, iv, 16); remLen = blockChainLen%16; ivLen = (( remLen > 0) ? remLen: 16 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index 788921bae7..2731398f73 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -45,7 +45,7 @@ typedef struct { uint32_t opMode; uint32_t channel; uint32_t swapType; - uint32_t *iv; + uint32_t iv[4]; unsigned char prv_iv[16]; uint32_t buf[8]; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 389bcb7659..72b8674ab9 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -37,19 +37,11 @@ static void mbedtls_zeroize( void *v, size_t n ) volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; } - - -static uint32_t au32MyAESIV[4] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}; - + extern volatile int g_AES_done; // Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) -static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); -static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); - static void swapInitVector(unsigned char iv[16]) { @@ -110,7 +102,7 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) //osDelay(300); } ctx->channel = i; - ctx->iv = au32MyAESIV; + memset(ctx->iv, 0, sizeof (ctx->iv)); /* Unlock protected registers */ SYS_UnlockReg(); @@ -205,6 +197,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, unsigned char* pIn; unsigned char* pOut; + MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; + MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); @@ -305,7 +299,7 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, while( length > 0 ) { ctx->opMode = AES_MODE_CBC; swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; + memcpy(ctx->iv, iv, 16); if( mode == MBEDTLS_AES_ENCRYPT ) { ctx->encDec = 1; @@ -423,7 +417,7 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; + memcpy(ctx->iv, iv, 16); remLen = blockChainLen%16; ivLen = (( remLen > 0) ? remLen: 16 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index 8b98e73ef0..5d5f90f0e3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -48,7 +48,7 @@ typedef struct { uint32_t opMode; uint32_t channel; uint32_t swapType; - uint32_t *iv; + uint32_t iv[4]; unsigned char prv_iv[16]; uint32_t buf[8]; } From 796d1c696b9c5958fbb580d48721beeb4d0b0c33 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 14 Sep 2017 14:26:54 +0800 Subject: [PATCH 036/118] Remove AES alter. dead code --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 13 ------ .../TARGET_NUC472/aes/aes_alt.c | 43 +++++-------------- .../TARGET_NUC472/aes/aes_alt.h | 3 -- 3 files changed, 10 insertions(+), 49 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index e11c9431a0..643b221ee2 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -61,19 +61,6 @@ static void swapInitVector(unsigned char iv[16]) } } -/* IRQHandler: To share CRYPTO_IRQHandler() with TRNG & other crypto IPs - For ex: - volatile void CRYPTO_IRQHandler() - { - ... - if (AES_GET_INT_FLAG()) { - g_AES_done = 1; - AES_CLR_INT_FLAG(); - } - ... - } -*/ - /* AES available channel 0~3 */ static unsigned char channel_flag[4]= {0x00,0x00,0x00,0x00}; // 0: idle, 1: busy diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 72b8674ab9..5afcea5b6d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -27,17 +27,20 @@ #if defined(MBEDTLS_AES_ALT) #include + #include "NUC472_442.h" #include "mbed_toolchain.h" #include "mbed_assert.h" + + /* Implementation that should never be optimized out by the compiler */ static void mbedtls_zeroize( void *v, size_t n ) { volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; } - + extern volatile int g_AES_done; // Must be a multiple of 16 bytes block size @@ -58,15 +61,8 @@ static void swapInitVector(unsigned char iv[16]) } } -//volatile void CRYPTO_IRQHandler() -//{ -// if (AES_GET_INT_FLAG()) { -// g_AES_done = 1; -// AES_CLR_INT_FLAG(); -// } -//} -// AES available channel 0~3 +/* AES available channel 0~3 */ static unsigned char channel_flag[4]= {0x00,0x00,0x00,0x00}; // 0: idle, 1: busy static int channel_alloc() { @@ -91,15 +87,11 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) { int i =-1; -// sw_mbedtls_aes_init(ctx); -// return; - memset( ctx, 0, sizeof( mbedtls_aes_context ) ); ctx->swapType = AES_IN_OUT_SWAP; while( (i = channel_alloc()) < 0 ) { mbed_assert_internal("No available AES channel", __FILE__, __LINE__); - //osDelay(300); } ctx->channel = i; memset(ctx->iv, 0, sizeof (ctx->iv)); @@ -121,14 +113,6 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ) if( ctx == NULL ) return; - /* Unlock protected registers */ -// SYS_UnlockReg(); -// CLK_DisableModuleClock(CRPT_MODULE); - /* Lock protected registers */ -// SYS_LockReg(); - -// NVIC_DisableIRQ(CRPT_IRQn); -// AES_DISABLE_INT(); channel_free(ctx->channel); mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); } @@ -231,11 +215,8 @@ void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, 16); - } /* @@ -245,12 +226,8 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, 16); - - } /* @@ -261,8 +238,6 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - ctx->opMode = AES_MODE_ECB; if( mode == MBEDTLS_AES_ENCRYPT ) mbedtls_aes_encrypt( ctx, input, output ); @@ -287,6 +262,7 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, unsigned char temp[16]; int length = len; int blockChainLen; + if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); @@ -316,7 +292,7 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, length -= blockChainLen; input += blockChainLen; output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain + if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain } @@ -340,11 +316,12 @@ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, int c; size_t n = *iv_off; unsigned char iv_tmp[16]; + if( mode == MBEDTLS_AES_DECRYPT ) { while( length-- ) { if( n == 0) mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode + else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode memcpy(iv_tmp, iv, n); mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); memcpy(iv, iv_tmp, n); @@ -436,7 +413,7 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, length -= blockChainLen; input += blockChainLen; output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain + if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain } *iv_off = remLen; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index 5d5f90f0e3..2731398f73 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -20,12 +20,9 @@ * * This file is part of mbed TLS (https://tls.mbed.org) */ - #ifndef MBEDTLS_AES_ALT_H #define MBEDTLS_AES_ALT_H -#include "mbedtls/aes.h" - #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation From 325c23e073d2714efe87eaae71eecd5607de89c0 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 14 Sep 2017 15:07:25 +0800 Subject: [PATCH 037/118] Fix AES DMA buffer cannot locate at ROM region --- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 12 ++++++++++-- .../TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 12 ++++++++++-- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 643b221ee2..81486a6c41 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -181,18 +181,26 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, unsigned char* pIn; unsigned char* pOut; + /* AES DMA buffer requires to be: + * 1) Word-aligned + * 2) Located in 0x2xxxxxxx range + */ MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; + MBED_ASSERT(((((uint32_t) au8OutputData) & 0x03) == 0) && ((((uint32_t) au8OutputData) & 0x20000000) == 0x20000000)); + MBED_ASSERT(((((uint32_t) au8InputData) & 0x03) == 0) && ((((uint32_t) au8InputData) & 0x20000000) == 0x20000000)); AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); - if( ((uint32_t)input) & 0x03 ) { + /* AES DMA buffer requirements same as above */ + if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = (unsigned char*)input; } - if( (((uint32_t)output) & 0x03) || (dataSize%4)) { // HW CFB output byte count must be multiple of word + /* AES DMA buffer requirements same as above */ + if ((((uint32_t) output) & 0x03) || ((((uint32_t) output) & 0x20000000) != 0x20000000)) { pOut = au8OutputData; } else { pOut = output; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 5afcea5b6d..5385874855 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -181,18 +181,26 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, unsigned char* pIn; unsigned char* pOut; + /* AES DMA buffer requires to be: + * 1) Word-aligned + * 2) Located in 0x2xxxxxxx range + */ MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; + MBED_ASSERT(((((uint32_t) au8OutputData) & 0x03) == 0) && ((((uint32_t) au8OutputData) & 0x20000000) == 0x20000000)); + MBED_ASSERT(((((uint32_t) au8InputData) & 0x03) == 0) && ((((uint32_t) au8InputData) & 0x20000000) == 0x20000000)); AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); - if( ((uint32_t)input) & 0x03 ) { + /* AES DMA buffer requirements same as above */ + if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = (unsigned char*)input; } - if( (((uint32_t)output) & 0x03) || (dataSize%4)) { // HW CFB output byte count must be multiple of word + /* AES DMA buffer requirements same as above */ + if ((((uint32_t) output) & 0x03) || ((((uint32_t) output) & 0x20000000) != 0x20000000)) { pOut = au8OutputData; } else { pOut = output; From cfbbd67a7389b1af80c8d7db5f713a8f2e97a621 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 14 Sep 2017 16:56:59 +0800 Subject: [PATCH 038/118] Support multiple contexts in AES alter. with context save & restore --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 47 ++++--------------- .../TARGET_NUC472/aes/aes_alt.c | 47 ++++--------------- 2 files changed, 18 insertions(+), 76 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 81486a6c41..b8923031d2 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -61,39 +61,14 @@ static void swapInitVector(unsigned char iv[16]) } } - -/* AES available channel 0~3 */ -static unsigned char channel_flag[4]= {0x00,0x00,0x00,0x00}; // 0: idle, 1: busy -static int channel_alloc() -{ - int i; - for(i=0; i< (int)sizeof(channel_flag); i++) { - if( channel_flag[i] == 0x00 ) { - channel_flag[i] = 0x01; - return i; - } - } - return(-1); -} - -static void channel_free(int i) -{ - if( i >=0 && i < (int)sizeof(channel_flag) ) - channel_flag[i] = 0x00; -} - - void mbedtls_aes_init( mbedtls_aes_context *ctx ) { - int i =-1; - memset( ctx, 0, sizeof( mbedtls_aes_context ) ); ctx->swapType = AES_IN_OUT_SWAP; - while( (i = channel_alloc()) < 0 ) { - mbed_assert_internal("No available AES channel", __FILE__, __LINE__); - } - ctx->channel = i; + /* We support multiple contexts with context save & restore and so needs just one + * H/W channel. Always use H/W channel #0. */ + ctx->channel = 0; memset(ctx->iv, 0, sizeof (ctx->iv)); /* Unlock protected registers */ @@ -108,12 +83,9 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) void mbedtls_aes_free( mbedtls_aes_context *ctx ) { - - if( ctx == NULL ) return; - channel_free(ctx->channel); mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); } @@ -125,7 +97,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, { unsigned int i; - switch( keybits ) { case 128: ctx->keySize = AES_KEY_SIZE_128; @@ -140,8 +111,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); } - - // key swap for( i = 0; i < ( keybits >> 5 ); i++ ) { ctx->buf[i] = (*(key+i*4) << 24) | @@ -149,8 +118,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, (*(key+2+i*4) << 8) | (*(key+3+i*4) ); } - AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); - return( 0 ); } @@ -163,13 +130,11 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, { int ret; - /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) goto exit; exit: - return( ret ); } @@ -192,6 +157,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); + AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { memcpy(au8InputData, input, dataSize); @@ -214,6 +180,11 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, if( pOut != output ) memcpy(output, au8OutputData, dataSize); + /* Save IV for next block */ + ctx->iv[0] = CRPT->AES_FDBCK[0]; + ctx->iv[1] = CRPT->AES_FDBCK[1]; + ctx->iv[2] = CRPT->AES_FDBCK[2]; + ctx->iv[3] = CRPT->AES_FDBCK[3]; } /* diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 5385874855..f71d65fb23 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -61,39 +61,14 @@ static void swapInitVector(unsigned char iv[16]) } } - -/* AES available channel 0~3 */ -static unsigned char channel_flag[4]= {0x00,0x00,0x00,0x00}; // 0: idle, 1: busy -static int channel_alloc() -{ - int i; - for(i=0; i< (int)sizeof(channel_flag); i++) { - if( channel_flag[i] == 0x00 ) { - channel_flag[i] = 0x01; - return i; - } - } - return(-1); -} - -static void channel_free(int i) -{ - if( i >=0 && i < (int)sizeof(channel_flag) ) - channel_flag[i] = 0x00; -} - - void mbedtls_aes_init( mbedtls_aes_context *ctx ) { - int i =-1; - memset( ctx, 0, sizeof( mbedtls_aes_context ) ); ctx->swapType = AES_IN_OUT_SWAP; - while( (i = channel_alloc()) < 0 ) { - mbed_assert_internal("No available AES channel", __FILE__, __LINE__); - } - ctx->channel = i; + /* We support multiple contexts with context save & restore and so needs just one + * H/W channel. Always use H/W channel #0. */ + ctx->channel = 0; memset(ctx->iv, 0, sizeof (ctx->iv)); /* Unlock protected registers */ @@ -108,12 +83,9 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) void mbedtls_aes_free( mbedtls_aes_context *ctx ) { - - if( ctx == NULL ) return; - channel_free(ctx->channel); mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); } @@ -125,7 +97,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, { unsigned int i; - switch( keybits ) { case 128: ctx->keySize = AES_KEY_SIZE_128; @@ -140,8 +111,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); } - - // key swap for( i = 0; i < ( keybits >> 5 ); i++ ) { ctx->buf[i] = (*(key+i*4) << 24) | @@ -149,8 +118,6 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, (*(key+2+i*4) << 8) | (*(key+3+i*4) ); } - AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); - return( 0 ); } @@ -163,13 +130,11 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, { int ret; - /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) goto exit; exit: - return( ret ); } @@ -192,6 +157,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); AES_SetInitVect(ctx->channel, ctx->iv); + AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { memcpy(au8InputData, input, dataSize); @@ -214,6 +180,11 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, if( pOut != output ) memcpy(output, au8OutputData, dataSize); + /* Save IV for next block */ + ctx->iv[0] = CRPT->AES_FDBCK0; + ctx->iv[1] = CRPT->AES_FDBCK1; + ctx->iv[2] = CRPT->AES_FDBCK2; + ctx->iv[3] = CRPT->AES_FDBCK3; } /* From aca8ae7fc4435598f264ca1726b455e0a7f7e4d5 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 19 Sep 2017 10:56:34 +0800 Subject: [PATCH 039/118] Refine AES alter. code --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 23 ++++++++----------- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 1 - .../TARGET_NUC472/aes/aes_alt.c | 23 ++++++++----------- .../TARGET_NUC472/aes/aes_alt.h | 1 - 4 files changed, 20 insertions(+), 28 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index b8923031d2..379bc8e36c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -66,10 +66,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) memset( ctx, 0, sizeof( mbedtls_aes_context ) ); ctx->swapType = AES_IN_OUT_SWAP; - /* We support multiple contexts with context save & restore and so needs just one - * H/W channel. Always use H/W channel #0. */ - ctx->channel = 0; - memset(ctx->iv, 0, sizeof (ctx->iv)); /* Unlock protected registers */ SYS_UnlockReg(); @@ -143,7 +139,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16], int dataSize) { - unsigned char* pIn; + const unsigned char* pIn; unsigned char* pOut; /* AES DMA buffer requires to be: @@ -155,15 +151,18 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, MBED_ASSERT(((((uint32_t) au8OutputData) & 0x03) == 0) && ((((uint32_t) au8OutputData) & 0x20000000) == 0x20000000)); MBED_ASSERT(((((uint32_t) au8InputData) & 0x03) == 0) && ((((uint32_t) au8InputData) & 0x20000000) == 0x20000000)); - AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); - AES_SetInitVect(ctx->channel, ctx->iv); - AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); + /* We support multiple contexts with context save & restore and so needs just one + * H/W channel. Always use H/W channel #0. */ + + AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); + AES_SetInitVect(0, ctx->iv); + AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { - pIn = (unsigned char*)input; + pIn = input; } /* AES DMA buffer requirements same as above */ if ((((uint32_t) output) & 0x03) || ((((uint32_t) output) & 0x20000000) != 0x20000000)) { @@ -172,10 +171,10 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, pOut = output; } - AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); + AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); g_AES_done = 0; - AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT); + AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); if( pOut != output ) memcpy(output, au8OutputData, dataSize); @@ -259,13 +258,11 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, if( mode == MBEDTLS_AES_ENCRYPT ) { ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() memcpy( iv, output+blockChainLen-16, 16 ); } else { memcpy( temp, input+blockChainLen-16, 16 ); ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() memcpy( iv, temp, 16 ); } length -= blockChainLen; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index 2731398f73..da9ee17316 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -43,7 +43,6 @@ typedef struct { uint32_t keySize; uint32_t encDec; uint32_t opMode; - uint32_t channel; uint32_t swapType; uint32_t iv[4]; unsigned char prv_iv[16]; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index f71d65fb23..260296b509 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -66,10 +66,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) memset( ctx, 0, sizeof( mbedtls_aes_context ) ); ctx->swapType = AES_IN_OUT_SWAP; - /* We support multiple contexts with context save & restore and so needs just one - * H/W channel. Always use H/W channel #0. */ - ctx->channel = 0; - memset(ctx->iv, 0, sizeof (ctx->iv)); /* Unlock protected registers */ SYS_UnlockReg(); @@ -143,7 +139,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16], int dataSize) { - unsigned char* pIn; + const unsigned char* pIn; unsigned char* pOut; /* AES DMA buffer requires to be: @@ -155,15 +151,18 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, MBED_ASSERT(((((uint32_t) au8OutputData) & 0x03) == 0) && ((((uint32_t) au8OutputData) & 0x20000000) == 0x20000000)); MBED_ASSERT(((((uint32_t) au8InputData) & 0x03) == 0) && ((((uint32_t) au8InputData) & 0x20000000) == 0x20000000)); - AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); - AES_SetInitVect(ctx->channel, ctx->iv); - AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); + /* We support multiple contexts with context save & restore and so needs just one + * H/W channel. Always use H/W channel #0. */ + + AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); + AES_SetInitVect(0, ctx->iv); + AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { - pIn = (unsigned char*)input; + pIn = input; } /* AES DMA buffer requirements same as above */ if ((((uint32_t) output) & 0x03) || ((((uint32_t) output) & 0x20000000) != 0x20000000)) { @@ -172,10 +171,10 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, pOut = output; } - AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); + AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); g_AES_done = 0; - AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT); + AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); if( pOut != output ) memcpy(output, au8OutputData, dataSize); @@ -259,13 +258,11 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, if( mode == MBEDTLS_AES_ENCRYPT ) { ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() memcpy( iv, output+blockChainLen-16, 16 ); } else { memcpy( temp, input+blockChainLen-16, 16 ); ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() memcpy( iv, temp, 16 ); } length -= blockChainLen; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index 2731398f73..da9ee17316 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -43,7 +43,6 @@ typedef struct { uint32_t keySize; uint32_t encDec; uint32_t opMode; - uint32_t channel; uint32_t swapType; uint32_t iv[4]; unsigned char prv_iv[16]; From 2642be273a3c7435148e0d9573229f59ba70a50d Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 19 Sep 2017 13:32:54 +0800 Subject: [PATCH 040/118] Refine AES alter. DMA buffer code --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 45 +++++++++++++------ .../TARGET_NUC472/aes/aes_alt.c | 45 +++++++++++++------ 2 files changed, 62 insertions(+), 28 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 379bc8e36c..c81de01619 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -27,10 +27,12 @@ #if defined(MBEDTLS_AES_ALT) #include +#include #include "M480.h" #include "mbed_toolchain.h" #include "mbed_assert.h" +#include "mbed_error.h" @@ -61,6 +63,17 @@ static void swapInitVector(unsigned char iv[16]) } } +/* Check if buffer can be used for AES DMA. It requires to be: + * 1) Word-aligned + * 2) Located in 0x2xxxxxxx region + */ +static bool aes_dma_buff_compat(const void *buff) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && ((buff_ & 0x20000000) == 0x20000000)); +} + void mbedtls_aes_init( mbedtls_aes_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_aes_context ) ); @@ -144,12 +157,13 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* AES DMA buffer requires to be: * 1) Word-aligned - * 2) Located in 0x2xxxxxxx range + * 2) Located in 0x2xxxxxxx region */ MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; - MBED_ASSERT(((((uint32_t) au8OutputData) & 0x03) == 0) && ((((uint32_t) au8OutputData) & 0x20000000) == 0x20000000)); - MBED_ASSERT(((((uint32_t) au8InputData) & 0x03) == 0) && ((((uint32_t) au8InputData) & 0x20000000) == 0x20000000)); + if ((! aes_dma_buff_compat(au8OutputData)) || (! aes_dma_buff_compat(au8InputData))) { + error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x2xxxxxxx region."); + } /* We support multiple contexts with context save & restore and so needs just one * H/W channel. Always use H/W channel #0. */ @@ -158,14 +172,17 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ - if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { + if (! aes_dma_buff_compat(input)) { + if (dataSize > MAX_DMA_CHAIN_SIZE) { + error("Internal AES alter. error. DMA buffer is too small."); + } memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = input; } /* AES DMA buffer requirements same as above */ - if ((((uint32_t) output) & 0x03) || ((((uint32_t) output) & 0x20000000) != 0x20000000)) { + if (! aes_dma_buff_compat(output)) { pOut = au8OutputData; } else { pOut = output; @@ -177,8 +194,13 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); - if( pOut != output ) memcpy(output, au8OutputData, dataSize); - + if( pOut != output ) { + if (dataSize > MAX_DMA_CHAIN_SIZE) { + error("Internal AES alter. error. DMA buffer is too small."); + } + memcpy(output, au8OutputData, dataSize); + } + /* Save IV for next block */ ctx->iv[0] = CRPT->AES_FDBCK[0]; ctx->iv[1] = CRPT->AES_FDBCK[1]; @@ -244,13 +266,10 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else { - blockChainLen = length; - } while( length > 0 ) { + blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; + ctx->opMode = AES_MODE_CBC; swapInitVector(iv); // iv SWAP memcpy(ctx->iv, iv, 16); @@ -268,8 +287,6 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, length -= blockChainLen; input += blockChainLen; output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } return( 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 260296b509..bc1ffe5c58 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -27,10 +27,12 @@ #if defined(MBEDTLS_AES_ALT) #include +#include #include "NUC472_442.h" #include "mbed_toolchain.h" #include "mbed_assert.h" +#include "mbed_error.h" @@ -61,6 +63,17 @@ static void swapInitVector(unsigned char iv[16]) } } +/* Check if buffer can be used for AES DMA. It requires to be: + * 1) Word-aligned + * 2) Located in 0x2xxxxxxx region + */ +static bool aes_dma_buff_compat(const void *buff) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && ((buff_ & 0x20000000) == 0x20000000)); +} + void mbedtls_aes_init( mbedtls_aes_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_aes_context ) ); @@ -144,12 +157,13 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* AES DMA buffer requires to be: * 1) Word-aligned - * 2) Located in 0x2xxxxxxx range + * 2) Located in 0x2xxxxxxx region */ MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; - MBED_ASSERT(((((uint32_t) au8OutputData) & 0x03) == 0) && ((((uint32_t) au8OutputData) & 0x20000000) == 0x20000000)); - MBED_ASSERT(((((uint32_t) au8InputData) & 0x03) == 0) && ((((uint32_t) au8InputData) & 0x20000000) == 0x20000000)); + if ((! aes_dma_buff_compat(au8OutputData)) || (! aes_dma_buff_compat(au8InputData))) { + error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x2xxxxxxx region."); + } /* We support multiple contexts with context save & restore and so needs just one * H/W channel. Always use H/W channel #0. */ @@ -158,14 +172,17 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ - if ((((uint32_t) input) & 0x03) || ((((uint32_t) input) & 0x20000000) != 0x20000000)) { + if (! aes_dma_buff_compat(input)) { + if (dataSize > MAX_DMA_CHAIN_SIZE) { + error("Internal AES alter. error. DMA buffer is too small."); + } memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = input; } /* AES DMA buffer requirements same as above */ - if ((((uint32_t) output) & 0x03) || ((((uint32_t) output) & 0x20000000) != 0x20000000)) { + if (! aes_dma_buff_compat(output)) { pOut = au8OutputData; } else { pOut = output; @@ -177,8 +194,13 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); - if( pOut != output ) memcpy(output, au8OutputData, dataSize); - + if( pOut != output ) { + if (dataSize > MAX_DMA_CHAIN_SIZE) { + error("Internal AES alter. error. DMA buffer is too small."); + } + memcpy(output, au8OutputData, dataSize); + } + /* Save IV for next block */ ctx->iv[0] = CRPT->AES_FDBCK0; ctx->iv[1] = CRPT->AES_FDBCK1; @@ -244,13 +266,10 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else { - blockChainLen = length; - } while( length > 0 ) { + blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; + ctx->opMode = AES_MODE_CBC; swapInitVector(iv); // iv SWAP memcpy(ctx->iv, iv, 16); @@ -268,8 +287,6 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, length -= blockChainLen; input += blockChainLen; output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } return( 0 ); From 3aae8ad4a332519c6cfa8b2ccef2b8dd550541b5 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 20 Sep 2017 10:17:12 +0800 Subject: [PATCH 041/118] Rework AES alter. CFB128 1. Fix bug on non-block aligned data size 2. More concise --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 179 ++++++++---------- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 1 - .../TARGET_NUC472/aes/aes_alt.c | 179 ++++++++---------- .../TARGET_NUC472/aes/aes_alt.h | 1 - 4 files changed, 152 insertions(+), 208 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index c81de01619..3745bd1a16 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -294,122 +294,95 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) -/* - * AES-CFB128 buffer encryption/decryption - */ -/* Support partial block encryption/decryption */ -static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) -{ - int c; - size_t n = *iv_off; - unsigned char iv_tmp[16]; - - if( mode == MBEDTLS_AES_DECRYPT ) { - while( length-- ) { - if( n == 0) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - c = *input++; - *output++ = (unsigned char)( c ^ iv[n] ); - iv[n] = (unsigned char) c; - - n = ( n + 1 ) & 0x0F; - } - } else { - while( length-- ) { - if( n == 0 ) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); - - n = ( n + 1 ) & 0x0F; - } - } - - *iv_off = n; - - return( 0 ); -} - int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, int mode, - size_t len, + size_t length, size_t *iv_off, unsigned char iv[16], const unsigned char *input, unsigned char *output ) { + int c; size_t n = *iv_off; - unsigned char temp[16]; - int length=len; - int blockChainLen; - int remLen=0; - int ivLen; + /* First incomplete block*/ + if (n % 16) { + size_t rmn = 16 - n; + rmn = (rmn > length) ? length : rmn; + + while( rmn -- ) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } - // proceed: start with partial block by ECB mode first - if( n !=0 ) { - __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n, iv_off, iv, input, output); - input += (16 - n); - output += (16 - n); - length -= (16 - n); - } - - // For address or byte count non-word alignment, go through reserved DMA buffer. - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { // Must reserved DMA buffer for each block - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else if(length%4) { // Need reserved DMA buffer once for last chain - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); - } else { // Not need reserved DMA buffer - blockChainLen = length; - } - - // proceed: start with block alignment - while( length > 0 ) { - - ctx->opMode = AES_MODE_CFB; - - swapInitVector(iv); // iv SWAP - - memcpy(ctx->iv, iv, 16); - remLen = blockChainLen%16; - ivLen = (( remLen > 0) ? remLen: 16 ); - - if( mode == MBEDTLS_AES_DECRYPT ) { - memcpy(temp, input+blockChainLen - ivLen, ivLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16, 16); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy(iv,temp, ivLen); - } else { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16, 16); - memcpy(iv,output+blockChainLen-ivLen,ivLen); + n = ( n + 1 ) & 0x0F; + length --; } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain } - *iv_off = remLen; + /* Middle complete block(s) */ + size_t block_chain_len = length / 16 * 16; + + if (block_chain_len) { + ctx->opMode = AES_MODE_CFB; + if (mode == MBEDTLS_AES_DECRYPT) { + ctx->encDec = 0; + } + else { + ctx->encDec = 1; + } + + while (block_chain_len) { + size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; + + memcpy(ctx->iv, iv, 16); + swapInitVector(ctx->iv); // iv SWAP + + __nvt_aes_crypt(ctx, input, output, block_chain_len2); + + input += block_chain_len2; + output += block_chain_len2; + length -= block_chain_len2; + + /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output + * for iv of next block cipher. */ + memcpy(iv, ctx->iv, 16); + swapInitVector(iv); + + block_chain_len -= block_chain_len2; + } + } + + /* Last incomplete block */ + size_t last_block_len = length; + + if (last_block_len) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + size_t rmn = last_block_len; + rmn = (rmn > length) ? length : rmn; + + while (rmn --) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } + + n = ( n + 1 ) & 0x0F; + length --; + } + } + + *iv_off = n; return( 0 ); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index da9ee17316..4a91ba399d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -45,7 +45,6 @@ typedef struct { uint32_t opMode; uint32_t swapType; uint32_t iv[4]; - unsigned char prv_iv[16]; uint32_t buf[8]; } mbedtls_aes_context; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index bc1ffe5c58..a0766b3c97 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -294,122 +294,95 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) -/* - * AES-CFB128 buffer encryption/decryption - */ -/* Support partial block encryption/decryption */ -static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) -{ - int c; - size_t n = *iv_off; - unsigned char iv_tmp[16]; - - if( mode == MBEDTLS_AES_DECRYPT ) { - while( length-- ) { - if( n == 0) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - c = *input++; - *output++ = (unsigned char)( c ^ iv[n] ); - iv[n] = (unsigned char) c; - - n = ( n + 1 ) & 0x0F; - } - } else { - while( length-- ) { - if( n == 0 ) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) { // For previous cryption is CFB mode - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); - - n = ( n + 1 ) & 0x0F; - } - } - - *iv_off = n; - - return( 0 ); -} - int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, int mode, - size_t len, + size_t length, size_t *iv_off, unsigned char iv[16], const unsigned char *input, unsigned char *output ) { + int c; size_t n = *iv_off; - unsigned char temp[16]; - int length=len; - int blockChainLen; - int remLen=0; - int ivLen; + /* First incomplete block*/ + if (n % 16) { + size_t rmn = 16 - n; + rmn = (rmn > length) ? length : rmn; + + while( rmn -- ) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } - // proceed: start with partial block by ECB mode first - if( n !=0 ) { - __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n, iv_off, iv, input, output); - input += (16 - n); - output += (16 - n); - length -= (16 - n); - } - - // For address or byte count non-word alignment, go through reserved DMA buffer. - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) { // Must reserved DMA buffer for each block - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else if(length%4) { // Need reserved DMA buffer once for last chain - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); - } else { // Not need reserved DMA buffer - blockChainLen = length; - } - - // proceed: start with block alignment - while( length > 0 ) { - - ctx->opMode = AES_MODE_CFB; - - swapInitVector(iv); // iv SWAP - - memcpy(ctx->iv, iv, 16); - remLen = blockChainLen%16; - ivLen = (( remLen > 0) ? remLen: 16 ); - - if( mode == MBEDTLS_AES_DECRYPT ) { - memcpy(temp, input+blockChainLen - ivLen, ivLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16, 16); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy(iv,temp, ivLen); - } else { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16, 16); - memcpy(iv,output+blockChainLen-ivLen,ivLen); + n = ( n + 1 ) & 0x0F; + length --; } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain } - *iv_off = remLen; + /* Middle complete block(s) */ + size_t block_chain_len = length / 16 * 16; + + if (block_chain_len) { + ctx->opMode = AES_MODE_CFB; + if (mode == MBEDTLS_AES_DECRYPT) { + ctx->encDec = 0; + } + else { + ctx->encDec = 1; + } + + while (block_chain_len) { + size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; + + memcpy(ctx->iv, iv, 16); + swapInitVector(ctx->iv); // iv SWAP + + __nvt_aes_crypt(ctx, input, output, block_chain_len2); + + input += block_chain_len2; + output += block_chain_len2; + length -= block_chain_len2; + + /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output + * for iv of next block cipher. */ + memcpy(iv, ctx->iv, 16); + swapInitVector(iv); + + block_chain_len -= block_chain_len2; + } + } + + /* Last incomplete block */ + size_t last_block_len = length; + + if (last_block_len) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + size_t rmn = last_block_len; + rmn = (rmn > length) ? length : rmn; + + while (rmn --) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } + + n = ( n + 1 ) & 0x0F; + length --; + } + } + + *iv_off = n; return( 0 ); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index da9ee17316..4a91ba399d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -45,7 +45,6 @@ typedef struct { uint32_t opMode; uint32_t swapType; uint32_t iv[4]; - unsigned char prv_iv[16]; uint32_t buf[8]; } mbedtls_aes_context; From 743930978c27cc8e883070d172ce6a1765bac2d2 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 20 Sep 2017 13:11:19 +0800 Subject: [PATCH 042/118] Refine AES alter. code with IV endianness --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 39 ++++++++----------- .../TARGET_NUC472/aes/aes_alt.c | 39 ++++++++----------- 2 files changed, 34 insertions(+), 44 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 3745bd1a16..46d9c944bb 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -33,6 +33,7 @@ #include "mbed_toolchain.h" #include "mbed_assert.h" #include "mbed_error.h" +#include "nu_bitutil.h" @@ -48,21 +49,6 @@ extern volatile int g_AES_done; // Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) -static void swapInitVector(unsigned char iv[16]) -{ - unsigned int* piv; - int i; - // iv SWAP - piv = (unsigned int*)iv; - for( i=0; i< 4; i++) { - *piv = (((*piv) & 0x000000FF) << 24) | - (((*piv) & 0x0000FF00) << 8) | - (((*piv) & 0x00FF0000) >> 8) | - (((*piv) & 0xFF000000) >> 24); - piv++; - } -} - /* Check if buffer can be used for AES DMA. It requires to be: * 1) Word-aligned * 2) Located in 0x2xxxxxxx region @@ -271,8 +257,11 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; ctx->opMode = AES_MODE_CBC; - swapInitVector(iv); // iv SWAP - memcpy(ctx->iv, iv, 16); + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); if( mode == MBEDTLS_AES_ENCRYPT ) { ctx->encDec = 1; @@ -340,9 +329,12 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, while (block_chain_len) { size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; - memcpy(ctx->iv, iv, 16); - swapInitVector(ctx->iv); // iv SWAP - + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + __nvt_aes_crypt(ctx, input, output, block_chain_len2); input += block_chain_len2; @@ -351,8 +343,11 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output * for iv of next block cipher. */ - memcpy(iv, ctx->iv, 16); - swapInitVector(iv); + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); block_chain_len -= block_chain_len2; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index a0766b3c97..b3443872de 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -33,6 +33,7 @@ #include "mbed_toolchain.h" #include "mbed_assert.h" #include "mbed_error.h" +#include "nu_bitutil.h" @@ -48,21 +49,6 @@ extern volatile int g_AES_done; // Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) -static void swapInitVector(unsigned char iv[16]) -{ - unsigned int* piv; - int i; - // iv SWAP - piv = (unsigned int*)iv; - for( i=0; i< 4; i++) { - *piv = (((*piv) & 0x000000FF) << 24) | - (((*piv) & 0x0000FF00) << 8) | - (((*piv) & 0x00FF0000) >> 8) | - (((*piv) & 0xFF000000) >> 24); - piv++; - } -} - /* Check if buffer can be used for AES DMA. It requires to be: * 1) Word-aligned * 2) Located in 0x2xxxxxxx region @@ -271,8 +257,11 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; ctx->opMode = AES_MODE_CBC; - swapInitVector(iv); // iv SWAP - memcpy(ctx->iv, iv, 16); + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); if( mode == MBEDTLS_AES_ENCRYPT ) { ctx->encDec = 1; @@ -340,9 +329,12 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, while (block_chain_len) { size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; - memcpy(ctx->iv, iv, 16); - swapInitVector(ctx->iv); // iv SWAP - + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + __nvt_aes_crypt(ctx, input, output, block_chain_len2); input += block_chain_len2; @@ -351,8 +343,11 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output * for iv of next block cipher. */ - memcpy(iv, ctx->iv, 16); - swapInitVector(iv); + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); block_chain_len -= block_chain_len2; } From ce2e1ea1699dfa7c37f1e92d831757aea3264f6d Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 20 Sep 2017 13:25:34 +0800 Subject: [PATCH 043/118] Add comment for AES alter. context --- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 12 ++++++------ .../TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index 4a91ba399d..648c9988db 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -40,12 +40,12 @@ extern "C" { * generating an extra round key */ typedef struct { - uint32_t keySize; - uint32_t encDec; - uint32_t opMode; - uint32_t swapType; - uint32_t iv[4]; - uint32_t buf[8]; + uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ + uint32_t encDec; /* 0: decrypt, 1: encrypt */ + uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ + uint32_t swapType; /* Input/Output data endianness */ + uint32_t iv[4]; /* IV for next block cipher */ + uint32_t buf[8]; /* Cipher key */ } mbedtls_aes_context; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index 4a91ba399d..648c9988db 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -40,12 +40,12 @@ extern "C" { * generating an extra round key */ typedef struct { - uint32_t keySize; - uint32_t encDec; - uint32_t opMode; - uint32_t swapType; - uint32_t iv[4]; - uint32_t buf[8]; + uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ + uint32_t encDec; /* 0: decrypt, 1: encrypt */ + uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ + uint32_t swapType; /* Input/Output data endianness */ + uint32_t iv[4]; /* IV for next block cipher */ + uint32_t buf[8]; /* Cipher key */ } mbedtls_aes_context; From f4e0228ffee62c95d431c38b6a2442de2e3313f7 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Sep 2017 13:50:34 +0800 Subject: [PATCH 044/118] Add comment for DES alter. context --- .../targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h | 8 +++++--- .../targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h index 3165ba81d0..161808b978 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h @@ -33,9 +33,11 @@ extern "C" { * \brief DES context structure */ typedef struct { - int enc; /*!< 0: dec, 1: enc */ - uint16_t keyopt; - uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ + int enc; /* 0: dec, 1: enc */ + uint16_t keyopt; /* 1: All three keys are independent. + * 2: K1 and K2 are independent, and K3 = K1. + * 3: All three keys are identical, i.e. K1 = K2 = K3. */ + uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /* 3DES keys */ } mbedtls_des_context; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h index 054a9f0b78..a3df9777e7 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h @@ -34,9 +34,11 @@ extern "C" { * \brief DES context structure */ typedef struct { - int enc; /*!< 0: dec, 1: enc */ - uint16_t keyopt; - uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ + int enc; /* 0: dec, 1: enc */ + uint16_t keyopt; /* 1: All three keys are independent. + * 2: K1 and K2 are independent, and K3 = K1. + * 3: All three keys are identical, i.e. K1 = K2 = K3. */ + uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /* 3DES keys */ } mbedtls_des_context; From 90eb34b4deb21f3865e566ec96424b83743f7be7 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Sep 2017 14:11:04 +0800 Subject: [PATCH 045/118] Refine DES alter. code --- .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 2 +- .../mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index cb7effa7bd..b19716ba28 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -340,7 +340,7 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; - while (rmn) { + while (rmn > 0) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; uint32_t ivh, ivl; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index cb7effa7bd..b19716ba28 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -340,7 +340,7 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; - while (rmn) { + while (rmn > 0) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; uint32_t ivh, ivl; From 60cbdac3835ca59da36b60ff3582a9373f41e58a Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Sep 2017 14:45:26 +0800 Subject: [PATCH 046/118] Remove redundant S/W DES code This S/W DES code was to test DES H/W port before. --- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.h | 2 - .../TARGET_M480/des/des_alt_sw.c | 766 ------------------ .../TARGET_M480/des/des_alt_sw.h | 275 ------- .../TARGET_NUC472/des/des_alt.h | 1 - .../TARGET_NUC472/des/des_alt_sw.c | 766 ------------------ .../TARGET_NUC472/des/des_alt_sw.h | 277 ------- 6 files changed, 2087 deletions(-) delete mode 100644 features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c delete mode 100644 features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h delete mode 100644 features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c delete mode 100644 features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h index 161808b978..cf4e6908aa 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h @@ -22,8 +22,6 @@ #include #include -#include "des.h" -#include "des_alt_sw.h" #ifdef __cplusplus extern "C" { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c deleted file mode 100644 index d3968b464b..0000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c +++ /dev/null @@ -1,766 +0,0 @@ -/* - * FIPS-46-3 compliant Triple-DES implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -/* - * DES, on which TDES is based, was originally designed by Horst Feistel - * at IBM in 1974, and was adopted as a standard by NIST (formerly NBS). - * - * http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf - */ - -#include "mbedtls/des.h" - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include - -/* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) -{ - volatile unsigned char *p = (unsigned char*)v; - while( n-- ) *p++ = 0; -} - -/* - * 32-bit integer manipulation macros (big endian) - */ -#ifndef GET_UINT32_BE -#define GET_UINT32_BE(n,b,i) \ -{ \ - (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ - | ( (uint32_t) (b)[(i) + 1] << 16 ) \ - | ( (uint32_t) (b)[(i) + 2] << 8 ) \ - | ( (uint32_t) (b)[(i) + 3] ); \ -} -#endif - -#ifndef PUT_UINT32_BE -#define PUT_UINT32_BE(n,b,i) \ -{ \ - (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ - (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ - (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ - (b)[(i) + 3] = (unsigned char) ( (n) ); \ -} -#endif - -/* - * Expanded DES S-boxes - */ -static const uint32_t SB1[64] = { - 0x01010400, 0x00000000, 0x00010000, 0x01010404, - 0x01010004, 0x00010404, 0x00000004, 0x00010000, - 0x00000400, 0x01010400, 0x01010404, 0x00000400, - 0x01000404, 0x01010004, 0x01000000, 0x00000004, - 0x00000404, 0x01000400, 0x01000400, 0x00010400, - 0x00010400, 0x01010000, 0x01010000, 0x01000404, - 0x00010004, 0x01000004, 0x01000004, 0x00010004, - 0x00000000, 0x00000404, 0x00010404, 0x01000000, - 0x00010000, 0x01010404, 0x00000004, 0x01010000, - 0x01010400, 0x01000000, 0x01000000, 0x00000400, - 0x01010004, 0x00010000, 0x00010400, 0x01000004, - 0x00000400, 0x00000004, 0x01000404, 0x00010404, - 0x01010404, 0x00010004, 0x01010000, 0x01000404, - 0x01000004, 0x00000404, 0x00010404, 0x01010400, - 0x00000404, 0x01000400, 0x01000400, 0x00000000, - 0x00010004, 0x00010400, 0x00000000, 0x01010004 -}; - -static const uint32_t SB2[64] = { - 0x80108020, 0x80008000, 0x00008000, 0x00108020, - 0x00100000, 0x00000020, 0x80100020, 0x80008020, - 0x80000020, 0x80108020, 0x80108000, 0x80000000, - 0x80008000, 0x00100000, 0x00000020, 0x80100020, - 0x00108000, 0x00100020, 0x80008020, 0x00000000, - 0x80000000, 0x00008000, 0x00108020, 0x80100000, - 0x00100020, 0x80000020, 0x00000000, 0x00108000, - 0x00008020, 0x80108000, 0x80100000, 0x00008020, - 0x00000000, 0x00108020, 0x80100020, 0x00100000, - 0x80008020, 0x80100000, 0x80108000, 0x00008000, - 0x80100000, 0x80008000, 0x00000020, 0x80108020, - 0x00108020, 0x00000020, 0x00008000, 0x80000000, - 0x00008020, 0x80108000, 0x00100000, 0x80000020, - 0x00100020, 0x80008020, 0x80000020, 0x00100020, - 0x00108000, 0x00000000, 0x80008000, 0x00008020, - 0x80000000, 0x80100020, 0x80108020, 0x00108000 -}; - -static const uint32_t SB3[64] = { - 0x00000208, 0x08020200, 0x00000000, 0x08020008, - 0x08000200, 0x00000000, 0x00020208, 0x08000200, - 0x00020008, 0x08000008, 0x08000008, 0x00020000, - 0x08020208, 0x00020008, 0x08020000, 0x00000208, - 0x08000000, 0x00000008, 0x08020200, 0x00000200, - 0x00020200, 0x08020000, 0x08020008, 0x00020208, - 0x08000208, 0x00020200, 0x00020000, 0x08000208, - 0x00000008, 0x08020208, 0x00000200, 0x08000000, - 0x08020200, 0x08000000, 0x00020008, 0x00000208, - 0x00020000, 0x08020200, 0x08000200, 0x00000000, - 0x00000200, 0x00020008, 0x08020208, 0x08000200, - 0x08000008, 0x00000200, 0x00000000, 0x08020008, - 0x08000208, 0x00020000, 0x08000000, 0x08020208, - 0x00000008, 0x00020208, 0x00020200, 0x08000008, - 0x08020000, 0x08000208, 0x00000208, 0x08020000, - 0x00020208, 0x00000008, 0x08020008, 0x00020200 -}; - -static const uint32_t SB4[64] = { - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802080, 0x00800081, 0x00800001, 0x00002001, - 0x00000000, 0x00802000, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00800080, 0x00800001, - 0x00000001, 0x00002000, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002001, 0x00002080, - 0x00800081, 0x00000001, 0x00002080, 0x00800080, - 0x00002000, 0x00802080, 0x00802081, 0x00000081, - 0x00800080, 0x00800001, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00000000, 0x00802000, - 0x00002080, 0x00800080, 0x00800081, 0x00000001, - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802081, 0x00000081, 0x00000001, 0x00002000, - 0x00800001, 0x00002001, 0x00802080, 0x00800081, - 0x00002001, 0x00002080, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002000, 0x00802080 -}; - -static const uint32_t SB5[64] = { - 0x00000100, 0x02080100, 0x02080000, 0x42000100, - 0x00080000, 0x00000100, 0x40000000, 0x02080000, - 0x40080100, 0x00080000, 0x02000100, 0x40080100, - 0x42000100, 0x42080000, 0x00080100, 0x40000000, - 0x02000000, 0x40080000, 0x40080000, 0x00000000, - 0x40000100, 0x42080100, 0x42080100, 0x02000100, - 0x42080000, 0x40000100, 0x00000000, 0x42000000, - 0x02080100, 0x02000000, 0x42000000, 0x00080100, - 0x00080000, 0x42000100, 0x00000100, 0x02000000, - 0x40000000, 0x02080000, 0x42000100, 0x40080100, - 0x02000100, 0x40000000, 0x42080000, 0x02080100, - 0x40080100, 0x00000100, 0x02000000, 0x42080000, - 0x42080100, 0x00080100, 0x42000000, 0x42080100, - 0x02080000, 0x00000000, 0x40080000, 0x42000000, - 0x00080100, 0x02000100, 0x40000100, 0x00080000, - 0x00000000, 0x40080000, 0x02080100, 0x40000100 -}; - -static const uint32_t SB6[64] = { - 0x20000010, 0x20400000, 0x00004000, 0x20404010, - 0x20400000, 0x00000010, 0x20404010, 0x00400000, - 0x20004000, 0x00404010, 0x00400000, 0x20000010, - 0x00400010, 0x20004000, 0x20000000, 0x00004010, - 0x00000000, 0x00400010, 0x20004010, 0x00004000, - 0x00404000, 0x20004010, 0x00000010, 0x20400010, - 0x20400010, 0x00000000, 0x00404010, 0x20404000, - 0x00004010, 0x00404000, 0x20404000, 0x20000000, - 0x20004000, 0x00000010, 0x20400010, 0x00404000, - 0x20404010, 0x00400000, 0x00004010, 0x20000010, - 0x00400000, 0x20004000, 0x20000000, 0x00004010, - 0x20000010, 0x20404010, 0x00404000, 0x20400000, - 0x00404010, 0x20404000, 0x00000000, 0x20400010, - 0x00000010, 0x00004000, 0x20400000, 0x00404010, - 0x00004000, 0x00400010, 0x20004010, 0x00000000, - 0x20404000, 0x20000000, 0x00400010, 0x20004010 -}; - -static const uint32_t SB7[64] = { - 0x00200000, 0x04200002, 0x04000802, 0x00000000, - 0x00000800, 0x04000802, 0x00200802, 0x04200800, - 0x04200802, 0x00200000, 0x00000000, 0x04000002, - 0x00000002, 0x04000000, 0x04200002, 0x00000802, - 0x04000800, 0x00200802, 0x00200002, 0x04000800, - 0x04000002, 0x04200000, 0x04200800, 0x00200002, - 0x04200000, 0x00000800, 0x00000802, 0x04200802, - 0x00200800, 0x00000002, 0x04000000, 0x00200800, - 0x04000000, 0x00200800, 0x00200000, 0x04000802, - 0x04000802, 0x04200002, 0x04200002, 0x00000002, - 0x00200002, 0x04000000, 0x04000800, 0x00200000, - 0x04200800, 0x00000802, 0x00200802, 0x04200800, - 0x00000802, 0x04000002, 0x04200802, 0x04200000, - 0x00200800, 0x00000000, 0x00000002, 0x04200802, - 0x00000000, 0x00200802, 0x04200000, 0x00000800, - 0x04000002, 0x04000800, 0x00000800, 0x00200002 -}; - -static const uint32_t SB8[64] = { - 0x10001040, 0x00001000, 0x00040000, 0x10041040, - 0x10000000, 0x10001040, 0x00000040, 0x10000000, - 0x00040040, 0x10040000, 0x10041040, 0x00041000, - 0x10041000, 0x00041040, 0x00001000, 0x00000040, - 0x10040000, 0x10000040, 0x10001000, 0x00001040, - 0x00041000, 0x00040040, 0x10040040, 0x10041000, - 0x00001040, 0x00000000, 0x00000000, 0x10040040, - 0x10000040, 0x10001000, 0x00041040, 0x00040000, - 0x00041040, 0x00040000, 0x10041000, 0x00001000, - 0x00000040, 0x10040040, 0x00001000, 0x00041040, - 0x10001000, 0x00000040, 0x10000040, 0x10040000, - 0x10040040, 0x10000000, 0x00040000, 0x10001040, - 0x00000000, 0x10041040, 0x00040040, 0x10000040, - 0x10040000, 0x10001000, 0x10001040, 0x00000000, - 0x10041040, 0x00041000, 0x00041000, 0x00001040, - 0x00001040, 0x00040040, 0x10000000, 0x10041000 -}; - -/* - * PC1: left and right halves bit-swap - */ -static const uint32_t LHs[16] = { - 0x00000000, 0x00000001, 0x00000100, 0x00000101, - 0x00010000, 0x00010001, 0x00010100, 0x00010101, - 0x01000000, 0x01000001, 0x01000100, 0x01000101, - 0x01010000, 0x01010001, 0x01010100, 0x01010101 -}; - -static const uint32_t RHs[16] = { - 0x00000000, 0x01000000, 0x00010000, 0x01010000, - 0x00000100, 0x01000100, 0x00010100, 0x01010100, - 0x00000001, 0x01000001, 0x00010001, 0x01010001, - 0x00000101, 0x01000101, 0x00010101, 0x01010101, -}; - -/* - * Initial Permutation macro - */ -#define DES_IP(X,Y) \ -{ \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T; \ - X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF; \ -} - -/* - * Final Permutation macro - */ -#define DES_FP(X,Y) \ -{ \ - X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T; \ - Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF; \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ -} - -/* - * DES round macro - */ -#define DES_ROUND(X,Y) \ -{ \ - T = *SK++ ^ X; \ - Y ^= SB8[ (T ) & 0x3F ] ^ \ - SB6[ (T >> 8) & 0x3F ] ^ \ - SB4[ (T >> 16) & 0x3F ] ^ \ - SB2[ (T >> 24) & 0x3F ]; \ - \ - T = *SK++ ^ ((X << 28) | (X >> 4)); \ - Y ^= SB7[ (T ) & 0x3F ] ^ \ - SB5[ (T >> 8) & 0x3F ] ^ \ - SB3[ (T >> 16) & 0x3F ] ^ \ - SB1[ (T >> 24) & 0x3F ]; \ -} - -#define SWAP(a,b) { uint32_t t = a; a = b; b = t; t = 0; } - -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des3_sw_context ) ); -} - -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des3_sw_context ) ); -} - -static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 - }; - -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - key[i] = odd_parity_table[key[i] / 2]; -} - -/* - * Check the given key's parity, returns 1 on failure, 0 on SUCCESS - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - if( key[i] != odd_parity_table[key[i] / 2] ) - return( 1 ); - - return( 0 ); -} - -/* - * Table of weak and semi-weak keys - * - * Source: http://en.wikipedia.org/wiki/Weak_key - * - * Weak: - * Alternating ones + zeros (0x0101010101010101) - * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE) - * '0xE0E0E0E0F1F1F1F1' - * '0x1F1F1F1F0E0E0E0E' - * - * Semi-weak: - * 0x011F011F010E010E and 0x1F011F010E010E01 - * 0x01E001E001F101F1 and 0xE001E001F101F101 - * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01 - * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E - * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E - * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1 - * - */ - -#define WEAK_KEY_COUNT 16 - -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { - { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, - { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, - { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, - { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 }, - - { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E }, - { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 }, - { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 }, - { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 }, - { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE }, - { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 }, - { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 }, - { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E }, - { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE }, - { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E }, - { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE }, - { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 } -}; - -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < WEAK_KEY_COUNT; i++ ) - if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 ) - return( 1 ); - - return( 0 ); -} - -void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - uint32_t X, Y, T; - - GET_UINT32_BE( X, key, 0 ); - GET_UINT32_BE( Y, key, 4 ); - - /* - * Permuted Choice 1 - */ - T = ((Y >> 4) ^ X) & 0x0F0F0F0F; - X ^= T; - Y ^= (T << 4); - T = ((Y ) ^ X) & 0x10101010; - X ^= T; - Y ^= (T ); - - X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2) - | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) - | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) - | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); - - Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2) - | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) - | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) - | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); - - X &= 0x0FFFFFFF; - Y &= 0x0FFFFFFF; - - /* - * calculate subkeys - */ - for( i = 0; i < 16; i++ ) { - if( i < 2 || i == 8 || i == 15 ) { - X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF; - Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF; - } else { - X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF; - Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF; - } - - *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000) - | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) - | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) - | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) - | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) - | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) - | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) - | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) - | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) - | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) - | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); - - *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000) - | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) - | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) - | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) - | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) - | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) - | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) - | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) - | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) - | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) - | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); - } -} - -/* - * DES key schedule (56-bit, encryption) - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - mbedtls_des_setkey( ctx->sk, key ); - - return( 0 ); -} - -/* - * DES key schedule (56-bit, decryption) - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - mbedtls_des_setkey( ctx->sk, key ); - - for( i = 0; i < 16; i += 2 ) { - SWAP( ctx->sk[i ], ctx->sk[30 - i] ); - SWAP( ctx->sk[i + 1], ctx->sk[31 - i] ); - } - - return( 0 ); -} - -static void des3_set2key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[MBEDTLS_DES_KEY_SIZE*2] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - - for( i = 0; i < 32; i += 2 ) { - dsk[i ] = esk[30 - i]; - dsk[i + 1] = esk[31 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - esk[i + 64] = esk[i ]; - esk[i + 65] = esk[i + 1]; - - dsk[i + 64] = dsk[i ]; - dsk[i + 65] = dsk[i + 1]; - } -} - -/* - * Triple-DES key schedule (112-bit, encryption) - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (112-bit, decryption) - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -static void des3_set3key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[24] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - mbedtls_des_setkey( esk + 64, key + 16 ); - - for( i = 0; i < 32; i += 2 ) { - dsk[i ] = esk[94 - i]; - dsk[i + 1] = esk[95 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - dsk[i + 64] = esk[30 - i]; - dsk[i + 65] = esk[31 - i]; - } -} - -/* - * Triple-DES key schedule (168-bit, encryption) - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (168-bit, decryption) - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * DES-ECB block encryption/decryption - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * DES-CBC buffer encryption/decryption - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) { - while( length > 0 ) { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } else { /* MBEDTLS_DES_DECRYPT */ - while( length > 0 ) { - memcpy( temp, input, 8 ); - mbedtls_des_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/* - * 3DES-ECB block encryption/decryption - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - for( i = 0; i < 8; i++ ) { - DES_ROUND( X, Y ); - DES_ROUND( Y, X ); - } - - for( i = 0; i < 8; i++ ) { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * 3DES-CBC buffer encryption/decryption - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) { - while( length > 0 ) { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des3_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } else { /* MBEDTLS_DES_DECRYPT */ - while( length > 0 ) { - memcpy( temp, input, 8 ); - mbedtls_des3_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h deleted file mode 100644 index 36ef2f28d9..0000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h +++ /dev/null @@ -1,275 +0,0 @@ -/** - * \file des.h - * - * \brief DES block cipher - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -#ifndef MBEDTLS_DES_ALT_SW_H -#define MBEDTLS_DES_ALT_SW_H - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief DES context structure - */ -typedef struct { - uint32_t sk[32]; /*!< DES subkeys */ -} -mbedtls_des_sw_context; - -/** - * \brief Triple-DES context structure - */ -typedef struct { - uint32_t sk[96]; /*!< 3DES subkeys */ -} -mbedtls_des3_sw_context; - -/** - * \brief Initialize DES context - * - * \param ctx DES context to be initialized - */ -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ); - -/** - * \brief Clear DES context - * - * \param ctx DES context to be cleared - */ -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ); - -/** - * \brief Initialize Triple-DES context - * - * \param ctx DES3 context to be initialized - */ -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Clear Triple-DES context - * - * \param ctx DES3 context to be cleared - */ -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Set key parity on the given key to odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - */ -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key parity on the given key is odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - * - * \return 0 is parity was ok, 1 if parity was not correct. - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key is not a weak or semi-weak DES key - * - * \param key 8-byte secret key - * - * \return 0 if no weak key was found, 1 if a weak key was identified. - */ -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, encryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, decryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Triple-DES key schedule (112-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (112-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (168-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief Triple-DES key schedule (168-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief DES-ECB block encryption/decryption - * - * \param ctx DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief 3DES-ECB block encryption/decryption - * - * \param ctx 3DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief 3DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx 3DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief Internal function for key expansion. - * (Only exposed to allow overriding it, - * see MBEDTLS_DES_SETKEY_ALT) - * - * \param SK Round keys - * \param key Base key - */ -void mbedtls_des_sw_setkey( uint32_t SK[32], - const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ - -#endif /* des.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h index a3df9777e7..9fda2763a1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h @@ -24,7 +24,6 @@ #include #include -#include "des_alt_sw.h" #ifdef __cplusplus extern "C" { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c deleted file mode 100644 index d3968b464b..0000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c +++ /dev/null @@ -1,766 +0,0 @@ -/* - * FIPS-46-3 compliant Triple-DES implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -/* - * DES, on which TDES is based, was originally designed by Horst Feistel - * at IBM in 1974, and was adopted as a standard by NIST (formerly NBS). - * - * http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf - */ - -#include "mbedtls/des.h" - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include - -/* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) -{ - volatile unsigned char *p = (unsigned char*)v; - while( n-- ) *p++ = 0; -} - -/* - * 32-bit integer manipulation macros (big endian) - */ -#ifndef GET_UINT32_BE -#define GET_UINT32_BE(n,b,i) \ -{ \ - (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ - | ( (uint32_t) (b)[(i) + 1] << 16 ) \ - | ( (uint32_t) (b)[(i) + 2] << 8 ) \ - | ( (uint32_t) (b)[(i) + 3] ); \ -} -#endif - -#ifndef PUT_UINT32_BE -#define PUT_UINT32_BE(n,b,i) \ -{ \ - (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ - (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ - (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ - (b)[(i) + 3] = (unsigned char) ( (n) ); \ -} -#endif - -/* - * Expanded DES S-boxes - */ -static const uint32_t SB1[64] = { - 0x01010400, 0x00000000, 0x00010000, 0x01010404, - 0x01010004, 0x00010404, 0x00000004, 0x00010000, - 0x00000400, 0x01010400, 0x01010404, 0x00000400, - 0x01000404, 0x01010004, 0x01000000, 0x00000004, - 0x00000404, 0x01000400, 0x01000400, 0x00010400, - 0x00010400, 0x01010000, 0x01010000, 0x01000404, - 0x00010004, 0x01000004, 0x01000004, 0x00010004, - 0x00000000, 0x00000404, 0x00010404, 0x01000000, - 0x00010000, 0x01010404, 0x00000004, 0x01010000, - 0x01010400, 0x01000000, 0x01000000, 0x00000400, - 0x01010004, 0x00010000, 0x00010400, 0x01000004, - 0x00000400, 0x00000004, 0x01000404, 0x00010404, - 0x01010404, 0x00010004, 0x01010000, 0x01000404, - 0x01000004, 0x00000404, 0x00010404, 0x01010400, - 0x00000404, 0x01000400, 0x01000400, 0x00000000, - 0x00010004, 0x00010400, 0x00000000, 0x01010004 -}; - -static const uint32_t SB2[64] = { - 0x80108020, 0x80008000, 0x00008000, 0x00108020, - 0x00100000, 0x00000020, 0x80100020, 0x80008020, - 0x80000020, 0x80108020, 0x80108000, 0x80000000, - 0x80008000, 0x00100000, 0x00000020, 0x80100020, - 0x00108000, 0x00100020, 0x80008020, 0x00000000, - 0x80000000, 0x00008000, 0x00108020, 0x80100000, - 0x00100020, 0x80000020, 0x00000000, 0x00108000, - 0x00008020, 0x80108000, 0x80100000, 0x00008020, - 0x00000000, 0x00108020, 0x80100020, 0x00100000, - 0x80008020, 0x80100000, 0x80108000, 0x00008000, - 0x80100000, 0x80008000, 0x00000020, 0x80108020, - 0x00108020, 0x00000020, 0x00008000, 0x80000000, - 0x00008020, 0x80108000, 0x00100000, 0x80000020, - 0x00100020, 0x80008020, 0x80000020, 0x00100020, - 0x00108000, 0x00000000, 0x80008000, 0x00008020, - 0x80000000, 0x80100020, 0x80108020, 0x00108000 -}; - -static const uint32_t SB3[64] = { - 0x00000208, 0x08020200, 0x00000000, 0x08020008, - 0x08000200, 0x00000000, 0x00020208, 0x08000200, - 0x00020008, 0x08000008, 0x08000008, 0x00020000, - 0x08020208, 0x00020008, 0x08020000, 0x00000208, - 0x08000000, 0x00000008, 0x08020200, 0x00000200, - 0x00020200, 0x08020000, 0x08020008, 0x00020208, - 0x08000208, 0x00020200, 0x00020000, 0x08000208, - 0x00000008, 0x08020208, 0x00000200, 0x08000000, - 0x08020200, 0x08000000, 0x00020008, 0x00000208, - 0x00020000, 0x08020200, 0x08000200, 0x00000000, - 0x00000200, 0x00020008, 0x08020208, 0x08000200, - 0x08000008, 0x00000200, 0x00000000, 0x08020008, - 0x08000208, 0x00020000, 0x08000000, 0x08020208, - 0x00000008, 0x00020208, 0x00020200, 0x08000008, - 0x08020000, 0x08000208, 0x00000208, 0x08020000, - 0x00020208, 0x00000008, 0x08020008, 0x00020200 -}; - -static const uint32_t SB4[64] = { - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802080, 0x00800081, 0x00800001, 0x00002001, - 0x00000000, 0x00802000, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00800080, 0x00800001, - 0x00000001, 0x00002000, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002001, 0x00002080, - 0x00800081, 0x00000001, 0x00002080, 0x00800080, - 0x00002000, 0x00802080, 0x00802081, 0x00000081, - 0x00800080, 0x00800001, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00000000, 0x00802000, - 0x00002080, 0x00800080, 0x00800081, 0x00000001, - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802081, 0x00000081, 0x00000001, 0x00002000, - 0x00800001, 0x00002001, 0x00802080, 0x00800081, - 0x00002001, 0x00002080, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002000, 0x00802080 -}; - -static const uint32_t SB5[64] = { - 0x00000100, 0x02080100, 0x02080000, 0x42000100, - 0x00080000, 0x00000100, 0x40000000, 0x02080000, - 0x40080100, 0x00080000, 0x02000100, 0x40080100, - 0x42000100, 0x42080000, 0x00080100, 0x40000000, - 0x02000000, 0x40080000, 0x40080000, 0x00000000, - 0x40000100, 0x42080100, 0x42080100, 0x02000100, - 0x42080000, 0x40000100, 0x00000000, 0x42000000, - 0x02080100, 0x02000000, 0x42000000, 0x00080100, - 0x00080000, 0x42000100, 0x00000100, 0x02000000, - 0x40000000, 0x02080000, 0x42000100, 0x40080100, - 0x02000100, 0x40000000, 0x42080000, 0x02080100, - 0x40080100, 0x00000100, 0x02000000, 0x42080000, - 0x42080100, 0x00080100, 0x42000000, 0x42080100, - 0x02080000, 0x00000000, 0x40080000, 0x42000000, - 0x00080100, 0x02000100, 0x40000100, 0x00080000, - 0x00000000, 0x40080000, 0x02080100, 0x40000100 -}; - -static const uint32_t SB6[64] = { - 0x20000010, 0x20400000, 0x00004000, 0x20404010, - 0x20400000, 0x00000010, 0x20404010, 0x00400000, - 0x20004000, 0x00404010, 0x00400000, 0x20000010, - 0x00400010, 0x20004000, 0x20000000, 0x00004010, - 0x00000000, 0x00400010, 0x20004010, 0x00004000, - 0x00404000, 0x20004010, 0x00000010, 0x20400010, - 0x20400010, 0x00000000, 0x00404010, 0x20404000, - 0x00004010, 0x00404000, 0x20404000, 0x20000000, - 0x20004000, 0x00000010, 0x20400010, 0x00404000, - 0x20404010, 0x00400000, 0x00004010, 0x20000010, - 0x00400000, 0x20004000, 0x20000000, 0x00004010, - 0x20000010, 0x20404010, 0x00404000, 0x20400000, - 0x00404010, 0x20404000, 0x00000000, 0x20400010, - 0x00000010, 0x00004000, 0x20400000, 0x00404010, - 0x00004000, 0x00400010, 0x20004010, 0x00000000, - 0x20404000, 0x20000000, 0x00400010, 0x20004010 -}; - -static const uint32_t SB7[64] = { - 0x00200000, 0x04200002, 0x04000802, 0x00000000, - 0x00000800, 0x04000802, 0x00200802, 0x04200800, - 0x04200802, 0x00200000, 0x00000000, 0x04000002, - 0x00000002, 0x04000000, 0x04200002, 0x00000802, - 0x04000800, 0x00200802, 0x00200002, 0x04000800, - 0x04000002, 0x04200000, 0x04200800, 0x00200002, - 0x04200000, 0x00000800, 0x00000802, 0x04200802, - 0x00200800, 0x00000002, 0x04000000, 0x00200800, - 0x04000000, 0x00200800, 0x00200000, 0x04000802, - 0x04000802, 0x04200002, 0x04200002, 0x00000002, - 0x00200002, 0x04000000, 0x04000800, 0x00200000, - 0x04200800, 0x00000802, 0x00200802, 0x04200800, - 0x00000802, 0x04000002, 0x04200802, 0x04200000, - 0x00200800, 0x00000000, 0x00000002, 0x04200802, - 0x00000000, 0x00200802, 0x04200000, 0x00000800, - 0x04000002, 0x04000800, 0x00000800, 0x00200002 -}; - -static const uint32_t SB8[64] = { - 0x10001040, 0x00001000, 0x00040000, 0x10041040, - 0x10000000, 0x10001040, 0x00000040, 0x10000000, - 0x00040040, 0x10040000, 0x10041040, 0x00041000, - 0x10041000, 0x00041040, 0x00001000, 0x00000040, - 0x10040000, 0x10000040, 0x10001000, 0x00001040, - 0x00041000, 0x00040040, 0x10040040, 0x10041000, - 0x00001040, 0x00000000, 0x00000000, 0x10040040, - 0x10000040, 0x10001000, 0x00041040, 0x00040000, - 0x00041040, 0x00040000, 0x10041000, 0x00001000, - 0x00000040, 0x10040040, 0x00001000, 0x00041040, - 0x10001000, 0x00000040, 0x10000040, 0x10040000, - 0x10040040, 0x10000000, 0x00040000, 0x10001040, - 0x00000000, 0x10041040, 0x00040040, 0x10000040, - 0x10040000, 0x10001000, 0x10001040, 0x00000000, - 0x10041040, 0x00041000, 0x00041000, 0x00001040, - 0x00001040, 0x00040040, 0x10000000, 0x10041000 -}; - -/* - * PC1: left and right halves bit-swap - */ -static const uint32_t LHs[16] = { - 0x00000000, 0x00000001, 0x00000100, 0x00000101, - 0x00010000, 0x00010001, 0x00010100, 0x00010101, - 0x01000000, 0x01000001, 0x01000100, 0x01000101, - 0x01010000, 0x01010001, 0x01010100, 0x01010101 -}; - -static const uint32_t RHs[16] = { - 0x00000000, 0x01000000, 0x00010000, 0x01010000, - 0x00000100, 0x01000100, 0x00010100, 0x01010100, - 0x00000001, 0x01000001, 0x00010001, 0x01010001, - 0x00000101, 0x01000101, 0x00010101, 0x01010101, -}; - -/* - * Initial Permutation macro - */ -#define DES_IP(X,Y) \ -{ \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T; \ - X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF; \ -} - -/* - * Final Permutation macro - */ -#define DES_FP(X,Y) \ -{ \ - X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T; \ - Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF; \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ -} - -/* - * DES round macro - */ -#define DES_ROUND(X,Y) \ -{ \ - T = *SK++ ^ X; \ - Y ^= SB8[ (T ) & 0x3F ] ^ \ - SB6[ (T >> 8) & 0x3F ] ^ \ - SB4[ (T >> 16) & 0x3F ] ^ \ - SB2[ (T >> 24) & 0x3F ]; \ - \ - T = *SK++ ^ ((X << 28) | (X >> 4)); \ - Y ^= SB7[ (T ) & 0x3F ] ^ \ - SB5[ (T >> 8) & 0x3F ] ^ \ - SB3[ (T >> 16) & 0x3F ] ^ \ - SB1[ (T >> 24) & 0x3F ]; \ -} - -#define SWAP(a,b) { uint32_t t = a; a = b; b = t; t = 0; } - -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des3_sw_context ) ); -} - -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des3_sw_context ) ); -} - -static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 - }; - -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - key[i] = odd_parity_table[key[i] / 2]; -} - -/* - * Check the given key's parity, returns 1 on failure, 0 on SUCCESS - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - if( key[i] != odd_parity_table[key[i] / 2] ) - return( 1 ); - - return( 0 ); -} - -/* - * Table of weak and semi-weak keys - * - * Source: http://en.wikipedia.org/wiki/Weak_key - * - * Weak: - * Alternating ones + zeros (0x0101010101010101) - * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE) - * '0xE0E0E0E0F1F1F1F1' - * '0x1F1F1F1F0E0E0E0E' - * - * Semi-weak: - * 0x011F011F010E010E and 0x1F011F010E010E01 - * 0x01E001E001F101F1 and 0xE001E001F101F101 - * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01 - * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E - * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E - * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1 - * - */ - -#define WEAK_KEY_COUNT 16 - -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { - { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, - { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, - { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, - { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 }, - - { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E }, - { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 }, - { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 }, - { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 }, - { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE }, - { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 }, - { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 }, - { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E }, - { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE }, - { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E }, - { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE }, - { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 } -}; - -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < WEAK_KEY_COUNT; i++ ) - if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 ) - return( 1 ); - - return( 0 ); -} - -void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - uint32_t X, Y, T; - - GET_UINT32_BE( X, key, 0 ); - GET_UINT32_BE( Y, key, 4 ); - - /* - * Permuted Choice 1 - */ - T = ((Y >> 4) ^ X) & 0x0F0F0F0F; - X ^= T; - Y ^= (T << 4); - T = ((Y ) ^ X) & 0x10101010; - X ^= T; - Y ^= (T ); - - X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2) - | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) - | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) - | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); - - Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2) - | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) - | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) - | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); - - X &= 0x0FFFFFFF; - Y &= 0x0FFFFFFF; - - /* - * calculate subkeys - */ - for( i = 0; i < 16; i++ ) { - if( i < 2 || i == 8 || i == 15 ) { - X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF; - Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF; - } else { - X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF; - Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF; - } - - *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000) - | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) - | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) - | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) - | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) - | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) - | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) - | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) - | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) - | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) - | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); - - *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000) - | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) - | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) - | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) - | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) - | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) - | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) - | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) - | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) - | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) - | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); - } -} - -/* - * DES key schedule (56-bit, encryption) - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - mbedtls_des_setkey( ctx->sk, key ); - - return( 0 ); -} - -/* - * DES key schedule (56-bit, decryption) - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - mbedtls_des_setkey( ctx->sk, key ); - - for( i = 0; i < 16; i += 2 ) { - SWAP( ctx->sk[i ], ctx->sk[30 - i] ); - SWAP( ctx->sk[i + 1], ctx->sk[31 - i] ); - } - - return( 0 ); -} - -static void des3_set2key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[MBEDTLS_DES_KEY_SIZE*2] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - - for( i = 0; i < 32; i += 2 ) { - dsk[i ] = esk[30 - i]; - dsk[i + 1] = esk[31 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - esk[i + 64] = esk[i ]; - esk[i + 65] = esk[i + 1]; - - dsk[i + 64] = dsk[i ]; - dsk[i + 65] = dsk[i + 1]; - } -} - -/* - * Triple-DES key schedule (112-bit, encryption) - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (112-bit, decryption) - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -static void des3_set3key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[24] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - mbedtls_des_setkey( esk + 64, key + 16 ); - - for( i = 0; i < 32; i += 2 ) { - dsk[i ] = esk[94 - i]; - dsk[i + 1] = esk[95 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - dsk[i + 64] = esk[30 - i]; - dsk[i + 65] = esk[31 - i]; - } -} - -/* - * Triple-DES key schedule (168-bit, encryption) - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (168-bit, decryption) - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * DES-ECB block encryption/decryption - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * DES-CBC buffer encryption/decryption - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) { - while( length > 0 ) { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } else { /* MBEDTLS_DES_DECRYPT */ - while( length > 0 ) { - memcpy( temp, input, 8 ); - mbedtls_des_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/* - * 3DES-ECB block encryption/decryption - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - for( i = 0; i < 8; i++ ) { - DES_ROUND( X, Y ); - DES_ROUND( Y, X ); - } - - for( i = 0; i < 8; i++ ) { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * 3DES-CBC buffer encryption/decryption - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) { - while( length > 0 ) { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des3_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } else { /* MBEDTLS_DES_DECRYPT */ - while( length > 0 ) { - memcpy( temp, input, 8 ); - mbedtls_des3_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h deleted file mode 100644 index 24d4b13a47..0000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h +++ /dev/null @@ -1,277 +0,0 @@ -/** - * \file des.h - * - * \brief DES block cipher - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -#ifndef MBEDTLS_DES_ALT_SW_H -#define MBEDTLS_DES_ALT_SW_H - -#include "mbedtls/des.h" - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief DES context structure - */ -typedef struct { - uint32_t sk[32]; /*!< DES subkeys */ -} -mbedtls_des_sw_context; - -/** - * \brief Triple-DES context structure - */ -typedef struct { - uint32_t sk[96]; /*!< 3DES subkeys */ -} -mbedtls_des3_sw_context; - -/** - * \brief Initialize DES context - * - * \param ctx DES context to be initialized - */ -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ); - -/** - * \brief Clear DES context - * - * \param ctx DES context to be cleared - */ -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ); - -/** - * \brief Initialize Triple-DES context - * - * \param ctx DES3 context to be initialized - */ -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Clear Triple-DES context - * - * \param ctx DES3 context to be cleared - */ -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Set key parity on the given key to odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - */ -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key parity on the given key is odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - * - * \return 0 is parity was ok, 1 if parity was not correct. - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key is not a weak or semi-weak DES key - * - * \param key 8-byte secret key - * - * \return 0 if no weak key was found, 1 if a weak key was identified. - */ -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, encryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, decryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Triple-DES key schedule (112-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (112-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (168-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief Triple-DES key schedule (168-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief DES-ECB block encryption/decryption - * - * \param ctx DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief 3DES-ECB block encryption/decryption - * - * \param ctx 3DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief 3DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx 3DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief Internal function for key expansion. - * (Only exposed to allow overriding it, - * see MBEDTLS_DES_SETKEY_ALT) - * - * \param SK Round keys - * \param key Base key - */ -void mbedtls_des_sw_setkey( uint32_t SK[32], - const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ - -#endif /* des.h */ From 2ddc1410f0045be16cfbe9d0a8dcf9d43ac77752 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Sep 2017 15:43:32 +0800 Subject: [PATCH 047/118] Refine config check code --- .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 2 ++ .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h | 2 ++ .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h | 2 ++ .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h | 2 ++ .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h | 2 ++ .../mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h | 2 ++ 6 files changed, 12 insertions(+) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index 648c9988db..912c4865c6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -23,6 +23,8 @@ #ifndef MBEDTLS_AES_ALT_H #define MBEDTLS_AES_ALT_H +#include "mbedtls/aes.h" + #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h index cf4e6908aa..9fda2763a1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h @@ -17,6 +17,8 @@ #ifndef MBEDTLS_DES_ALT_H #define MBEDTLS_DES_ALT_H +#include "mbedtls/des.h" + #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h index 9c0a92f368..9471b628ba 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h @@ -16,6 +16,8 @@ #ifndef MBEDTLS_SHA1_ALT_H #define MBEDTLS_SHA1_ALT_H +#include "mbedtls/sha1.h" + #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h index c23c7eae5e..eedca82eea 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h @@ -16,6 +16,8 @@ #ifndef MBEDTLS_SHA256_ALT_H #define MBEDTLS_SHA256_ALT_H +#include "mbedtls/sha256.h" + #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h index 1d85833d46..f4c6f75b37 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h @@ -16,6 +16,8 @@ #ifndef MBEDTLS_SHA512_ALT_H #define MBEDTLS_SHA512_ALT_H +#include "mbedtls/sha512.h" + #if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index 648c9988db..912c4865c6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -23,6 +23,8 @@ #ifndef MBEDTLS_AES_ALT_H #define MBEDTLS_AES_ALT_H +#include "mbedtls/aes.h" + #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation From bc366a1c314a463aa9a9adef8de4faf6fd4e0fa8 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Fri, 22 Sep 2017 11:47:47 +0800 Subject: [PATCH 048/118] Fix AES alter. DMA buffer check --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 16 +++++++++------- .../TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 16 +++++++++------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 46d9c944bb..2469d88778 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -51,13 +51,15 @@ extern volatile int g_AES_done; /* Check if buffer can be used for AES DMA. It requires to be: * 1) Word-aligned - * 2) Located in 0x2xxxxxxx region + * 2) Located in 0x20000000-0x2FFFFFFF region */ -static bool aes_dma_buff_compat(const void *buff) +static bool aes_dma_buff_compat(const void *buff, unsigned buff_size) { uint32_t buff_ = (uint32_t) buff; - return (((buff_ & 0x03) == 0) && ((buff_ & 0x20000000) == 0x20000000)); + return (((buff_ & 0x03) == 0) && /* Word-aligned */ + (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ + ((((unsigned) buff) + buff_size) <= 0x30000000)); } void mbedtls_aes_init( mbedtls_aes_context *ctx ) @@ -147,8 +149,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, */ MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; - if ((! aes_dma_buff_compat(au8OutputData)) || (! aes_dma_buff_compat(au8InputData))) { - error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x2xxxxxxx region."); + if ((! aes_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! aes_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } /* We support multiple contexts with context save & restore and so needs just one @@ -158,7 +160,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(input)) { + if (! aes_dma_buff_compat(input, dataSize)) { if (dataSize > MAX_DMA_CHAIN_SIZE) { error("Internal AES alter. error. DMA buffer is too small."); } @@ -168,7 +170,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, pIn = input; } /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(output)) { + if (! aes_dma_buff_compat(output, dataSize)) { pOut = au8OutputData; } else { pOut = output; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index b3443872de..6f21af1743 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -51,13 +51,15 @@ extern volatile int g_AES_done; /* Check if buffer can be used for AES DMA. It requires to be: * 1) Word-aligned - * 2) Located in 0x2xxxxxxx region + * 2) Located in 0x20000000-0x2FFFFFFF region */ -static bool aes_dma_buff_compat(const void *buff) +static bool aes_dma_buff_compat(const void *buff, unsigned buff_size) { uint32_t buff_ = (uint32_t) buff; - return (((buff_ & 0x03) == 0) && ((buff_ & 0x20000000) == 0x20000000)); + return (((buff_ & 0x03) == 0) && /* Word-aligned */ + (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ + ((((unsigned) buff) + buff_size) <= 0x30000000)); } void mbedtls_aes_init( mbedtls_aes_context *ctx ) @@ -147,8 +149,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, */ MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; - if ((! aes_dma_buff_compat(au8OutputData)) || (! aes_dma_buff_compat(au8InputData))) { - error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x2xxxxxxx region."); + if ((! aes_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! aes_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } /* We support multiple contexts with context save & restore and so needs just one @@ -158,7 +160,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(input)) { + if (! aes_dma_buff_compat(input, dataSize)) { if (dataSize > MAX_DMA_CHAIN_SIZE) { error("Internal AES alter. error. DMA buffer is too small."); } @@ -168,7 +170,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, pIn = input; } /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(output)) { + if (! aes_dma_buff_compat(output, dataSize)) { pOut = au8OutputData; } else { pOut = output; From e60198e946b62dc1c5548c1192d1801a79c46873 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 26 Sep 2017 09:49:09 +0800 Subject: [PATCH 049/118] Refine AES alter. input/output data endianness --- .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 5 ++--- .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 1 - .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 5 ++--- .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h | 1 - 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 2469d88778..ce8de2c35f 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -66,8 +66,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - ctx->swapType = AES_IN_OUT_SWAP; - /* Unlock protected registers */ SYS_UnlockReg(); CLK_EnableModuleClock(CRPT_MODULE); @@ -156,7 +154,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* We support multiple contexts with context save & restore and so needs just one * H/W channel. Always use H/W channel #0. */ - AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); + /* AES_IN_OUT_SWAP: Let H/W know both input/output data are arranged in little-endian */ + AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index 912c4865c6..a371804aa8 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -45,7 +45,6 @@ typedef struct { uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ uint32_t encDec; /* 0: decrypt, 1: encrypt */ uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ - uint32_t swapType; /* Input/Output data endianness */ uint32_t iv[4]; /* IV for next block cipher */ uint32_t buf[8]; /* Cipher key */ } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 6f21af1743..61b4e8848d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -66,8 +66,6 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - ctx->swapType = AES_IN_OUT_SWAP; - /* Unlock protected registers */ SYS_UnlockReg(); CLK_EnableModuleClock(CRPT_MODULE); @@ -156,7 +154,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* We support multiple contexts with context save & restore and so needs just one * H/W channel. Always use H/W channel #0. */ - AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); + /* AES_IN_OUT_SWAP: Let H/W know both input/output data are arranged in little-endian */ + AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->buf, ctx->keySize); /* AES DMA buffer requirements same as above */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index 912c4865c6..a371804aa8 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -45,7 +45,6 @@ typedef struct { uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ uint32_t encDec; /* 0: decrypt, 1: encrypt */ uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ - uint32_t swapType; /* Input/Output data endianness */ uint32_t iv[4]; /* IV for next block cipher */ uint32_t buf[8]; /* Cipher key */ } From 416c4fa7f6196bdd72591fd5aad7237aef2dd177 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 26 Sep 2017 10:12:39 +0800 Subject: [PATCH 050/118] Fix AES alter. DMA buffer could locate at unsupported region --- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 6 ++++-- .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index ce8de2c35f..878f8d9abb 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -49,6 +49,10 @@ extern volatile int g_AES_done; // Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) +/* Backup buffer for DMA if user buffer doesn't meet requirements. */ +MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; +MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; + /* Check if buffer can be used for AES DMA. It requires to be: * 1) Word-aligned * 2) Located in 0x20000000-0x2FFFFFFF region @@ -145,8 +149,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; - MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; if ((! aes_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! aes_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 61b4e8848d..c8bd88e23a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -49,6 +49,10 @@ extern volatile int g_AES_done; // Must be a multiple of 16 bytes block size #define MAX_DMA_CHAIN_SIZE (16*6) +/* Backup buffer for DMA if user buffer doesn't meet requirements. */ +MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; +MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; + /* Check if buffer can be used for AES DMA. It requires to be: * 1) Word-aligned * 2) Located in 0x20000000-0x2FFFFFFF region @@ -145,8 +149,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - MBED_ALIGN(4) uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; - MBED_ALIGN(4) uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; if ((! aes_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! aes_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } From 5785ecfb76cf5a1adb60d4bcb081c40acd9a1632 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 26 Sep 2017 10:57:14 +0800 Subject: [PATCH 051/118] Fix DES alter. DMA buffer could locate at unsupported region --- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 33 ++++++++++++++++--- .../TARGET_NUC472/des/des_alt.c | 33 ++++++++++++++++--- 2 files changed, 56 insertions(+), 10 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index b19716ba28..e8ca4624a1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -20,9 +20,29 @@ #if defined(MBEDTLS_DES_ALT) #include +#include #include "crypto-misc.h" #include "nu_bitutil.h" #include "mbed_toolchain.h" +#include "mbed_error.h" + +// Must be a multiple of 64-bit block size +#define MAXSIZE_DMABUF (8 * 5) +MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; +MBED_ALIGN(4) static uint8_t dmabuf_out[MAXSIZE_DMABUF]; + +/* Check if buffer can be used for DES DMA. It requires to be: + * 1) Word-aligned + * 2) Located in 0x20000000-0x2FFFFFFF region + */ +static bool des_dma_buff_compat(const void *buff, unsigned buff_size) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned */ + (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ + ((((unsigned) buff) + buff_size) <= 0x30000000)); +} static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output); @@ -301,6 +321,14 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } + /* DES DMA buffer requires to be: + * 1) Word-aligned + * 2) Located in 0x2xxxxxxx region + */ + if ((! des_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! des_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); + } + // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); @@ -335,11 +363,6 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S const unsigned char *in_pos = input; unsigned char *out_pos = output; - // Must be a multiple of 64-bit block size -#define MAXSIZE_DMABUF (8 * 5) - MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; - MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; - while (rmn > 0) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index b19716ba28..e8ca4624a1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -20,9 +20,29 @@ #if defined(MBEDTLS_DES_ALT) #include +#include #include "crypto-misc.h" #include "nu_bitutil.h" #include "mbed_toolchain.h" +#include "mbed_error.h" + +// Must be a multiple of 64-bit block size +#define MAXSIZE_DMABUF (8 * 5) +MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; +MBED_ALIGN(4) static uint8_t dmabuf_out[MAXSIZE_DMABUF]; + +/* Check if buffer can be used for DES DMA. It requires to be: + * 1) Word-aligned + * 2) Located in 0x20000000-0x2FFFFFFF region + */ +static bool des_dma_buff_compat(const void *buff, unsigned buff_size) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned */ + (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ + ((((unsigned) buff) + buff_size) <= 0x30000000)); +} static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output); @@ -301,6 +321,14 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } + /* DES DMA buffer requires to be: + * 1) Word-aligned + * 2) Located in 0x2xxxxxxx region + */ + if ((! des_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! des_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); + } + // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); @@ -335,11 +363,6 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S const unsigned char *in_pos = input; unsigned char *out_pos = output; - // Must be a multiple of 64-bit block size -#define MAXSIZE_DMABUF (8 * 5) - MBED_ALIGN(4) uint8_t dmabuf_in[MAXSIZE_DMABUF]; - MBED_ALIGN(4) uint8_t dmabuf_out[MAXSIZE_DMABUF]; - while (rmn > 0) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; From 41f4e1a12c6ceb50b2fa9c9180f7597a874a5623 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 26 Sep 2017 14:16:35 +0800 Subject: [PATCH 052/118] Coordinate crypto init among AES/DES/SHA/PRNG Add counter to track crypto init among crypto sub-modules. It includes: 1. Enable crypto clock 2. Enable crypto interrupt As counter gets zero, crypto clock is disabled to save power. --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 24 ++++----- .../TARGET_NUVOTON/TARGET_M480/crypto-misc.c | 51 +++++++++++++++++-- .../TARGET_NUVOTON/TARGET_M480/crypto-misc.h | 1 + .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 8 ++- .../TARGET_M480/sha/sha_alt_hw.c | 9 ++++ .../TARGET_NUC472/aes/aes_alt.c | 24 ++++----- .../TARGET_NUC472/crypto-misc.c | 51 +++++++++++++++++-- .../TARGET_NUC472/crypto-misc.h | 1 + .../TARGET_NUC472/des/des_alt.c | 8 ++- .../TARGET_NUC472/sha/sha_alt_hw.c | 6 +++ targets/TARGET_NUVOTON/TARGET_M480/trng_api.c | 19 ++++--- .../TARGET_NUVOTON/TARGET_NUC472/trng_api.c | 15 +++--- 12 files changed, 161 insertions(+), 56 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 878f8d9abb..749c66f8ef 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -34,8 +34,7 @@ #include "mbed_assert.h" #include "mbed_error.h" #include "nu_bitutil.h" - - +#include "crypto-misc.h" /* Implementation that should never be optimized out by the compiler */ static void mbedtls_zeroize( void *v, size_t n ) @@ -69,15 +68,6 @@ static bool aes_dma_buff_compat(const void *buff, unsigned buff_size) void mbedtls_aes_init( mbedtls_aes_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - - /* Unlock protected registers */ - SYS_UnlockReg(); - CLK_EnableModuleClock(CRPT_MODULE); - /* Lock protected registers */ - SYS_LockReg(); - - NVIC_EnableIRQ(CRPT_IRQn); - AES_ENABLE_INT(); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) @@ -153,6 +143,11 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* Init crypto module */ + crypto_init(); + /* Enable AES interrupt */ + AES_ENABLE_INT(); + /* We support multiple contexts with context save & restore and so needs just one * H/W channel. Always use H/W channel #0. */ @@ -182,7 +177,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, g_AES_done = 0; AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); - + if( pOut != output ) { if (dataSize > MAX_DMA_CHAIN_SIZE) { error("Internal AES alter. error. DMA buffer is too small."); @@ -195,6 +190,11 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, ctx->iv[1] = CRPT->AES_FDBCK[1]; ctx->iv[2] = CRPT->AES_FDBCK[2]; ctx->iv[3] = CRPT->AES_FDBCK[3]; + + /* Disable AES interrupt */ + AES_DISABLE_INT(); + /* Uninit crypto module */ + crypto_uninit(); } /* diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c index c5d49bb0dd..42bb503edf 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c @@ -17,21 +17,62 @@ #include "cmsis.h" #include "mbed_assert.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include #include "nu_modutil.h" #include "nu_bitutil.h" #include "crypto-misc.h" -static int crypto_inited = 0; static int crypto_sha_avail = 1; +/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ +static uint16_t crypto_init_counter = 0U; + +/* As crypto init counter changes from 0 to 1: + * + * 1. Enable crypto clock + * 2. Enable crypto interrupt + */ void crypto_init(void) { - if (crypto_inited) { - return; + core_util_critical_section_enter(); + if (crypto_init_counter == USHRT_MAX) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would overflow (> USHRT_MAX)"); } - crypto_inited = 1; + core_util_atomic_incr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 1) { + SYS_UnlockReg(); // Unlock protected register + CLK_EnableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + + NVIC_EnableIRQ(CRPT_IRQn); + } + core_util_critical_section_exit(); +} - CLK_EnableModuleClock(CRPT_MODULE); +/* As crypto init counter changes from 1 to 0: + * + * 1. Disable crypto interrupt + * 2. Disable crypto clock + */ +void crypto_uninit(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == 0) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would underflow (< 0)"); + } + core_util_atomic_decr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 0) { + NVIC_DisableIRQ(CRPT_IRQn); + + SYS_UnlockReg(); // Unlock protected register + CLK_DisableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + } + core_util_critical_section_exit(); } /* Implementation that should never be optimized out by the compiler */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h index 8d55449712..a6d2f70bb4 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h @@ -22,6 +22,7 @@ extern "C" { #endif void crypto_init(void); +void crypto_uninit(void); void crypto_zeroize(void *v, size_t n); int crypto_sha_acquire(void); void crypto_sha_release(void); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index e8ca4624a1..078af8e172 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -49,7 +49,6 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S void mbedtls_des_init(mbedtls_des_context *ctx) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des_context)); } @@ -64,7 +63,6 @@ void mbedtls_des_free( mbedtls_des_context *ctx ) void mbedtls_des3_init( mbedtls_des3_context *ctx ) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des3_context)); } @@ -329,6 +327,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* Init crypto module */ + crypto_init(); + // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); @@ -418,6 +419,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S } } + /* Uninit crypto module */ + crypto_uninit(); + return 0; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index 521165383a..57fc0139b1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -39,6 +39,7 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); memset(ctx, 0, sizeof(crypto_sha_context)); } @@ -49,6 +50,8 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) return; } + /* Uninit crypto module */ + crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); } @@ -113,6 +116,7 @@ void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[6 void mbedtls_sha256_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); memset(ctx, 0, sizeof(crypto_sha_context)); } @@ -123,6 +127,8 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) return; } + /* Uninit crypto module */ + crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); } @@ -189,6 +195,7 @@ void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data void mbedtls_sha512_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); memset(ctx, 0, sizeof(crypto_sha_context)); } @@ -199,6 +206,8 @@ void mbedtls_sha512_hw_free(crypto_sha_context *ctx) return; } + /* Uninit crypto module */ + crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index c8bd88e23a..5af0bebacc 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -34,8 +34,7 @@ #include "mbed_assert.h" #include "mbed_error.h" #include "nu_bitutil.h" - - +#include "crypto-misc.h" /* Implementation that should never be optimized out by the compiler */ static void mbedtls_zeroize( void *v, size_t n ) @@ -69,15 +68,6 @@ static bool aes_dma_buff_compat(const void *buff, unsigned buff_size) void mbedtls_aes_init( mbedtls_aes_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - - /* Unlock protected registers */ - SYS_UnlockReg(); - CLK_EnableModuleClock(CRPT_MODULE); - /* Lock protected registers */ - SYS_LockReg(); - - NVIC_EnableIRQ(CRPT_IRQn); - AES_ENABLE_INT(); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) @@ -153,6 +143,11 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* Init crypto module */ + crypto_init(); + /* Enable AES interrupt */ + AES_ENABLE_INT(); + /* We support multiple contexts with context save & restore and so needs just one * H/W channel. Always use H/W channel #0. */ @@ -182,7 +177,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, g_AES_done = 0; AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); - + if( pOut != output ) { if (dataSize > MAX_DMA_CHAIN_SIZE) { error("Internal AES alter. error. DMA buffer is too small."); @@ -195,6 +190,11 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, ctx->iv[1] = CRPT->AES_FDBCK1; ctx->iv[2] = CRPT->AES_FDBCK2; ctx->iv[3] = CRPT->AES_FDBCK3; + + /* Disable AES interrupt */ + AES_DISABLE_INT(); + /* Uninit crypto module */ + crypto_uninit(); } /* diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c index c5d49bb0dd..42bb503edf 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c @@ -17,21 +17,62 @@ #include "cmsis.h" #include "mbed_assert.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include #include "nu_modutil.h" #include "nu_bitutil.h" #include "crypto-misc.h" -static int crypto_inited = 0; static int crypto_sha_avail = 1; +/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ +static uint16_t crypto_init_counter = 0U; + +/* As crypto init counter changes from 0 to 1: + * + * 1. Enable crypto clock + * 2. Enable crypto interrupt + */ void crypto_init(void) { - if (crypto_inited) { - return; + core_util_critical_section_enter(); + if (crypto_init_counter == USHRT_MAX) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would overflow (> USHRT_MAX)"); } - crypto_inited = 1; + core_util_atomic_incr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 1) { + SYS_UnlockReg(); // Unlock protected register + CLK_EnableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + + NVIC_EnableIRQ(CRPT_IRQn); + } + core_util_critical_section_exit(); +} - CLK_EnableModuleClock(CRPT_MODULE); +/* As crypto init counter changes from 1 to 0: + * + * 1. Disable crypto interrupt + * 2. Disable crypto clock + */ +void crypto_uninit(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == 0) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would underflow (< 0)"); + } + core_util_atomic_decr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 0) { + NVIC_DisableIRQ(CRPT_IRQn); + + SYS_UnlockReg(); // Unlock protected register + CLK_DisableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + } + core_util_critical_section_exit(); } /* Implementation that should never be optimized out by the compiler */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h index 8d55449712..a6d2f70bb4 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h @@ -22,6 +22,7 @@ extern "C" { #endif void crypto_init(void); +void crypto_uninit(void); void crypto_zeroize(void *v, size_t n); int crypto_sha_acquire(void); void crypto_sha_release(void); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index e8ca4624a1..078af8e172 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -49,7 +49,6 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S void mbedtls_des_init(mbedtls_des_context *ctx) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des_context)); } @@ -64,7 +63,6 @@ void mbedtls_des_free( mbedtls_des_context *ctx ) void mbedtls_des3_init( mbedtls_des3_context *ctx ) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des3_context)); } @@ -329,6 +327,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* Init crypto module */ + crypto_init(); + // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); @@ -418,6 +419,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S } } + /* Uninit crypto module */ + crypto_uninit(); + return 0; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index a653cd7a96..ab8181cc65 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -39,6 +39,7 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); memset(ctx, 0, sizeof(crypto_sha_context)); } @@ -49,6 +50,8 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) return; } + /* Uninit crypto module */ + crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); } @@ -113,6 +116,7 @@ void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[6 void mbedtls_sha256_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); memset(ctx, 0, sizeof(crypto_sha_context)); } @@ -123,6 +127,8 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) return; } + /* Uninit crypto module */ + crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c index 24d15537e4..74cabee52a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c @@ -21,6 +21,7 @@ #include "cmsis.h" #include "us_ticker_api.h" #include "trng_api.h" +#include "crypto-misc.h" /* * Get Random number generator. @@ -63,23 +64,21 @@ static void trng_get(unsigned char *pConversionData) void trng_init(trng_t *obj) { (void)obj; - /* Unlock protected registers */ - SYS_UnlockReg(); - /* Enable IP clock */ - CLK_EnableModuleClock(CRPT_MODULE); - - /* Lock protected registers */ - SYS_LockReg(); - - NVIC_EnableIRQ(CRPT_IRQn); + + /* Init crypto module */ + crypto_init(); + PRNG_ENABLE_INT(); } void trng_free(trng_t *obj) { (void)obj; + PRNG_DISABLE_INT(); - NVIC_DisableIRQ(CRPT_IRQn); + + /* Uninit crypto module */ + crypto_uninit(); } int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c index a1f55b48f6..1b6b24cf06 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c @@ -26,6 +26,7 @@ #include "NUC472_442.h" #include "us_ticker_api.h" #include "trng_api.h" +#include "crypto-misc.h" /* * Get Random number generator. @@ -68,23 +69,21 @@ static void trng_get(unsigned char *pConversionData) void trng_init(trng_t *obj) { (void)obj; - /* Unlock protected registers */ - SYS_UnlockReg(); - /* Enable IP clock */ - CLK_EnableModuleClock(CRPT_MODULE); - /* Lock protected registers */ - SYS_LockReg(); + /* Init crypto module */ + crypto_init(); - NVIC_EnableIRQ(CRPT_IRQn); PRNG_ENABLE_INT(); } void trng_free(trng_t *obj) { (void)obj; + PRNG_DISABLE_INT(); - NVIC_DisableIRQ(CRPT_IRQn); + + /* Uninit crypto module */ + crypto_uninit(); } int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) From 1f3565ec3594762f68a9179943d1d1e7101a31e9 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 26 Sep 2017 16:34:11 +0800 Subject: [PATCH 053/118] Guard from re-entry into crypto H/W --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 7 +++ .../TARGET_NUVOTON/TARGET_M480/crypto-misc.c | 54 +++++++++++++++---- .../TARGET_NUVOTON/TARGET_M480/crypto-misc.h | 19 ++++++- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 7 +++ .../TARGET_NUC472/aes/aes_alt.c | 7 +++ .../TARGET_NUC472/crypto-misc.c | 54 +++++++++++++++---- .../TARGET_NUC472/crypto-misc.h | 19 ++++++- .../TARGET_NUC472/des/des_alt.c | 7 +++ 8 files changed, 150 insertions(+), 24 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 749c66f8ef..5e54e767ad 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -143,6 +143,10 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of AES H/W */ + while (! crypto_aes_acquire()); + /* Init crypto module */ crypto_init(); /* Enable AES interrupt */ @@ -195,6 +199,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_DISABLE_INT(); /* Uninit crypto module */ crypto_uninit(); + + /* Release ownership of AES H/W */ + crypto_aes_release(); } /* diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c index 42bb503edf..195cb6ce25 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c @@ -24,11 +24,19 @@ #include "nu_bitutil.h" #include "crypto-misc.h" -static int crypto_sha_avail = 1; +/* Track if AES H/W is available */ +static uint16_t crypto_aes_avail = 1; +/* Track if DES H/W is available */ +static uint16_t crypto_des_avail = 1; +/* Track if SHA H/W is available */ +static uint16_t crypto_sha_avail = 1; /* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ static uint16_t crypto_init_counter = 0U; +static bool crypto_submodule_acquire(uint16_t *submodule_avail); +static void crypto_submodule_release(uint16_t *submodule_avail); + /* As crypto init counter changes from 0 to 1: * * 1. Enable crypto clock @@ -84,20 +92,44 @@ void crypto_zeroize(void *v, size_t n) } } -int crypto_sha_acquire(void) +bool crypto_aes_acquire(void) { - if (crypto_sha_avail) { - crypto_sha_avail = 0; - return 1; - } else { - return 0; - } + return crypto_submodule_acquire(&crypto_aes_avail); +} +void crypto_aes_release(void) +{ + crypto_submodule_release(&crypto_aes_avail); +} + +bool crypto_des_acquire(void) +{ + return crypto_submodule_acquire(&crypto_des_avail); +} + +void crypto_des_release(void) +{ + crypto_submodule_release(&crypto_des_avail); +} + +bool crypto_sha_acquire(void) +{ + return crypto_submodule_acquire(&crypto_sha_avail); } void crypto_sha_release(void) { - if (! crypto_sha_avail) { - crypto_sha_avail = 1; - } + crypto_submodule_release(&crypto_sha_avail); +} + +static bool crypto_submodule_acquire(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 1; + return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0); +} + +static void crypto_submodule_release(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 0; + while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h index a6d2f70bb4..e33103ebe6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h @@ -17,14 +17,31 @@ #ifndef MBED_CRYPTO_MISC_H #define MBED_CRYPTO_MISC_H +#include + #ifdef __cplusplus extern "C" { #endif +/* Init/Uninit crypto module */ void crypto_init(void); void crypto_uninit(void); + void crypto_zeroize(void *v, size_t n); -int crypto_sha_acquire(void); + +/* Acquire/release ownership of AES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_aes_acquire(void); +void crypto_aes_release(void); + +/* Acquire/release ownership of DES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_des_acquire(void); +void crypto_des_release(void); + +/* Acquire/release ownership of SHA H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_sha_acquire(void); void crypto_sha_release(void); #ifdef __cplusplus diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 078af8e172..55bf5f1806 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -327,6 +327,10 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of DES H/W */ + while (! crypto_des_acquire()); + /* Init crypto module */ crypto_init(); @@ -422,6 +426,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Uninit crypto module */ crypto_uninit(); + /* Release ownership of DES H/W */ + crypto_des_release(); + return 0; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 5af0bebacc..b2c77afa8a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -143,6 +143,10 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of AES H/W */ + while (! crypto_aes_acquire()); + /* Init crypto module */ crypto_init(); /* Enable AES interrupt */ @@ -195,6 +199,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_DISABLE_INT(); /* Uninit crypto module */ crypto_uninit(); + + /* Release ownership of AES H/W */ + crypto_aes_release(); } /* diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c index 42bb503edf..195cb6ce25 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c @@ -24,11 +24,19 @@ #include "nu_bitutil.h" #include "crypto-misc.h" -static int crypto_sha_avail = 1; +/* Track if AES H/W is available */ +static uint16_t crypto_aes_avail = 1; +/* Track if DES H/W is available */ +static uint16_t crypto_des_avail = 1; +/* Track if SHA H/W is available */ +static uint16_t crypto_sha_avail = 1; /* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ static uint16_t crypto_init_counter = 0U; +static bool crypto_submodule_acquire(uint16_t *submodule_avail); +static void crypto_submodule_release(uint16_t *submodule_avail); + /* As crypto init counter changes from 0 to 1: * * 1. Enable crypto clock @@ -84,20 +92,44 @@ void crypto_zeroize(void *v, size_t n) } } -int crypto_sha_acquire(void) +bool crypto_aes_acquire(void) { - if (crypto_sha_avail) { - crypto_sha_avail = 0; - return 1; - } else { - return 0; - } + return crypto_submodule_acquire(&crypto_aes_avail); +} +void crypto_aes_release(void) +{ + crypto_submodule_release(&crypto_aes_avail); +} + +bool crypto_des_acquire(void) +{ + return crypto_submodule_acquire(&crypto_des_avail); +} + +void crypto_des_release(void) +{ + crypto_submodule_release(&crypto_des_avail); +} + +bool crypto_sha_acquire(void) +{ + return crypto_submodule_acquire(&crypto_sha_avail); } void crypto_sha_release(void) { - if (! crypto_sha_avail) { - crypto_sha_avail = 1; - } + crypto_submodule_release(&crypto_sha_avail); +} + +static bool crypto_submodule_acquire(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 1; + return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0); +} + +static void crypto_submodule_release(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 0; + while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h index a6d2f70bb4..e33103ebe6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h @@ -17,14 +17,31 @@ #ifndef MBED_CRYPTO_MISC_H #define MBED_CRYPTO_MISC_H +#include + #ifdef __cplusplus extern "C" { #endif +/* Init/Uninit crypto module */ void crypto_init(void); void crypto_uninit(void); + void crypto_zeroize(void *v, size_t n); -int crypto_sha_acquire(void); + +/* Acquire/release ownership of AES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_aes_acquire(void); +void crypto_aes_release(void); + +/* Acquire/release ownership of DES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_des_acquire(void); +void crypto_des_release(void); + +/* Acquire/release ownership of SHA H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_sha_acquire(void); void crypto_sha_release(void); #ifdef __cplusplus diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 078af8e172..55bf5f1806 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -327,6 +327,10 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of DES H/W */ + while (! crypto_des_acquire()); + /* Init crypto module */ crypto_init(); @@ -422,6 +426,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Uninit crypto module */ crypto_uninit(); + /* Release ownership of DES H/W */ + crypto_des_release(); + return 0; } From 9c52660e5283877c8895885d9fbec8804a4de055 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 26 Sep 2017 17:32:52 +0800 Subject: [PATCH 054/118] Optimize AES alter. code --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 33 +++++++++++-------- .../TARGET_NUC472/aes/aes_alt.c | 33 +++++++++++-------- 2 files changed, 40 insertions(+), 26 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 5e54e767ad..60e70b1685 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -255,7 +255,6 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, const unsigned char *input, unsigned char *output ) { - unsigned char temp[16]; int length = len; int blockChainLen; @@ -263,31 +262,39 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + ctx->opMode = AES_MODE_CBC; + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + if( mode == MBEDTLS_AES_ENCRYPT ) { + ctx->encDec = 1; + } + else { + ctx->encDec = 0; + } + while( length > 0 ) { blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; - - ctx->opMode = AES_MODE_CBC; - /* Fetch IV byte data in big-endian */ - ctx->iv[0] = nu_get32_be(iv); - ctx->iv[1] = nu_get32_be(iv + 4); - ctx->iv[2] = nu_get32_be(iv + 8); - ctx->iv[3] = nu_get32_be(iv + 12); if( mode == MBEDTLS_AES_ENCRYPT ) { - ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy( iv, output+blockChainLen-16, 16 ); } else { - memcpy( temp, input+blockChainLen-16, 16 ); - ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy( iv, temp, 16 ); } length -= blockChainLen; input += blockChainLen; output += blockChainLen; } + /* Save IV for next block cipher */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + return( 0 ); } #endif /* MBEDTLS_CIPHER_MODE_CBC */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index b2c77afa8a..3acf43d1fb 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -255,7 +255,6 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, const unsigned char *input, unsigned char *output ) { - unsigned char temp[16]; int length = len; int blockChainLen; @@ -263,31 +262,39 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + ctx->opMode = AES_MODE_CBC; + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + if( mode == MBEDTLS_AES_ENCRYPT ) { + ctx->encDec = 1; + } + else { + ctx->encDec = 0; + } + while( length > 0 ) { blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; - - ctx->opMode = AES_MODE_CBC; - /* Fetch IV byte data in big-endian */ - ctx->iv[0] = nu_get32_be(iv); - ctx->iv[1] = nu_get32_be(iv + 4); - ctx->iv[2] = nu_get32_be(iv + 8); - ctx->iv[3] = nu_get32_be(iv + 12); if( mode == MBEDTLS_AES_ENCRYPT ) { - ctx->encDec = 1; __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy( iv, output+blockChainLen-16, 16 ); } else { - memcpy( temp, input+blockChainLen-16, 16 ); - ctx->encDec = 0; __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy( iv, temp, 16 ); } length -= blockChainLen; input += blockChainLen; output += blockChainLen; } + /* Save IV for next block cipher */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + return( 0 ); } #endif /* MBEDTLS_CIPHER_MODE_CBC */ From a89cb2e5b91705514d2bca5105fc3293a19ca29f Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 27 Sep 2017 10:19:46 +0800 Subject: [PATCH 055/118] Fix AES alter. CFB128 error --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 32 +++++++++---------- .../TARGET_NUC472/aes/aes_alt.c | 32 +++++++++---------- 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 60e70b1685..ddb8fcda24 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -343,31 +343,31 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, ctx->encDec = 1; } + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + while (block_chain_len) { size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; - - /* Fetch IV byte data in big-endian */ - ctx->iv[0] = nu_get32_be(iv); - ctx->iv[1] = nu_get32_be(iv + 4); - ctx->iv[2] = nu_get32_be(iv + 8); - ctx->iv[3] = nu_get32_be(iv + 12); - + __nvt_aes_crypt(ctx, input, output, block_chain_len2); input += block_chain_len2; output += block_chain_len2; length -= block_chain_len2; - - /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output - * for iv of next block cipher. */ - /* Fetch IV byte data in big-endian */ - ctx->iv[0] = nu_get32_be(iv); - ctx->iv[1] = nu_get32_be(iv + 4); - ctx->iv[2] = nu_get32_be(iv + 8); - ctx->iv[3] = nu_get32_be(iv + 12); - + block_chain_len -= block_chain_len2; } + + /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output + * for iv of next block cipher. */ + /* Fetch IV byte data in big-endian */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); } /* Last incomplete block */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 3acf43d1fb..be03f0cdb5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -343,31 +343,31 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, ctx->encDec = 1; } + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + while (block_chain_len) { size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; - - /* Fetch IV byte data in big-endian */ - ctx->iv[0] = nu_get32_be(iv); - ctx->iv[1] = nu_get32_be(iv + 4); - ctx->iv[2] = nu_get32_be(iv + 8); - ctx->iv[3] = nu_get32_be(iv + 12); - + __nvt_aes_crypt(ctx, input, output, block_chain_len2); input += block_chain_len2; output += block_chain_len2; length -= block_chain_len2; - - /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output - * for iv of next block cipher. */ - /* Fetch IV byte data in big-endian */ - ctx->iv[0] = nu_get32_be(iv); - ctx->iv[1] = nu_get32_be(iv + 4); - ctx->iv[2] = nu_get32_be(iv + 8); - ctx->iv[3] = nu_get32_be(iv + 12); - + block_chain_len -= block_chain_len2; } + + /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output + * for iv of next block cipher. */ + /* Fetch IV byte data in big-endian */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); } /* Last incomplete block */ From d6987bb6be03c2980a87c22e723a5ba72b7cb587 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 27 Sep 2017 14:29:40 +0800 Subject: [PATCH 056/118] Refine AES/DES alter. code --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 72 ++++++++----------- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 7 +- .../TARGET_NUVOTON/TARGET_M480/crypto-misc.c | 9 +++ .../TARGET_NUVOTON/TARGET_M480/crypto-misc.h | 7 ++ .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 21 ++---- .../TARGET_NUC472/aes/aes_alt.c | 72 ++++++++----------- .../TARGET_NUC472/aes/aes_alt.h | 7 +- .../TARGET_NUC472/crypto-misc.c | 9 +++ .../TARGET_NUC472/crypto-misc.h | 7 ++ .../TARGET_NUC472/des/des_alt.c | 21 ++---- 10 files changed, 102 insertions(+), 130 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index ddb8fcda24..3296f01532 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -45,25 +45,14 @@ static void mbedtls_zeroize( void *v, size_t n ) extern volatile int g_AES_done; -// Must be a multiple of 16 bytes block size +/* DMA compatible backup buffer if user buffer doesn't meet requirements + * + * MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. + * Its value is estimated to trade memory footprint off against performance. + */ #define MAX_DMA_CHAIN_SIZE (16*6) - -/* Backup buffer for DMA if user buffer doesn't meet requirements. */ MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; - -/* Check if buffer can be used for AES DMA. It requires to be: - * 1) Word-aligned - * 2) Located in 0x20000000-0x2FFFFFFF region - */ -static bool aes_dma_buff_compat(const void *buff, unsigned buff_size) -{ - uint32_t buff_ = (uint32_t) buff; - - return (((buff_ & 0x03) == 0) && /* Word-aligned */ - (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ - ((((unsigned) buff) + buff_size) <= 0x30000000)); -} void mbedtls_aes_init( mbedtls_aes_context *ctx ) { @@ -102,7 +91,7 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, // key swap for( i = 0; i < ( keybits >> 5 ); i++ ) { - ctx->buf[i] = (*(key+i*4) << 24) | + ctx->keys[i] = (*(key+i*4) << 24) | (*(key+1+i*4) << 16) | (*(key+2+i*4) << 8) | (*(key+3+i*4) ); @@ -127,19 +116,29 @@ exit: return( ret ); } - +/* Do AES encrypt/decrypt with H/W accelerator + * + * NOTE: As input/output buffer doesn't follow constraint of DMA buffer, static allocated + * DMA compatible buffer is used for DMA instead and this needs extra copy. + * + * NOTE: dataSize requires to be: + * 1) Multiple of block size 16 + * 2) <= MAX_DMA_CHAIN_SIZE + */ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16], int dataSize) + const unsigned char *input, + unsigned char *output, size_t dataSize) { const unsigned char* pIn; unsigned char* pOut; + MBED_ASSERT((dataSize % 16 == 0) && (dataSize <= MAX_DMA_CHAIN_SIZE)); + /* AES DMA buffer requires to be: * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! aes_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! aes_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } @@ -158,19 +157,16 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* AES_IN_OUT_SWAP: Let H/W know both input/output data are arranged in little-endian */ AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); AES_SetInitVect(0, ctx->iv); - AES_SetKey(0, ctx->buf, ctx->keySize); + AES_SetKey(0, ctx->keys, ctx->keySize); /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(input, dataSize)) { - if (dataSize > MAX_DMA_CHAIN_SIZE) { - error("Internal AES alter. error. DMA buffer is too small."); - } + if (! crypto_dma_buff_compat(input, dataSize)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = input; } /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(output, dataSize)) { + if (! crypto_dma_buff_compat(output, dataSize)) { pOut = au8OutputData; } else { pOut = output; @@ -183,9 +179,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, while (!g_AES_done); if( pOut != output ) { - if (dataSize > MAX_DMA_CHAIN_SIZE) { - error("Internal AES alter. error. DMA buffer is too small."); - } memcpy(output, au8OutputData, dataSize); } @@ -311,12 +304,9 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, int c; size_t n = *iv_off; - /* First incomplete block*/ + /* First incomplete block */ if (n % 16) { - size_t rmn = 16 - n; - rmn = (rmn > length) ? length : rmn; - - while( rmn -- ) { + while (n && length) { if (mode == MBEDTLS_AES_DECRYPT) { c = *input++; *output++ = (unsigned char)( c ^ iv[n] ); @@ -332,7 +322,7 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, } /* Middle complete block(s) */ - size_t block_chain_len = length / 16 * 16; + size_t block_chain_len = length - (length % 16); if (block_chain_len) { ctx->opMode = AES_MODE_CFB; @@ -371,15 +361,10 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, } /* Last incomplete block */ - size_t last_block_len = length; - - if (last_block_len) { + if (length) { mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - - size_t rmn = last_block_len; - rmn = (rmn > length) ? length : rmn; - while (rmn --) { + while (length --) { if (mode == MBEDTLS_AES_DECRYPT) { c = *input++; *output++ = (unsigned char)( c ^ iv[n] ); @@ -390,7 +375,6 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, } n = ( n + 1 ) & 0x0F; - length --; } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index a371804aa8..e907fd62e3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -35,18 +35,13 @@ extern "C" { /** * \brief AES context structure - * - * \note buf is able to hold 32 extra bytes, which can be used: - * - for alignment purposes if VIA padlock is used, and/or - * - to simplify key expansion in the 256-bit case by - * generating an extra round key */ typedef struct { uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ uint32_t encDec; /* 0: decrypt, 1: encrypt */ uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ uint32_t iv[4]; /* IV for next block cipher */ - uint32_t buf[8]; /* Cipher key */ + uint32_t keys[8]; /* Cipher key */ } mbedtls_aes_context; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c index 195cb6ce25..714438e012 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c @@ -122,6 +122,15 @@ void crypto_sha_release(void) crypto_submodule_release(&crypto_sha_avail); } +bool crypto_dma_buff_compat(const void *buff, size_t buff_size) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned */ + (buff_ >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ + ((buff_ + buff_size) <= 0x30000000)); +} + static bool crypto_submodule_acquire(uint16_t *submodule_avail) { uint16_t expectedCurrentValue = 1; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h index e33103ebe6..d64b9629c6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h @@ -44,6 +44,13 @@ void crypto_des_release(void); bool crypto_sha_acquire(void); void crypto_sha_release(void); +/* Check if buffer can be used for crypto DMA. It requires to be: + * + * 1) Word-aligned + * 2) Located in 0x20000000-0x2FFFFFFF region + */ +bool crypto_dma_buff_compat(const void *buff, size_t buff_size); + #ifdef __cplusplus } #endif diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 55bf5f1806..342824d5ea 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -26,24 +26,15 @@ #include "mbed_toolchain.h" #include "mbed_error.h" -// Must be a multiple of 64-bit block size +/* DMA buffer + * + * MAXSIZE_DMABUF must be a multiple of 64-bit block size. + * Its value is estimated to trade memory footprint off against performance. + */ #define MAXSIZE_DMABUF (8 * 5) MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; MBED_ALIGN(4) static uint8_t dmabuf_out[MAXSIZE_DMABUF]; -/* Check if buffer can be used for DES DMA. It requires to be: - * 1) Word-aligned - * 2) Located in 0x20000000-0x2FFFFFFF region - */ -static bool des_dma_buff_compat(const void *buff, unsigned buff_size) -{ - uint32_t buff_ = (uint32_t) buff; - - return (((buff_ & 0x03) == 0) && /* Word-aligned */ - (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ - ((((unsigned) buff) + buff_size) <= 0x30000000)); -} - static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output); @@ -323,7 +314,7 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! des_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! des_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index be03f0cdb5..ce918d4e16 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -45,25 +45,14 @@ static void mbedtls_zeroize( void *v, size_t n ) extern volatile int g_AES_done; -// Must be a multiple of 16 bytes block size +/* DMA compatible backup buffer if user buffer doesn't meet requirements + * + * MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. + * Its value is estimated to trade memory footprint off against performance. + */ #define MAX_DMA_CHAIN_SIZE (16*6) - -/* Backup buffer for DMA if user buffer doesn't meet requirements. */ MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; - -/* Check if buffer can be used for AES DMA. It requires to be: - * 1) Word-aligned - * 2) Located in 0x20000000-0x2FFFFFFF region - */ -static bool aes_dma_buff_compat(const void *buff, unsigned buff_size) -{ - uint32_t buff_ = (uint32_t) buff; - - return (((buff_ & 0x03) == 0) && /* Word-aligned */ - (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ - ((((unsigned) buff) + buff_size) <= 0x30000000)); -} void mbedtls_aes_init( mbedtls_aes_context *ctx ) { @@ -102,7 +91,7 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, // key swap for( i = 0; i < ( keybits >> 5 ); i++ ) { - ctx->buf[i] = (*(key+i*4) << 24) | + ctx->keys[i] = (*(key+i*4) << 24) | (*(key+1+i*4) << 16) | (*(key+2+i*4) << 8) | (*(key+3+i*4) ); @@ -127,19 +116,29 @@ exit: return( ret ); } - +/* Do AES encrypt/decrypt with H/W accelerator + * + * NOTE: As input/output buffer doesn't follow constraint of DMA buffer, static allocated + * DMA compatible buffer is used for DMA instead and this needs extra copy. + * + * NOTE: dataSize requires to be: + * 1) Multiple of block size 16 + * 2) <= MAX_DMA_CHAIN_SIZE + */ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16], int dataSize) + const unsigned char *input, + unsigned char *output, size_t dataSize) { const unsigned char* pIn; unsigned char* pOut; + MBED_ASSERT((dataSize % 16 == 0) && (dataSize <= MAX_DMA_CHAIN_SIZE)); + /* AES DMA buffer requires to be: * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! aes_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! aes_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } @@ -158,19 +157,16 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, /* AES_IN_OUT_SWAP: Let H/W know both input/output data are arranged in little-endian */ AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); AES_SetInitVect(0, ctx->iv); - AES_SetKey(0, ctx->buf, ctx->keySize); + AES_SetKey(0, ctx->keys, ctx->keySize); /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(input, dataSize)) { - if (dataSize > MAX_DMA_CHAIN_SIZE) { - error("Internal AES alter. error. DMA buffer is too small."); - } + if (! crypto_dma_buff_compat(input, dataSize)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = input; } /* AES DMA buffer requirements same as above */ - if (! aes_dma_buff_compat(output, dataSize)) { + if (! crypto_dma_buff_compat(output, dataSize)) { pOut = au8OutputData; } else { pOut = output; @@ -183,9 +179,6 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, while (!g_AES_done); if( pOut != output ) { - if (dataSize > MAX_DMA_CHAIN_SIZE) { - error("Internal AES alter. error. DMA buffer is too small."); - } memcpy(output, au8OutputData, dataSize); } @@ -311,12 +304,9 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, int c; size_t n = *iv_off; - /* First incomplete block*/ + /* First incomplete block */ if (n % 16) { - size_t rmn = 16 - n; - rmn = (rmn > length) ? length : rmn; - - while( rmn -- ) { + while (n && length) { if (mode == MBEDTLS_AES_DECRYPT) { c = *input++; *output++ = (unsigned char)( c ^ iv[n] ); @@ -332,7 +322,7 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, } /* Middle complete block(s) */ - size_t block_chain_len = length / 16 * 16; + size_t block_chain_len = length - (length % 16); if (block_chain_len) { ctx->opMode = AES_MODE_CFB; @@ -371,15 +361,10 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, } /* Last incomplete block */ - size_t last_block_len = length; - - if (last_block_len) { + if (length) { mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - - size_t rmn = last_block_len; - rmn = (rmn > length) ? length : rmn; - while (rmn --) { + while (length --) { if (mode == MBEDTLS_AES_DECRYPT) { c = *input++; *output++ = (unsigned char)( c ^ iv[n] ); @@ -390,7 +375,6 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, } n = ( n + 1 ) & 0x0F; - length --; } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index a371804aa8..e907fd62e3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -35,18 +35,13 @@ extern "C" { /** * \brief AES context structure - * - * \note buf is able to hold 32 extra bytes, which can be used: - * - for alignment purposes if VIA padlock is used, and/or - * - to simplify key expansion in the 256-bit case by - * generating an extra round key */ typedef struct { uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ uint32_t encDec; /* 0: decrypt, 1: encrypt */ uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ uint32_t iv[4]; /* IV for next block cipher */ - uint32_t buf[8]; /* Cipher key */ + uint32_t keys[8]; /* Cipher key */ } mbedtls_aes_context; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c index 195cb6ce25..714438e012 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c @@ -122,6 +122,15 @@ void crypto_sha_release(void) crypto_submodule_release(&crypto_sha_avail); } +bool crypto_dma_buff_compat(const void *buff, size_t buff_size) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned */ + (buff_ >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ + ((buff_ + buff_size) <= 0x30000000)); +} + static bool crypto_submodule_acquire(uint16_t *submodule_avail) { uint16_t expectedCurrentValue = 1; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h index e33103ebe6..d64b9629c6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h @@ -44,6 +44,13 @@ void crypto_des_release(void); bool crypto_sha_acquire(void); void crypto_sha_release(void); +/* Check if buffer can be used for crypto DMA. It requires to be: + * + * 1) Word-aligned + * 2) Located in 0x20000000-0x2FFFFFFF region + */ +bool crypto_dma_buff_compat(const void *buff, size_t buff_size); + #ifdef __cplusplus } #endif diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 55bf5f1806..342824d5ea 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -26,24 +26,15 @@ #include "mbed_toolchain.h" #include "mbed_error.h" -// Must be a multiple of 64-bit block size +/* DMA buffer + * + * MAXSIZE_DMABUF must be a multiple of 64-bit block size. + * Its value is estimated to trade memory footprint off against performance. + */ #define MAXSIZE_DMABUF (8 * 5) MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; MBED_ALIGN(4) static uint8_t dmabuf_out[MAXSIZE_DMABUF]; -/* Check if buffer can be used for DES DMA. It requires to be: - * 1) Word-aligned - * 2) Located in 0x20000000-0x2FFFFFFF region - */ -static bool des_dma_buff_compat(const void *buff, unsigned buff_size) -{ - uint32_t buff_ = (uint32_t) buff; - - return (((buff_ & 0x03) == 0) && /* Word-aligned */ - (((unsigned) buff_) >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ - ((((unsigned) buff) + buff_size) <= 0x30000000)); -} - static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output); @@ -323,7 +314,7 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! des_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! des_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } From 77c53f8d06dcc2986ef26be758d70cea2e642139 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 27 Sep 2017 17:32:58 +0800 Subject: [PATCH 057/118] Coordinate crypto interrupt handler among AES/PRNG --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 2 -- .../TARGET_NUVOTON/TARGET_M480/crypto-misc.c | 15 +++++++++++++ .../TARGET_NUVOTON/TARGET_M480/crypto-misc.h | 8 +++++++ .../TARGET_NUC472/aes/aes_alt.c | 2 -- .../TARGET_NUC472/crypto-misc.c | 15 +++++++++++++ .../TARGET_NUC472/crypto-misc.h | 8 +++++++ targets/TARGET_NUVOTON/TARGET_M480/trng_api.c | 21 +------------------ .../TARGET_NUVOTON/TARGET_NUC472/trng_api.c | 21 +------------------ 8 files changed, 48 insertions(+), 44 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 3296f01532..faca8ca3b8 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -43,8 +43,6 @@ static void mbedtls_zeroize( void *v, size_t n ) while( n-- ) *p++ = 0; } -extern volatile int g_AES_done; - /* DMA compatible backup buffer if user buffer doesn't meet requirements * * MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c index 714438e012..52018f237b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c @@ -24,6 +24,9 @@ #include "nu_bitutil.h" #include "crypto-misc.h" +volatile int g_PRNG_done; +volatile int g_AES_done; + /* Track if AES H/W is available */ static uint16_t crypto_aes_avail = 1; /* Track if DES H/W is available */ @@ -142,3 +145,15 @@ static void crypto_submodule_release(uint16_t *submodule_avail) uint16_t expectedCurrentValue = 0; while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); } + +/* Crypto interrupt handler */ +void CRYPTO_IRQHandler() +{ + if (PRNG_GET_INT_FLAG()) { + g_PRNG_done = 1; + PRNG_CLR_INT_FLAG(); + } else if (AES_GET_INT_FLAG()) { + g_AES_done = 1; + AES_CLR_INT_FLAG(); + } +} diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h index d64b9629c6..7ac7e399ab 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h @@ -23,6 +23,14 @@ extern "C" { #endif +/* Flags to indicate crypto H/W operation has done + * + * Crypto driver would clear it before trigger and wait for it. + * Crypto interrupt handler would set it on done or error. + */ +extern volatile int g_PRNG_done; +extern volatile int g_AES_done; + /* Init/Uninit crypto module */ void crypto_init(void); void crypto_uninit(void); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index ce918d4e16..dcddf1da74 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -43,8 +43,6 @@ static void mbedtls_zeroize( void *v, size_t n ) while( n-- ) *p++ = 0; } -extern volatile int g_AES_done; - /* DMA compatible backup buffer if user buffer doesn't meet requirements * * MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c index 714438e012..52018f237b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c @@ -24,6 +24,9 @@ #include "nu_bitutil.h" #include "crypto-misc.h" +volatile int g_PRNG_done; +volatile int g_AES_done; + /* Track if AES H/W is available */ static uint16_t crypto_aes_avail = 1; /* Track if DES H/W is available */ @@ -142,3 +145,15 @@ static void crypto_submodule_release(uint16_t *submodule_avail) uint16_t expectedCurrentValue = 0; while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); } + +/* Crypto interrupt handler */ +void CRYPTO_IRQHandler() +{ + if (PRNG_GET_INT_FLAG()) { + g_PRNG_done = 1; + PRNG_CLR_INT_FLAG(); + } else if (AES_GET_INT_FLAG()) { + g_AES_done = 1; + AES_CLR_INT_FLAG(); + } +} diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h index d64b9629c6..7ac7e399ab 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h @@ -23,6 +23,14 @@ extern "C" { #endif +/* Flags to indicate crypto H/W operation has done + * + * Crypto driver would clear it before trigger and wait for it. + * Crypto interrupt handler would set it on done or error. + */ +extern volatile int g_PRNG_done; +extern volatile int g_AES_done; + /* Init/Uninit crypto module */ void crypto_init(void); void crypto_uninit(void); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c index 74cabee52a..eeb0a34730 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c @@ -29,25 +29,6 @@ #define PRNG_KEY_SIZE (0x20UL) -static volatile int g_PRNG_done; -volatile int g_AES_done; - -/* Implementation that should never be optimized out by the compiler */ -static void trng_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; -} - -void CRYPTO_IRQHandler() -{ - if (PRNG_GET_INT_FLAG()) { - g_PRNG_done = 1; - PRNG_CLR_INT_FLAG(); - } else if (AES_GET_INT_FLAG()) { - g_AES_done = 1; - AES_CLR_INT_FLAG(); - } -} - static void trng_get(unsigned char *pConversionData) { uint32_t *p32ConversionData; @@ -97,7 +78,7 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l trng_get(tmpBuff); memcpy(output, tmpBuff, length); cur_length += length; - trng_zeroize(tmpBuff, sizeof(tmpBuff)); + crypto_zeroize(tmpBuff, sizeof(tmpBuff)); } *output_length = cur_length; return 0; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c index 1b6b24cf06..b705b7c585 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c @@ -34,25 +34,6 @@ #define PRNG_KEY_SIZE (0x20UL) -static volatile int g_PRNG_done; -volatile int g_AES_done; - -/* Implementation that should never be optimized out by the compiler */ -static void trng_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; -} - -void CRYPTO_IRQHandler() -{ - if (PRNG_GET_INT_FLAG()) { - g_PRNG_done = 1; - PRNG_CLR_INT_FLAG(); - } else if (AES_GET_INT_FLAG()) { - g_AES_done = 1; - AES_CLR_INT_FLAG(); - } -} - static void trng_get(unsigned char *pConversionData) { uint32_t *p32ConversionData; @@ -102,7 +83,7 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l trng_get(tmpBuff); memcpy(output, tmpBuff, length); cur_length += length; - trng_zeroize(tmpBuff, sizeof(tmpBuff)); + crypto_zeroize(tmpBuff, sizeof(tmpBuff)); } *output_length = cur_length; return 0; From 0a56b34d0eb8ffe3f0ef7cb291e611a6097c175f Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 27 Sep 2017 18:42:12 +0800 Subject: [PATCH 058/118] Refine AES alter. key endianness code --- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 7 ++----- .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 7 ++----- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index faca8ca3b8..fca7ce9026 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -87,12 +87,9 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); } - // key swap + /* Fetch key byte data in big-endian */ for( i = 0; i < ( keybits >> 5 ); i++ ) { - ctx->keys[i] = (*(key+i*4) << 24) | - (*(key+1+i*4) << 16) | - (*(key+2+i*4) << 8) | - (*(key+3+i*4) ); + ctx->keys[i] = nu_get32_be(key + i * 4); } return( 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index dcddf1da74..50f41fd4a6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -87,12 +87,9 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); } - // key swap + /* Fetch key byte data in big-endian */ for( i = 0; i < ( keybits >> 5 ); i++ ) { - ctx->keys[i] = (*(key+i*4) << 24) | - (*(key+1+i*4) << 16) | - (*(key+2+i*4) << 8) | - (*(key+3+i*4) ); + ctx->keys[i] = nu_get32_be(key + i * 4); } return( 0 ); From 56087fe0a4a0c3041be114510828df5062601ee7 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Fri, 29 Sep 2017 14:19:17 +0800 Subject: [PATCH 059/118] Fix compile error as mbedtls is not included Currently, trng_api.c is located in targets/ and AES/DES/SHA alter. are located in mbedtls/. They have shared crypto code. If they could locate at same location e.g. mbedtls/, the shared crypto code placement would be more reasonable. --- .../TARGET_NUVOTON/TARGET_M480/crypto}/crypto-misc.c | 0 .../TARGET_NUVOTON/TARGET_M480/crypto}/crypto-misc.h | 0 .../TARGET_NUVOTON/TARGET_NUC472/crypto}/crypto-misc.c | 0 .../TARGET_NUVOTON/TARGET_NUC472/crypto}/crypto-misc.h | 0 4 files changed, 0 insertions(+), 0 deletions(-) rename {features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480 => targets/TARGET_NUVOTON/TARGET_M480/crypto}/crypto-misc.c (100%) rename {features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480 => targets/TARGET_NUVOTON/TARGET_M480/crypto}/crypto-misc.h (100%) rename {features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472 => targets/TARGET_NUVOTON/TARGET_NUC472/crypto}/crypto-misc.c (100%) rename {features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472 => targets/TARGET_NUVOTON/TARGET_NUC472/crypto}/crypto-misc.h (100%) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c similarity index 100% rename from features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c rename to targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h similarity index 100% rename from features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h rename to targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c similarity index 100% rename from features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h similarity index 100% rename from features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h From ad7024687e67af6a65597351020200b643fa8299 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Mon, 6 Nov 2017 11:37:29 +0800 Subject: [PATCH 060/118] Fix compile error with disabled crypto For example, even though MBEDTLS_SHA512_C is disabled (via #undef MBEDTLS_SHA512_C), mbedtls_sha512_context is still necessary due to referenced in sha512.h. --- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h | 2 -- .../TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h | 2 -- .../TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h | 8 -------- .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h | 2 -- .../TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h | 2 -- .../TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h | 2 -- .../targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h | 6 ------ 16 files changed, 42 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index e907fd62e3..23625b5b67 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -25,7 +25,6 @@ #include "mbedtls/aes.h" -#if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation // @@ -259,6 +258,5 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, #endif /* MBEDTLS_AES_ALT */ -#endif /* MBEDTLS_AES_C */ #endif /* aes_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h index 9fda2763a1..09b693c524 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h @@ -19,7 +19,6 @@ #include "mbedtls/des.h" -#if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include @@ -271,6 +270,5 @@ void mbedtls_des_setkey( uint32_t SK[32], #endif #endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ #endif /* des_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h index 9471b628ba..9e1fa6a73d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h @@ -18,7 +18,6 @@ #include "mbedtls/sha1.h" -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include "sha_alt_hw.h" @@ -95,6 +94,5 @@ void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[6 #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h index 416779ed3c..5ba3aa853d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h @@ -23,7 +23,6 @@ #ifndef MBEDTLS_SHA1_ALT_SW_H #define MBEDTLS_SHA1_ALT_SW_H -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include @@ -98,6 +97,5 @@ void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h index eedca82eea..53ca35ffd3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h @@ -18,7 +18,6 @@ #include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include "sha_alt_hw.h" @@ -97,6 +96,5 @@ void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char da #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h index c10b08144e..6c292b7516 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h @@ -23,7 +23,6 @@ #ifndef MBEDTLS_SHA256_ALT_SW_H #define MBEDTLS_SHA256_ALT_SW_H -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include @@ -101,6 +100,5 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h index f4c6f75b37..a028beeeb0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h @@ -18,7 +18,6 @@ #include "mbedtls/sha512.h" -#if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) #include "sha_alt_hw.h" @@ -97,6 +96,5 @@ void mbedtls_sha512_process( mbedtls_sha512_context *ctx, const unsigned char da #endif #endif /* MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA512_C */ #endif /* sha512_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h index 485d01105b..6c0aed4056 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h @@ -23,7 +23,6 @@ #ifndef MBEDTLS_SHA512_ALT_SW_H #define MBEDTLS_SHA512_ALT_SW_H -#if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) #include @@ -101,6 +100,5 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c #endif #endif /* MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA512_C */ #endif /* sha512_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h index bc833c2e5d..e8cad3b2de 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h @@ -16,7 +16,6 @@ #ifndef MBEDTLS_SHA_ALT_HW_H #define MBEDTLS_SHA_ALT_HW_H -#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) #include @@ -44,7 +43,6 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast); void crypto_sha_getinternstate(unsigned char output[], size_t olen); -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); @@ -57,9 +55,7 @@ void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ) void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); @@ -73,9 +69,7 @@ void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ -#if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) void mbedtls_sha512_hw_init( crypto_sha_context *ctx ); @@ -89,13 +83,11 @@ void mbedtls_sha512_hw_finish( crypto_sha_context *ctx, unsigned char output[64] void mbedtls_sha512_hw_process( crypto_sha_context *ctx, const unsigned char data[128] ); #endif /* MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA512_C */ #ifdef __cplusplus } #endif #endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C*/ #endif /* sha_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index e907fd62e3..23625b5b67 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -25,7 +25,6 @@ #include "mbedtls/aes.h" -#if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation // @@ -259,6 +258,5 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, #endif /* MBEDTLS_AES_ALT */ -#endif /* MBEDTLS_AES_C */ #endif /* aes_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h index 9fda2763a1..09b693c524 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h @@ -19,7 +19,6 @@ #include "mbedtls/des.h" -#if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include @@ -271,6 +270,5 @@ void mbedtls_des_setkey( uint32_t SK[32], #endif #endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ #endif /* des_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h index 9471b628ba..9e1fa6a73d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h @@ -18,7 +18,6 @@ #include "mbedtls/sha1.h" -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include "sha_alt_hw.h" @@ -95,6 +94,5 @@ void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[6 #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h index 3be7272be6..7c84756481 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h @@ -25,7 +25,6 @@ #include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include @@ -100,6 +99,5 @@ void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h index eedca82eea..53ca35ffd3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h @@ -18,7 +18,6 @@ #include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include "sha_alt_hw.h" @@ -97,6 +96,5 @@ void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char da #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h index feb75a3604..bd96f5cdda 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h @@ -25,7 +25,6 @@ #include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include @@ -103,6 +102,5 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h index b43ac43e46..c66632b9de 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h @@ -16,7 +16,6 @@ #ifndef MBEDTLS_SHA_ALT_HW_H #define MBEDTLS_SHA_ALT_HW_H -#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) #include @@ -44,7 +43,6 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast); void crypto_sha_getinternstate(unsigned char output[], size_t olen); -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); @@ -57,9 +55,7 @@ void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ) void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); @@ -73,13 +69,11 @@ void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #ifdef __cplusplus } #endif #endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */ #endif /* sha_alt_hw.h */ From 0b5160273425a86a1943bc11e6e741390999b5c4 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 7 Nov 2017 14:00:16 +0800 Subject: [PATCH 061/118] Refine AES/DES alter. DMA buffer requirement comment --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 14 ++++++++++---- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 14 ++++++++++---- .../TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 14 ++++++++++---- .../TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 14 ++++++++++---- 4 files changed, 40 insertions(+), 16 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index fca7ce9026..e527e23004 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -43,10 +43,15 @@ static void mbedtls_zeroize( void *v, size_t n ) while( n-- ) *p++ = 0; } -/* DMA compatible backup buffer if user buffer doesn't meet requirements +/* AES DMA compatible backup buffer if user buffer doesn't meet requirements * - * MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. - * Its value is estimated to trade memory footprint off against performance. + * AES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * AES DMA buffer size MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. + * Its value is estimated to trade memory footprint off against performance. + * */ #define MAX_DMA_CHAIN_SIZE (16*6) MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; @@ -133,7 +138,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || + (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 342824d5ea..cd5e287e24 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -26,10 +26,15 @@ #include "mbed_toolchain.h" #include "mbed_error.h" -/* DMA buffer +/* DES DMA compatible buffer requirements * - * MAXSIZE_DMABUF must be a multiple of 64-bit block size. - * Its value is estimated to trade memory footprint off against performance. + * DES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * DES DMA buffer size MAXSIZE_DMABUF must be a multiple of 64-bit block size. + * Its value is estimated to trade memory footprint off against performance. + * */ #define MAXSIZE_DMABUF (8 * 5) MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; @@ -314,7 +319,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || + (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 50f41fd4a6..d3fe7bebd6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -43,10 +43,15 @@ static void mbedtls_zeroize( void *v, size_t n ) while( n-- ) *p++ = 0; } -/* DMA compatible backup buffer if user buffer doesn't meet requirements +/* AES DMA compatible backup buffer if user buffer doesn't meet requirements * - * MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. - * Its value is estimated to trade memory footprint off against performance. + * AES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * AES DMA buffer size MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. + * Its value is estimated to trade memory footprint off against performance. + * */ #define MAX_DMA_CHAIN_SIZE (16*6) MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; @@ -133,7 +138,8 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || + (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 342824d5ea..cd5e287e24 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -26,10 +26,15 @@ #include "mbed_toolchain.h" #include "mbed_error.h" -/* DMA buffer +/* DES DMA compatible buffer requirements * - * MAXSIZE_DMABUF must be a multiple of 64-bit block size. - * Its value is estimated to trade memory footprint off against performance. + * DES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * DES DMA buffer size MAXSIZE_DMABUF must be a multiple of 64-bit block size. + * Its value is estimated to trade memory footprint off against performance. + * */ #define MAXSIZE_DMABUF (8 * 5) MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; @@ -314,7 +319,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S * 1) Word-aligned * 2) Located in 0x2xxxxxxx region */ - if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || + (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } From 402d2d26ec93180145d3e6a85ddd8eb3d1335bbf Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 8 Nov 2017 10:19:21 +0800 Subject: [PATCH 062/118] Strengthen crypto DMA buffer check 1. Catch incompatible buffer range, where buffer base = 0xffffff00 and buffer size = 0x100. 2. Add buffer size alignment check. --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 15 ++++++++------- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 11 ++++++----- .../TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 15 ++++++++------- .../TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 11 ++++++----- .../TARGET_M480/crypto/crypto-misc.c | 10 +++++----- .../TARGET_M480/crypto/crypto-misc.h | 10 +++++----- .../TARGET_NUC472/crypto/crypto-misc.c | 10 +++++----- .../TARGET_NUC472/crypto/crypto-misc.h | 10 +++++----- 8 files changed, 48 insertions(+), 44 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index e527e23004..072b0e4d1b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -134,12 +134,13 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, MBED_ASSERT((dataSize % 16 == 0) && (dataSize <= MAX_DMA_CHAIN_SIZE)); - /* AES DMA buffer requires to be: - * 1) Word-aligned - * 2) Located in 0x2xxxxxxx region + /* AES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 16-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region */ - if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || - (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE, 16)) || + (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE, 16))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } @@ -160,14 +161,14 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->keys, ctx->keySize); /* AES DMA buffer requirements same as above */ - if (! crypto_dma_buff_compat(input, dataSize)) { + if (! crypto_dma_buff_compat(input, dataSize, 16)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = input; } /* AES DMA buffer requirements same as above */ - if (! crypto_dma_buff_compat(output, dataSize)) { + if (! crypto_dma_buff_compat(output, dataSize, 16)) { pOut = au8OutputData; } else { pOut = output; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index cd5e287e24..e2b83b6370 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -315,12 +315,13 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } - /* DES DMA buffer requires to be: - * 1) Word-aligned - * 2) Located in 0x2xxxxxxx region + /* DES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 8-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region */ - if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || - (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF, 8)) || + (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF, 8))) { error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index d3fe7bebd6..86de2130f6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -134,12 +134,13 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, MBED_ASSERT((dataSize % 16 == 0) && (dataSize <= MAX_DMA_CHAIN_SIZE)); - /* AES DMA buffer requires to be: - * 1) Word-aligned - * 2) Located in 0x2xxxxxxx region + /* AES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 16-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region */ - if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE)) || - (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE))) { + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE, 16)) || + (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE, 16))) { error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } @@ -160,14 +161,14 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->keys, ctx->keySize); /* AES DMA buffer requirements same as above */ - if (! crypto_dma_buff_compat(input, dataSize)) { + if (! crypto_dma_buff_compat(input, dataSize, 16)) { memcpy(au8InputData, input, dataSize); pIn = au8InputData; } else { pIn = input; } /* AES DMA buffer requirements same as above */ - if (! crypto_dma_buff_compat(output, dataSize)) { + if (! crypto_dma_buff_compat(output, dataSize, 16)) { pOut = au8OutputData; } else { pOut = output; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index cd5e287e24..e2b83b6370 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -315,12 +315,13 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } - /* DES DMA buffer requires to be: - * 1) Word-aligned - * 2) Located in 0x2xxxxxxx region + /* DES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 8-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region */ - if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF)) || - (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF))) { + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF, 8)) || + (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF, 8))) { error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c index 52018f237b..4c4c52d04f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c @@ -125,13 +125,13 @@ void crypto_sha_release(void) crypto_submodule_release(&crypto_sha_avail); } -bool crypto_dma_buff_compat(const void *buff, size_t buff_size) +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) { uint32_t buff_ = (uint32_t) buff; - - return (((buff_ & 0x03) == 0) && /* Word-aligned */ - (buff_ >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ - ((buff_ + buff_size) <= 0x30000000)); + + return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */ + ((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */ + (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ } static bool crypto_submodule_acquire(uint16_t *submodule_avail) diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h index 7ac7e399ab..1527a59c6d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h @@ -52,12 +52,12 @@ void crypto_des_release(void); bool crypto_sha_acquire(void); void crypto_sha_release(void); -/* Check if buffer can be used for crypto DMA. It requires to be: - * - * 1) Word-aligned - * 2) Located in 0x20000000-0x2FFFFFFF region +/* Check if buffer can be used for crypto DMA. It has the following requirements: + * (1) Word-aligned buffer base address + * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. + * (3) Located in 0x20000000-0x2FFFFFFF region */ -bool crypto_dma_buff_compat(const void *buff, size_t buff_size); +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); #ifdef __cplusplus } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c index 52018f237b..4c4c52d04f 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c @@ -125,13 +125,13 @@ void crypto_sha_release(void) crypto_submodule_release(&crypto_sha_avail); } -bool crypto_dma_buff_compat(const void *buff, size_t buff_size) +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) { uint32_t buff_ = (uint32_t) buff; - - return (((buff_ & 0x03) == 0) && /* Word-aligned */ - (buff_ >= 0x20000000) && /* 0x20000000-0x2FFFFFFF */ - ((buff_ + buff_size) <= 0x30000000)); + + return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */ + ((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */ + (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ } static bool crypto_submodule_acquire(uint16_t *submodule_avail) diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h index 7ac7e399ab..1527a59c6d 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h @@ -52,12 +52,12 @@ void crypto_des_release(void); bool crypto_sha_acquire(void); void crypto_sha_release(void); -/* Check if buffer can be used for crypto DMA. It requires to be: - * - * 1) Word-aligned - * 2) Located in 0x20000000-0x2FFFFFFF region +/* Check if buffer can be used for crypto DMA. It has the following requirements: + * (1) Word-aligned buffer base address + * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. + * (3) Located in 0x20000000-0x2FFFFFFF region */ -bool crypto_dma_buff_compat(const void *buff, size_t buff_size); +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); #ifdef __cplusplus } From e7f75b069fbf555c533842c5a69734a81b890683 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 8 Nov 2017 11:32:34 +0800 Subject: [PATCH 063/118] Fix SHA H/W is not stopped in corner case Take SHA1 for example, without the fix, SHA H/W is not stopped in either case: (1) ctx->total == 0 in mbedtls_sha1_hw_finish() (2) mbedtls_sha1_hw_finish() is not called by upper layer --- .../TARGET_M480/sha/sha_alt_hw.c | 18 ++++++++++++------ .../TARGET_NUC472/sha/sha_alt_hw.c | 12 ++++++++---- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index 57fc0139b1..d5e93cc5af 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -50,6 +50,8 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) return; } + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; + /* Uninit crypto module */ crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); @@ -91,8 +93,6 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, 20); - - CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } else { mbedtls_sha1_sw_context ctx_sw; @@ -101,6 +101,8 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) mbedtls_sha1_sw_finish(&ctx_sw, output); mbedtls_sha1_sw_free(&ctx_sw); } + + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) @@ -127,6 +129,8 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) return; } + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; + /* Uninit crypto module */ crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); @@ -169,8 +173,6 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224_384 ? 28 : 32); - - CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } else { mbedtls_sha256_sw_context ctx_sw; @@ -179,6 +181,8 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) mbedtls_sha256_sw_finish(&ctx_sw, output); mbedtls_sha256_sw_free(&ctx_sw); } + + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) @@ -206,6 +210,8 @@ void mbedtls_sha512_hw_free(crypto_sha_context *ctx) return; } + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; + /* Uninit crypto module */ crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); @@ -248,8 +254,6 @@ void mbedtls_sha512_hw_finish(crypto_sha_context *ctx, unsigned char output[64]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224_384 ? 48 : 64); - - CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } else { mbedtls_sha512_sw_context ctx_sw; @@ -258,6 +262,8 @@ void mbedtls_sha512_hw_finish(crypto_sha_context *ctx, unsigned char output[64]) mbedtls_sha512_sw_finish(&ctx_sw, output); mbedtls_sha512_sw_free(&ctx_sw); } + + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } void mbedtls_sha512_hw_process(crypto_sha_context *ctx, const unsigned char data[128]) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index ab8181cc65..2a7c52f025 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -50,6 +50,8 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) return; } + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; + /* Uninit crypto module */ crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); @@ -91,8 +93,6 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, 20); - - CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; } else { mbedtls_sha1_sw_context ctx_sw; @@ -101,6 +101,8 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) mbedtls_sha1_sw_finish(&ctx_sw, output); mbedtls_sha1_sw_free(&ctx_sw); } + + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; } void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) @@ -127,6 +129,8 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) return; } + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; + /* Uninit crypto module */ crypto_uninit(); crypto_zeroize(ctx, sizeof(crypto_sha_context)); @@ -169,8 +173,6 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224 ? 28 : 32); - - CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; } else { mbedtls_sha256_sw_context ctx_sw; @@ -179,6 +181,8 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) mbedtls_sha256_sw_finish(&ctx_sw, output); mbedtls_sha256_sw_free(&ctx_sw); } + + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; } void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) From e1714d1d58bc04062bfca0d5ca0a63828088654d Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 9 Nov 2017 09:19:36 +0800 Subject: [PATCH 064/118] Fix SHA H/W resource leakage in context cloning --- .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c | 15 +++++++++++++++ .../TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c | 15 +++++++++++++++ .../TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c | 15 +++++++++++++++ .../TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c | 15 +++++++++++++++ .../TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c | 15 +++++++++++++++ 5 files changed, 75 insertions(+) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index 5ef56e9040..21ce76f954 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -51,6 +51,21 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { + // If dst is H/W context, we need to change it to S/W context first before cloning to. + while (dst->ishw) { + mbedtls_sha1_free(dst); + // We just want S/W context, so we lock SHA H/W resource if it is available. + if (crypto_sha_acquire()) { + mbedtls_sha1_init(dst); + crypto_sha_release(); + } + else { + mbedtls_sha1_init(dst); + } + + // We still have potential to get H/W context due to race condition. Retry if need be. + } + if (src->ishw) { // Clone S/W ctx from H/W ctx dst->ishw = 0; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index 4c95a206cc..414dc2e74f 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -51,6 +51,21 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { + // If dst is H/W context, we need to change it to S/W context first before cloning to. + while (dst->ishw) { + mbedtls_sha256_free(dst); + // We just want S/W context, so we lock SHA H/W resource if it is available. + if (crypto_sha_acquire()) { + mbedtls_sha256_init(dst); + crypto_sha_release(); + } + else { + mbedtls_sha256_init(dst); + } + + // We still have potential to get H/W context due to race condition. Retry if need be. + } + if (src->ishw) { // Clone S/W ctx from H/W ctx dst->ishw = 0; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index a36fc2b680..6114ad82f3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -51,6 +51,21 @@ void mbedtls_sha512_free(mbedtls_sha512_context *ctx) void mbedtls_sha512_clone(mbedtls_sha512_context *dst, const mbedtls_sha512_context *src) { + // If dst is H/W context, we need to change it to S/W context first before cloning to. + while (dst->ishw) { + mbedtls_sha512_free(dst); + // We just want S/W context, so we lock SHA H/W resource if it is available. + if (crypto_sha_acquire()) { + mbedtls_sha512_init(dst); + crypto_sha_release(); + } + else { + mbedtls_sha512_init(dst); + } + + // We still have potential to get H/W context due to race condition. Retry if need be. + } + if (src->ishw) { // Clone S/W ctx from H/W ctx dst->ishw = 0; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index 5ef56e9040..21ce76f954 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -51,6 +51,21 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { + // If dst is H/W context, we need to change it to S/W context first before cloning to. + while (dst->ishw) { + mbedtls_sha1_free(dst); + // We just want S/W context, so we lock SHA H/W resource if it is available. + if (crypto_sha_acquire()) { + mbedtls_sha1_init(dst); + crypto_sha_release(); + } + else { + mbedtls_sha1_init(dst); + } + + // We still have potential to get H/W context due to race condition. Retry if need be. + } + if (src->ishw) { // Clone S/W ctx from H/W ctx dst->ishw = 0; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index 965b026099..2bbf66b099 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -51,6 +51,21 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { + // If dst is H/W context, we need to change it to S/W context first before cloning to. + while (dst->ishw) { + mbedtls_sha256_free(dst); + // We just want S/W context, so we lock SHA H/W resource if it is available. + if (crypto_sha_acquire()) { + mbedtls_sha256_init(dst); + crypto_sha_release(); + } + else { + mbedtls_sha256_init(dst); + } + + // We still have potential to get H/W context due to race condition. Retry if need be. + } + if (src->ishw) { // Clone S/W ctx from H/W ctx dst->ishw = 0; From 2ba799462aae151cf297069f9479eeba8db62f26 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 9 Nov 2017 09:36:25 +0800 Subject: [PATCH 065/118] Guard against SHA internal state size is not word-aligned in SHA alter. --- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c | 5 +++++ .../targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index d5e93cc5af..81d16bfdd7 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -24,6 +24,7 @@ #include "nu_bitutil.h" #include "mbed_assert.h" +#include "mbed_error.h" #include "crypto-misc.h" #include @@ -416,6 +417,10 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input void crypto_sha_getinternstate(unsigned char output[], size_t olen) { + if (olen & 0x3) { + error("Internal error in SHA alter. SHA internal state size requires to be a multiple of 4 bytes."); + } + uint32_t *in_pos = (uint32_t *) &CRPT->HMAC_DGST[0]; unsigned char *out_pos = output; uint32_t rmn = olen; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index 2a7c52f025..b09a9c34e5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -24,6 +24,7 @@ #include "nu_bitutil.h" #include "mbed_assert.h" +#include "mbed_error.h" #include "crypto-misc.h" #include @@ -312,6 +313,10 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input void crypto_sha_getinternstate(unsigned char output[], size_t olen) { + if (olen & 0x3) { + error("Internal error in SHA alter. SHA internal state size requires to be a multiple of 4 bytes."); + } + uint32_t *in_pos = (uint32_t *) &CRPT->SHA_DGST0; unsigned char *out_pos = output; uint32_t rmn = olen; From 5498bdad87c36960dd5142c11b8c79f24589fd67 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 9 Nov 2017 15:55:42 +0800 Subject: [PATCH 066/118] Refine code with SHA context selection in SHA alter. --- .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c | 29 ++++++++++--------- .../TARGET_M480/sha/sha256_alt.c | 29 ++++++++++--------- .../TARGET_M480/sha/sha512_alt.c | 29 ++++++++++--------- .../TARGET_NUC472/sha/sha1_alt.c | 29 ++++++++++--------- .../TARGET_NUC472/sha/sha256_alt.c | 29 ++++++++++--------- 5 files changed, 80 insertions(+), 65 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index 21ce76f954..4265a79537 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -23,9 +23,15 @@ #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { + if (try_hw && crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha1_hw_init(&ctx->hw_ctx); } else { @@ -34,6 +40,11 @@ void mbedtls_sha1_init(mbedtls_sha1_context *ctx) } } +void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +{ + mbedtls_sha1_init_internal(ctx, 1); +} + void mbedtls_sha1_free(mbedtls_sha1_context *ctx) { if (ctx == NULL) { @@ -52,18 +63,10 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - while (dst->ishw) { + if (dst->ishw) { mbedtls_sha1_free(dst); - // We just want S/W context, so we lock SHA H/W resource if it is available. - if (crypto_sha_acquire()) { - mbedtls_sha1_init(dst); - crypto_sha_release(); - } - else { - mbedtls_sha1_init(dst); - } - - // We still have potential to get H/W context due to race condition. Retry if need be. + // Force S/W context + mbedtls_sha1_init_internal(dst, 0); } if (src->ishw) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index 414dc2e74f..a4f608a8a3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -23,9 +23,15 @@ #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { + if (try_hw && crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha256_hw_init(&ctx->hw_ctx); } else { @@ -34,6 +40,11 @@ void mbedtls_sha256_init(mbedtls_sha256_context *ctx) } } +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +{ + mbedtls_sha256_init_internal(ctx, 1); +} + void mbedtls_sha256_free(mbedtls_sha256_context *ctx) { if (ctx == NULL) { @@ -52,18 +63,10 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - while (dst->ishw) { + if (dst->ishw) { mbedtls_sha256_free(dst); - // We just want S/W context, so we lock SHA H/W resource if it is available. - if (crypto_sha_acquire()) { - mbedtls_sha256_init(dst); - crypto_sha_release(); - } - else { - mbedtls_sha256_init(dst); - } - - // We still have potential to get H/W context due to race condition. Retry if need be. + // Force S/W context + mbedtls_sha256_init_internal(dst, 0); } if (src->ishw) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index 6114ad82f3..bf4b704428 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -23,9 +23,15 @@ #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha512_init(mbedtls_sha512_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha512_init_internal(mbedtls_sha512_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { + if (try_hw && crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha512_hw_init(&ctx->hw_ctx); } else { @@ -34,6 +40,11 @@ void mbedtls_sha512_init(mbedtls_sha512_context *ctx) } } +void mbedtls_sha512_init(mbedtls_sha512_context *ctx) +{ + mbedtls_sha512_init_internal(ctx, 1); +} + void mbedtls_sha512_free(mbedtls_sha512_context *ctx) { if (ctx == NULL) { @@ -52,18 +63,10 @@ void mbedtls_sha512_clone(mbedtls_sha512_context *dst, const mbedtls_sha512_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - while (dst->ishw) { + if (dst->ishw) { mbedtls_sha512_free(dst); - // We just want S/W context, so we lock SHA H/W resource if it is available. - if (crypto_sha_acquire()) { - mbedtls_sha512_init(dst); - crypto_sha_release(); - } - else { - mbedtls_sha512_init(dst); - } - - // We still have potential to get H/W context due to race condition. Retry if need be. + // Force S/W context + mbedtls_sha512_init_internal(dst, 0); } if (src->ishw) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index 21ce76f954..4265a79537 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -23,9 +23,15 @@ #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { + if (try_hw && crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha1_hw_init(&ctx->hw_ctx); } else { @@ -34,6 +40,11 @@ void mbedtls_sha1_init(mbedtls_sha1_context *ctx) } } +void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +{ + mbedtls_sha1_init_internal(ctx, 1); +} + void mbedtls_sha1_free(mbedtls_sha1_context *ctx) { if (ctx == NULL) { @@ -52,18 +63,10 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - while (dst->ishw) { + if (dst->ishw) { mbedtls_sha1_free(dst); - // We just want S/W context, so we lock SHA H/W resource if it is available. - if (crypto_sha_acquire()) { - mbedtls_sha1_init(dst); - crypto_sha_release(); - } - else { - mbedtls_sha1_init(dst); - } - - // We still have potential to get H/W context due to race condition. Retry if need be. + // Force S/W context + mbedtls_sha1_init_internal(dst, 0); } if (src->ishw) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index 2bbf66b099..1d608b54c5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -23,9 +23,15 @@ #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { + if (try_hw && crypto_sha_acquire()) { ctx->ishw = 1; mbedtls_sha256_hw_init(&ctx->hw_ctx); } else { @@ -34,6 +40,11 @@ void mbedtls_sha256_init(mbedtls_sha256_context *ctx) } } +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +{ + mbedtls_sha256_init_internal(ctx, 1); +} + void mbedtls_sha256_free(mbedtls_sha256_context *ctx) { if (ctx == NULL) { @@ -52,18 +63,10 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - while (dst->ishw) { + if (dst->ishw) { mbedtls_sha256_free(dst); - // We just want S/W context, so we lock SHA H/W resource if it is available. - if (crypto_sha_acquire()) { - mbedtls_sha256_init(dst); - crypto_sha_release(); - } - else { - mbedtls_sha256_init(dst); - } - - // We still have potential to get H/W context due to race condition. Retry if need be. + // Force S/W context + mbedtls_sha256_init_internal(dst, 0); } if (src->ishw) { From 1c8128831bc06f6ac652a1b04819dd583e6b2a2a Mon Sep 17 00:00:00 2001 From: ccli8 Date: Mon, 20 Nov 2017 09:17:52 +0800 Subject: [PATCH 067/118] Remove superfluous code in AES alter. --- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 7 ++----- .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 7 ++----- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 072b0e4d1b..c53c38600c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -274,11 +274,8 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, while( length > 0 ) { blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; - if( mode == MBEDTLS_AES_ENCRYPT ) { - __nvt_aes_crypt(ctx, input, output, blockChainLen); - } else { - __nvt_aes_crypt(ctx, input, output, blockChainLen); - } + __nvt_aes_crypt(ctx, input, output, blockChainLen); + length -= blockChainLen; input += blockChainLen; output += blockChainLen; diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 86de2130f6..1de420b53a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -274,11 +274,8 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, while( length > 0 ) { blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; - if( mode == MBEDTLS_AES_ENCRYPT ) { - __nvt_aes_crypt(ctx, input, output, blockChainLen); - } else { - __nvt_aes_crypt(ctx, input, output, blockChainLen); - } + __nvt_aes_crypt(ctx, input, output, blockChainLen); + length -= blockChainLen; input += blockChainLen; output += blockChainLen; From 7bd32f2bd4e1d4b225fc64717c3aaf9a16b6e7a1 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 21 Nov 2017 11:42:21 +0800 Subject: [PATCH 068/118] Fix multiple calls to SHA free in SHA alter. --- .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c | 32 +++++++++---------- .../TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h | 2 +- .../TARGET_M480/sha/sha256_alt.c | 32 +++++++++---------- .../TARGET_M480/sha/sha256_alt.h | 2 +- .../TARGET_M480/sha/sha512_alt.c | 32 +++++++++---------- .../TARGET_M480/sha/sha512_alt.h | 2 +- .../TARGET_NUC472/sha/sha1_alt.c | 32 +++++++++---------- .../TARGET_NUC472/sha/sha1_alt.h | 2 +- .../TARGET_NUC472/sha/sha256_alt.c | 32 +++++++++---------- .../TARGET_NUC472/sha/sha256_alt.h | 2 +- 10 files changed, 85 insertions(+), 85 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index 4265a79537..761c8c33d9 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -32,10 +32,10 @@ static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { if (try_hw && crypto_sha_acquire()) { - ctx->ishw = 1; + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha1_hw_init(&ctx->hw_ctx); } else { - ctx->ishw = 0; + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha1_sw_init(&ctx->sw_ctx); } } @@ -51,27 +51,27 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - if (dst->ishw) { + if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha1_free(dst); // Force S/W context mbedtls_sha1_init_internal(dst, 0); } - if (src->ishw) { + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -89,7 +89,7 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -100,9 +100,9 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, */ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_starts(&ctx->hw_ctx); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_starts(&ctx->sw_ctx); } } @@ -112,9 +112,9 @@ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) */ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -124,18 +124,18 @@ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, */ void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_finish(&ctx->hw_ctx, output); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_process(&ctx->hw_ctx, data); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h index 9e1fa6a73d..59f519fac9 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h @@ -33,7 +33,7 @@ struct mbedtls_sha1_context_s; * \brief SHA-1 context structure */ typedef struct mbedtls_sha1_context_s { - int ishw; + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha1_sw_context sw_ctx; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index a4f608a8a3..09ec8e4335 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -32,10 +32,10 @@ static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { if (try_hw && crypto_sha_acquire()) { - ctx->ishw = 1; + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha256_hw_init(&ctx->hw_ctx); } else { - ctx->ishw = 0; + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha256_sw_init(&ctx->sw_ctx); } } @@ -51,27 +51,27 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - if (dst->ishw) { + if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha256_free(dst); // Force S/W context mbedtls_sha256_init_internal(dst, 0); } - if (src->ishw) { + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -90,7 +90,7 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -101,9 +101,9 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, */ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224); } } @@ -113,9 +113,9 @@ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) */ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -125,18 +125,18 @@ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *inp */ void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_finish(&ctx->hw_ctx, output); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_process(&ctx->hw_ctx, data); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h index 53ca35ffd3..04ff65fd18 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h @@ -33,7 +33,7 @@ struct mbedtls_sha256_context_s; * \brief SHA-256 context structure */ typedef struct mbedtls_sha256_context_s { - int ishw; + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha256_sw_context sw_ctx; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index bf4b704428..ce25a5e861 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -32,10 +32,10 @@ static void mbedtls_sha512_init_internal(mbedtls_sha512_context *ctx, int try_hw) { if (try_hw && crypto_sha_acquire()) { - ctx->ishw = 1; + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha512_hw_init(&ctx->hw_ctx); } else { - ctx->ishw = 0; + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha512_sw_init(&ctx->sw_ctx); } } @@ -51,27 +51,27 @@ void mbedtls_sha512_free(mbedtls_sha512_context *ctx) return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha512_clone(mbedtls_sha512_context *dst, const mbedtls_sha512_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - if (dst->ishw) { + if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha512_free(dst); // Force S/W context mbedtls_sha512_init_internal(dst, 0); } - if (src->ishw) { + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -91,7 +91,7 @@ void mbedtls_sha512_clone(mbedtls_sha512_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha512_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -102,9 +102,9 @@ void mbedtls_sha512_clone(mbedtls_sha512_context *dst, */ void mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_starts(&ctx->hw_ctx, is384); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_starts(&ctx->sw_ctx, is384); } } @@ -114,9 +114,9 @@ void mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384) */ void mbedtls_sha512_update(mbedtls_sha512_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_update(&ctx->hw_ctx, input, ilen); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -126,18 +126,18 @@ void mbedtls_sha512_update(mbedtls_sha512_context *ctx, const unsigned char *inp */ void mbedtls_sha512_finish(mbedtls_sha512_context *ctx, unsigned char output[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_finish(&ctx->hw_ctx, output); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha512_process(mbedtls_sha512_context *ctx, const unsigned char data[128]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_process(&ctx->hw_ctx, data); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h index a028beeeb0..afd0294ca3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h @@ -33,7 +33,7 @@ struct mbedtls_sha512_context_s; * \brief SHA-512 context structure */ typedef struct mbedtls_sha512_context_s { - int ishw; + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha512_sw_context sw_ctx; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index 4265a79537..761c8c33d9 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -32,10 +32,10 @@ static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { if (try_hw && crypto_sha_acquire()) { - ctx->ishw = 1; + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha1_hw_init(&ctx->hw_ctx); } else { - ctx->ishw = 0; + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha1_sw_init(&ctx->sw_ctx); } } @@ -51,27 +51,27 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - if (dst->ishw) { + if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha1_free(dst); // Force S/W context mbedtls_sha1_init_internal(dst, 0); } - if (src->ishw) { + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -89,7 +89,7 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -100,9 +100,9 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, */ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_starts(&ctx->hw_ctx); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_starts(&ctx->sw_ctx); } } @@ -112,9 +112,9 @@ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) */ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -124,18 +124,18 @@ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, */ void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_finish(&ctx->hw_ctx, output); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_process(&ctx->hw_ctx, data); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h index 9e1fa6a73d..59f519fac9 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h @@ -33,7 +33,7 @@ struct mbedtls_sha1_context_s; * \brief SHA-1 context structure */ typedef struct mbedtls_sha1_context_s { - int ishw; + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha1_sw_context sw_ctx; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index 1d608b54c5..57ed6d5b3c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -32,10 +32,10 @@ static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { if (try_hw && crypto_sha_acquire()) { - ctx->ishw = 1; + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha256_hw_init(&ctx->hw_ctx); } else { - ctx->ishw = 0; + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha256_sw_init(&ctx->sw_ctx); } } @@ -51,27 +51,27 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { // If dst is H/W context, we need to change it to S/W context first before cloning to. - if (dst->ishw) { + if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha256_free(dst); // Force S/W context mbedtls_sha256_init_internal(dst, 0); } - if (src->ishw) { + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -90,7 +90,7 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -101,9 +101,9 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, */ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224); } } @@ -113,9 +113,9 @@ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) */ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -125,18 +125,18 @@ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *inp */ void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_finish(&ctx->hw_ctx, output); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_process(&ctx->hw_ctx, data); - } else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h index 53ca35ffd3..04ff65fd18 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h @@ -33,7 +33,7 @@ struct mbedtls_sha256_context_s; * \brief SHA-256 context structure */ typedef struct mbedtls_sha256_context_s { - int ishw; + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha256_sw_context sw_ctx; } From ada9a9e24889c33d60cd42d21bf7e2ee712dc4ba Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 21 Nov 2017 14:07:16 +0800 Subject: [PATCH 069/118] Refine comment with BSP driver use in DES alter. --- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 16 +++++++++++----- .../TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 16 +++++++++++----- 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index e2b83b6370..2382557765 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -332,7 +332,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Init crypto module */ crypto_init(); - // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. + /* NOTE: Don't call driver function TDES_Open in BSP because we don't want its internal multiple context (channel) support. + * Multiple context (channel) support has done in the upper layer. + */ CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); @@ -345,8 +347,10 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; } - // Set DES/TDES keys - // NOTE: Don't call driver function TDES_SetKey in BSP because it doesn't support endian swap. + /* Set DES/TDES keys + * + * NOTE: TDES_SetKey in BSP is not used because we need to make up an extra 2-dimension array to pass keys. + */ uint32_t val; volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0)); val = nu_get32_be(key[0] + 0); @@ -378,8 +382,10 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - // Start enc/dec. - // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting. + /* Start enc/dec. + * + * NOTE: Don't call driver function TDES_Start in BSP because of the multiple context (channel) reason as above. + */ CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index e2b83b6370..2382557765 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -332,7 +332,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Init crypto module */ crypto_init(); - // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. + /* NOTE: Don't call driver function TDES_Open in BSP because we don't want its internal multiple context (channel) support. + * Multiple context (channel) support has done in the upper layer. + */ CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); @@ -345,8 +347,10 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; } - // Set DES/TDES keys - // NOTE: Don't call driver function TDES_SetKey in BSP because it doesn't support endian swap. + /* Set DES/TDES keys + * + * NOTE: TDES_SetKey in BSP is not used because we need to make up an extra 2-dimension array to pass keys. + */ uint32_t val; volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0)); val = nu_get32_be(key[0] + 0); @@ -378,8 +382,10 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - // Start enc/dec. - // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting. + /* Start enc/dec. + * + * NOTE: Don't call driver function TDES_Start in BSP because of the multiple context (channel) reason as above. + */ CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); From acbc4e49ba913df518ea788dd6294d4f0e383688 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 21 Nov 2017 14:36:13 +0800 Subject: [PATCH 070/118] Add parameter check for configuring DES registers in DES alter. --- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 24 +++++++++++++++++++ .../TARGET_NUC472/des/des_alt.c | 24 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 2382557765..4ffee8565e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -311,10 +311,34 @@ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output) { + if ((keyopt < 1) || (keyopt > 3)) { + error("Key option in DES alter. requires to be 1/2/3."); + } + + if (key == NULL) { + error("Meet null key pointer in DES alter."); + } + + if ((enc != 0) && (enc != 1)) { + error("Enc/dec flag in DES alter. requires to be 0/1."); + } + + if ((tdes_opmode < DES_MODE_ECB) || (tdes_opmode > DES_MODE_CTR)) { + error("Block cipher mode of operations in DES alter. requires to be ECB/CBC/CFB/OFB/CTR."); + } + if (length % 8) { return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } + if (iv == NULL) { + error("Meet null IV pointer in DES alter."); + } + + if (input == NULL || output == NULL) { + error("Meet null input/output pointer in DES alter."); + } + /* DES DMA buffer has the following requirements: * (1) Word-aligned buffer base address * (2) 8-byte aligned buffer size diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 2382557765..4ffee8565e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -311,10 +311,34 @@ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, unsigned char iv[8], const unsigned char *input, unsigned char *output) { + if ((keyopt < 1) || (keyopt > 3)) { + error("Key option in DES alter. requires to be 1/2/3."); + } + + if (key == NULL) { + error("Meet null key pointer in DES alter."); + } + + if ((enc != 0) && (enc != 1)) { + error("Enc/dec flag in DES alter. requires to be 0/1."); + } + + if ((tdes_opmode < DES_MODE_ECB) || (tdes_opmode > DES_MODE_CTR)) { + error("Block cipher mode of operations in DES alter. requires to be ECB/CBC/CFB/OFB/CTR."); + } + if (length % 8) { return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } + if (iv == NULL) { + error("Meet null IV pointer in DES alter."); + } + + if (input == NULL || output == NULL) { + error("Meet null input/output pointer in DES alter."); + } + /* DES DMA buffer has the following requirements: * (1) Word-aligned buffer base address * (2) 8-byte aligned buffer size From 523ca0a7e481ae80f41b17a45d63b15dfe4043f9 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Tue, 21 Nov 2017 17:08:25 +0800 Subject: [PATCH 071/118] Fix parameter check for TMODE/OPMODE in DES alter. --- .../mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 4 ++-- .../targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 4ffee8565e..74eb054b4c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -323,8 +323,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S error("Enc/dec flag in DES alter. requires to be 0/1."); } - if ((tdes_opmode < DES_MODE_ECB) || (tdes_opmode > DES_MODE_CTR)) { - error("Block cipher mode of operations in DES alter. requires to be ECB/CBC/CFB/OFB/CTR."); + if (tdes_opmode & ~(CRPT_TDES_CTL_TMODE_Msk | CRPT_TDES_CTL_OPMODE_Msk)) { + error("Invalid TMODE/OPMODE in DES alter."); } if (length % 8) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 4ffee8565e..74eb054b4c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -323,8 +323,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S error("Enc/dec flag in DES alter. requires to be 0/1."); } - if ((tdes_opmode < DES_MODE_ECB) || (tdes_opmode > DES_MODE_CTR)) { - error("Block cipher mode of operations in DES alter. requires to be ECB/CBC/CFB/OFB/CTR."); + if (tdes_opmode & ~(CRPT_TDES_CTL_TMODE_Msk | CRPT_TDES_CTL_OPMODE_Msk)) { + error("Invalid TMODE/OPMODE in DES alter."); } if (length % 8) { From 101892527fbecd780cb41d4bbf02642feecaab5a Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 22 Nov 2017 09:18:55 +0800 Subject: [PATCH 072/118] Update BSP crypto driver --- .../device/StdDriver/nuc472_crypto.c | 97 +++++++++++++------ .../device/StdDriver/nuc472_crypto.h | 4 +- 2 files changed, 68 insertions(+), 33 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c index 379f6a1d30..10d37ed576 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c @@ -1,8 +1,8 @@ /**************************************************************************//** * @file crypto.c * @version V1.10 - * $Revision: 11 $ - * $Date: 14/10/03 1:54p $ + * $Revision: 12 $ + * $Date: 15/11/06 2:17p $ * @brief Cryptographic Accelerator driver source file * * @note @@ -141,13 +141,15 @@ void AES_Start(int32_t u32Channel, uint32_t u32DMAMode) */ void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) { - int i, wcnt; - uint32_t *key_ptr; + uint32_t i, wcnt, key_reg_addr; - key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3C)); - wcnt = 4 + u32KeySize*2; - for (i = 0; i < wcnt; i++, key_ptr++) - *key_ptr = au32Keys[i]; + key_reg_addr = (uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3CUL); + wcnt = 4UL + u32KeySize*2UL; + + for (i = 0U; i < wcnt; i++) { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } } /** @@ -158,12 +160,14 @@ void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) */ void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]) { - int i; - uint32_t *key_ptr; + uint32_t i, key_reg_addr; - key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3C)); - for (i = 0; i < 4; i++, key_ptr++) - *key_ptr = au32IV[i]; + key_reg_addr = (uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3CUL); + + for (i = 0U; i < 4U; i++) { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } } /** @@ -177,15 +181,24 @@ void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]) void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt) { - *(uint32_t *)((uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3C)) = u32SrcAddr; - *(uint32_t *)((uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3C)) = u32DstAddr; - *(uint32_t *)((uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3C)) = u32TransCnt; + uint32_t reg_addr; + + reg_addr = (uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3CUL); + outpw(reg_addr, u32TransCnt); } /** * @brief Open TDES encrypt/decrypt function. * @param[in] u32Channel TDES channel. Must be 0~3. * @param[in] u32EncDec 1: TDES encode; 0: TDES decode + * @param[in] Is3DES 1: TDES; 0: DES + * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode * @param[in] u32OpMode TDES operation mode, including: * - \ref TDES_MODE_ECB * - \ref TDES_MODE_CBC @@ -203,12 +216,18 @@ void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, * - \ref TDES_IN_OUT_WHL_SWAP * @return None */ -void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType) +void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, + uint32_t u32OpMode, uint32_t u32SwapType) { g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) | (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) | - u32OpMode | - (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + if (Is3DES) { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk; + } + if (Is3Key) { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk; + } } /** @@ -229,17 +248,21 @@ void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode) /** * @brief Set TDES keys * @param[in] u32Channel TDES channel. Must be 0~3. - * @param[in] au8Keys The TDES keys. + * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word. * @return None */ -void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]) +void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]) { - int i; - uint8_t *pu8TKey; + uint32_t i, reg_addr; - pu8TKey = (uint8_t *)((uint32_t)&CRPT->TDES0_KEY1H + (0x40 * u32Channel)); - for (i = 0; i < 3; i++, pu8TKey+=8) - memcpy(pu8TKey, &au8Keys[i][0], 8); + reg_addr = (uint32_t)&CRPT->TDES0_KEY1H + (0x40UL * u32Channel); + + for (i = 0U; i < 3U; i++) { + outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */ + reg_addr += 4UL; + outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */ + reg_addr += 4UL; + } } /** @@ -251,8 +274,13 @@ void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]) */ void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) { - *(uint32_t *)((uint32_t)&CRPT->TDES0_IVH + 0x40 * u32Channel) = u32IVH; - *(uint32_t *)((uint32_t)&CRPT->TDES0_IVL + 0x40 * u32Channel) = u32IVL; + uint32_t reg_addr; + + reg_addr = (uint32_t)&CRPT->TDES0_IVH + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVH); + + reg_addr = (uint32_t)&CRPT->TDES0_IVL + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVL); } /** @@ -266,9 +294,16 @@ void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt) { - *(uint32_t *)((uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40)) = u32SrcAddr; - *(uint32_t *)((uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40)) = u32DstAddr; - *(uint32_t *)((uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40)) = u32TransCnt; + uint32_t reg_addr; + + reg_addr = (uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40UL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40UL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40UL); + outpw(reg_addr, u32TransCnt); } /** diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h index c8210e5286..4ffc9d2cd3 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h @@ -275,9 +275,9 @@ void AES_Start(int32_t u32Channel, uint32_t u32DMAMode); void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]); void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); -void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType); +void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType); void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode); -void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]); +void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]); void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL); void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType); From c8c980473a465a1040ea7c764c8be761270d9ba2 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 22 Nov 2017 11:18:14 +0800 Subject: [PATCH 073/118] Call BSP driver rather than direct register access in DES alter. --- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 68 +++++++++---------- .../TARGET_NUC472/des/des_alt.c | 68 +++++++++---------- 2 files changed, 66 insertions(+), 70 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 74eb054b4c..d73a4368ec 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -356,39 +356,40 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Init crypto module */ crypto_init(); - /* NOTE: Don't call driver function TDES_Open in BSP because we don't want its internal multiple context (channel) support. - * Multiple context (channel) support has done in the upper layer. + /* Configure TDES_CTL register + * + * BSP TDES driver supports multiple channels. Just use channel #0. + * + * Relationship of keying option and TDES H/W mode configuration + * 1: All three keys are independent ==> TDES 3-key mode (TMODE=1, 3KEYS=1) + * 2: K1 and K2 are independent, and K3 = K1 ==> TDES 2-key mode (TMODE=1, 3KEYS=0) + * 3: All three keys are identical, i.e. K1 = K2 = K3 ==> DES mode (TMODE=0) + * + * tdes_opmode is combination of TMODE/OPMODE, but TDES_Open I/F requires TMODE/OPMODE to be separate. + * We need to divide tdes_opmode to TMODE and OPMODE. + * + * TDES_IN_OUT_WHL_SWAP lets TDES H/W know input/output data are arranged in below for DMA transfer: + * 1. BE for byte sequence in word + * 2. BE for word sequence in double-word */ - CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | - tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); + TDES_Open(0, // Channel number (0~4) + enc, // 0: decode, 1: encode + (tdes_opmode & CRPT_TDES_CTL_TMODE_Msk) ? 1 : 0, // 0: DES, 1: TDES + (keyopt == 1) ? 1 : 0, // 0: TDES 2-key mode, 1: TDES 3-key mode + tdes_opmode & CRPT_TDES_CTL_OPMODE_Msk, // ECB/CBC/CFB/OFB/CTR + TDES_IN_OUT_WHL_SWAP); // TDES_NO_SWAP~TDES_IN_OUT_WHL_SWAP - // Keying option 1: All three keys are independent. - // Keying option 2: K1 and K2 are independent, and K3 = K1. - // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. - if (keyopt == 1) { - CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk; - } else { - CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; + /* Set DES/TDES keys + * + * TDES_SetKey requires 3x2 word array. Change 3x8 byte array to 3x2 word array. + */ + unsigned i; + uint32_t keys3x2[3][2]; + for (i = 0; i < 3; i ++ ) { + keys3x2[i][0] = nu_get32_be(key[i] + 0); + keys3x2[i][1] = nu_get32_be(key[i] + 4); } - - /* Set DES/TDES keys - * - * NOTE: TDES_SetKey in BSP is not used because we need to make up an extra 2-dimension array to pass keys. - */ - uint32_t val; - volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0)); - val = nu_get32_be(key[0] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[0] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 4); - *tdes_key ++ = val; + TDES_SetKey(0, keys3x2); uint32_t rmn = length; const unsigned char *in_pos = input; @@ -406,11 +407,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - /* Start enc/dec. - * - * NOTE: Don't call driver function TDES_Start in BSP because of the multiple context (channel) reason as above. - */ - CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); + /* Start enc/dec */ + TDES_Start(0, CRYPTO_DMA_ONE_SHOT); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); memcpy(out_pos, dmabuf_out, data_len); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 74eb054b4c..d73a4368ec 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -356,39 +356,40 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Init crypto module */ crypto_init(); - /* NOTE: Don't call driver function TDES_Open in BSP because we don't want its internal multiple context (channel) support. - * Multiple context (channel) support has done in the upper layer. + /* Configure TDES_CTL register + * + * BSP TDES driver supports multiple channels. Just use channel #0. + * + * Relationship of keying option and TDES H/W mode configuration + * 1: All three keys are independent ==> TDES 3-key mode (TMODE=1, 3KEYS=1) + * 2: K1 and K2 are independent, and K3 = K1 ==> TDES 2-key mode (TMODE=1, 3KEYS=0) + * 3: All three keys are identical, i.e. K1 = K2 = K3 ==> DES mode (TMODE=0) + * + * tdes_opmode is combination of TMODE/OPMODE, but TDES_Open I/F requires TMODE/OPMODE to be separate. + * We need to divide tdes_opmode to TMODE and OPMODE. + * + * TDES_IN_OUT_WHL_SWAP lets TDES H/W know input/output data are arranged in below for DMA transfer: + * 1. BE for byte sequence in word + * 2. BE for word sequence in double-word */ - CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | - tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); + TDES_Open(0, // Channel number (0~4) + enc, // 0: decode, 1: encode + (tdes_opmode & CRPT_TDES_CTL_TMODE_Msk) ? 1 : 0, // 0: DES, 1: TDES + (keyopt == 1) ? 1 : 0, // 0: TDES 2-key mode, 1: TDES 3-key mode + tdes_opmode & CRPT_TDES_CTL_OPMODE_Msk, // ECB/CBC/CFB/OFB/CTR + TDES_IN_OUT_WHL_SWAP); // TDES_NO_SWAP~TDES_IN_OUT_WHL_SWAP - // Keying option 1: All three keys are independent. - // Keying option 2: K1 and K2 are independent, and K3 = K1. - // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. - if (keyopt == 1) { - CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk; - } else { - CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; + /* Set DES/TDES keys + * + * TDES_SetKey requires 3x2 word array. Change 3x8 byte array to 3x2 word array. + */ + unsigned i; + uint32_t keys3x2[3][2]; + for (i = 0; i < 3; i ++ ) { + keys3x2[i][0] = nu_get32_be(key[i] + 0); + keys3x2[i][1] = nu_get32_be(key[i] + 4); } - - /* Set DES/TDES keys - * - * NOTE: TDES_SetKey in BSP is not used because we need to make up an extra 2-dimension array to pass keys. - */ - uint32_t val; - volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0)); - val = nu_get32_be(key[0] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[0] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 4); - *tdes_key ++ = val; + TDES_SetKey(0, keys3x2); uint32_t rmn = length; const unsigned char *in_pos = input; @@ -406,11 +407,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - /* Start enc/dec. - * - * NOTE: Don't call driver function TDES_Start in BSP because of the multiple context (channel) reason as above. - */ - CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); + /* Start enc/dec */ + TDES_Start(0, CRYPTO_DMA_ONE_SHOT); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); memcpy(out_pos, dmabuf_out, data_len); From da84f715bfa2a23ddbc0a682da5b6c60e6b0e56f Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 23 Nov 2017 11:29:59 +0800 Subject: [PATCH 074/118] Add memory barrier for DMA transfer in AES/DES alter. --- .../targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 8 ++++++++ .../targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 8 ++++++++ .../targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c | 8 ++++++++ .../targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 8 ++++++++ 4 files changed, 32 insertions(+) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index c53c38600c..725f95c58f 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -177,6 +177,14 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); g_AES_done = 0; + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index d73a4368ec..63565da9bb 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -407,6 +407,14 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); /* Start enc/dec */ TDES_Start(0, CRYPTO_DMA_ONE_SHOT); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 1de420b53a..67df8f5425 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -177,6 +177,14 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); g_AES_done = 0; + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); AES_Start(0, CRYPTO_DMA_ONE_SHOT); while (!g_AES_done); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index d73a4368ec..63565da9bb 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -407,6 +407,14 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); /* Start enc/dec */ TDES_Start(0, CRYPTO_DMA_ONE_SHOT); while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); From c0fe23b1efe9d4a6d6cc100be2c08581536b2a84 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Fri, 15 Dec 2017 10:37:07 +0800 Subject: [PATCH 075/118] Refine code in SHA alter. --- .../TARGET_M480/sha/sha_alt_hw.c | 65 +++++++++---------- .../TARGET_M480/sha/sha_alt_hw.h | 2 +- .../TARGET_NUC472/sha/sha_alt_hw.c | 34 +++++----- .../TARGET_NUC472/sha/sha_alt_hw.h | 2 +- 4 files changed, 51 insertions(+), 52 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index 81d16bfdd7..c9d462d091 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -42,7 +42,7 @@ void mbedtls_sha1_hw_init(crypto_sha_context *ctx) { /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha1_hw_free(crypto_sha_context *ctx) @@ -55,7 +55,7 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) /* Uninit crypto module */ crypto_uninit(); - crypto_zeroize(ctx, sizeof(crypto_sha_context)); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha1_hw_clone(crypto_sha_context *dst, @@ -121,7 +121,7 @@ void mbedtls_sha256_hw_init(crypto_sha_context *ctx) { /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha256_hw_free(crypto_sha_context *ctx) @@ -134,7 +134,7 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) /* Uninit crypto module */ crypto_uninit(); - crypto_zeroize(ctx, sizeof(crypto_sha_context)); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha256_hw_clone(crypto_sha_context *dst, @@ -202,7 +202,7 @@ void mbedtls_sha512_hw_init(crypto_sha_context *ctx) { /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha512_hw_free(crypto_sha_context *ctx) @@ -215,7 +215,7 @@ void mbedtls_sha512_hw_free(crypto_sha_context *ctx) /* Uninit crypto module */ crypto_uninit(); - crypto_zeroize(ctx, sizeof(crypto_sha_context)); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha512_hw_clone(crypto_sha_context *dst, @@ -322,9 +322,8 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input int rmn = ilen; uint32_t sha_ctl_start = (CRPT->HMAC_CTL & ~(CRPT_HMAC_CTL_DMALAST_Msk | CRPT_HMAC_CTL_DMAEN_Msk | CRPT_HMAC_CTL_HMACEN_Msk)) | CRPT_HMAC_CTL_START_Msk; uint32_t sha_opmode = (CRPT->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; - uint32_t DGST0_old = 0, DGST1_old = 0, DGST2_old = 0, DGST3_old = 0, DGST4_old = 0, DGST5_old = 0, DGST6_old = 0, DGST7_old = 0, - DGST8_old = 0, DGST9_old = 0, DGST10_old = 0, DGST11_old = 0, DGST12_old = 0, DGST13_old = 0, DGST14_old = 0, DGST15_old = 0; - + uint32_t DGSTs[16] = { 0 }; + while (rmn > 0) { CRPT->HMAC_CTL = sha_ctl_start; @@ -340,26 +339,26 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input } else { switch (sha_opmode) { case SHA_MODE_SHA512: - DGST15_old = CRPT->HMAC_DGST[15]; - DGST14_old = CRPT->HMAC_DGST[14]; - DGST13_old = CRPT->HMAC_DGST[13]; - DGST12_old = CRPT->HMAC_DGST[12]; + DGSTs[12] = CRPT->HMAC_DGST[12]; + DGSTs[13] = CRPT->HMAC_DGST[13]; + DGSTs[14] = CRPT->HMAC_DGST[14]; + DGSTs[15] = CRPT->HMAC_DGST[15]; case SHA_MODE_SHA384: - DGST11_old = CRPT->HMAC_DGST[11]; - DGST10_old = CRPT->HMAC_DGST[10]; - DGST9_old = CRPT->HMAC_DGST[9]; - DGST8_old = CRPT->HMAC_DGST[8]; + DGSTs[8] = CRPT->HMAC_DGST[8]; + DGSTs[9] = CRPT->HMAC_DGST[9]; + DGSTs[10] = CRPT->HMAC_DGST[10]; + DGSTs[11] = CRPT->HMAC_DGST[11]; case SHA_MODE_SHA256: - DGST7_old = CRPT->HMAC_DGST[7]; + DGSTs[7] = CRPT->HMAC_DGST[7]; case SHA_MODE_SHA224: - DGST5_old = CRPT->HMAC_DGST[5]; - DGST6_old = CRPT->HMAC_DGST[6]; + DGSTs[5] = CRPT->HMAC_DGST[5]; + DGSTs[6] = CRPT->HMAC_DGST[6]; case SHA_MODE_SHA1: - DGST0_old = CRPT->HMAC_DGST[0]; - DGST1_old = CRPT->HMAC_DGST[1]; - DGST2_old = CRPT->HMAC_DGST[2]; - DGST3_old = CRPT->HMAC_DGST[3]; - DGST4_old = CRPT->HMAC_DGST[4]; + DGSTs[0] = CRPT->HMAC_DGST[0]; + DGSTs[1] = CRPT->HMAC_DGST[1]; + DGSTs[2] = CRPT->HMAC_DGST[2]; + DGSTs[3] = CRPT->HMAC_DGST[3]; + DGSTs[4] = CRPT->HMAC_DGST[4]; } CRPT->HMAC_CTL = sha_ctl_start; @@ -383,30 +382,30 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input while (! isfinish) { switch (sha_opmode) { case SHA_MODE_SHA512: - if (DGST12_old != CRPT->HMAC_DGST[12] || DGST13_old != CRPT->HMAC_DGST[13] || DGST14_old != CRPT->HMAC_DGST[14] || - DGST15_old != CRPT->HMAC_DGST[15]) { + if (DGSTs[12] != CRPT->HMAC_DGST[12] || DGSTs[13] != CRPT->HMAC_DGST[13] || DGSTs[14] != CRPT->HMAC_DGST[14] || + DGSTs[15] != CRPT->HMAC_DGST[15]) { isfinish = 1; break; } case SHA_MODE_SHA384: - if (DGST8_old != CRPT->HMAC_DGST[8] || DGST9_old != CRPT->HMAC_DGST[9] || DGST10_old != CRPT->HMAC_DGST[10] || - DGST11_old != CRPT->HMAC_DGST[11]) { + if (DGSTs[8] != CRPT->HMAC_DGST[8] || DGSTs[9] != CRPT->HMAC_DGST[9] || DGSTs[10] != CRPT->HMAC_DGST[10] || + DGSTs[11] != CRPT->HMAC_DGST[11]) { isfinish = 1; break; } case SHA_MODE_SHA256: - if (DGST7_old != CRPT->HMAC_DGST[7]) { + if (DGSTs[7] != CRPT->HMAC_DGST[7]) { isfinish = 1; break; } case SHA_MODE_SHA224: - if (DGST5_old != CRPT->HMAC_DGST[5] || DGST6_old != CRPT->HMAC_DGST[6]) { + if (DGSTs[5] != CRPT->HMAC_DGST[5] || DGSTs[6] != CRPT->HMAC_DGST[6]) { isfinish = 1; break; } case SHA_MODE_SHA1: - if (DGST0_old != CRPT->HMAC_DGST[0] || DGST1_old != CRPT->HMAC_DGST[1] || DGST2_old != CRPT->HMAC_DGST[2] || - DGST3_old != CRPT->HMAC_DGST[3] || DGST4_old != CRPT->HMAC_DGST[4]) { + if (DGSTs[0] != CRPT->HMAC_DGST[0] || DGSTs[1] != CRPT->HMAC_DGST[1] || DGSTs[2] != CRPT->HMAC_DGST[2] || + DGSTs[3] != CRPT->HMAC_DGST[3] || DGSTs[4] != CRPT->HMAC_DGST[4]) { isfinish = 1; break; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h index e8cad3b2de..a492609be3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h @@ -30,7 +30,7 @@ extern "C" { */ typedef struct { uint32_t total; /*!< number of bytes processed */ - unsigned char buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ + uint8_t buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ uint16_t buffer_left; uint16_t blocksize; /*!< block size */ uint32_t blocksize_mask; /*!< block size mask */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index b09a9c34e5..e0b1860047 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -42,7 +42,7 @@ void mbedtls_sha1_hw_init(crypto_sha_context *ctx) { /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha1_hw_free(crypto_sha_context *ctx) @@ -55,7 +55,7 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) /* Uninit crypto module */ crypto_uninit(); - crypto_zeroize(ctx, sizeof(crypto_sha_context)); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha1_hw_clone(crypto_sha_context *dst, @@ -121,7 +121,7 @@ void mbedtls_sha256_hw_init(crypto_sha_context *ctx) { /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha256_hw_free(crypto_sha_context *ctx) @@ -134,7 +134,7 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) /* Uninit crypto module */ crypto_uninit(); - crypto_zeroize(ctx, sizeof(crypto_sha_context)); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha256_hw_clone(crypto_sha_context *dst, @@ -241,7 +241,7 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input int rmn = ilen; uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk; uint32_t sha_opmode = (CRPT->SHA_CTL & CRPT_SHA_CTL_OPMODE_Msk) >> CRPT_SHA_CTL_OPMODE_Pos; - uint32_t DGST0_old, DGST1_old, DGST2_old, DGST3_old, DGST4_old, DGST5_old, DGST6_old, DGST7_old; + uint32_t DGSTs[8] = { 0 }; while (rmn > 0) { CRPT->SHA_CTL = sha_ctl_start; @@ -258,16 +258,16 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input } else { switch (sha_opmode) { case SHA_MODE_SHA256: - DGST7_old = CRPT->SHA_DGST7; + DGSTs[7] = CRPT->SHA_DGST7; case SHA_MODE_SHA224: - DGST5_old = CRPT->SHA_DGST5; - DGST6_old = CRPT->SHA_DGST6; + DGSTs[5] = CRPT->SHA_DGST5; + DGSTs[6] = CRPT->SHA_DGST6; case SHA_MODE_SHA1: - DGST0_old = CRPT->SHA_DGST0; - DGST1_old = CRPT->SHA_DGST1; - DGST2_old = CRPT->SHA_DGST2; - DGST3_old = CRPT->SHA_DGST3; - DGST4_old = CRPT->SHA_DGST4; + DGSTs[0] = CRPT->SHA_DGST0; + DGSTs[1] = CRPT->SHA_DGST1; + DGSTs[2] = CRPT->SHA_DGST2; + DGSTs[3] = CRPT->SHA_DGST3; + DGSTs[4] = CRPT->SHA_DGST4; } CRPT->SHA_CTL = sha_ctl_start; @@ -291,18 +291,18 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input while (! isfinish) { switch (sha_opmode) { case SHA_MODE_SHA256: - if (DGST7_old != CRPT->SHA_DGST7) { + if (DGSTs[7] != CRPT->SHA_DGST7) { isfinish = 1; break; } case SHA_MODE_SHA224: - if (DGST5_old != CRPT->SHA_DGST5 || DGST6_old != CRPT->SHA_DGST6) { + if (DGSTs[5] != CRPT->SHA_DGST5 || DGSTs[6] != CRPT->SHA_DGST6) { isfinish = 1; break; } case SHA_MODE_SHA1: - if (DGST0_old != CRPT->SHA_DGST0 || DGST1_old != CRPT->SHA_DGST1 || DGST2_old != CRPT->SHA_DGST2 || - DGST3_old != CRPT->SHA_DGST3 || DGST4_old != CRPT->SHA_DGST4) { + if (DGSTs[0] != CRPT->SHA_DGST0 || DGSTs[1] != CRPT->SHA_DGST1 || DGSTs[2] != CRPT->SHA_DGST2 || + DGSTs[3] != CRPT->SHA_DGST3 || DGSTs[4] != CRPT->SHA_DGST4) { isfinish = 1; break; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h index c66632b9de..18caf697e0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h @@ -30,7 +30,7 @@ extern "C" { */ typedef struct { uint32_t total; /*!< number of bytes processed */ - unsigned char buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ + uint8_t buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ uint16_t buffer_left; uint16_t blocksize; /*!< block size */ uint32_t blocksize_mask; /*!< block size mask */ From 9374e435458a263a89c50730f52b710b0f43ebad Mon Sep 17 00:00:00 2001 From: ccli8 Date: Fri, 15 Dec 2017 10:38:57 +0800 Subject: [PATCH 076/118] Add comment for crypto_zeroize --- targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h | 2 ++ targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h index 1527a59c6d..4bee4f644c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h @@ -35,6 +35,8 @@ extern volatile int g_AES_done; void crypto_init(void); void crypto_uninit(void); +/* Clear buffer to zero + * Implementation that should never be optimized out by the compiler */ void crypto_zeroize(void *v, size_t n); /* Acquire/release ownership of AES H/W */ diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h index 1527a59c6d..4bee4f644c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h @@ -35,6 +35,8 @@ extern volatile int g_AES_done; void crypto_init(void); void crypto_uninit(void); +/* Clear buffer to zero + * Implementation that should never be optimized out by the compiler */ void crypto_zeroize(void *v, size_t n); /* Acquire/release ownership of AES H/W */ From 274a54eb8b0b122de6dddd94adb2546532c1b765 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Fri, 15 Dec 2017 13:49:51 +0800 Subject: [PATCH 077/118] Refine flow control code between crypto start and crypto ISR --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 12 +--- .../TARGET_NUC472/aes/aes_alt.c | 12 +--- .../TARGET_M480/crypto/crypto-misc.c | 56 +++++++++++++++++-- .../TARGET_M480/crypto/crypto-misc.h | 29 +++++++--- targets/TARGET_NUVOTON/TARGET_M480/trng_api.c | 4 +- .../TARGET_NUC472/crypto/crypto-misc.c | 56 +++++++++++++++++-- .../TARGET_NUC472/crypto/crypto-misc.h | 29 +++++++--- .../TARGET_NUVOTON/TARGET_NUC472/trng_api.c | 7 +-- 8 files changed, 153 insertions(+), 52 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 725f95c58f..855d415f78 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -176,17 +176,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); - g_AES_done = 0; - /* Ensure memory accesses above are completed before DMA is started - * - * Replacing __DSB() with __DMB() is also OK in this case. - * - * Refer to "multi-master systems" section with DMA in: - * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf - */ - __DSB(); + crypto_aes_prestart(); AES_Start(0, CRYPTO_DMA_ONE_SHOT); - while (!g_AES_done); + crypto_aes_wait(); if( pOut != output ) { memcpy(output, au8OutputData, dataSize); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index 67df8f5425..f8a1c97d5e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -176,17 +176,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); - g_AES_done = 0; - /* Ensure memory accesses above are completed before DMA is started - * - * Replacing __DSB() with __DMB() is also OK in this case. - * - * Refer to "multi-master systems" section with DMA in: - * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf - */ - __DSB(); + crypto_aes_prestart(); AES_Start(0, CRYPTO_DMA_ONE_SHOT); - while (!g_AES_done); + crypto_aes_wait(); if( pOut != output ) { memcpy(output, au8OutputData, dataSize); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c index 4c4c52d04f..bc7a58a30c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c @@ -24,9 +24,6 @@ #include "nu_bitutil.h" #include "crypto-misc.h" -volatile int g_PRNG_done; -volatile int g_AES_done; - /* Track if AES H/W is available */ static uint16_t crypto_aes_avail = 1; /* Track if DES H/W is available */ @@ -40,6 +37,14 @@ static uint16_t crypto_init_counter = 0U; static bool crypto_submodule_acquire(uint16_t *submodule_avail); static void crypto_submodule_release(uint16_t *submodule_avail); +/* Track if PRNG H/W operation is done */ +static volatile uint16_t crypto_prng_done; +/* Track if AES H/W operation is done */ +static volatile uint16_t crypto_aes_done; + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done); +static bool crypto_submodule_wait(volatile uint16_t *submodule_done); + /* As crypto init counter changes from 0 to 1: * * 1. Enable crypto clock @@ -125,6 +130,26 @@ void crypto_sha_release(void) crypto_submodule_release(&crypto_sha_avail); } +void crypto_prng_prestart(void) +{ + crypto_submodule_prestart(&crypto_prng_done); +} + +bool crypto_prng_wait(void) +{ + return crypto_submodule_wait(&crypto_prng_done); +} + +void crypto_aes_prestart(void) +{ + crypto_submodule_prestart(&crypto_aes_done); +} + +bool crypto_aes_wait(void) +{ + return crypto_submodule_wait(&crypto_aes_done); +} + bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) { uint32_t buff_ = (uint32_t) buff; @@ -146,14 +171,35 @@ static void crypto_submodule_release(uint16_t *submodule_avail) while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); } +static void crypto_submodule_prestart(volatile uint16_t *submodule_done) +{ + *submodule_done = 0; + + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); +} + +static bool crypto_submodule_wait(volatile uint16_t *submodule_done) +{ + while (! *submodule_done); + + return true; +} + /* Crypto interrupt handler */ void CRYPTO_IRQHandler() { if (PRNG_GET_INT_FLAG()) { - g_PRNG_done = 1; + crypto_prng_done = 1; PRNG_CLR_INT_FLAG(); } else if (AES_GET_INT_FLAG()) { - g_AES_done = 1; + crypto_aes_done = 1; AES_CLR_INT_FLAG(); } } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h index 4bee4f644c..bec4a96ba5 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h @@ -23,14 +23,6 @@ extern "C" { #endif -/* Flags to indicate crypto H/W operation has done - * - * Crypto driver would clear it before trigger and wait for it. - * Crypto interrupt handler would set it on done or error. - */ -extern volatile int g_PRNG_done; -extern volatile int g_AES_done; - /* Init/Uninit crypto module */ void crypto_init(void); void crypto_uninit(void); @@ -54,6 +46,27 @@ void crypto_des_release(void); bool crypto_sha_acquire(void); void crypto_sha_release(void); +/* Flow control between crypto/xxx start and crypto/xxx ISR + * + * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. + * + * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction. + * + * On finish, return of crypto_xxx_wait indicates success or not: + * true if successful + * false if failed + * + * Example: Start AES H/W and wait for its finish + * crypto_aes_prestart(); + * AES_Start(); + * crypto_aes_wait(); + */ +void crypto_prng_prestart(void); +bool crypto_prng_wait(void); +void crypto_aes_prestart(void); +bool crypto_aes_wait(void); + + /* Check if buffer can be used for crypto DMA. It has the following requirements: * (1) Word-aligned buffer base address * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. diff --git a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c index eeb0a34730..305be2bd21 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c @@ -36,8 +36,9 @@ static void trng_get(unsigned char *pConversionData) p32ConversionData = (uint32_t *)pConversionData; PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read()); + crypto_prng_prestart(); PRNG_Start(); - while (!g_PRNG_done); + crypto_prng_wait(); PRNG_Read(p32ConversionData); } @@ -85,4 +86,3 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l } #endif - diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c index 4c4c52d04f..bc7a58a30c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c @@ -24,9 +24,6 @@ #include "nu_bitutil.h" #include "crypto-misc.h" -volatile int g_PRNG_done; -volatile int g_AES_done; - /* Track if AES H/W is available */ static uint16_t crypto_aes_avail = 1; /* Track if DES H/W is available */ @@ -40,6 +37,14 @@ static uint16_t crypto_init_counter = 0U; static bool crypto_submodule_acquire(uint16_t *submodule_avail); static void crypto_submodule_release(uint16_t *submodule_avail); +/* Track if PRNG H/W operation is done */ +static volatile uint16_t crypto_prng_done; +/* Track if AES H/W operation is done */ +static volatile uint16_t crypto_aes_done; + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done); +static bool crypto_submodule_wait(volatile uint16_t *submodule_done); + /* As crypto init counter changes from 0 to 1: * * 1. Enable crypto clock @@ -125,6 +130,26 @@ void crypto_sha_release(void) crypto_submodule_release(&crypto_sha_avail); } +void crypto_prng_prestart(void) +{ + crypto_submodule_prestart(&crypto_prng_done); +} + +bool crypto_prng_wait(void) +{ + return crypto_submodule_wait(&crypto_prng_done); +} + +void crypto_aes_prestart(void) +{ + crypto_submodule_prestart(&crypto_aes_done); +} + +bool crypto_aes_wait(void) +{ + return crypto_submodule_wait(&crypto_aes_done); +} + bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) { uint32_t buff_ = (uint32_t) buff; @@ -146,14 +171,35 @@ static void crypto_submodule_release(uint16_t *submodule_avail) while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); } +static void crypto_submodule_prestart(volatile uint16_t *submodule_done) +{ + *submodule_done = 0; + + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); +} + +static bool crypto_submodule_wait(volatile uint16_t *submodule_done) +{ + while (! *submodule_done); + + return true; +} + /* Crypto interrupt handler */ void CRYPTO_IRQHandler() { if (PRNG_GET_INT_FLAG()) { - g_PRNG_done = 1; + crypto_prng_done = 1; PRNG_CLR_INT_FLAG(); } else if (AES_GET_INT_FLAG()) { - g_AES_done = 1; + crypto_aes_done = 1; AES_CLR_INT_FLAG(); } } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h index 4bee4f644c..bec4a96ba5 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h @@ -23,14 +23,6 @@ extern "C" { #endif -/* Flags to indicate crypto H/W operation has done - * - * Crypto driver would clear it before trigger and wait for it. - * Crypto interrupt handler would set it on done or error. - */ -extern volatile int g_PRNG_done; -extern volatile int g_AES_done; - /* Init/Uninit crypto module */ void crypto_init(void); void crypto_uninit(void); @@ -54,6 +46,27 @@ void crypto_des_release(void); bool crypto_sha_acquire(void); void crypto_sha_release(void); +/* Flow control between crypto/xxx start and crypto/xxx ISR + * + * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. + * + * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction. + * + * On finish, return of crypto_xxx_wait indicates success or not: + * true if successful + * false if failed + * + * Example: Start AES H/W and wait for its finish + * crypto_aes_prestart(); + * AES_Start(); + * crypto_aes_wait(); + */ +void crypto_prng_prestart(void); +bool crypto_prng_wait(void); +void crypto_aes_prestart(void); +bool crypto_aes_wait(void); + + /* Check if buffer can be used for crypto DMA. It has the following requirements: * (1) Word-aligned buffer base address * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c index b705b7c585..153e1ef42c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c @@ -23,7 +23,6 @@ #include #include #include "cmsis.h" -#include "NUC472_442.h" #include "us_ticker_api.h" #include "trng_api.h" #include "crypto-misc.h" @@ -41,8 +40,9 @@ static void trng_get(unsigned char *pConversionData) p32ConversionData = (uint32_t *)pConversionData; PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read()); + crypto_prng_prestart(); PRNG_Start(); - while (!g_PRNG_done); + crypto_prng_wait(); PRNG_Read(p32ConversionData); } @@ -88,6 +88,5 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l *output_length = cur_length; return 0; } - -#endif +#endif From e352fc48bdecc5a8789cd796d8b482477cbe35ba Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 20 Dec 2017 10:41:16 +0800 Subject: [PATCH 078/118] Use interrupt signal rather than polling to check operation completion in DES alter. This is to be consistent with PRNG/AES. --- .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 16 ++++++---------- .../TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c | 16 ++++++---------- .../TARGET_M480/crypto/crypto-misc.c | 15 +++++++++++++++ .../TARGET_M480/crypto/crypto-misc.h | 2 ++ .../TARGET_NUC472/crypto/crypto-misc.c | 15 +++++++++++++++ .../TARGET_NUC472/crypto/crypto-misc.h | 2 ++ 6 files changed, 46 insertions(+), 20 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 63565da9bb..fdbb9775c5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -355,6 +355,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Init crypto module */ crypto_init(); + /* Enable DES interrupt */ + TDES_ENABLE_INT(); /* Configure TDES_CTL register * @@ -407,17 +409,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - /* Ensure memory accesses above are completed before DMA is started - * - * Replacing __DSB() with __DMB() is also OK in this case. - * - * Refer to "multi-master systems" section with DMA in: - * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf - */ - __DSB(); - /* Start enc/dec */ + crypto_des_prestart(); TDES_Start(0, CRYPTO_DMA_ONE_SHOT); - while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); + crypto_des_wait(); memcpy(out_pos, dmabuf_out, data_len); in_pos += data_len; @@ -457,6 +451,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S } } + /* Disable DES interrupt */ + TDES_DISABLE_INT(); /* Uninit crypto module */ crypto_uninit(); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 63565da9bb..fdbb9775c5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -355,6 +355,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S /* Init crypto module */ crypto_init(); + /* Enable DES interrupt */ + TDES_ENABLE_INT(); /* Configure TDES_CTL register * @@ -407,17 +409,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - /* Ensure memory accesses above are completed before DMA is started - * - * Replacing __DSB() with __DMB() is also OK in this case. - * - * Refer to "multi-master systems" section with DMA in: - * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf - */ - __DSB(); - /* Start enc/dec */ + crypto_des_prestart(); TDES_Start(0, CRYPTO_DMA_ONE_SHOT); - while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); + crypto_des_wait(); memcpy(out_pos, dmabuf_out, data_len); in_pos += data_len; @@ -457,6 +451,8 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S } } + /* Disable DES interrupt */ + TDES_DISABLE_INT(); /* Uninit crypto module */ crypto_uninit(); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c index bc7a58a30c..daddc4fa9f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c @@ -41,6 +41,8 @@ static void crypto_submodule_release(uint16_t *submodule_avail); static volatile uint16_t crypto_prng_done; /* Track if AES H/W operation is done */ static volatile uint16_t crypto_aes_done; +/* Track if DES H/W operation is done */ +static volatile uint16_t crypto_des_done; static void crypto_submodule_prestart(volatile uint16_t *submodule_done); static bool crypto_submodule_wait(volatile uint16_t *submodule_done); @@ -150,6 +152,16 @@ bool crypto_aes_wait(void) return crypto_submodule_wait(&crypto_aes_done); } +void crypto_des_prestart(void) +{ + crypto_submodule_prestart(&crypto_des_done); +} + +bool crypto_des_wait(void) +{ + return crypto_submodule_wait(&crypto_des_done); +} + bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) { uint32_t buff_ = (uint32_t) buff; @@ -201,5 +213,8 @@ void CRYPTO_IRQHandler() } else if (AES_GET_INT_FLAG()) { crypto_aes_done = 1; AES_CLR_INT_FLAG(); + } else if (TDES_GET_INT_FLAG()) { + crypto_des_done = 1; + TDES_CLR_INT_FLAG(); } } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h index bec4a96ba5..356c02706b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h @@ -65,6 +65,8 @@ void crypto_prng_prestart(void); bool crypto_prng_wait(void); void crypto_aes_prestart(void); bool crypto_aes_wait(void); +void crypto_des_prestart(void); +bool crypto_des_wait(void); /* Check if buffer can be used for crypto DMA. It has the following requirements: diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c index bc7a58a30c..daddc4fa9f 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c @@ -41,6 +41,8 @@ static void crypto_submodule_release(uint16_t *submodule_avail); static volatile uint16_t crypto_prng_done; /* Track if AES H/W operation is done */ static volatile uint16_t crypto_aes_done; +/* Track if DES H/W operation is done */ +static volatile uint16_t crypto_des_done; static void crypto_submodule_prestart(volatile uint16_t *submodule_done); static bool crypto_submodule_wait(volatile uint16_t *submodule_done); @@ -150,6 +152,16 @@ bool crypto_aes_wait(void) return crypto_submodule_wait(&crypto_aes_done); } +void crypto_des_prestart(void) +{ + crypto_submodule_prestart(&crypto_des_done); +} + +bool crypto_des_wait(void) +{ + return crypto_submodule_wait(&crypto_des_done); +} + bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) { uint32_t buff_ = (uint32_t) buff; @@ -201,5 +213,8 @@ void CRYPTO_IRQHandler() } else if (AES_GET_INT_FLAG()) { crypto_aes_done = 1; AES_CLR_INT_FLAG(); + } else if (TDES_GET_INT_FLAG()) { + crypto_des_done = 1; + TDES_CLR_INT_FLAG(); } } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h index bec4a96ba5..356c02706b 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h @@ -65,6 +65,8 @@ void crypto_prng_prestart(void); bool crypto_prng_wait(void); void crypto_aes_prestart(void); bool crypto_aes_wait(void); +void crypto_des_prestart(void); +bool crypto_des_wait(void); /* Check if buffer can be used for crypto DMA. It has the following requirements: From 1fea28672520bffa05289642a88fff14f5e38440 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 20 Dec 2017 11:04:54 +0800 Subject: [PATCH 079/118] Guard from reordering DMA wait and post-wait for crypto modules --- targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c | 5 ++++- targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c index daddc4fa9f..0c830a5dfc 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c @@ -200,7 +200,10 @@ static void crypto_submodule_prestart(volatile uint16_t *submodule_done) static bool crypto_submodule_wait(volatile uint16_t *submodule_done) { while (! *submodule_done); - + + /* Ensure while loop above and subsequent code are not reordered */ + __DSB(); + return true; } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c index daddc4fa9f..0c830a5dfc 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c @@ -200,7 +200,10 @@ static void crypto_submodule_prestart(volatile uint16_t *submodule_done) static bool crypto_submodule_wait(volatile uint16_t *submodule_done) { while (! *submodule_done); - + + /* Ensure while loop above and subsequent code are not reordered */ + __DSB(); + return true; } From 0243435047b40deb854e2a34017d6ed4a82549b6 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Dec 2017 11:04:33 +0800 Subject: [PATCH 080/118] Remove duplicate configuration of CRPT->SHA_CTL/CRPT->HMAC_CTL in SHA alter. --- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c | 6 ++---- .../targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index c9d462d091..e35a31efa3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -156,7 +156,7 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP, 0); - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; return; @@ -237,7 +237,7 @@ void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384) SHA_Open(is384 ? SHA_MODE_SHA384 : SHA_MODE_SHA512, SHA_NO_SWAP, 0); - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; return; @@ -325,8 +325,6 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input uint32_t DGSTs[16] = { 0 }; while (rmn > 0) { - CRPT->HMAC_CTL = sha_ctl_start; - uint32_t data = nu_get32_be(in_pos); if (rmn <= 4) { // Last word of a (in)complete block if (islast) { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index e0b1860047..45103bc66d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -76,7 +76,7 @@ void mbedtls_sha1_hw_starts(crypto_sha_context *ctx) SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP); - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk; return; @@ -156,7 +156,7 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP); - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk; return; @@ -244,8 +244,6 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input uint32_t DGSTs[8] = { 0 }; while (rmn > 0) { - CRPT->SHA_CTL = sha_ctl_start; - uint32_t data = nu_get32_be(in_pos); if (rmn <= 4) { // Last word of a (in)complete block if (islast) { From fd650adceed2066c0b043b6d56e52c2d0aa0fd1e Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Dec 2017 14:17:15 +0800 Subject: [PATCH 081/118] Fix indefinite loop in SHA alter. --- .../TARGET_M480/sha/sha_alt_hw.c | 23 ++++- .../TARGET_NUC472/sha/sha_alt_hw.c | 23 ++++- targets/TARGET_NUVOTON/nu_timer.h | 93 +++++++++++++++++++ 3 files changed, 135 insertions(+), 4 deletions(-) create mode 100644 targets/TARGET_NUVOTON/nu_timer.h diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index e35a31efa3..54d63741c1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -23,6 +23,7 @@ #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) #include "nu_bitutil.h" +#include "nu_timer.h" #include "mbed_assert.h" #include "mbed_error.h" #include "crypto-misc.h" @@ -374,9 +375,20 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input if (islast) { // Finish of last block while (CRPT->HMAC_STS & CRPT_HMAC_STS_BUSY_Msk); } else { // Finish of non-last block - // No H/W flag to indicate finish of non-last block process. - // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement. + /* SHA accelerator doesn't export a flag to indicate non-last block process has finished. + * Per designer, if the digest (SHA_DGSTx) code changes after the last word of the block is input, + * this indicates the non-last block process has finished. + * + * There is a rare case that two digest codes are the same for + * two non-last block processes in a row. + * To address it, we use a count-down timer to detect it. + * As the count-down timer expires, we see it as finished. + */ int isfinish = 0; + struct nu_countdown_ctx_s ctx; + + // Set up 2s timeout + nu_countdown_init(&ctx, 2000*1000); while (! isfinish) { switch (sha_opmode) { case SHA_MODE_SHA512: @@ -408,7 +420,14 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input break; } } + + if (nu_countdown_expired(&ctx)) { + // We may meet a rare case that the current digest code and the previous one are the same. + isfinish = 1; + } } + // Must pair nu_countdown_init with nu_countdown_free in the end + nu_countdown_free(&ctx); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index 45103bc66d..c6dc7394ac 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -23,6 +23,7 @@ #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) #include "nu_bitutil.h" +#include "nu_timer.h" #include "mbed_assert.h" #include "mbed_error.h" #include "crypto-misc.h" @@ -283,9 +284,20 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input if (islast) { // Finish of last block while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk); } else { // Finish of non-last block - // No H/W flag to indicate finish of non-last block process. - // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement. + /* SHA accelerator doesn't export a flag to indicate non-last block process has finished. + * Per designer, if the digest (SHA_DGSTx) code changes after the last word of the block is input, + * this indicates the non-last block process has finished. + * + * There is a rare case that two digest codes are the same for + * two non-last block processes in a row. + * To address it, we use a count-down timer to detect it. + * As the count-down timer expires, we see it as finished. + */ int isfinish = 0; + struct nu_countdown_ctx_s ctx; + + // Set up 2s timeout + nu_countdown_init(&ctx, 2000*1000); while (! isfinish) { switch (sha_opmode) { case SHA_MODE_SHA256: @@ -305,7 +317,14 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input break; } } + + if (nu_countdown_expired(&ctx)) { + // We may meet a rare case that the current digest code and the previous one are the same. + isfinish = 1; + } } + // Must pair nu_countdown_init with nu_countdown_free in the end + nu_countdown_free(&ctx); } } diff --git a/targets/TARGET_NUVOTON/nu_timer.h b/targets/TARGET_NUVOTON/nu_timer.h new file mode 100644 index 0000000000..08683370fc --- /dev/null +++ b/targets/TARGET_NUVOTON/nu_timer.h @@ -0,0 +1,93 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef NU_TIMER_H +#define NU_TIMER_H + +#include +#include +#include "cmsis.h" +#include "mbed_sleep.h" +#include "mbed_critical.h" +#include "ticker_api.h" +#include "us_ticker_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* A simple count-down timer used for Nuvoton ported drivers + * + * NOTE: nu_countdown_init must be paired with nu_countdown_free. + * + * Example: + * nu_countdown_ctx_s ctx; + * + * // Set up 2 ms timeout + * nu_countdown_init(&ctx, 2000); + * + * // Timed-wait for a task + * while (true) { + * // Poll the task + * + * if (nu_countdown_expired(&ctx)) { + * // Timeout + * } + * } + * + * // Must pair nu_countdown_init with nu_countdown_free in the end + * nu_countdown_free(&ctx); + */ + +struct nu_countdown_ctx_s { + const ticker_data_t * _ticker_data; // Hold ticker_data_t + us_timestamp_t _interval_end_us; // End of interval in us + bool _expired; // Expired or not +}; + +__STATIC_INLINE void nu_countdown_init(struct nu_countdown_ctx_s *ctx, us_timestamp_t interval_us) +{ + core_util_critical_section_enter(); + sleep_manager_lock_deep_sleep(); + ctx->_ticker_data = get_us_ticker_data(); + ctx->_interval_end_us = ticker_read_us(ctx->_ticker_data) + interval_us; + ctx->_expired = false; + core_util_critical_section_exit(); +} + +__STATIC_INLINE bool nu_countdown_expired(struct nu_countdown_ctx_s *ctx) +{ + core_util_critical_section_enter(); + if (! ctx->_expired) { + ctx->_expired = ticker_read_us(ctx->_ticker_data) >= ctx->_interval_end_us; + } + core_util_critical_section_exit(); + + return ctx->_expired; +} + +__STATIC_INLINE void nu_countdown_free(struct nu_countdown_ctx_s *ctx) +{ + core_util_critical_section_enter(); + sleep_manager_unlock_deep_sleep(); + core_util_critical_section_exit(); +} + +#ifdef __cplusplus +} +#endif + +#endif From 2caeb92b5f28958e5add909a700a9f2083ab6c51 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Dec 2017 16:05:55 +0800 Subject: [PATCH 082/118] Fix context clone corner case in SHA alter. As destination/source contexts are the same, we return immediately. --- .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c | 5 +++++ .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c | 5 +++++ .../targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c | 5 +++++ .../targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c | 5 +++++ .../targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c | 5 +++++ 5 files changed, 25 insertions(+) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index 761c8c33d9..35d7122610 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -63,6 +63,11 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + // If dst is H/W context, we need to change it to S/W context first before cloning to. if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha1_free(dst); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index 09ec8e4335..c4e27dfa5f 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -63,6 +63,11 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + // If dst is H/W context, we need to change it to S/W context first before cloning to. if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha256_free(dst); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index ce25a5e861..48baf9132f 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -63,6 +63,11 @@ void mbedtls_sha512_free(mbedtls_sha512_context *ctx) void mbedtls_sha512_clone(mbedtls_sha512_context *dst, const mbedtls_sha512_context *src) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + // If dst is H/W context, we need to change it to S/W context first before cloning to. if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha512_free(dst); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index 761c8c33d9..35d7122610 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -63,6 +63,11 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx) void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + // If dst is H/W context, we need to change it to S/W context first before cloning to. if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha1_free(dst); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index 57ed6d5b3c..b576d7a767 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -63,6 +63,11 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx) void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + // If dst is H/W context, we need to change it to S/W context first before cloning to. if (dst->active_ctx == &dst->hw_ctx) { mbedtls_sha256_free(dst); From 5938e6b73a364164e97ce20e6af2132086d36ab4 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 21 Dec 2017 16:10:18 +0800 Subject: [PATCH 083/118] Remove unnecessary H/W context clone functions in SHA alter. --- .../TARGET_M480/sha/sha_alt_hw.c | 18 ------------------ .../TARGET_M480/sha/sha_alt_hw.h | 6 ------ .../TARGET_NUC472/sha/sha_alt_hw.c | 12 ------------ .../TARGET_NUC472/sha/sha_alt_hw.h | 4 ---- 4 files changed, 40 deletions(-) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index 54d63741c1..1067fb4057 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -59,12 +59,6 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) crypto_zeroize(ctx, sizeof(*ctx)); } -void mbedtls_sha1_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; -} - void mbedtls_sha1_hw_starts(crypto_sha_context *ctx) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. @@ -138,12 +132,6 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) crypto_zeroize(ctx, sizeof(*ctx)); } -void mbedtls_sha256_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; -} - void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. @@ -219,12 +207,6 @@ void mbedtls_sha512_hw_free(crypto_sha_context *ctx) crypto_zeroize(ctx, sizeof(*ctx)); } -void mbedtls_sha512_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; -} - void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h index a492609be3..120a8abdf7 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h @@ -47,8 +47,6 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); void mbedtls_sha1_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha1_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha1_hw_starts( crypto_sha_context *ctx ); void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ); @@ -60,8 +58,6 @@ void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[ void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); void mbedtls_sha256_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha256_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 ); void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); @@ -74,8 +70,6 @@ void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char dat void mbedtls_sha512_hw_init( crypto_sha_context *ctx ); void mbedtls_sha512_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha512_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384 ); void mbedtls_sha512_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index c6dc7394ac..246a75858b 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -59,12 +59,6 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) crypto_zeroize(ctx, sizeof(*ctx)); } -void mbedtls_sha1_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; -} - void mbedtls_sha1_hw_starts(crypto_sha_context *ctx) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. @@ -138,12 +132,6 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) crypto_zeroize(ctx, sizeof(*ctx)); } -void mbedtls_sha256_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; -} - void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h index 18caf697e0..9b91f7c27a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h @@ -47,8 +47,6 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); void mbedtls_sha1_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha1_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha1_hw_starts( crypto_sha_context *ctx ); void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ); @@ -60,8 +58,6 @@ void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[ void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); void mbedtls_sha256_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha256_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 ); void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); From 51087a9f508e4c7d62233a6830b1e582572fc11c Mon Sep 17 00:00:00 2001 From: ccli8 Date: Mon, 25 Dec 2017 10:54:56 +0800 Subject: [PATCH 084/118] Fix DMA input/output buffers are overlapped in AES alter. --- .../TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c | 9 ++++++ .../TARGET_NUVOTON/TARGET_M480/des/des_alt.c | 1 + .../TARGET_NUC472/aes/aes_alt.c | 9 ++++++ .../TARGET_NUC472/des/des_alt.c | 1 + .../TARGET_M480/crypto/crypto-misc.c | 32 +++++++++++++++++++ .../TARGET_M480/crypto/crypto-misc.h | 3 ++ .../TARGET_NUC472/crypto/crypto-misc.c | 32 +++++++++++++++++++ .../TARGET_NUC472/crypto/crypto-misc.h | 3 ++ 8 files changed, 90 insertions(+) diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 855d415f78..69a6f790af 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -160,6 +160,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->keys, ctx->keySize); + /* AES DMA buffer requirements same as above */ if (! crypto_dma_buff_compat(input, dataSize, 16)) { memcpy(au8InputData, input, dataSize); @@ -174,6 +175,14 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, pOut = output; } + /* Even though AES H/W has limited support for overlapped DMA input/output buffers, + * we still seek to one backup buffer to make them non-overlapped for simplicity. */ + if (crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } + MBED_ASSERT(! crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)); + AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); crypto_aes_prestart(); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index fdbb9775c5..2ef63f4b3c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -407,6 +407,7 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S memcpy(dmabuf_in, in_pos, data_len); + /* We always use DMA backup buffers, which are guaranteed to be non-overlapped. */ TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); crypto_des_prestart(); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index f8a1c97d5e..af52848035 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -160,6 +160,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); AES_SetInitVect(0, ctx->iv); AES_SetKey(0, ctx->keys, ctx->keySize); + /* AES DMA buffer requirements same as above */ if (! crypto_dma_buff_compat(input, dataSize, 16)) { memcpy(au8InputData, input, dataSize); @@ -174,6 +175,14 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, pOut = output; } + /* Even though AES H/W has limited support for overlapped DMA input/output buffers, + * we still seek to one backup buffer to make them non-overlapped for simplicity. */ + if (crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } + MBED_ASSERT(! crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)); + AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); crypto_aes_prestart(); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index fdbb9775c5..2ef63f4b3c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -407,6 +407,7 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S memcpy(dmabuf_in, in_pos, data_len); + /* We always use DMA backup buffers, which are guaranteed to be non-overlapped. */ TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); crypto_des_prestart(); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c index 0c830a5dfc..808bfd38b8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c @@ -171,6 +171,38 @@ bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_alig (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ } +/* Overlap cases + * + * 1. in_buff in front of out_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + * + * 2. out_buff in front of in_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size) +{ + uint32_t in = (uint32_t) in_buff; + uint32_t in_end = in + in_buff_size; + uint32_t out = (uint32_t) out_buff; + uint32_t out_end = out + out_buff_size; + + bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end); + + return overlap; +} + static bool crypto_submodule_acquire(uint16_t *submodule_avail) { uint16_t expectedCurrentValue = 1; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h index 356c02706b..f2cc89797f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h @@ -76,6 +76,9 @@ bool crypto_des_wait(void); */ bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); +/* Check if input/output buffers are overlapped */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size); + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c index 0c830a5dfc..808bfd38b8 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c @@ -171,6 +171,38 @@ bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_alig (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ } +/* Overlap cases + * + * 1. in_buff in front of out_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + * + * 2. out_buff in front of in_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size) +{ + uint32_t in = (uint32_t) in_buff; + uint32_t in_end = in + in_buff_size; + uint32_t out = (uint32_t) out_buff; + uint32_t out_end = out + out_buff_size; + + bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end); + + return overlap; +} + static bool crypto_submodule_acquire(uint16_t *submodule_avail) { uint16_t expectedCurrentValue = 1; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h index 356c02706b..f2cc89797f 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h @@ -76,6 +76,9 @@ bool crypto_des_wait(void); */ bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); +/* Check if input/output buffers are overlapped */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size); + #ifdef __cplusplus } #endif From 1ca129ae547ddbe1551e3cd88ed7e510521b2129 Mon Sep 17 00:00:00 2001 From: Adam Heinrich Date: Fri, 29 Dec 2017 15:26:04 +0100 Subject: [PATCH 085/118] NUCLEO_F413ZH: Add support for the NUCLEO-F413ZH board Merged from the existing TARGET_DISCO_F413ZH code (which has the same MCU) and TARGET_NUCLEO_F412ZG code (which has the same Nucleo-144 board and pinout). --- .../targets/TARGET_STM/USBHAL_IP_OTGFSHS.h | 1 + .../targets/TARGET_STM/USBHAL_STM32.h | 1 + .../targets/TARGET_STM/USBHALHost_STM.h | 2 + features/unsupported/tests/mbed/can/main.cpp | 5 +- .../tests/mbed/can_interrupt/main.cpp | 5 +- .../tests/mbed/can_loopback/main.cpp | 3 +- .../TARGET_NUCLEO_F413ZH/PeripheralNames.h | 90 ++++ .../TARGET_NUCLEO_F413ZH/PeripheralPins.c | 396 ++++++++++++++++++ .../TARGET_NUCLEO_F413ZH/PinNames.h | 261 ++++++++++++ .../TARGET_NUCLEO_F413ZH/system_clock.c | 269 ++++++++++++ targets/targets.json | 18 + tools/build_travis.py | 7 + tools/export/sw4stm32/__init__.py | 5 + tools/tests.py | 8 +- 14 files changed, 1062 insertions(+), 9 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h index aed73f082f..84c535a04d 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h @@ -140,6 +140,7 @@ USBHAL::USBHAL(void) { defined(TARGET_NUCLEO_F401RE) || \ defined(TARGET_NUCLEO_F411RE) || \ defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ defined(TARGET_NUCLEO_F429ZI) || \ defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_F446ZE) || \ diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h index ca7dfec734..bb6cdda740 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h @@ -22,6 +22,7 @@ defined(TARGET_NUCLEO_F401RE) || \ defined(TARGET_NUCLEO_F411RE) || \ defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ defined(TARGET_NUCLEO_F429ZI) || \ defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_F446ZE) || \ diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h index 0060efed00..4f8b5c58a4 100644 --- a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h +++ b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h @@ -67,6 +67,7 @@ static gpio_t gpio_powerpin; // NUCLEO_144 boards #elif defined(TARGET_NUCLEO_F207ZG) || \ defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ defined(TARGET_NUCLEO_F429ZI) || \ defined(TARGET_NUCLEO_F439ZI) || \ defined(TARGET_NUCLEO_F446ZE) || \ @@ -189,6 +190,7 @@ USBHALHost::USBHALHost() defined(TARGET_NUCLEO_L486RG) || \ defined(TARGET_NUCLEO_F207ZG) || \ defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ defined(TARGET_NUCLEO_F429ZI) || \ defined(TARGET_NUCLEO_F439ZI) || \ defined(TARGET_NUCLEO_F446ZE) || \ diff --git a/features/unsupported/tests/mbed/can/main.cpp b/features/unsupported/tests/mbed/can/main.cpp index 6f58a3d18c..6ecc386eaa 100644 --- a/features/unsupported/tests/mbed/can/main.cpp +++ b/features/unsupported/tests/mbed/can/main.cpp @@ -21,7 +21,8 @@ CAN can1(PD_0, PD_1); defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F103RB) || \ defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_L476RG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) + defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) || \ + defined(TARGET_NUCLEO_F413ZH) CAN can1(PA_11, PA_12); #elif defined(TARGET_DISCO_F469NI) ||defined(TARGET_DISCO_F746NG) CAN can1(PB_8, PB_9); @@ -36,7 +37,7 @@ CAN can2(p30, p29); #elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_DISCO_F469NI) || \ defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F746ZG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_DISCO_F746NG) + defined(TARGET_DISCO_F746NG) || defined(TARGET_NUCLEO_F413ZH) CAN can2(PB_5, PB_6); #endif char counter = 0; diff --git a/features/unsupported/tests/mbed/can_interrupt/main.cpp b/features/unsupported/tests/mbed/can_interrupt/main.cpp index 16e0709b69..289f569fdb 100644 --- a/features/unsupported/tests/mbed/can_interrupt/main.cpp +++ b/features/unsupported/tests/mbed/can_interrupt/main.cpp @@ -21,7 +21,8 @@ CAN can1(PD_0, PD_1); defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F103RB) || \ defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_L476RG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) + defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) || \ + defined(TARGET_NUCLEO_F413ZH) CAN can1(PA_11, PA_12); #elif defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG) CAN can1(PB_8, PB_9); @@ -36,7 +37,7 @@ CAN can2(p30, p29); #elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_DISCO_F469NI) || \ defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F746ZG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_DISCO_F746NG) + defined(TARGET_DISCO_F746NG) || defined(TARGET_NUCLEO_F413ZH) CAN can2(PB_5, PB_6); #endif char counter = 0; diff --git a/features/unsupported/tests/mbed/can_loopback/main.cpp b/features/unsupported/tests/mbed/can_loopback/main.cpp index 76a6947d13..f67377b723 100644 --- a/features/unsupported/tests/mbed/can_loopback/main.cpp +++ b/features/unsupported/tests/mbed/can_loopback/main.cpp @@ -20,7 +20,8 @@ CAN can1(P5_9, P5_10); defined(TARGET_DISCO_F429ZI) || \ defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_DISCO_L476VG) || defined(TARGET_DISCO_L475VG_IOT01A) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_L432KC) + defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_L432KC) || \ + defined(TARGET_NUCLEO_F413ZH) CAN can1(PA_11, PA_12); #elif defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG) || \ defined(TARGET_NUCLEO_F446ZE) || defined(TARGET_NUCLEO_F103RB) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h new file mode 100644 index 0000000000..5a74e14367 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE, + UART_9 = (int)UART9_BASE, + UART_10 = (int)UART10_BASE +} UARTName; + +#define STDIO_UART_TX PD_8 +#define STDIO_UART_RX PD_9 +#define STDIO_UART UART_3 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + FMPI2C_1 = (int)FMPI2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE, + CAN_3 = (int)CAN3_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c new file mode 100644 index 0000000000..01e5ded312 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c @@ -0,0 +1,396 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // Connected to LED1 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_3_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LED2 + {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LED3 + {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)}, + {PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PD_12, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PD_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// Pins using PWM_5 (TIM5) cannot be used as TIM5 is already used by ticker. +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, + {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, + {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, + {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, + {PA_6_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, + {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, + {PA_7_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, + {PA_7_ALT1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, + {PA_7_ALT2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // Connected to LED1 + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // Connected to LED1 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // Connected to LED1 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // Connected to LED2 + {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, + {PB_8_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, + {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, + {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, + {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // Connected to LED3 + {PB_14_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // Connected to LED3 + {PB_14_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // Connected to LED3 + {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, + {PB_15_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, + {PB_15_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, +// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, +// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, +// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, +// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PA_15_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX + {PD_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_1, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_12, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PB_3_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED2 + {PB_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX + {PD_14, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PG_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_11, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED3 + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_10_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_5_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_6_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED3 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_5_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, // Connected to LED1 + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_2_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_4_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_4, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h new file mode 100644 index 0000000000..2060e5cb23 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h @@ -0,0 +1,261 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, + PA_3 = 0x03, + PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, + PA_5 = 0x05, + PA_5_ALT0 = PA_5|ALT0, + PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT1 = PA_7|ALT1, + PA_7_ALT2 = PA_7|ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_10_ALT0 = PA_10|ALT0, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_12_ALT0 = PA_12|ALT0, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15|ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT1 = PB_0|ALT1, + PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT1 = PB_1|ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PA_4|ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, + PB_6 = 0x16, + PB_6_ALT0 = PB_6|ALT0, + PB_7 = 0x17, + PB_8 = 0x18, + PB_8_ALT0 = PB_8|ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9|ALT0, + PB_10 = 0x1A, + PB_10_ALT0 = PB_10|ALT0, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_12_ALT0 = PB_12|ALT0, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13|ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT1 = PB_14|ALT1, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15|ALT0, + PB_15_ALT1 = PB_15|ALT1, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_6_ALT0 = PC_6|ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7|ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8|ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9|ALT0, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11|ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_2_ALT0 = PE_2|ALT0, + PE_3 = 0x43, + PE_4 = 0x44, + PE_4_ALT0 = PE_4|ALT0, + PE_5 = 0x45, + PE_5_ALT0 = PE_5|ALT0, + PE_6 = 0x46, + PE_6_ALT0 = PE_6|ALT0, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_11_ALT0 = PE_11|ALT0, + PE_12 = 0x4C, + PE_12_ALT0 = PE_12|ALT0, + PE_13 = 0x4D, + PE_13_ALT0 = PE_13|ALT0, + PE_14 = 0x4E, + PE_14_ALT0 = PE_14|ALT0, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PA_3, + A1 = PC_0, + A2 = PC_3, + A3 = PC_1, + A4 = PC_4, + A5 = PC_5, + D0 = PG_9, + D1 = PG_14, + D2 = PF_15, + D3 = PE_13, + D4 = PF_14, + D5 = PE_11, + D6 = PE_9, + D7 = PF_13, + D8 = PF_12, + D9 = PD_15, + D10 = PD_14, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PB_0, // Green + LED2 = PB_7, // Blue + LED3 = PB_14, // Red + LED4 = LED1, + LED_RED = LED3, + USER_BUTTON = PC_13, + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = PD_8, + SERIAL_RX = PD_9, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + //USB pins + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c new file mode 100644 index 0000000000..34aa173313 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c @@ -0,0 +1,269 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 + * AHBCLK (MHz) | 100 + * APB1CLK (MHz) | 50 + * APB2CLK (MHz) | 100 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "mbed_assert.h" + + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLI2S output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/targets.json b/targets/targets.json index ca11e7e011..74129bf634 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1093,6 +1093,24 @@ "release_versions": ["2", "5"], "device_name": "STM32F413ZH" }, + "NUCLEO_F413ZH": { + "inherits": ["FAMILY_STM32"], + "supported_form_factors": ["ARDUINO"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32F4", "STM32F413xx", "STM32F413ZH", "STM32F413xH"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + } + }, + "detect_code": ["0743"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], + "release_versions": ["2", "5"], + "device_name": "STM32F413ZH" + }, "ELMO_F411RE": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], diff --git a/tools/build_travis.py b/tools/build_travis.py index 325a68d728..370282f083 100644 --- a/tools/build_travis.py +++ b/tools/build_travis.py @@ -52,6 +52,7 @@ build_list = [ { "target": "NUCLEO_F410RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_F412ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F413ZH", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_L432KC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_L476RG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_L011K4", "toolchains": "GCC_ARM", "libs": ["dsp"] }, @@ -243,6 +244,12 @@ linking_list = [ "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], } }, + {"target": "NUCLEO_F413ZH", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, {"target": "NUCLEO_F429ZI", "toolchains": "GCC_ARM", "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index 9d55dae8fe..8bcf75f9a4 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -189,6 +189,11 @@ class Sw4STM32(GNUARMEclipse): 'name': 'NUCLEO-F411RE', 'mcuId': 'STM32F411RETx' }, + 'NUCLEO_F413ZH': + { + 'name': 'NUCLEO-F413ZH', + 'mcuId': 'STM32F413ZHTx' + }, 'NUCLEO_F429ZI': { 'name': 'NUCLEO-F429ZI', diff --git a/tools/tests.py b/tools/tests.py index 4b31665d34..0c23875864 100644 --- a/tools/tests.py +++ b/tools/tests.py @@ -320,7 +320,7 @@ TESTS = [ "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_A28", "description": "CAN loopback test", @@ -334,7 +334,7 @@ TESTS = [ "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_A29", "description": "i2c_master_slave_asynch", @@ -589,7 +589,7 @@ TESTS = [ "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE", "DISCO_F469NI", "NUCLEO_F207ZG", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_30", "description": "CAN network test using interrupts", @@ -600,7 +600,7 @@ TESTS = [ "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE", "NUCLEO_F446ZE", "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_31", "description": "PWM LED test", From f07c985707ee23442f9c7c7387f67c88bcb721fd Mon Sep 17 00:00:00 2001 From: gorazd Date: Mon, 4 Dec 2017 10:12:39 +0100 Subject: [PATCH 086/118] ff_lpc546xx: add enet fsl_phy.c/.h move to ../drivers to reuse it lwip: add hardware_init.c --- .../hardware_init_LPC546XX.c | 227 ++++++++++++++++++ .../hardware_init_LPC546XX.c} | 0 .../{TARGET_LPCXpresso => drivers}/fsl_phy.c | 0 .../{TARGET_LPCXpresso => drivers}/fsl_phy.h | 0 targets/targets.json | 1 - 5 files changed, 227 insertions(+), 1 deletion(-) create mode 100644 features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_FF_LPC546XX/hardware_init_LPC546XX.c rename features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/{harware_init_LPC546XX.c => TARGET_LPCXpresso/hardware_init_LPC546XX.c} (100%) rename targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/{TARGET_LPCXpresso => drivers}/fsl_phy.c (100%) rename targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/{TARGET_LPCXpresso => drivers}/fsl_phy.h (100%) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_FF_LPC546XX/hardware_init_LPC546XX.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_FF_LPC546XX/hardware_init_LPC546XX.c new file mode 100644 index 0000000000..096689e5e5 --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_FF_LPC546XX/hardware_init_LPC546XX.c @@ -0,0 +1,227 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_iocon.h" + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INPFILT_OFF 0x0200u /*!<@brief Input filter disabled */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_FAST 0x0400u /*!<@brief Fast mode, slew rate control is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/******************************************************************************* + * Code + ******************************************************************************/ +void lpc546xx_init_eth_hardware(void) +{ + CLOCK_EnableClock(kCLOCK_InputMux); + + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin10_config = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN10 (coords: P2) is configured as SWO */ + IOCON_PinMuxSet(IOCON, 0U, 10U, port0_pin10_config); + + const uint32_t port1_pin10_config = (/* Pin is configured as ENET_TXD1 */ + IOCON_PIO_FUNC1 /* IOCON_PIO_FUNC1 */ | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN10 (coords: E14) is configured as ENET_TXD1 */ + IOCON_PinMuxSet(IOCON, 1U, 10U, port1_pin10_config); + + + const uint32_t port1_pin18_config = (/* Pin is configured as ENET_PHY_RST */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN18 (coords: H11) is configured as ENET_PHY_RST */ + IOCON_PinMuxSet(IOCON, 1U, 18U, port1_pin18_config); + + const uint32_t port1_pin14_config = (/* Pin is configured as ENET_RX_DV */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN14 (coords: B9) is configured as ENET_RX_DV */ + IOCON_PinMuxSet(IOCON, 1U, 14U, port1_pin14_config); + + const uint32_t port1_pin12_config = (/* Pin is configured as ENET_RXD0 */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN12 (coords: A9) is configured as ENET_RXD0 */ + IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config); + + const uint32_t port1_pin13_config = (/* Pin is configured as ENET_RXD1 */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN12 (coords: A6) is configured as ENET_RXD1 */ + IOCON_PinMuxSet(IOCON, 1U, 13U, port1_pin13_config); + + const uint32_t port1_pin11_config = (/* Pin is configured as ENET_TX_EN */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN13 (coords: B6) is configured as ENET_TX_EN */ + IOCON_PinMuxSet(IOCON, 1U, 11U, port1_pin11_config); + + const uint32_t port1_pin15_config = (/* Pin is configured as ENET_RX_CLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN14 (coords: B5) is configured as ENET_RX_CLK */ + IOCON_PinMuxSet(IOCON, 1U, 15U, port1_pin15_config); + + const uint32_t port1_pin16_config = (/* Pin is configured as ENET_MDC */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN15 (coords: A4) is configured as ENET_MDC */ + IOCON_PinMuxSet(IOCON, 1U, 16U, port1_pin16_config); + + const uint32_t port1_pin17_config = (/* Pin is configured as ENET_MDIO */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN16 (coords: C4) is configured as ENET_MDIO */ + IOCON_PinMuxSet(IOCON, 1U, 17U, port1_pin17_config); + + const uint32_t port1_pin9_config = (/* Pin is configured as ENET_TXD0 */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN8 (coords: B14) is configured as ENET_TXD0 */ + IOCON_PinMuxSet(IOCON, 1U, 9U, port1_pin9_config); +} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/harware_init_LPC546XX.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_LPCXpresso/hardware_init_LPC546XX.c similarity index 100% rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/harware_init_LPC546XX.c rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_LPCXpresso/hardware_init_LPC546XX.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h diff --git a/targets/targets.json b/targets/targets.json index 74129bf634..6adc2b076f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -744,7 +744,6 @@ "FF_LPC546XX": { "inherits": ["LPC546XX"], "extra_labels_remove" : ["LPCXpresso"], - "features_remove": ["LWIP"], "supported_form_factors": [""], "detect_code": ["8081"] }, From 4a2ace99d50b8fb19bee6f235049f7ed49e50e1d Mon Sep 17 00:00:00 2001 From: gorazd Date: Wed, 6 Dec 2017 09:40:27 +0100 Subject: [PATCH 087/118] ff_lpc546xx: change led1 and led3 and p26 pins --- .../TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c | 2 +- .../TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c index bb555ca3b7..ca4d335efa 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c @@ -120,6 +120,6 @@ const PinMap PinMap_PWM[] = { {P0_19 , PWM_3, 4}, {P0_22 , PWM_4, 4}, {P0_28 , PWM_8, 4}, - {P0_29 , PWM_9, 4}, + {P1_31 , PWM_7, 4}, {NC , NC, 0} }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h index bc22e8e4bc..c51fe2c23c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h @@ -183,9 +183,9 @@ typedef enum { // mbed original LED naming - LED1 = P0_13, + LED1 = P1_3, LED2 = P1_27, - LED3 = P0_14, + LED3 = P1_26, LED4 = P1_28, @@ -223,7 +223,7 @@ typedef enum { p23 = P0_19, p24 = P0_22, p25 = P0_28, - p26 = P0_29, + p26 = P1_31, p27 = P1_30, p28 = P1_29, p29 = P0_0, From f42db05e550f350e94aa6bbcdca3f8e327cc7470 Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Thu, 14 Dec 2017 17:18:31 +0200 Subject: [PATCH 088/118] Add minimal debug info to release and develop profiles. This allows minimal debugging and allows tools like mbed-os-linker-report to work properly. Because debugging info is kept in .elf file and not flashed to device there is no side effects to flash sizes. --- tools/profiles/develop.json | 2 +- tools/profiles/release.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 465a1853f8..8bf0db68a7 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-fno-builtin", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os"], + "-fomit-frame-pointer", "-Os", "-g1"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu99"], "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"], diff --git a/tools/profiles/release.json b/tools/profiles/release.json index 11207322d6..1fa503836d 100644 --- a/tools/profiles/release.json +++ b/tools/profiles/release.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-fno-builtin", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os", "-DNDEBUG"], + "-fomit-frame-pointer", "-Os", "-DNDEBUG", "-g1"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu99"], "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"], From fd800caced87545e12924b781b1e5424614ccd8b Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 21 Dec 2017 10:50:47 +0100 Subject: [PATCH 089/118] STM32 : issue to exit deepsleep when RTC has not been initialized --- targets/TARGET_STM/rtc_api.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 2b9b31a769..0f851a2e52 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -288,6 +288,7 @@ int rtc_isenabled(void) void rtc_synchronize(void) { + RtcHandle.Instance = RTC; if (HAL_RTC_WaitForSynchro(&RtcHandle) != HAL_OK) { error("rtc_synchronize error\n"); } @@ -298,6 +299,7 @@ void rtc_synchronize(void) static void RTC_IRQHandler(void) { /* Update HAL state */ + RtcHandle.Instance = RTC; HAL_RTCEx_WakeUpTimerIRQHandler(&RtcHandle); /* In case of registered handler, call it. */ if (irq_handler) { @@ -339,6 +341,7 @@ void rtc_set_wake_up_timer(uint32_t delta) NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler); NVIC_EnableIRQ(RTC_WKUP_IRQn); + RtcHandle.Instance = RTC; if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, 0xFFFF & WakeUpCounter, WakeUpClock[DivIndex-1]) != HAL_OK) { error("rtc_set_wake_up_timer init error (%d)\n", DivIndex); } @@ -346,6 +349,7 @@ void rtc_set_wake_up_timer(uint32_t delta) void rtc_deactivate_wake_up_timer(void) { + RtcHandle.Instance = RTC; HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle); } From 50ceca76ced9821761d96a41ab58b6e69e513071 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 10:29:53 -0600 Subject: [PATCH 090/118] Handle multiple args per line in IAR cmd parser --- tools/memap.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index 0b468f8a59..f8f7369e4b 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -432,16 +432,15 @@ class MemapParser(object): for line in lines: if line.startswith("*"): break - is_cmdline_file = RE_CMDLINE_FILE_IAR.match(line) - if is_cmdline_file: - full_path = is_cmdline_file.group(1) - self.cmd_modules[os.path.basename(full_path)] = full_path + for arg in line.split(" "): + arg = arg.rstrip(" \n") + if (not arg.startswith("-")) and arg.endswith(".o"): + self.cmd_modules[os.path.basename(arg)] = arg common_prefix = os.path.dirname(os.path.commonprefix(self.cmd_modules.values())) self.cmd_modules = {s: os.path.relpath(f, common_prefix) for s, f in self.cmd_modules.items()} - def parse_map_file_iar(self, file_desc): """ Main logic to decode IAR map files From 2e5fd744e9a581930f111574de8f245aa91384c3 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 10:31:00 -0600 Subject: [PATCH 091/118] Use os.sep and os.join instead of string ops --- tools/memap.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index f8f7369e4b..221d6a3c64 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -136,7 +136,6 @@ class MemapParser(object): txt - the path to parse the object and module name from """ - line = line.replace('\\', '/') test_re_mbed_os_name = re.match(RE_OBJECT_FILE_GCC, line) if test_re_mbed_os_name: @@ -145,7 +144,7 @@ class MemapParser(object): # corner case: certain objects are provided by the GCC toolchain if 'arm-none-eabi' in line: - return '[lib]/misc/' + object_name + return os.path.join('[lib]', 'misc', object_name) return object_name else: @@ -153,10 +152,10 @@ class MemapParser(object): test_re_obj_name = re.match(RE_LIBRARY_OBJECT_GCC, line) if test_re_obj_name: - object_name = test_re_obj_name.group(1) + '/' + \ - test_re_obj_name.group(2) + object_name = os.path.join(test_re_obj_name.group(1), + test_re_obj_name.group(2)) - return '[lib]/' + object_name + return os.path.join('[lib]', object_name) else: print "Unknown object name found in GCC map file: %s" % line @@ -241,8 +240,9 @@ class MemapParser(object): else: is_obj = re.match(RE_OBJECT_ARMCC, line) if is_obj: - object_name = os.path.basename(is_obj.group(1)) + '/' + is_obj.group(3) - return '[lib]/' + object_name + object_name = os.path.join(os.path.basename(is_obj.group(1)), + is_obj.group(3)) + return os.path.join('[lib]', object_name) else: print "Malformed input found when parsing ARMCC map: %s" % line return '[misc]' @@ -472,7 +472,7 @@ class MemapParser(object): object_name = self.check_new_object_lib_iar(line) if object_name and current_library: - temp = '[lib]' + '/'+ current_library + '/'+ object_name + temp = os.path.join('[lib]', current_library, object_name) self.module_replace(object_name, temp) @@ -495,10 +495,10 @@ class MemapParser(object): else: self.short_modules = dict() for module_name, v in self.modules.items(): - split_name = module_name.split('/') + split_name = module_name.split(os.sep) if split_name[0] == '': split_name = split_name[1:] - new_name = "/".join(split_name[:depth]) + new_name = os.path.join(*split_name[:depth]) self.short_modules.setdefault(new_name, {}) for section_idx, value in v.items(): self.short_modules[new_name].setdefault(section_idx, 0) From 6607c3b75511e8dbb0b8ed8ce4c0a547a0706b04 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 10:42:29 -0600 Subject: [PATCH 092/118] Format memap --- tools/memap.py | 67 ++++++++++---------------------------------------- 1 file changed, 13 insertions(+), 54 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index 221d6a3c64..f5574b17e0 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -50,12 +50,11 @@ class MemapParser(object): sections = ('.text', '.data', '.bss', '.heap', '.stack') def __init__(self): - """ General initialization - """ - # list of all modules and their sections - self.modules = dict() # full list - doesn't change with depth - self.short_modules = dict() # short version with specific depth + # full list - doesn't change with depth + self.modules = dict() + # short version with specific depth + self.short_modules = dict() # sections must be defined in this order to take irrelevant out self.all_sections = self.sections + self.other_sections + \ @@ -64,27 +63,27 @@ class MemapParser(object): # Memory report (sections + summary) self.mem_report = [] - # Just the memory summary section + # Memory summary self.mem_summary = dict() + # Totals of ".text", ".data" and ".bss" self.subtotal = dict() + # Flash no associated with a module self.misc_flash_mem = 0 # Modules passed to the linker on the command line # this is a dict because modules are looked up by their basename self.cmd_modules = {} - def module_add(self, object_name, size, section): - """ Adds a module / section to the list + """ Adds a module or section to the list Positional arguments: object_name - name of the entry to add size - the size of the module being added section - the section the module contributes to """ - if not object_name or not size or not section: return @@ -117,7 +116,6 @@ class MemapParser(object): Positional arguments: line - the line to check for a new section """ - for i in self.all_sections: if line.startswith(i): # should name of the section (assuming it's a known one) @@ -135,11 +133,9 @@ class MemapParser(object): Positional arguments: txt - the path to parse the object and module name from """ - test_re_mbed_os_name = re.match(RE_OBJECT_FILE_GCC, line) if test_re_mbed_os_name: - object_name = test_re_mbed_os_name.group(1) # corner case: certain objects are provided by the GCC toolchain @@ -148,15 +144,12 @@ class MemapParser(object): return object_name else: - test_re_obj_name = re.match(RE_LIBRARY_OBJECT_GCC, line) if test_re_obj_name: object_name = os.path.join(test_re_obj_name.group(1), test_re_obj_name.group(2)) - return os.path.join('[lib]', object_name) - else: print "Unknown object name found in GCC map file: %s" % line return '[misc]' @@ -171,7 +164,6 @@ class MemapParser(object): Positional arguments: line - the line to parse a section from """ - is_fill = re.match(RE_FILL_SECTION_GCC, line) if is_fill: o_name = '[fill]' @@ -193,7 +185,6 @@ class MemapParser(object): Positional arguments: file_desc - a stream object to parse as a gcc map file """ - current_section = 'unknown' with file_desc as infile: @@ -211,7 +202,6 @@ class MemapParser(object): current_section = next_section object_name, object_size = self.parse_section_gcc(line) - self.module_add(object_name, object_size, current_section) common_prefix = os.path.dirname(os.path.commonprefix([ @@ -232,9 +222,7 @@ class MemapParser(object): Positional arguments: line - the line containing the object or library """ - - # simple object (not library) - if line[-2] == '.' and line[-1] == 'o': + if line.endswith(".o"): return line else: @@ -247,8 +235,6 @@ class MemapParser(object): print "Malformed input found when parsing ARMCC map: %s" % line return '[misc]' - - def parse_section_armcc(self, line): """ Parse data from an armcc map file @@ -260,11 +246,9 @@ class MemapParser(object): Positional arguments: line - the line to parse the section data from """ - test_re_armcc = re.match(RE_ARMCC, line) if test_re_armcc: - size = int(test_re_armcc.group(2), 16) if test_re_armcc.group(4) == 'RO': @@ -283,7 +267,7 @@ class MemapParser(object): return ["", 0, ""] # check name of object or library - object_name = self.parse_object_name_armcc(\ + object_name = self.parse_object_name_armcc( test_re_armcc.group(6)) return [object_name, size, section] @@ -297,8 +281,6 @@ class MemapParser(object): Positional arguments: line - the line containing the object or library """ - - # simple object (not library) if object_name.endswith(".o"): try: return self.cmd_modules[object_name] @@ -307,7 +289,6 @@ class MemapParser(object): else: return '[misc]' - def parse_section_iar(self, line): """ Parse data from an IAR map file @@ -325,13 +306,8 @@ class MemapParser(object): Positional_arguments: line - the line to parse section data from """ - test_re_iar = re.match(RE_IAR, line) - if test_re_iar: - - size = int(test_re_iar.group(4), 16) - if (test_re_iar.group(2) == 'const' or test_re_iar.group(2) == 'ro code'): section = '.text' @@ -348,14 +324,16 @@ class MemapParser(object): section = '.data' else: print "Malformed input found when parsing IAR map: %s" % line + return ["", 0, ""] # lookup object in dictionary and return module name object_name = self.parse_object_name_iar(test_re_iar.group(5)) + size = int(test_re_iar.group(4), 16) return [object_name, size, section] else: - return ["", 0, ""] # no valid entry + return ["", 0, ""] def parse_map_file_armcc(self, file_desc): """ Main logic to decode armc5 map files @@ -363,9 +341,7 @@ class MemapParser(object): Positional arguments: file_desc - a file like object to parse as an armc5 map file """ - with file_desc as infile: - # Search area to parse for line in infile: if line.startswith(' Base Addr Size'): @@ -387,18 +363,13 @@ class MemapParser(object): new_modules[name] = stats self.modules = new_modules - - def check_new_library_iar(self, line): """ Searches for libraries and returns name. Example: m7M_tls.a: [43] """ - - test_address_line = re.match(RE_LIBRARY_IAR, line) - if test_address_line: return test_address_line.group(1) else: @@ -415,9 +386,7 @@ class MemapParser(object): I64DivZer.o 2 """ - test_address_line = re.match(RE_OBJECT_LIBRARY_IAR, line) - if test_address_line: return test_address_line.group(1) else: @@ -447,7 +416,6 @@ class MemapParser(object): Positional arguments: file_desc - a file like object to parse as an IAR map file """ - with file_desc as infile: self.parse_iar_command_line(infile) @@ -463,7 +431,6 @@ class MemapParser(object): current_library = "" for line in infile: - library = self.check_new_library_iar(line) if library: @@ -475,7 +442,6 @@ class MemapParser(object): temp = os.path.join('[lib]', current_library, object_name) self.module_replace(object_name, temp) - def reduce_depth(self, depth): """ populates the short_modules attribute with a truncated module list @@ -504,7 +470,6 @@ class MemapParser(object): self.short_modules[new_name].setdefault(section_idx, 0) self.short_modules[new_name][section_idx] += self.modules[module_name][section_idx] - export_formats = ["json", "csv-ci", "table"] def generate_output(self, export_format, depth, file_output=None): @@ -519,10 +484,8 @@ class MemapParser(object): Returns: generated string for the 'table' format, otherwise None """ - self.reduce_depth(depth) self.compute_report() - try: if file_output: file_desc = open(file_output, 'wb') @@ -550,7 +513,6 @@ class MemapParser(object): """ file_desc.write(json.dumps(self.mem_report, indent=4)) file_desc.write('\n') - return None def generate_csv(self, file_desc): @@ -577,7 +539,6 @@ class MemapParser(object): csv_writer.writerow(csv_module_section) csv_writer.writerow(csv_sizes) - return None def generate_table(self, file_desc): @@ -659,7 +620,6 @@ class MemapParser(object): mapfile - the file name of the memory map file toolchain - the toolchain used to create the file """ - result = True try: with open(mapfile, 'r') as file_input: @@ -679,7 +639,6 @@ class MemapParser(object): def main(): """Entry Point""" - version = '0.4.0' # Parser handling From a38aafe41964b3439a4c12d095bb3dd55dc71f0e Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 11:19:25 -0600 Subject: [PATCH 093/118] Rework parsing dispatch Parsing dispatch now uses a metaclass as a Trait and a series of classes that implement the trait for dispatching parsing. This structure gives each parser it's own namespace, avoiding tacking on suffixes to each attribute indicating which parser uses it. --- tools/memap.py | 330 ++++++++++++++++++--------------- tools/test/memap/parse_test.py | 16 +- 2 files changed, 193 insertions(+), 153 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index f5574b17e0..c582f5e218 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -2,6 +2,7 @@ """Memory Map File Analyser for ARM mbed""" +import abc import sys import os import re @@ -14,67 +15,19 @@ from prettytable import PrettyTable from utils import argparse_filestring_type, \ argparse_lowercase_hyphen_type, argparse_uppercase_type -RE_ARMCC = re.compile( - r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$') -RE_IAR = re.compile( - r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s' - r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$') -RE_CMDLINE_FILE_IAR = re.compile(r'^#\s+(.+\.o)') -RE_LIBRARY_IAR = re.compile(r'^(.+\.a)\:.+$') -RE_OBJECT_LIBRARY_IAR = re.compile(r'^\s+(.+\.o)\s.*') - -RE_OBJECT_FILE_GCC = re.compile(r'^(.+\/.+\.o)$') -RE_LIBRARY_OBJECT_GCC = re.compile(r'^.+\/lib(.+\.a)\((.+\.o)\)$') -RE_STD_SECTION_GCC = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$') -RE_FILL_SECTION_GCC = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$') - -RE_OBJECT_ARMCC = re.compile(r'(.+\.(l|ar))\((.+\.o)\)') - - -class MemapParser(object): - """An object that represents parsed results, parses the memory map files, - and writes out different file types of memory results - """ - - print_sections = ('.text', '.data', '.bss') - - misc_flash_sections = ('.interrupts', '.flash_config') - - other_sections = ('.interrupts_ram', '.init', '.ARM.extab', +class _Parser(object): + """Internal interface for parsing""" + __metaclass__ = abc.ABCMeta + SECTIONS = ('.text', '.data', '.bss', '.heap', '.stack') + MISC_FLASH_SECTIONS = ('.interrupts', '.flash_config') + OTHER_SECTIONS = ('.interrupts_ram', '.init', '.ARM.extab', '.ARM.exidx', '.ARM.attributes', '.eh_frame', '.init_array', '.fini_array', '.jcr', '.stab', '.stabstr', '.ARM.exidx', '.ARM') - # sections to print info (generic for all toolchains) - sections = ('.text', '.data', '.bss', '.heap', '.stack') - def __init__(self): - # list of all modules and their sections - # full list - doesn't change with depth self.modules = dict() - # short version with specific depth - self.short_modules = dict() - - # sections must be defined in this order to take irrelevant out - self.all_sections = self.sections + self.other_sections + \ - self.misc_flash_sections + ('unknown', 'OUTPUT') - - # Memory report (sections + summary) - self.mem_report = [] - - # Memory summary - self.mem_summary = dict() - - # Totals of ".text", ".data" and ".bss" - self.subtotal = dict() - - # Flash no associated with a module - self.misc_flash_mem = 0 - - # Modules passed to the linker on the command line - # this is a dict because modules are looked up by their basename - self.cmd_modules = {} def module_add(self, object_name, size, section): """ Adds a module or section to the list @@ -109,14 +62,38 @@ class MemapParser(object): self.modules[new_object] = self.modules[old_object] del self.modules[old_object] - def check_new_section_gcc(self, line): - """ Check whether a new section in a map file has been detected (only - applies to gcc) + @abc.abstractmethod + def parse_mapfile(self, mapfile): + """Parse a given file object pointing to a map file + + Positional arguments: + mapfile - an open file object that reads a map file + + return value - a dict mapping from object names to section dicts, + where a section dict maps from sections to sizes + """ + raise NotImplemented + + +class _GccParser(_Parser): + RE_OBJECT_FILE = re.compile(r'^(.+\/.+\.o)$') + RE_LIBRARY_OBJECT = re.compile(r'^.+\/lib(.+\.a)\((.+\.o)\)$') + RE_STD_SECTION = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$') + RE_FILL_SECTION = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$') + + ALL_SECTIONS = _Parser.SECTIONS + _Parser.OTHER_SECTIONS + \ + _Parser.MISC_FLASH_SECTIONS + ('unknown', 'OUTPUT') + + def check_new_section(self, line): + """ Check whether a new section in a map file has been detected Positional arguments: line - the line to check for a new section + + return value - A section name, if a new section was found, False + otherwise """ - for i in self.all_sections: + for i in self.ALL_SECTIONS: if line.startswith(i): # should name of the section (assuming it's a known one) return i @@ -127,13 +104,15 @@ class MemapParser(object): return False # everything else, means no change in section - def parse_object_name_gcc(self, line): + def parse_object_name(self, line): """ Parse a path to object file Positional arguments: - txt - the path to parse the object and module name from + line - the path to parse the object and module name from + + return value - an object file name """ - test_re_mbed_os_name = re.match(RE_OBJECT_FILE_GCC, line) + test_re_mbed_os_name = re.match(self.RE_OBJECT_FILE, line) if test_re_mbed_os_name: object_name = test_re_mbed_os_name.group(1) @@ -144,7 +123,7 @@ class MemapParser(object): return object_name else: - test_re_obj_name = re.match(RE_LIBRARY_OBJECT_GCC, line) + test_re_obj_name = re.match(self.RE_LIBRARY_OBJECT, line) if test_re_obj_name: object_name = os.path.join(test_re_obj_name.group(1), @@ -154,32 +133,32 @@ class MemapParser(object): print "Unknown object name found in GCC map file: %s" % line return '[misc]' - def parse_section_gcc(self, line): + def parse_section(self, line): """ Parse data from a section of gcc map file examples: 0x00004308 0x7c ./BUILD/K64F/GCC_ARM/mbed-os/hal/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.o - .text 0x00000608 0x198 ./BUILD/K64F/GCC_ARM/mbed-os/core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/HAL_CM4.o + .text 0x00000608 0x198 ./BUILD/K64F/GCC_ARM/mbed-os/core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN/HAL_CM4.o Positional arguments: line - the line to parse a section from """ - is_fill = re.match(RE_FILL_SECTION_GCC, line) + is_fill = re.match(self.RE_FILL_SECTION, line) if is_fill: o_name = '[fill]' o_size = int(is_fill.group(2), 16) return [o_name, o_size] - is_section = re.match(RE_STD_SECTION_GCC, line) + is_section = re.match(self.RE_STD_SECTION, line) if is_section: o_size = int(is_section.group(2), 16) if o_size: - o_name = self.parse_object_name_gcc(is_section.group(3)) + o_name = self.parse_object_name(is_section.group(3)) return [o_name, o_size] return ["", 0] - def parse_map_file_gcc(self, file_desc): + def parse_mapfile(self, file_desc): """ Main logic to decode gcc map files Positional arguments: @@ -194,14 +173,14 @@ class MemapParser(object): break for line in infile: - next_section = self.check_new_section_gcc(line) + next_section = self.check_new_section(line) if next_section == "OUTPUT": break elif next_section: current_section = next_section - object_name, object_size = self.parse_section_gcc(line) + object_name, object_size = self.parse_section(line) self.module_add(object_name, object_size, current_section) common_prefix = os.path.dirname(os.path.commonprefix([ @@ -214,9 +193,15 @@ class MemapParser(object): new_modules[os.path.relpath(name, common_prefix)] = stats else: new_modules[name] = stats - self.modules = new_modules + return new_modules - def parse_object_name_armcc(self, line): + +class _ArmccParser(_Parser): + RE = re.compile( + r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$') + RE_OBJECT = re.compile(r'(.+\.(l|ar))\((.+\.o)\)') + + def parse_object_name(self, line): """ Parse object file Positional arguments: @@ -226,7 +211,7 @@ class MemapParser(object): return line else: - is_obj = re.match(RE_OBJECT_ARMCC, line) + is_obj = re.match(self.RE_OBJECT, line) if is_obj: object_name = os.path.join(os.path.basename(is_obj.group(1)), is_obj.group(3)) @@ -235,47 +220,91 @@ class MemapParser(object): print "Malformed input found when parsing ARMCC map: %s" % line return '[misc]' - def parse_section_armcc(self, line): + def parse_section(self, line): """ Parse data from an armcc map file Examples of armcc map file: Base_Addr Size Type Attr Idx E Section Name Object - 0x00000000 0x00000400 Data RO 11222 RESET startup_MK64F12.o + 0x00000000 0x00000400 Data RO 11222 self.RESET startup_MK64F12.o 0x00000410 0x00000008 Code RO 49364 * !!!main c_w.l(__main.o) Positional arguments: line - the line to parse the section data from """ - test_re_armcc = re.match(RE_ARMCC, line) + test_re = re.match(self.RE, line) - if test_re_armcc: - size = int(test_re_armcc.group(2), 16) + if test_re: + size = int(test_re.group(2), 16) - if test_re_armcc.group(4) == 'RO': + if test_re.group(4) == 'RO': section = '.text' else: - if test_re_armcc.group(3) == 'Data': + if test_re.group(3) == 'Data': section = '.data' - elif test_re_armcc.group(3) == 'Zero': + elif test_re.group(3) == 'Zero': section = '.bss' - elif test_re_armcc.group(3) == 'Code': + elif test_re.group(3) == 'Code': section = '.text' else: print "Malformed input found when parsing armcc map: %s, %r" %\ - (line, test_re_armcc.groups()) + (line, test_re.groups()) return ["", 0, ""] # check name of object or library - object_name = self.parse_object_name_armcc( - test_re_armcc.group(6)) + object_name = self.parse_object_name( + test_re.group(6)) return [object_name, size, section] else: return ["", 0, ""] - def parse_object_name_iar(self, object_name): + def parse_mapfile(self, file_desc): + """ Main logic to decode armc5 map files + + Positional arguments: + file_desc - a file like object to parse as an armc5 map file + """ + with file_desc as infile: + # Search area to parse + for line in infile: + if line.startswith(' Base Addr Size'): + break + + # Start decoding the map file + for line in infile: + self.module_add(*self.parse_section(line)) + + common_prefix = os.path.dirname(os.path.commonprefix([ + o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))])) + new_modules = {} + for name, stats in self.modules.items(): + if name == "anon$$obj.o" or name.startswith("[lib]"): + new_modules[name] = stats + elif name.endswith(".o"): + new_modules[os.path.relpath(name, common_prefix)] = stats + else: + new_modules[name] = stats + return new_modules + + +class _IarParser(_Parser): + RE = re.compile( + r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s' + r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$') + + RE_CMDLINE_FILE = re.compile(r'^#\s+(.+\.o)') + RE_LIBRARY = re.compile(r'^(.+\.a)\:.+$') + RE_OBJECT_LIBRARY = re.compile(r'^\s+(.+\.o)\s.*') + + def __init__(self): + _Parser.__init__(self) + # Modules passed to the linker on the command line + # this is a dict because modules are looked up by their basename + self.cmd_modules = {} + + def parse_object_name(self, object_name): """ Parse object file Positional arguments: @@ -289,7 +318,7 @@ class MemapParser(object): else: return '[misc]' - def parse_section_iar(self, line): + def parse_section(self, line): """ Parse data from an IAR map file Examples of IAR map file: @@ -306,76 +335,48 @@ class MemapParser(object): Positional_arguments: line - the line to parse section data from """ - test_re_iar = re.match(RE_IAR, line) - if test_re_iar: - if (test_re_iar.group(2) == 'const' or - test_re_iar.group(2) == 'ro code'): + test_re = re.match(self.RE, line) + if test_re: + if (test_re.group(2) == 'const' or + test_re.group(2) == 'ro code'): section = '.text' - elif (test_re_iar.group(2) == 'zero' or - test_re_iar.group(2) == 'uninit'): - if test_re_iar.group(1)[0:4] == 'HEAP': + elif (test_re.group(2) == 'zero' or + test_re.group(2) == 'uninit'): + if test_re.group(1)[0:4] == 'HEAP': section = '.heap' - elif test_re_iar.group(1)[0:6] == 'CSTACK': + elif test_re.group(1)[0:6] == 'CSTACK': section = '.stack' else: section = '.bss' # default section - elif test_re_iar.group(2) == 'inited': + elif test_re.group(2) == 'inited': section = '.data' else: print "Malformed input found when parsing IAR map: %s" % line return ["", 0, ""] # lookup object in dictionary and return module name - object_name = self.parse_object_name_iar(test_re_iar.group(5)) + object_name = self.parse_object_name(test_re.group(5)) - size = int(test_re_iar.group(4), 16) + size = int(test_re.group(4), 16) return [object_name, size, section] else: return ["", 0, ""] - def parse_map_file_armcc(self, file_desc): - """ Main logic to decode armc5 map files - - Positional arguments: - file_desc - a file like object to parse as an armc5 map file - """ - with file_desc as infile: - # Search area to parse - for line in infile: - if line.startswith(' Base Addr Size'): - break - - # Start decoding the map file - for line in infile: - self.module_add(*self.parse_section_armcc(line)) - - common_prefix = os.path.dirname(os.path.commonprefix([ - o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))])) - new_modules = {} - for name, stats in self.modules.items(): - if name == "anon$$obj.o" or name.startswith("[lib]"): - new_modules[name] = stats - elif name.endswith(".o"): - new_modules[os.path.relpath(name, common_prefix)] = stats - else: - new_modules[name] = stats - self.modules = new_modules - - def check_new_library_iar(self, line): + def check_new_library(self, line): """ Searches for libraries and returns name. Example: m7M_tls.a: [43] """ - test_address_line = re.match(RE_LIBRARY_IAR, line) + test_address_line = re.match(self.RE_LIBRARY, line) if test_address_line: return test_address_line.group(1) else: return "" - def check_new_object_lib_iar(self, line): + def check_new_object_lib(self, line): """ Searches for objects within a library section and returns name. Example: rt7M_tl.a: [44] @@ -386,13 +387,13 @@ class MemapParser(object): I64DivZer.o 2 """ - test_address_line = re.match(RE_OBJECT_LIBRARY_IAR, line) + test_address_line = re.match(self.RE_OBJECT_LIBRARY, line) if test_address_line: return test_address_line.group(1) else: return "" - def parse_iar_command_line(self, lines): + def parse_command_line(self, lines): """Parse the files passed on the command line to the iar linker Positional arguments: @@ -410,37 +411,72 @@ class MemapParser(object): self.cmd_modules = {s: os.path.relpath(f, common_prefix) for s, f in self.cmd_modules.items()} - def parse_map_file_iar(self, file_desc): + def parse_mapfile(self, file_desc): """ Main logic to decode IAR map files Positional arguments: file_desc - a file like object to parse as an IAR map file """ with file_desc as infile: - self.parse_iar_command_line(infile) + self.parse_command_line(infile) for line in infile: if line.startswith(' Section '): break for line in infile: - self.module_add(*self.parse_section_iar(line)) + self.module_add(*self.parse_section(line)) if line.startswith('*** MODULE SUMMARY'): # finish section break current_library = "" for line in infile: - library = self.check_new_library_iar(line) + library = self.check_new_library(line) if library: current_library = library - object_name = self.check_new_object_lib_iar(line) + object_name = self.check_new_object_lib(line) if object_name and current_library: temp = os.path.join('[lib]', current_library, object_name) self.module_replace(object_name, temp) + return self.modules + + +class MemapParser(object): + """An object that represents parsed results, parses the memory map files, + and writes out different file types of memory results + """ + + print_sections = ('.text', '.data', '.bss') + + + # sections to print info (generic for all toolchains) + sections = _Parser.SECTIONS + misc_flash_sections = _Parser.MISC_FLASH_SECTIONS + other_sections = _Parser.OTHER_SECTIONS + + def __init__(self): + # list of all modules and their sections + # full list - doesn't change with depth + self.modules = dict() + # short version with specific depth + self.short_modules = dict() + + + # Memory report (sections + summary) + self.mem_report = [] + + # Memory summary + self.mem_summary = dict() + + # Totals of ".text", ".data" and ".bss" + self.subtotal = dict() + + # Flash no associated with a module + self.misc_flash_mem = 0 def reduce_depth(self, depth): """ @@ -620,22 +656,22 @@ class MemapParser(object): mapfile - the file name of the memory map file toolchain - the toolchain used to create the file """ - result = True + if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"): + parser = _ArmccParser() + elif toolchain == "GCC_ARM" or toolchain == "GCC_CR": + parser = _GccParser() + elif toolchain == "IAR": + parser = _IarParser() + else: + return False try: with open(mapfile, 'r') as file_input: - if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"): - self.parse_map_file_armcc(file_input) - elif toolchain == "GCC_ARM" or toolchain == "GCC_CR": - self.parse_map_file_gcc(file_input) - elif toolchain == "IAR": - self.parse_map_file_iar(file_input) - else: - result = False + self.modules = parser.parse_mapfile(file_input) + return True except IOError as error: print "I/O error({0}): {1}".format(error.errno, error.strerror) - result = False - return result + return False def main(): """Entry Point""" diff --git a/tools/test/memap/parse_test.py b/tools/test/memap/parse_test.py index 51eb9cae05..6047749029 100644 --- a/tools/test/memap/parse_test.py +++ b/tools/test/memap/parse_test.py @@ -5,7 +5,7 @@ import json import pytest -from tools.memap import MemapParser +from tools.memap import MemapParser, _ArmccParser from copy import deepcopy @@ -19,7 +19,9 @@ PARSED_ARM_DATA = { def test_parse_armcc(): memap = MemapParser() - memap.parse_map_file_armcc(open(join(dirname(__file__), "arm.map"))) + memap.parse(join(dirname(__file__), "arm.map"), "ARM") + assert memap.modules == PARSED_ARM_DATA + memap.parse(join(dirname(__file__), "arm.map"), "UARM") assert memap.modules == PARSED_ARM_DATA PARSED_IAR_GCC_DATA = { @@ -32,17 +34,19 @@ PARSED_IAR_GCC_DATA = { def test_parse_iar(): memap = MemapParser() - memap.parse_map_file_iar(open(join(dirname(__file__), "iar.map"))) + memap.parse(join(dirname(__file__), "iar.map"), "IAR") assert memap.modules == PARSED_IAR_GCC_DATA def test_parse_gcc(): memap = MemapParser() - memap.parse_map_file_gcc(open(join(dirname(__file__), "gcc.map"))) + memap.parse(join(dirname(__file__), "gcc.map"), "GCC_ARM") + assert memap.modules == PARSED_IAR_GCC_DATA + memap.parse(join(dirname(__file__), "gcc.map"), "GCC_CR") assert memap.modules == PARSED_IAR_GCC_DATA def test_add_empty_module(): - memap = MemapParser() + memap = _ArmccParser() old_modules = deepcopy(memap.modules) memap.module_add("", 8, ".data") assert(old_modules == memap.modules) @@ -52,7 +56,7 @@ def test_add_empty_module(): assert(old_modules == memap.modules) def test_add_full_module(): - memap = MemapParser() + memap = _ArmccParser() old_modules = deepcopy(memap.modules) memap.module_add("main.o", 8, ".data") assert(old_modules != memap.modules) From 94f4fdc72b8df01854682ee8e17eab73d4b2afd9 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 13:37:25 -0600 Subject: [PATCH 094/118] Correct Gcc builtin module naming --- tools/memap.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index c582f5e218..d5ad412aa5 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -77,7 +77,7 @@ class _Parser(object): class _GccParser(_Parser): RE_OBJECT_FILE = re.compile(r'^(.+\/.+\.o)$') - RE_LIBRARY_OBJECT = re.compile(r'^.+\/lib(.+\.a)\((.+\.o)\)$') + RE_LIBRARY_OBJECT = re.compile(r'^.+' + os.sep + r'lib((.+\.a)\((.+\.o)\))$') RE_STD_SECTION = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$') RE_FILL_SECTION = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$') @@ -119,7 +119,7 @@ class _GccParser(_Parser): # corner case: certain objects are provided by the GCC toolchain if 'arm-none-eabi' in line: - return os.path.join('[lib]', 'misc', object_name) + return os.path.join('[lib]', 'misc', os.path.basename(object_name)) return object_name else: From 70bb47fb64fd82ca809bcde34d4f76cade0cc6e7 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 14:19:00 -0600 Subject: [PATCH 095/118] Use non-scoped imports in memap --- tools/memap.py | 62 ++++++++++++++++++++++++-------------------------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index d5ad412aa5..b5c1b68814 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -2,13 +2,14 @@ """Memory Map File Analyser for ARM mbed""" -import abc -import sys -import os +from abc import abstractmethod, ABCMeta +from sys import stdout, exit, argv +from os import sep +from os.path import basename, dirname, join, relpath, commonprefix import re import csv import json -import argparse +from argparse import ArgumentParser from copy import deepcopy from prettytable import PrettyTable @@ -18,7 +19,7 @@ from utils import argparse_filestring_type, \ class _Parser(object): """Internal interface for parsing""" - __metaclass__ = abc.ABCMeta + __metaclass__ = ABCMeta SECTIONS = ('.text', '.data', '.bss', '.heap', '.stack') MISC_FLASH_SECTIONS = ('.interrupts', '.flash_config') OTHER_SECTIONS = ('.interrupts_ram', '.init', '.ARM.extab', @@ -45,7 +46,7 @@ class _Parser(object): self.modules[object_name][section] += size return - obj_split = os.sep + os.path.basename(object_name) + obj_split = sep + basename(object_name) for module_path, contents in self.modules.items(): if module_path.endswith(obj_split) or module_path == object_name: contents.setdefault(section, 0) @@ -62,7 +63,7 @@ class _Parser(object): self.modules[new_object] = self.modules[old_object] del self.modules[old_object] - @abc.abstractmethod + @abstractmethod def parse_mapfile(self, mapfile): """Parse a given file object pointing to a map file @@ -77,7 +78,7 @@ class _Parser(object): class _GccParser(_Parser): RE_OBJECT_FILE = re.compile(r'^(.+\/.+\.o)$') - RE_LIBRARY_OBJECT = re.compile(r'^.+' + os.sep + r'lib((.+\.a)\((.+\.o)\))$') + RE_LIBRARY_OBJECT = re.compile(r'^.+' + sep + r'lib((.+\.a)\((.+\.o)\))$') RE_STD_SECTION = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$') RE_FILL_SECTION = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$') @@ -119,16 +120,15 @@ class _GccParser(_Parser): # corner case: certain objects are provided by the GCC toolchain if 'arm-none-eabi' in line: - return os.path.join('[lib]', 'misc', os.path.basename(object_name)) + return join('[lib]', 'misc', basename(object_name)) return object_name else: test_re_obj_name = re.match(self.RE_LIBRARY_OBJECT, line) if test_re_obj_name: - object_name = os.path.join(test_re_obj_name.group(1), - test_re_obj_name.group(2)) - return os.path.join('[lib]', object_name) + return join('[lib]', test_re_obj_name.group(2), + test_re_obj_name.group(3)) else: print "Unknown object name found in GCC map file: %s" % line return '[misc]' @@ -183,14 +183,14 @@ class _GccParser(_Parser): object_name, object_size = self.parse_section(line) self.module_add(object_name, object_size, current_section) - common_prefix = os.path.dirname(os.path.commonprefix([ + common_prefix = dirname(commonprefix([ o for o in self.modules.keys() if (o.endswith(".o") and not o.startswith("[lib]"))])) new_modules = {} for name, stats in self.modules.items(): if name.startswith("[lib]"): new_modules[name] = stats elif name.endswith(".o"): - new_modules[os.path.relpath(name, common_prefix)] = stats + new_modules[relpath(name, common_prefix)] = stats else: new_modules[name] = stats return new_modules @@ -213,9 +213,7 @@ class _ArmccParser(_Parser): else: is_obj = re.match(self.RE_OBJECT, line) if is_obj: - object_name = os.path.join(os.path.basename(is_obj.group(1)), - is_obj.group(3)) - return os.path.join('[lib]', object_name) + return join('[lib]', basename(is_obj.group(1)), is_obj.group(3)) else: print "Malformed input found when parsing ARMCC map: %s" % line return '[misc]' @@ -276,14 +274,14 @@ class _ArmccParser(_Parser): for line in infile: self.module_add(*self.parse_section(line)) - common_prefix = os.path.dirname(os.path.commonprefix([ + common_prefix = dirname(commonprefix([ o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))])) new_modules = {} for name, stats in self.modules.items(): if name == "anon$$obj.o" or name.startswith("[lib]"): new_modules[name] = stats elif name.endswith(".o"): - new_modules[os.path.relpath(name, common_prefix)] = stats + new_modules[relpath(name, common_prefix)] = stats else: new_modules[name] = stats return new_modules @@ -405,10 +403,10 @@ class _IarParser(_Parser): for arg in line.split(" "): arg = arg.rstrip(" \n") if (not arg.startswith("-")) and arg.endswith(".o"): - self.cmd_modules[os.path.basename(arg)] = arg + self.cmd_modules[basename(arg)] = arg - common_prefix = os.path.dirname(os.path.commonprefix(self.cmd_modules.values())) - self.cmd_modules = {s: os.path.relpath(f, common_prefix) + common_prefix = dirname(commonprefix(self.cmd_modules.values())) + self.cmd_modules = {s: relpath(f, common_prefix) for s, f in self.cmd_modules.items()} def parse_mapfile(self, file_desc): @@ -440,7 +438,7 @@ class _IarParser(_Parser): object_name = self.check_new_object_lib(line) if object_name and current_library: - temp = os.path.join('[lib]', current_library, object_name) + temp = join('[lib]', current_library, object_name) self.module_replace(object_name, temp) return self.modules @@ -497,10 +495,10 @@ class MemapParser(object): else: self.short_modules = dict() for module_name, v in self.modules.items(): - split_name = module_name.split(os.sep) + split_name = module_name.split(sep) if split_name[0] == '': split_name = split_name[1:] - new_name = os.path.join(*split_name[:depth]) + new_name = join(*split_name[:depth]) self.short_modules.setdefault(new_name, {}) for section_idx, value in v.items(): self.short_modules[new_name].setdefault(section_idx, 0) @@ -526,7 +524,7 @@ class MemapParser(object): if file_output: file_desc = open(file_output, 'wb') else: - file_desc = sys.stdout + file_desc = stdout except IOError as error: print "I/O error({0}): {1}".format(error.errno, error.strerror) return False @@ -536,7 +534,7 @@ class MemapParser(object): 'table': self.generate_table}[export_format] output = to_call(file_desc) - if file_desc is not sys.stdout: + if file_desc is not stdout: file_desc.close() return output @@ -678,7 +676,7 @@ def main(): version = '0.4.0' # Parser handling - parser = argparse.ArgumentParser( + parser = ArgumentParser( description="Memory Map File Analyser for ARM mbed\nversion %s" % version) @@ -709,9 +707,9 @@ def main(): parser.add_argument('-v', '--version', action='version', version=version) # Parse/run command - if len(sys.argv) <= 1: + if len(argv) <= 1: parser.print_help() - sys.exit(1) + exit(1) args = parser.parse_args() @@ -721,7 +719,7 @@ def main(): # Parse and decode a map file if args.file and args.toolchain: if memap.parse(args.file, args.toolchain) is False: - sys.exit(0) + exit(0) if args.depth is None: depth = 2 # default depth level @@ -739,7 +737,7 @@ def main(): if args.export == 'table' and returned_string: print returned_string - sys.exit(0) + exit(0) if __name__ == "__main__": main() From be42b0d05df05654bbc6294e2186ec9e6f4ac76e Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 14:34:10 -0600 Subject: [PATCH 096/118] Test memap IAR for multiple arguments per line --- tools/test/memap/iar.map | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tools/test/memap/iar.map b/tools/test/memap/iar.map index 0fc3aae55d..ba3112a12f 100644 --- a/tools/test/memap/iar.map +++ b/tools/test/memap/iar.map @@ -10,12 +10,9 @@ # Command line = # -f # /common/path/.link_files.txt -# (-o -# --map=/common/path/project.map -# /common/path/project.elf -# /common/path/main.o -# /common/path/startup/startup.o -# /common/path/irqs/irqs.o +# (-o /common/path/project.elf +# --map=/common/path/project.map /common/path/main.o +# /common/path/startup/startup.o /common/path/irqs/irqs.o # /common/path/data/data.o # ############################################################################### From 3bc1928106c5d38067d9060328523420f84e1c8c Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 14:35:17 -0600 Subject: [PATCH 097/118] Test gcc memap parser with compiler provided .o's --- tools/test/memap/gcc.map | 1 + tools/test/memap/parse_test.py | 17 +++++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/tools/test/memap/gcc.map b/tools/test/memap/gcc.map index 58ff289e97..01e16cb868 100644 --- a/tools/test/memap/gcc.map +++ b/tools/test/memap/gcc.map @@ -8,6 +8,7 @@ Linker script and memory map 0x000000000001b200 0xc0 /common/path/startup/startup.o 0x000000000001b200 startup() 0x0000000000024020 0x8 /usr/lib/gcc/arm-none-eabi/7.1.0/../../../../arm-none-eabi/lib/armv6-m/libd16M_tlf.a(__main.o) + 0x0000000000024020 0x8 /usr/lib/gcc/arm-none-eabi/7.1.0/../../../../arm-none-eabi/lib/armv6-m/foo.o .data 0x0000000020002ef8 0xac8 load address 0x000000000002ca38 0x0000000020002ef8 __data_start__ = . diff --git a/tools/test/memap/parse_test.py b/tools/test/memap/parse_test.py index 6047749029..210a6fa9e2 100644 --- a/tools/test/memap/parse_test.py +++ b/tools/test/memap/parse_test.py @@ -24,7 +24,7 @@ def test_parse_armcc(): memap.parse(join(dirname(__file__), "arm.map"), "UARM") assert memap.modules == PARSED_ARM_DATA -PARSED_IAR_GCC_DATA = { +PARSED_IAR_DATA = { "startup/startup.o": {".text": 0xc0}, "[lib]/d16M_tlf.a/__main.o": {".text": 8}, "irqs/irqs.o": {".text": 0x98}, @@ -35,14 +35,23 @@ PARSED_IAR_GCC_DATA = { def test_parse_iar(): memap = MemapParser() memap.parse(join(dirname(__file__), "iar.map"), "IAR") - assert memap.modules == PARSED_IAR_GCC_DATA + assert memap.modules == PARSED_IAR_DATA + +PARSED_GCC_DATA = { + "startup/startup.o": {".text": 0xc0}, + "[lib]/d16M_tlf.a/__main.o": {".text": 8}, + "[lib]/misc/foo.o": {".text": 8}, + "irqs/irqs.o": {".text": 0x98}, + "data/data.o": {".data": 0x18, ".bss": 0x198}, + "main.o": {".text": 0x36}, +} def test_parse_gcc(): memap = MemapParser() memap.parse(join(dirname(__file__), "gcc.map"), "GCC_ARM") - assert memap.modules == PARSED_IAR_GCC_DATA + assert memap.modules == PARSED_GCC_DATA memap.parse(join(dirname(__file__), "gcc.map"), "GCC_CR") - assert memap.modules == PARSED_IAR_GCC_DATA + assert memap.modules == PARSED_GCC_DATA def test_add_empty_module(): From c8b353742f65826a95a09d539d3ef29eff7690c0 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 2 Jan 2018 14:36:10 -0600 Subject: [PATCH 098/118] Assert that reduce depth works and parameterize over path sep --- tools/test/memap/memap_test.py | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/tools/test/memap/memap_test.py b/tools/test/memap/memap_test.py index a0c84dda51..77259a721b 100644 --- a/tools/test/memap/memap_test.py +++ b/tools/test/memap/memap_test.py @@ -20,6 +20,7 @@ import json import pytest +import tools.memap from tools.memap import MemapParser from copy import deepcopy @@ -137,7 +138,7 @@ def memap_parser(): return memap_parser -def generate_test_helper(memap_parser, format, depth, file_output=None): +def generate_test_helper(memap_parser, format, depth, sep, file_output=None): """ Helper that tests that the member variables "modules" is unchanged after calling "generate_output" @@ -147,17 +148,21 @@ def generate_test_helper(memap_parser, format, depth, file_output=None): :param format: the file type to output :param file_output: the file to output to """ - old_modules = deepcopy(memap_parser.modules) + tools.memap.sep = sep memap_parser.generate_output(format, depth, file_output=file_output) assert memap_parser.modules == old_modules,\ "generate_output modified the 'modules' property" + for file_name in memap_parser.short_modules: + assert(len(file_name.split(tools.memap.sep)) <= depth) + @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_report_computed(memap_parser, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_report_computed(memap_parser, depth, sep): """ Test that a report and summary are computed @@ -165,7 +170,7 @@ def test_report_computed(memap_parser, depth): :param depth: the detail of the output """ - memap_parser.generate_output('table', depth) + memap_parser.generate_output('table', depth, sep) # Report is created after generating output assert memap_parser.mem_summary @@ -173,17 +178,19 @@ def test_report_computed(memap_parser, depth): @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_generate_output_table(memap_parser, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_generate_output_table(memap_parser, depth, sep): """ Test that an output of type "table" can be generated correctly :param memap_parser: Mocked parser :param depth: the detail of the output """ - generate_test_helper(memap_parser, 'table', depth) + generate_test_helper(memap_parser, 'table', depth, sep) @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_generate_output_json(memap_parser, tmpdir, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_generate_output_json(memap_parser, tmpdir, depth, sep): """ Test that an output of type "json" can be generated correctly :param memap_parser: Mocked parser @@ -191,13 +198,14 @@ def test_generate_output_json(memap_parser, tmpdir, depth): :param depth: the detail of the output """ file_name = str(tmpdir.join('output.json').realpath()) - generate_test_helper(memap_parser, 'json', depth, file_name) + generate_test_helper(memap_parser, 'json', depth, sep, file_name) assert isfile(file_name), "Failed to create json file" json.load(open(file_name)) @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_generate_output_csv_ci(memap_parser, tmpdir, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_generate_output_csv_ci(memap_parser, tmpdir, depth, sep): """ Test ensures that an output of type "csv-ci" can be generated correctly @@ -206,5 +214,5 @@ def test_generate_output_csv_ci(memap_parser, tmpdir, depth): :param depth: the detail of the output """ file_name = str(tmpdir.join('output.csv').realpath()) - generate_test_helper(memap_parser, 'csv-ci', depth, file_name) + generate_test_helper(memap_parser, 'csv-ci', depth, sep, file_name) assert isfile(file_name), "Failed to create csv-ci file" From b7cabdde043602b7511b3274c2d90ee0448bb3c6 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Wed, 3 Jan 2018 18:02:32 -0600 Subject: [PATCH 099/118] littlefs: Fixed positive seek bounds checking This bug was a result of an annoying corner case around intermingling signed and unsigned offsets. The boundary check that prevents seeking a file to a position before the file was preventing valid seeks with positive offsets. This corner case is a bit more complicated than it looks because the offset is signed, while the size of the file is unsigned. Simply casting both to signed or unsigned offsets won't handle large files. --- features/filesystem/littlefs/littlefs/lfs.c | 4 ++-- .../littlefs/littlefs/tests/test_seek.sh | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/features/filesystem/littlefs/littlefs/lfs.c b/features/filesystem/littlefs/littlefs/lfs.c index 04870925cd..cc6713a03d 100644 --- a/features/filesystem/littlefs/littlefs/lfs.c +++ b/features/filesystem/littlefs/littlefs/lfs.c @@ -1635,13 +1635,13 @@ lfs_soff_t lfs_file_seek(lfs_t *lfs, lfs_file_t *file, if (whence == LFS_SEEK_SET) { file->pos = off; } else if (whence == LFS_SEEK_CUR) { - if ((lfs_off_t)-off > file->pos) { + if (off < 0 && (lfs_off_t)-off > file->pos) { return LFS_ERR_INVAL; } file->pos = file->pos + off; } else if (whence == LFS_SEEK_END) { - if ((lfs_off_t)-off > file->size) { + if (off < 0 && (lfs_off_t)-off > file->size) { return LFS_ERR_INVAL; } diff --git a/features/filesystem/littlefs/littlefs/tests/test_seek.sh b/features/filesystem/littlefs/littlefs/tests/test_seek.sh index 6600cb2f5c..3b46892b6e 100755 --- a/features/filesystem/littlefs/littlefs/tests/test_seek.sh +++ b/features/filesystem/littlefs/littlefs/tests/test_seek.sh @@ -133,6 +133,14 @@ tests/test.py << TEST lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], 0, LFS_SEEK_CUR) => size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + + lfs_file_seek(&lfs, &file[0], size, LFS_SEEK_CUR) => 3*size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], pos, LFS_SEEK_SET) => pos; lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; @@ -174,6 +182,14 @@ tests/test.py << TEST lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], 0, LFS_SEEK_CUR) => size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + + lfs_file_seek(&lfs, &file[0], size, LFS_SEEK_CUR) => 3*size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], pos, LFS_SEEK_SET) => pos; lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; From 99e0ddf58135e453932d1711708420bf52699881 Mon Sep 17 00:00:00 2001 From: Prashant Ravi Date: Sat, 6 Jan 2018 00:00:50 +0800 Subject: [PATCH 100/118] Commit to fix the Online compiler issue for ARM mbed-os on REALTEK_RTL8195AM --- .../device/TOOLCHAIN_ARM_STD/rtl8195a.sct | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct index 4cf7eea1a8..d28c714867 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -13,8 +13,8 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { IMAGE2_TABLE 0x10007000 FIXED { - *rtl8195a_init.o(.image2.ram.data*, +FIRST) - *rtl8195a_init.o(.image2.validate.rodata*) + *rtl8195a_init*.o(.image2.ram.data*, +FIRST) + *rtl8195a_init*.o(.image2.validate.rodata*) } ER_IRAM +0 FIXED { @@ -25,14 +25,14 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { } RW_IRAM1 +0 UNINIT FIXED { - *rtl8195a_crypto.o(+RW) + *rtl8195a_crypto*.o(+RW) *libc.a (+RW) *(.sdram.data*) *lib_peripheral_mbed_arm.ar (+RW) } RW_IRAM2 +0 UNINIT FIXED { - *rtl8195a_crypto.o(+ZI, COMMON) + *rtl8195a_crypto*.o(+ZI, COMMON) *libc.a (+ZI, COMMON) *(.bss.thread_stack_main) *lib_peripheral_mbed_arm.ar (+ZI, COMMON) @@ -44,8 +44,8 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { LR_TCM 0x1FFF0000 0x10000 { TCM_OVERLAY 0x1FFF0000 0x10000 { - *lwip_mem.o(.bss*) - *lwip_memp.o(.bss*) + *lwip_mem*.o(.bss*) + *lwip_memp*.o(.bss*) *.o(.tcm.heap*) } } From 7b0f3564879f5e0acf6accc35142b11a2f94196e Mon Sep 17 00:00:00 2001 From: Prashant Ravi Date: Mon, 8 Jan 2018 10:49:46 +0800 Subject: [PATCH 101/118] Fixing changes as requested --- .../TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct index d28c714867..03f74e0f69 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -18,7 +18,7 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { } ER_IRAM +0 FIXED { - *rtl8195a_crypto.o (+RO) + *rtl8195a_crypto*.o (+RO) *(i.mbedtls*) *libc.a (+RO) *rtx_*.o (+RO) From 37fb081062deb0e3723cf8fad378eb888d0e72a7 Mon Sep 17 00:00:00 2001 From: Chris Seymour Date: Mon, 8 Jan 2018 19:50:18 +0000 Subject: [PATCH 102/118] Simple typo fix in the README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index f3335eb845..68b9acaaf0 100644 --- a/README.md +++ b/README.md @@ -28,7 +28,7 @@ The [release notes](https://os.mbed.com/releases) detail the current release. Yo ## Getting started for developers -We have a [developer webiste](https://os.mbed.com) for asking questions, engaging with others, finding information on boards and components, using an online IDE and compiler, reading the documentation and learning about what's new and what's coming next in Mbed OS. +We have a [developer website](https://os.mbed.com) for asking questions, engaging with others, finding information on boards and components, using an online IDE and compiler, reading the documentation and learning about what's new and what's coming next in Mbed OS. ## Getting started for contributors From 632f06d5ac1868ae05816f083d4d22d1d446e670 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 21 Dec 2017 12:08:39 +0100 Subject: [PATCH 103/118] STM32F0 : ST CUBE version update to V1.9.0 - Previous ST Cube version: V1.7.0 - CMSIS part update from 2.3.1 to 2.3.3 - HAL part update from 1.5.0 to 1.7.0 --- .../TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S | 2 - .../TOOLCHAIN_ARM_STD/startup_stm32f051x8.S | 2 - .../TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S | 40 +- .../TARGET_DISCO_F051R8/device/hal_tick.h | 6 +- .../TARGET_DISCO_F051R8/device/stm32f051x8.h | 222 ++-- .../TARGET_DISCO_F051R8/device/stm32f0xx.h | 6 +- .../TARGET_DISCO_F051R8/device/system_clock.c | 1 - .../device/system_stm32f0xx.h | 2 - .../TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S | 6 +- .../TOOLCHAIN_ARM_STD/startup_stm32f030x8.S | 6 +- .../TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S | 40 +- .../TOOLCHAIN_IAR/startup_stm32f030x8.S | 4 - .../TARGET_NUCLEO_F030R8/device/hal_tick.h | 6 +- .../TARGET_NUCLEO_F030R8/device/stm32f030x8.h | 214 ++-- .../TARGET_NUCLEO_F030R8/device/stm32f0xx.h | 6 +- .../device/system_clock.c | 1 - .../device/system_stm32f0xx.h | 2 - .../TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S | 2 - .../TOOLCHAIN_ARM_STD/startup_stm32f031x6.S | 2 - .../TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S | 40 +- .../TOOLCHAIN_IAR/startup_stm32f031x6.S | 4 - .../TARGET_NUCLEO_F031K6/device/hal_tick.h | 6 +- .../TARGET_NUCLEO_F031K6/device/stm32f031x6.h | 202 ++-- .../TARGET_NUCLEO_F031K6/device/stm32f0xx.h | 6 +- .../device/system_clock.c | 1 - .../device/system_stm32f0xx.h | 2 - .../TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S | 2 - .../TOOLCHAIN_ARM_STD/startup_stm32f042x6.S | 2 - .../TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S | 42 +- .../TOOLCHAIN_IAR/startup_stm32f042x6.S | 4 - .../TARGET_NUCLEO_F042K6/device/hal_tick.h | 6 +- .../TARGET_NUCLEO_F042K6/device/stm32f042x6.h | 218 ++-- .../TARGET_NUCLEO_F042K6/device/stm32f0xx.h | 6 +- .../device/system_stm32f0xx.h | 2 - .../TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S | 2 - .../TOOLCHAIN_ARM_STD/startup_stm32f070xb.S | 2 - .../TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S | 42 +- .../TOOLCHAIN_IAR/startup_stm32f070xb.S | 4 - .../TARGET_NUCLEO_F070RB/device/hal_tick.h | 6 +- .../TARGET_NUCLEO_F070RB/device/stm32f070xb.h | 220 ++-- .../TARGET_NUCLEO_F070RB/device/stm32f0xx.h | 6 +- .../device/system_clock.c | 1 - .../device/system_stm32f0xx.h | 2 - .../TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S | 2 - .../TOOLCHAIN_ARM_STD/startup_stm32f072xb.S | 2 - .../TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S | 46 +- .../TOOLCHAIN_IAR/startup_stm32f072xb.S | 4 - .../TARGET_NUCLEO_F072RB/device/hal_tick.h | 6 +- .../TARGET_NUCLEO_F072RB/device/stm32f072xb.h | 236 ++-- .../TARGET_NUCLEO_F072RB/device/stm32f0xx.h | 6 +- .../device/system_stm32f0xx.h | 2 - ...up_stm32f091rc.S => startup_stm32f091xc.S} | 2 - ...up_stm32f091rc.S => startup_stm32f091xc.S} | 2 - .../TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S | 40 +- .../TOOLCHAIN_IAR/startup_stm32f091xc.S | 4 - .../TARGET_NUCLEO_F091RC/device/hal_tick.h | 6 +- .../TARGET_NUCLEO_F091RC/device/stm32f091xc.h | 242 ++-- .../TARGET_NUCLEO_F091RC/device/stm32f0xx.h | 6 +- .../device/system_stm32f0xx.h | 2 - .../TARGET_STM32F0/analogin_device.c | 4 +- .../device/Release_Notes_stm32f0xx_hal.html | 916 -------------- .../TARGET_STM32F0/device/stm32_hal_legacy.h | 125 +- .../TARGET_STM32F0/device/stm32f0xx_hal.c | 50 +- .../TARGET_STM32F0/device/stm32f0xx_hal.h | 11 +- .../TARGET_STM32F0/device/stm32f0xx_hal_adc.c | 72 +- .../TARGET_STM32F0/device/stm32f0xx_hal_adc.h | 74 +- .../device/stm32f0xx_hal_adc_ex.c | 21 +- .../device/stm32f0xx_hal_adc_ex.h | 6 +- .../TARGET_STM32F0/device/stm32f0xx_hal_can.c | 960 +++++++++------ .../TARGET_STM32F0/device/stm32f0xx_hal_can.h | 258 ++-- .../TARGET_STM32F0/device/stm32f0xx_hal_cec.c | 72 +- .../TARGET_STM32F0/device/stm32f0xx_hal_cec.h | 48 +- .../device/stm32f0xx_hal_comp.c | 32 +- .../device/stm32f0xx_hal_comp.h | 16 +- .../device/stm32f0xx_hal_conf.h | 44 +- .../device/stm32f0xx_hal_cortex.c | 16 +- .../device/stm32f0xx_hal_cortex.h | 2 - .../TARGET_STM32F0/device/stm32f0xx_hal_crc.c | 140 +-- .../TARGET_STM32F0/device/stm32f0xx_hal_crc.h | 16 +- .../device/stm32f0xx_hal_crc_ex.c | 18 +- .../device/stm32f0xx_hal_crc_ex.h | 10 +- .../TARGET_STM32F0/device/stm32f0xx_hal_dac.c | 64 +- .../TARGET_STM32F0/device/stm32f0xx_hal_dac.h | 38 +- .../device/stm32f0xx_hal_dac_ex.c | 94 +- .../device/stm32f0xx_hal_dac_ex.h | 2 - .../TARGET_STM32F0/device/stm32f0xx_hal_def.h | 8 +- .../TARGET_STM32F0/device/stm32f0xx_hal_dma.c | 68 +- .../TARGET_STM32F0/device/stm32f0xx_hal_dma.h | 24 +- .../device/stm32f0xx_hal_dma_ex.h | 50 +- .../device/stm32f0xx_hal_flash.c | 6 +- .../device/stm32f0xx_hal_flash.h | 2 - .../device/stm32f0xx_hal_flash_ex.c | 13 +- .../device/stm32f0xx_hal_flash_ex.h | 2 - .../device/stm32f0xx_hal_gpio.c | 32 +- .../device/stm32f0xx_hal_gpio.h | 12 +- .../device/stm32f0xx_hal_gpio_ex.h | 4 +- .../TARGET_STM32F0/device/stm32f0xx_hal_i2c.c | 755 ++++++------ .../TARGET_STM32F0/device/stm32f0xx_hal_i2c.h | 56 +- .../device/stm32f0xx_hal_i2c_ex.c | 20 +- .../device/stm32f0xx_hal_i2c_ex.h | 14 +- .../TARGET_STM32F0/device/stm32f0xx_hal_i2s.c | 94 +- .../TARGET_STM32F0/device/stm32f0xx_hal_i2s.h | 22 +- .../device/stm32f0xx_hal_irda.c | 16 +- .../device/stm32f0xx_hal_irda.h | 98 +- .../device/stm32f0xx_hal_irda_ex.h | 10 +- .../device/stm32f0xx_hal_iwdg.c | 2 - .../device/stm32f0xx_hal_iwdg.h | 2 - .../TARGET_STM32F0/device/stm32f0xx_hal_pcd.c | 145 ++- .../TARGET_STM32F0/device/stm32f0xx_hal_pcd.h | 144 ++- .../device/stm32f0xx_hal_pcd_ex.c | 10 +- .../device/stm32f0xx_hal_pcd_ex.h | 6 +- .../TARGET_STM32F0/device/stm32f0xx_hal_pwr.c | 14 +- .../TARGET_STM32F0/device/stm32f0xx_hal_pwr.h | 6 +- .../device/stm32f0xx_hal_pwr_ex.c | 4 +- .../device/stm32f0xx_hal_pwr_ex.h | 2 - .../TARGET_STM32F0/device/stm32f0xx_hal_rcc.c | 6 +- .../TARGET_STM32F0/device/stm32f0xx_hal_rcc.h | 116 +- .../device/stm32f0xx_hal_rcc_ex.c | 47 +- .../device/stm32f0xx_hal_rcc_ex.h | 70 +- .../TARGET_STM32F0/device/stm32f0xx_hal_rtc.c | 94 +- .../TARGET_STM32F0/device/stm32f0xx_hal_rtc.h | 194 ++- .../device/stm32f0xx_hal_rtc_ex.c | 124 +- .../device/stm32f0xx_hal_rtc_ex.h | 210 ++-- .../device/stm32f0xx_hal_smartcard.c | 14 +- .../device/stm32f0xx_hal_smartcard.h | 118 +- .../device/stm32f0xx_hal_smartcard_ex.c | 14 +- .../device/stm32f0xx_hal_smartcard_ex.h | 6 +- .../device/stm32f0xx_hal_smbus.c | 1055 ++++++++++------- .../device/stm32f0xx_hal_smbus.h | 172 +-- .../TARGET_STM32F0/device/stm32f0xx_hal_spi.c | 392 ++++-- .../TARGET_STM32F0/device/stm32f0xx_hal_spi.h | 121 +- .../device/stm32f0xx_hal_spi_ex.c | 10 +- .../device/stm32f0xx_hal_spi_ex.h | 70 +- .../TARGET_STM32F0/device/stm32f0xx_hal_tim.c | 500 ++++---- .../TARGET_STM32F0/device/stm32f0xx_hal_tim.h | 164 +-- .../device/stm32f0xx_hal_tim_ex.c | 148 ++- .../device/stm32f0xx_hal_tim_ex.h | 2 - .../TARGET_STM32F0/device/stm32f0xx_hal_tsc.c | 46 +- .../TARGET_STM32F0/device/stm32f0xx_hal_tsc.h | 84 +- .../device/stm32f0xx_hal_uart.c | 90 +- .../device/stm32f0xx_hal_uart.h | 131 +- .../device/stm32f0xx_hal_uart_ex.c | 34 +- .../device/stm32f0xx_hal_uart_ex.h | 24 +- .../device/stm32f0xx_hal_usart.c | 31 +- .../device/stm32f0xx_hal_usart.h | 78 +- .../device/stm32f0xx_hal_usart_ex.h | 14 +- .../device/stm32f0xx_hal_wwdg.c | 2 - .../device/stm32f0xx_hal_wwdg.h | 4 +- .../TARGET_STM32F0/device/stm32f0xx_ll_adc.c | 2 - .../TARGET_STM32F0/device/stm32f0xx_ll_adc.h | 138 +-- .../TARGET_STM32F0/device/stm32f0xx_ll_bus.h | 2 - .../TARGET_STM32F0/device/stm32f0xx_ll_comp.c | 4 +- .../TARGET_STM32F0/device/stm32f0xx_ll_comp.h | 14 +- .../device/stm32f0xx_ll_cortex.h | 6 +- .../TARGET_STM32F0/device/stm32f0xx_ll_crc.c | 2 - .../TARGET_STM32F0/device/stm32f0xx_ll_crc.h | 12 +- .../TARGET_STM32F0/device/stm32f0xx_ll_crs.c | 2 - .../TARGET_STM32F0/device/stm32f0xx_ll_crs.h | 32 +- .../TARGET_STM32F0/device/stm32f0xx_ll_dac.c | 4 +- .../TARGET_STM32F0/device/stm32f0xx_ll_dac.h | 66 +- .../TARGET_STM32F0/device/stm32f0xx_ll_dma.c | 12 +- .../TARGET_STM32F0/device/stm32f0xx_ll_dma.h | 163 ++- .../TARGET_STM32F0/device/stm32f0xx_ll_exti.c | 4 +- .../TARGET_STM32F0/device/stm32f0xx_ll_exti.h | 8 +- .../TARGET_STM32F0/device/stm32f0xx_ll_gpio.c | 12 +- .../TARGET_STM32F0/device/stm32f0xx_ll_gpio.h | 43 +- .../TARGET_STM32F0/device/stm32f0xx_ll_i2c.c | 11 +- .../TARGET_STM32F0/device/stm32f0xx_ll_i2c.h | 80 +- .../TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h | 12 +- .../TARGET_STM32F0/device/stm32f0xx_ll_pwr.c | 2 - .../TARGET_STM32F0/device/stm32f0xx_ll_pwr.h | 126 +- .../TARGET_STM32F0/device/stm32f0xx_ll_rcc.c | 18 +- .../TARGET_STM32F0/device/stm32f0xx_ll_rcc.h | 46 +- .../TARGET_STM32F0/device/stm32f0xx_ll_rtc.c | 18 +- .../TARGET_STM32F0/device/stm32f0xx_ll_rtc.h | 210 ++-- .../TARGET_STM32F0/device/stm32f0xx_ll_spi.c | 2 - .../TARGET_STM32F0/device/stm32f0xx_ll_spi.h | 75 +- .../device/stm32f0xx_ll_system.h | 9 +- .../TARGET_STM32F0/device/stm32f0xx_ll_tim.c | 90 +- .../TARGET_STM32F0/device/stm32f0xx_ll_tim.h | 285 +++-- .../device/stm32f0xx_ll_usart.c | 30 +- .../device/stm32f0xx_ll_usart.h | 88 +- .../device/stm32f0xx_ll_utils.c | 22 +- .../device/stm32f0xx_ll_utils.h | 9 +- .../TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h | 4 +- .../TARGET_STM32F0/device/system_stm32f0xx.c | 2 - targets/TARGET_STM/hal_tick_32b.c | 4 +- targets/TARGET_STM/i2c_api.c | 2 +- 188 files changed, 6410 insertions(+), 6202 deletions(-) rename targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/{startup_stm32f091rc.S => startup_stm32f091xc.S} (99%) rename targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/{startup_stm32f091rc.S => startup_stm32f091xc.S} (99%) delete mode 100644 targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S index 6630f3629b..fedb462f5f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f051x8.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S index 71932f44e9..e8f7595f38 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f051x8.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S index 5ae8717ba3..70959f3f8d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f051x8.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h index 3f0c4e35f6..7e2cf35a02 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h @@ -46,11 +46,11 @@ #define TIM_MST TIM1 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() -#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h index 1be4bcc070..0149d3d741 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f051x8.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2805,56 +2803,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -3524,72 +3574,72 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3775,25 +3825,25 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3986,9 +4036,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -4020,6 +4070,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -6636,6 +6691,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h index b7cf48712f..9836a7e3d9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c index ccb1e96f4d..72fa4b7e7d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c @@ -212,7 +212,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h index 0e1378cd32..f654061771 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S index c82949c838..f83bb9d453 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S @@ -101,7 +101,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD 0 ; Reserved DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 DCD 0 ; Reserved DCD TIM14_IRQHandler ; TIM14 DCD TIM15_IRQHandler ; TIM15 @@ -120,7 +120,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -171,6 +171,7 @@ Default_Handler PROC EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM14_IRQHandler [WEAK] EXPORT TIM15_IRQHandler [WEAK] EXPORT TIM16_IRQHandler [WEAK] @@ -197,6 +198,7 @@ ADC1_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM3_IRQHandler +TIM6_IRQHandler TIM14_IRQHandler TIM15_IRQHandler TIM16_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S index 8d3a08bac1..f616165ec9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S @@ -74,7 +74,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD 0 ; Reserved DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 DCD 0 ; Reserved DCD TIM14_IRQHandler ; TIM14 DCD TIM15_IRQHandler ; TIM15 @@ -93,7 +93,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -144,6 +144,7 @@ Default_Handler PROC EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM14_IRQHandler [WEAK] EXPORT TIM15_IRQHandler [WEAK] EXPORT TIM16_IRQHandler [WEAK] @@ -170,6 +171,7 @@ ADC1_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM3_IRQHandler +TIM6_IRQHandler TIM14_IRQHandler TIM15_IRQHandler TIM16_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S index 4526736274..97a36cb81e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f030x8.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F030x8 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F030x8 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S index 8c13b3d330..f609cd8be2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f030x8.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F030x8 devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h index 3f0c4e35f6..7e2cf35a02 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h @@ -46,11 +46,11 @@ #define TIM_MST TIM1 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() -#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h index 0339d8a0da..c10d677ce3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f030x8.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2301,56 +2299,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -2990,63 +3040,63 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3220,19 +3270,19 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3414,9 +3464,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -3448,6 +3498,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -5322,7 +5377,10 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) - + +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h index 4a5b4d432e..0af10c21f3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c index 0e8886ed76..fe5ebfe73b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c @@ -213,7 +213,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h index 0e1378cd32..f654061771 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S index a6eea51afd..c46d4079c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f031x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S index 757a90de99..ac23206062 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f031x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S index 2d505708c3..6659250a3a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f031x6.s * @author MCD Application Team - * @version V2.2.2 - * @date 26-June-2015 - * @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F031x4/STM32F031x6 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S index c02773e1ac..c7a11a44e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f031x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2015 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h index e8d7455047..0b0e2f6035 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h @@ -45,11 +45,11 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h index f281ed9cb3..c4d15c3faa 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f031x6.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2359,56 +2357,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -3094,51 +3144,51 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3297,16 +3347,16 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3489,9 +3539,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -3523,6 +3573,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -5564,6 +5619,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /*********************** UART Instances : IRDA mode ***************************/ #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h index 3c26751294..ada004259c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c index 2e18b9cc29..6b57adbc6e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c @@ -213,7 +213,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h index 0e1378cd32..f654061771 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S index 25c8f93530..588b14a2b1 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f042x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S index 0144877486..af9dc49cf5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f042x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S index a751fe5784..f4fc3ae1ff 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f042x6.s * @author MCD Application Team - * @version V2.2.2 - * @date 26-June-2015 - * @brief STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F042x4/STM32F042x6 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /** * @brief This is the code that gets called when the processor first @@ -78,8 +80,6 @@ Reset_Handler: LDR R1, [R0] LSRS R1, R1, #24 LDR R2,=0x1F - MOVS R1, #0 - MOVS R2, #1 CMP R1, R2 BNE ApplicationStart @@ -96,21 +96,35 @@ Reset_Handler: ApplicationStart: /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S index 8cde7360b8..7772212e7c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f042x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2015 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h index 0caa0508c0..8fc6dd3afe 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h @@ -45,11 +45,11 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h index ffd0022e42..9530b33c1c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f042x6.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -6496,56 +6494,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -7264,69 +7314,69 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ #define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ +#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ #define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -7506,22 +7556,22 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -7733,9 +7783,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -7767,6 +7817,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -10528,6 +10583,9 @@ typedef struct (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM14)) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h index 6f844a2fad..b579f75dfb 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h index 0e1378cd32..f654061771 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S index 0814fae074..4c5c3ddb3d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f070xb.s ;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 05-December-2014 ;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S index 29a68407e0..2070432140 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f070xb.s ;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 05-December-2014 ;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S index 16ce3d8edb..72094b591a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f070xb.s * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 - * @brief STM32F070xb/STM32F070x8 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F070xb/STM32F070x8 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,7 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata - +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -65,21 +66,6 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - // Load from _sidata -> _sdata through _edata - // _sidata has a vma = lma in flash at the end of .text - // _sdata has a lma in flash but a vma of ram, so here we move it from where - // it was loaded (lma) into where it will be accessed (vma). - // Register Schema: - // r0 = _sdata, r1 = _edata, r2 = _sidata - // r3 = index (goes from 0 -> _sdata - _edata) - // r4 = temp var for *(_sidata + r3) or (_sdata + r3) - // This is all equivalent to this C: - // int index = 0; - // extern uint32_t *_sdata, *_sidata; - // while (_sdata + index < _edata) { - // *_sdata[index] = *_sidata[index]; - // index += 1; - // } ldr r0, =_sdata ldr r1, =_edata ldr r2, =_sidata @@ -92,16 +78,28 @@ CopyDataInit: adds r3, r3, #4 LoopCopyDataInit: - // while (_sdata + r3 < _edata) adds r4, r0, r3 - // if (r4 < r1) branch to CopyDataInit cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit - +/* Call static constructors */ + // bl __libc_init_array /* Call the application's entry point.*/ // bl main bl _start diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S index 7fcd91c9e4..144e3ecb01 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f070xb.s ;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 05-December-2014 ;* Description : STM32F070xB devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h index 3f0c4e35f6..7e2cf35a02 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h @@ -46,11 +46,11 @@ #define TIM_MST TIM1 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() -#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h index 25770e09f5..c5ccb91776 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f070xb.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2396,56 +2394,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -3120,75 +3170,75 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ -#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ -#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ +#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3373,19 +3423,19 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3577,9 +3627,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -3623,6 +3673,11 @@ typedef struct #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -5669,6 +5724,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h index 1e936ed869..f85e5fcaf1 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c index b870c189d7..0cc1885a6f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c @@ -216,7 +216,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h index 0e1378cd32..f654061771 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S index 23b894eaa0..d1a1f2fac6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f072xb.s ;* Author : MCD Application Team -;* Version : V2.0.0 -;* Date : 20-May-2014 ;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S index 33050eb33d..82ea5cdc5b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f072xb.s ;* Author : MCD Application Team -;* Version : V2.0.0 -;* Date : 20-May-2014 ;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S index 525d175a13..8c4a2e4b38 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f072xb.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F072x8/STM32F072xB devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F072x8/STM32F072xB devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,28 +66,42 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ - bl SystemInit + bl SystemInit /* Call static constructors */ - //bl __libc_init_array + //bl __libc_init_array /* Call the application's entry point.*/ - //bl main + //bl main /** * Calling the crt0 'cold-start' entry point. There __libc_init_array is called * and when existing hardware_init_hook() and software_init_hook() before diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S index 82a403f68b..b334e01ded 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f072xb.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h index 42c96c85c6..c6c8f2729f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h @@ -45,11 +45,11 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h index 18c8c9958c..5960276be2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f072xb.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -6934,56 +6932,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -7711,90 +7761,90 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ -#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ -#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ +#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ #define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ +#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ #define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -8001,28 +8051,28 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOERST_Pos (21U) #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */ -#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */ +#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -8248,9 +8298,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -8294,6 +8344,11 @@ typedef struct #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -11132,6 +11187,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h index 58c50fb30f..3aba5160dd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h index 0e1378cd32..f654061771 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S rename to targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S index d338b6ae5d..2df3392971 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f091xc.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S rename to targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S index d6f00552e8..dd63a9aca9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f091xc.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S index cc06a7ff62..ba5808009c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f091xc.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F091xC devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F091xC devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S index 682f12bc3d..4658aa996b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f091xc.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F091xc/STM32F098xc devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h index 42c96c85c6..c6c8f2729f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h @@ -45,11 +45,11 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h index afbadedaac..8b96be761a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f091xc.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -7405,56 +7403,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -8169,99 +8219,99 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_USART6RST_Pos (5U) #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ -#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 clock reset */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ #define RCC_APB2RSTR_USART7RST_Pos (6U) #define RCC_APB2RSTR_USART7RST_Msk (0x1U << RCC_APB2RSTR_USART7RST_Pos) /*!< 0x00000040 */ -#define RCC_APB2RSTR_USART7RST RCC_APB2RSTR_USART7RST_Msk /*!< USART7 clock reset */ +#define RCC_APB2RSTR_USART7RST RCC_APB2RSTR_USART7RST_Msk /*!< USART7 reset */ #define RCC_APB2RSTR_USART8RST_Pos (7U) #define RCC_APB2RSTR_USART8RST_Msk (0x1U << RCC_APB2RSTR_USART8RST_Pos) /*!< 0x00000080 */ -#define RCC_APB2RSTR_USART8RST RCC_APB2RSTR_USART8RST_Msk /*!< USART8 clock reset */ +#define RCC_APB2RSTR_USART8RST RCC_APB2RSTR_USART8RST_Msk /*!< USART8 reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ -#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ -#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ +#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ #define RCC_APB1RSTR_USART5RST_Pos (20U) #define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */ -#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 clock reset */ +#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ +#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ #define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -8480,28 +8530,28 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOERST_Pos (21U) #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */ -#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */ +#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -8729,9 +8779,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -8775,6 +8825,11 @@ typedef struct #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -11673,6 +11728,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h index c222d694ef..e07f12b04f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h index 0e1378cd32..f654061771 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c b/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c index f60f6bc02c..007513ecea 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c @@ -73,7 +73,7 @@ void analogin_init(analogin_t *obj, PinName pin) obj->handle.Init.Resolution = ADC_RESOLUTION_12B; obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; - obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; + obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; obj->handle.Init.LowPowerAutoWait = DISABLE; obj->handle.Init.LowPowerAutoPowerOff = DISABLE; obj->handle.Init.ContinuousConvMode = DISABLE; @@ -81,7 +81,7 @@ void analogin_init(analogin_t *obj, PinName pin) obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; + obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; __HAL_RCC_ADC1_CLK_ENABLE(); diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html b/targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html deleted file mode 100644 index d64f3ec73f..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html +++ /dev/null @@ -1,916 +0,0 @@ - -Release Notes for STM32F0xx HAL Drivers - -
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Release -Notes for STM32F0xx HAL Drivers

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Copyright -2016 STMicroelectronics

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Update History

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V1.5.0 -/ 04-November-2016

Main -Changes

  • Maintenance release to fix known defects and -enhancements implementation

HAL Drivers changes

  • - -Enhance HAL delay and time base implementation:
    • Add -new templates -stm32f0xx_hal_timebase_rtc_alarm_template.c, stm32f0xx_hal_timebase_rtc_wakeup_template.c -and stm32f0xx_hal_timebase_tim_template.c which can be used to override -the native -HAL time base functions (defined as weak) to use either RTC or -Timer as time -base tick source. For more details about the usage of these drivers, -please refer to HAL\HAL_TimeBase examples and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0
    • HAL IWDG driver: Overall driver rework for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: Overall driver rework for better implementation
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs 
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove -HAL CEC receive interrupt process function HAL_CEC_Receive_IT() -and enable the "receive"  mode during the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • HAL TIM driver : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure

  • HAL Generic
    • Update HAL Driver compliancy with:
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type)
      • MISRA -C 2004 rule 14.8 (the statement forming the body of a 'switch', -'while', 'do ... while', or 'for' statement shall be a compound -statement)
  • HAL IWDG
    • New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() -and HAL_IWDG_GetState() APIs
      • API functions are: 
        • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG -counter
        • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
    • Refer to the following example to identify the changes : IWDG_Reset, IWDG_WidowMode
  • HAL WWDG
    • New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() -and HAL_WWDG_GetState() APIs
      • Update HAL_WWDG_Refresh() API to remove counter parameter
      • New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt
      • API -functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), -HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()
    • Refer to the following example to identify the changes: WWDG_Example
  • HAL CEC
    • Overall driver rework with break of compatibility with HAL V1.4.0
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
      • Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC state information related to global Handle management and Tx Operations
      • Update CEC process to manage the new CEC states.
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
  • HAL UART/USART/IRDA/SMARTCARD
    • IRQ Handler global optimization 
    • New abort API: HAL_PPP_Abort(), HAL_PPP_Abort_IT()
    • Add error management in case of DMA transfer through - HAL_DMA_Abort_IT() and DMA XferAbortCallback()
    • Polling management update:
      • The user Timeout value must be estimated for the overall process -duration
  • HAL SPI
    • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency
      • Polling mode:
        • Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data
      •  Interrupt mode:
        • Minimize access on SPI registers
      • All modes:
        • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
        • Update timeout management to check on global processes
        • Update error code management in all processes
    • Fix regression in polling mode:
      • Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()
    • Fix regression in interrupt mode:
      • Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()
      • Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()
    • Prevent data -packing mode in reception for STM32F030x6, STM32F030x8, -STM32F031x6, STM32F038xx, STM32F051x8 and STM32F058xx
  • HAL DMA
    • Global - driver code optimization to reduce memory footprint 
    • Add - new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to - register/unregister the different callbacks identified by the enum - typedef HAL_DMA_CallbackIDTypeDef
    • Add - new Error Code HAL_DMA_ERROR_NOT_SUPPORTED
    • Remove - DMA HAL_DMA_STATE_READY_HALF & HAL_DMA_STATE_ERROR states in - HAL_DMA_StateTypeDef
  • HAL RTC
    • Interrupt flag cleared before enabling the interrupt in HAL_RTCEx_SetWakeUpTimer_IT()
  • HAL I2C
    • Disable I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init()
    • Move I2C_NO_OPTION_FRAME in private section
    • Use CMSIS bit for compilation switch instead of product switch
    • Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)
    • Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer
    • On slave, reset LISTEN_TX state in case of direction change
    • Remove GCC warnings
  • HAL TIM
    • API update : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure in order to set ARPE -bit from TIMx_CR1 register
    • New -API : add 2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and  -__HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit -from TIMx_CCMR1, TIMx_CCMR2 and TIMx_CCMR3 registers
    • Update TIM_SET_CAPTUREPOLARITY and TIM_RESET_CAPTUREPOLARITY definition to take into account CC4NP bit
    • Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()
  • HAL SMBUS
    • Update SMBUS_Master_ISR() and SMBUS_Slave_ISR() to ensure storage of last receive data
  • HAL - PCD 
    • Update - HAL_PCD_ActivateRemoteWakeup() and HAL_PCD_DeActivateRemoteWakeup() APIs - to add condition if LPM activated.
-

LL Drivers changes

  • LL GPIO
    • Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F0xx serie)
  • LL_TIM
    • Remove TIM_SMCR_OCCS compilation switch (useless for STM32F0xx serie)
  • LL_CRS
    • Update CRS_POSITION_XXX  definitions to use CMSIS definition instead of hardcoded values

V1.4.0 -/ 27-May-2016

  • First official release supporting the Low Level drivers for the STM32F0xx family:
    • Low Layer drivers APIs provide register level programming:
      they require deep knowledge of peripherals described in STM32F0xx Reference Manual.
    • Low Layer drivers are available for ADC, COMP, Cortex, CRC, CRS, DAC, DMA, EXTI, -GPIO, I2C, IWDG, PWR,
      RCC, RTC, SPI, TIM, USART and WWDG peripherals       and additional Low Level Bus, System and Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f0xx_ll_ppp.h files for PPP peripherals,
      there is no configuration file and each stm32f0xx_ll_ppp.h file must be included in user code.
  • Maintenance release to fix known defects and enhancements implementation.
  • HAL generic
    • Updated HAL Driver compliancy with MISRA C 2004 rules:
      • MISRA C 2004 rule 5.2 (tmpreg" variable shall not be used inside MACRO)
      • MISRA C 2004 rule 10.3 (illegal explicit conversion from type "unsigned int" to "uint16_t *).
      • MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).
      • MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).
      • MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators).
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).
      • MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself).
      • MISRA C 2004 rule 14.9 ('if {expression}' / 'else' construct shall be followed by a compound statement).
      • MISRA C 2004 rule 15.3 (all switch statements shall contain a final default clause).
      • MISRA C 2004 rule 16.3 (identifiers shall be given for all of the parameters in a function prototype declaration).
      • MISRA C 2004 rule 16.4 (identifiers used in the declaration and definition shall be identical).
      • MISRA C 2004 rule 19.10 (in function-like macro definition, each instance of a parameter shall be enclosed in parenthesis).
  • HAL
    • Changed uwTick to global to allow overwrite of HAL_IncTick().
  • HAL COMP
    • Added delay in COMP startup time required to reach propagation delay specification.
  • HAL CRC
    • Updated devices supporting Programmable Polynomial features: defines and functions prototypes are available only for
      STM32F071xB, STM32F072xB, STM32F078xx, STM32F091xC, STM32F098x devices.
    • Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).
  • HAL DMA
    • Added __HAL_DMA_GET_COUNTER() macro returning the number of remaining data units in the current DMA Channel transfer.
    • Provided -new function HAL_DMA_Abort_IT() to abort current DMA transfer -under interrupt mode without polling for DMA enable bit.
  • HAL GPIO
    • Updated IS_GPIO_PIN() macro to cover full u32 bits.
  • HAL I2C
    • Used macro definition for I2C instances supporting Wakeup from Stop mode.
    • Updated polling flags management within I2C slave DMA drivers.
    • Added support of repeated start feature in case of multimaster mode (allow master to keep I2C communication with slave).
    • Updated WaitOnFlag management (timeout measurement should be always cumulative).
    • Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).
    • Reworked DMA end process and I2C error management during DMA transfer.
  • HAL PWR
    • Aligned EWUPx pins and PWR functions with CMSIS definitions.
  • HAL IRDA
    • Modified IRDA_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Modified EIE bit setting in Tx and Rx transfers (Interrupt mode).
    • Updated IRDA_SetConfig() function following UART Baudrate calculation update.
    • Reviewed IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ.
    • Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.
  • HAL RCC
    • Performed optimizations for HAL_RCC_ClockConfig(), HAL_RCCEx_PeriphCLKConfig functions.
    • Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).
    • Updated HAL_RCC_OscConfig() function to enable PWR only if necessary for LSE configuration.
    • Corrected CRS interrupt sources.
    • Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.
    • Added missing HAL IRQHandler and callbacks API for CRS management.
    • Added missing RCC_CFGR_PLLNODIV definition for STM32F030x4/6 devices.
    • Removed HSI48State from structure RCC_OscInitTypeDef when device does not support HSI48.
    • Removed RCC_HSI48_OFF.
    • Removed flag RCC_FLAG_RMV which is write only.
    • Modified AHBPrescTable and APBPrescTable in HAL.
    • Renamed RCC_CRS_SYNCWARM to RCC_CRS_SYNCWARN.
    • Renamed RCC_CRS_TRIMOV to RCC_CRS_TRIMOVF.
  • HAL SPI
    • Updated HAL_SPI_TransmitReceive() function in slave mode to receive correctly the CRC when NSS pulse activated.
    • Added missing __IO in SPI_HandleTypeDef definition.
    • Updated IS_SPI_CRC_POLYNOMIAL macro definition as polynomial value should be odd only.
    • Updated -SPI_2linesTxISR_8BIT() and SPI_2linesTxISR_16BIT() functions: added -return so that SPI_2linesTxISR_8BITCRC() or SPI_2linesTxISR_16BITCRC() -function is called from HAL_SPI_TransmitReceive_IT() when CRC is -activated.
  • HAL TIM
    • Used IS_TIM_HALL_INTERFACE_INSTANCE macro instead of IS_TIM_XOR_INSTANCE macro in
      HAL_TIMEx_HallSensor_xxx() functions.
    • Updated HAL_TIM_ConfigOCrefClear() function to allow TIM_CLEARINPUTSOURCE_OCREFCLR as new ClearInputSource.
  • HAL UART-USART
    • Updated UART Baudrate calculation (UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros).
    • Updated USART_SetConfig() function following UART Baudrate calculation update.
    • Aligned UART-USART Stop Bits with others STM32 series.
    • Renamed IS_UART_WAKEUP_INSTANCE to IS_UART_WAKEUP_FROMSTOP_INSTANCE.
    • Modified UART_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Reviewed UART state machine to avoid cases where UART state is overwritten by UART IRQ.
    • Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.
  • HAL USB
    • Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.
    • Added missing USB_CNTR_SOFM when setting wInterrupt_Mask global variable used in HAL_PCD_Init.
  • HAL SMARTCARD
    • Aligned SMARTCARD Stop Bits with others STM32 series.
    • Modified SMARTCARD_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Updated SMARTCARD_SetConfig() function following UART Baudrate calculation update.
    • Reviewed SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ.

V1.3.1 -/ 29-January-2016

Main -Changes

  • Maintenance release to fix known defects and -enhancements implementation
  • HAL Generic
    • Updated HAL Driver compliancy with:
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).
      • MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).
    • Updated HAL weak empty callbacks to prevent unused argument compilation warnings.
    • Updated stm32f3xx_hal_msp.c files:
      • Removed reference to MicroXplorer.
    • Updated stm32f3xx_hal_conf.h files:
      • Set HSE_STARTUP_TIMEOUT value to 100ms instead of 5000ms
  • HAL ADC
    • Corrected ADC_CHANNEL_VREFINT enabling in the CCR register.
    • Corrected assert param of nb of discontinuous conversions when discontinuous mode is enabled.
    • Removed Flag EOS in HAL_ADC_GetValue().
  • HAL CAN
    • Corrected missing __HAL_UNLOCK when all Mailboxes are busy.
    • Added ERRI bit clear besides to clearing LEC bits in CAN_ESR register, in case of Error interrupt.
  • HAL CORTEX
    • Removed __HAL_CORTEX_SYSTICKCLK_CONFIG macro, replaced by HAL_SYSTICK_CLKSourceConfig() function.
  • HAL CRC
    • Updated CRC HAL_CRC_Calculate() and HAL_CRC_Accumulate() comments, handling input data pointers that are not * uint32_t.
  • HAL FLASH
    • Added FLASH API HAL_FLASHEx_OBGetUserData() to get the value saved in User data option byte.
    • Aligned Return value of HAL_FLASH_EndOfOperationCallback function (0xFFFFFFF) when process is finished.
  • HAL GPIO
    • Updated GPIO Output Speed literals naming to ensure HAL full compatibility.
    • Added GPIOD support for STM32070x6 devices.
    • Modified ADC poll for event to return timeout instead of error.
  • HAL I2C
    • Corrected wrong management of AF after NACK.
    • Aligned I2C driver with new state machine definition.
    • Corrected interrupt disabling in I2C_SlaveReceive_ISR() function.
    • Modified HAL_I2C_Master_Transmit to handle sending data of size 0.
    • Renamed I2C_CR1_DFN to I2C_CR1_DNF.
  • HAL PCD
    • Updated call to Double Buffering Counter Function.
  • HAL PWR
    • Added do { } while(0) in __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() multi statement macro.
  • HAL RCC
    • Performed optimizations for HAL_RCC_ClockConfig() function.
    • Corrected invertion in LSE drive capability Bit definition.
    • Performed optimizations for internal oscillators and PLL startup time.
    • Added GPIOD support for STM32070x6 devices.
    • Removed GPIOE support for STM32F030xC devices.
    • Add RCC_USBCLKSOURCE_NONE when HSI48 is not present.
    • Corrected definition for flag RCC_FLAG_V18PWRRST.
    • Added missing macro __HAL_RCC_LSEDRIVE_CONFIG.
    • Aligned naming of macros related to CRS_CFGR register.
    • Corrected __HAL_RCC_CRS_CLEAR_IT()/__HAL_RCC_CRS_CLEAR_FLAG() macros.
    • Removed Bit PLLNODIV for STM32F030x6 devices.
    • Review implementation to automatically enable backup domain.
    • Added RCC_IT_HSI48RDY definition.
    • Renamed __HAL_RCC_MCO_CONFIG() to __HAL_RCC_MCO1_CONFIG().
  • HAL RTC
    • Aligned different HAL_RTC_XXIRQHandler() implementations.
    • Check the behavior of flag WUTWF and corrected update of wakeup counter registers.
    • Added subsecond fration formula in HAL_RTC_GetTime() function.
    • Updated Bits mask literals used in macros definition.
  • HAL TIM
    • Corrected __HAL_TIM_SET_PRESCALER timer prescaler definition.
    • Protected SMCR register of possible overwrite in HAL_TIM_ConfigOCrefClear().
    • Corrected assert checks in HAL_TIM_ConfigClockSource().
  • HAL TSC
    • Updated IO default state management.
  • HAL UART-USART
    • Corrected behavior of HAL_UART_IRQ_Handler() (removed enabling/disabling of ERR IT source).
    • Corrected UART_FLAG_SBKF definition.
    • Corrected values used for max allowed baudrates constant definitions.
    • Removed -USART_CR2_LINEN/USART_CR3_IREN/USART_CR3_SCEN/USART_CR1_UESM bits -definitions for STM32F030x6, STM32F030x8, STM32F070xB, STM32F070x6, -STM32F030xC.
  • HAL WWDG
    • Aligned WWDG registers Bits naming between all families.

V1.3.0 -/ 26-June-2015

Main -Changes

  • Maintenance release to fix known defects and -enhancements implementation
  • Complete HAL API alignment (macro/function renaming)
  • HAL Generic
    • Update HAL drivers to be MISRA/C++ compliant.
    • Initialized handle lock in HAL_PPP_Init().
    • Add SYSCFG define macros to manage FM+ on GPIOs.
    • Use uint32_t instead of uint8_t/uint_16.
  • HAL ADC
    • Update ADC state machine. Missing state in function "HAL_ADCEx_Calibration_Start().
    • Align ADC_SOFTWARE_START literal on STM32L0xx.
    • HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.
    • HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.
    • ADC_ConversionStop(): correct wrong timeout value.
    • HAL_ADC_AnalogWDGConfig(): Add missing assert param.
    • Remove channel for monitoring VBAT power supply pin on F0 Value line devices.
    • Move -sampling time setting into ADC init stucture (keep setting into ADC -channel init stucture with comments of obsolete setting).
    • Move -__HAL_UNLOCK() before peripheral activation because if an interruption -occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be -executed while HAL still locked.
    • ADC_DMAConvCplt(): Add call to ADC error callback in case of error.
    • Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).
    • Simplify __HAL_ADC_GET_IT_SOURCE().
    • Add use of POSITION_VAL.
    • Add optimization of ADC stabilization delays.
  • HAL CAN 
    • Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().
    • Unlock the CAN process when communication error occurred.
    • Replace “uint32_t Data[8]” by “uint8_t Data[8]” in structures  CanTxMsgTypeDef and CanRxMsgTypeDef.
  • HAL CEC 
    • Add new API HAL_CEC_GetReceivedFrameSize() to get size of received frame
  • HAL CORTEX 
    • Add new macro IS_NVIC_DEVICE_IRQ() to -check on negative values of IRQn parameter
  • HAL CRC 
    • Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().
    • Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).
  • HAL DAC 
    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and -DAC_FLAG_DMAUDR2.
  • HAL DMA
    • Correct __HAL_DMA_GET_IT_SOURCE brief comments.
  • HAL FLASH
    • FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • Add missing macro __HAL_FLASH_GET_LATENCY.
    • Disable WRP not compliant with other family.
    • Add FLASH_BANK1_END defines.
    • Remove WRP defines for few defines under devices swicthes.
    • Add switch to handle option bits BOOT_SEL & nBOOT1 not present on STM32F030xC & STM32F070x6.
  • HAL GPIO 
    • stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.
  • HAL I2C
    • HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.
  • HAL I2S
    • HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.
  • HAL IRDA
    • HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL PWR
    • Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.
    • Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.
  • HAL RCC
    • Implement workaround to cover RCC limitation regarding Peripheral enable delay.
    • HAL_RCC_OscConfig(): correct test on LSEState.
    • Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.
    • Add defines for RCC_System_Clock_Source_Status.
    • Follow specific procedure to enable HSE.
    • Add macros to get the enable or disable status of peripheral clock.
    • HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.
    • Add interface HAL_RCCEx_GetPeriphCLKFreq.
  • HAL RTC
    • Add missing RTC_FLAG_INIT in flag list.
    • HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).
    • Remove RTC_FLAG_INIT as currently unused.
  • HAL SMARTCARD
    • Add missing IDLE flag management.
    • Align SMARTCARD_Last_Bit defines.
  • HAL SPI 
    • Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().
      In -that case only RX callback are used and the call of TX callback can -close the communication before the end of the RX processing.
    • SPI_2linesRxISR_8BIT(): -correct issue on RX 2lines with DataSize8bit, even buffer size and CRC -8bit (SPI_RXFIFO_THRESHOLD is not set).
    • Fit bit update add BSY flag check for all the process.
    • Add -__IO (volatile) to the "State" member of the SPI_HandleTypeDef -struct. to missing reset of the Dma Tx callback inside the -function -HAL_SPI_TransmitReceive_DMA().
  • HAL TIM
    • Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.
  • HAL UART
    • Add macro to control CTS and RTS from the customer applications.
    • UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.
    • Change DMA TX management to remove WaitOnFlag in ISR.
    • Add DMA circular mode support for the communication peripherals.
    • Add UART NVIC configuration in the HAL_UART_MspInit().
    • Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.
    • Modify UART DMA implementation issue (missed clear the TC bit in the SR).
    • Add a OVR flag clear prior resuming DMA RX transfer.
    • HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).
    • HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.
    • HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL USART
    • HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().
    • Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.
    • HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).
    • HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.
    • HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).
    • HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.

V1.2.1 -/ 09-January-2015

  • HAL 
    • stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 & channel2 for STM32F070xB only
  • HAL GPIO
    • stm32f0xx_hal_gpio_ex.h: add I2C1 as possible GPIO alternate function 3 for STM32F070xB
  • HAL RCC
    • stm32f0xx_hal_rcc_ex.h: add missing USART2_CLK_ENABLE/DISABLE() macros for STM32F070x6
  • HAL RTC -
    • stm32f0xx_hal_rtc_ex.h/.c: -Enable RTC periodic Wakeup timer feature on STM32F070xB -& STM32F030xC -
    • stm32f0xx_hal_rtc_ex.c: -remove HAL_RTCEx_Tamper3EventCallback() -API for STM32F070xB -& STM32F030xC, since -there is no TAMPER3 on those products.
    -
  • HAL UART -
    • stm32f0xx_hal_uart_ex.c/.h: -add HAL_RS485Ex_Init() API for STM32F0xx Value -Line devices

V1.2.0 -/ 05-December-2014

Main -Changes

-
  • HAL generic 
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • HandleTypeDef.ErrorCode must be typed uint32_t
    • Update HAL drivers to ensure compliancy w/ C++
    • Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h
    • Case mismatch between #include typo and effective file name generating compiler errors under Linux
    • Correct various issues for documentation generation (group name, doxygen tags, etc..)
    • Missing support of I2C_PAx_FMP of F04xx devices

  • HAL ADC 

    • Improve HAL ADC comments
    • Correct issue observed with ADC start simultaneous commands
    • Remove macro __HAL_ADC_OFR_CHANNEL() since OFRx register is not available on F0 devices.
  • HAL CAN 
    • ErrorCode field is now declared as __IO uint32 instead of enum HAL_CAN_ErrorTypeDef to fix C++ compilation issue

  • HAL CEC 

    • change ErrorCode field declaration from uint32_t  to __IO uint32_t

    • correct CEC state: Ready to Receive state lost upon Transmission end

  • HAL COMP 
    • State field is now declared as uint32_t instead of enum HAL_COMP_StateTypeDef to fix C++ compilation issue
    • change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t to fix C++ compilation issue

  • HAL CRC 

    • Wrong @ref in CRCLength field description for documentation generation 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.

  • HAL DAC 

    • HAL_DAC_Stop_DMA() code clean up

    • Use of internal macro MODIFY_REG() to update CR register

  • HAL DMA 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • DMA channel remap register renamed for compatibility with other STM32 devices.
    • Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description
  • HAL FLASH 
    • Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected
    • ErrorCode field is now declared as uint32 instead of enum FLASH_ErrorTypeDef to fix C++ compilation issue
    • change HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t to fix C++ compilation issue
    • Clean the error context to FLASH_ERROR_NONE before starting new Flash operation
    • Put all the clear flags in the FLASH_SetSerrorCode()
    • Stop the programming procedure in case of error detected in HAL_FLASH_Program()
    • Check error before doing new procedure in HAL_FLASH_IRQhandler()

  • HAL GPIO 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • correct Typo in 'How to use this driver' section & update comments
    • Add assert on GPIO PIN in HAL_GPIO_DeInit()
    • Add assert on GPIO AF instance to protect HAL_GPIO_Init() from impossible AF configuration
    • Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()
    • Reset Interrupt mode registers only in HAL_GPIO_DeInit()
  • HAL I2C
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • ErrorCode field is now declared as uint32 instead of enum HAL_I2C_ErrorTypeDef to fix C++ compilation issue

  • HAL I2S 

    • ErrorCode field is now declared as uint32 instead of enum HAL_I2S_ErrorTypeDef to fix C++ compilation issue.
    • Change HAL_I2S_GetError() type declaration from HAL_I2S_ErrorTypeDef to uint32_t to fix C++ compilation issue.
    • Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to fix Unused variable" warning w/ TrueSTUDIO.
    • Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c
    • Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)

  • HAL IRDA 

    • ErrorCode field is now declared as uint32 instead of enum HAL_IRDA_ErrorTypeDef to fix C++ compilation issue
    • Missing doxygen tags for IRDA_HandleTypeDef fields description

  • HAL PWR 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register:
  • HAL_PWR_DisableSleepOnExit()
  • HAL_PWR_EnableSleepOnExit()
  • HAL_PWR_EnableSEVOnPend()
  • HAL_PWR_DisableSEVOnPend()
    • Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode()

  • HAL RCC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay
    • Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to stm32f0xx_hal_rcc_ex.h since this feature is not supported on all F0 devices
    • Change HAL_RCCEx_CRSWaitSynchronization() type declaration from RCC_CRSStatusTypeDef to uint32_t to fix C++ compilation issue

  • HAL RTC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Enhance @note describing the use of HAL RTC APIs 
  • HAL SMARTCARD
    • ErrorCode field is now declared as uint32 instead of enum HAL_SMARTCARD_ErrorTypeDef to fix C++ compilation issue
  • HAL SMBUS
    • ErrorCode & PreviousState fields are now declared as uint32 instead of enum HAL_SMBUS_ErrorTypeDef & HAL_SMBUS_StateTypeDef to fix C++ compilation issue
    • Change HAL_SMBUS_GetState() type declaration from HAL_SMBUS_StateTypeDef to uint32_t to fix C++ compilation issue

  • HAL SPI 

    • ErrorCode field is now declared as uint32 instead of enum HAL_SPI_ErrorTypeDef to fix C++ compilation issue
    • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" warning w/ TrueSTUDIO.
    • Add DMA circular mode support on SPI HAL driver.
    • Internal -fucntion renaming: HAL_SPI_DMATransmitCplt(), -HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() & -HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError().
    • Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype
    • uint32_t driver alignment for compatibility with other STM32 devices
    • Add new API HAL_SPI_GetError(), which was missing on STM32F0xx family

  • HAL UART/USART 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.
    • ErrorCode field is now declared as uint32 instead of enum HAL_U(S)ART_ErrorTypeDef to fix C++ compilation issue
    • unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h
    • Add missing API HAL_StatusTypeDef HAL_LIN_SendBreak()
    • correct wrong USART_IT_CM value
    • correct issue with Lin mode data length
    • Add new value for Stop bit definition: UART_STOPBITS_1_5

  • HAL USB 

    • Add support of new STM32F0 value line devices STM32F070xB/x6.
    • Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description
    • Correct _HAL_PCD_CLEAR_FLAG() macros definition

  • HAL WWDG 

    • Add new macro to manage WWDG IT & correction:

      • __HAL_WWDG_DISABLE_IT()
      • __HAL_WWDG_GET_IT()
      • __HAL_WWDG_GET_IT_SOURCE()

V1.1.0 -/ 03-October-2014

Main -Changes

-
  • HAL generic 
    • general improvement of Doxygen Tags for CHM UM generation
    • Add support of new devices STM32F091xC, STM32F098xx in STM32F0xx HAL drivers
    • minor corrections for Pdf/Chm UM generation
    • Correction for MISRA 
    • [F098xx] Remove PVD IT line wrapper
    • FLAG&IT assert macros to be removed
    • Bad macro name in stm32F0xx_hal.c/.h files
    • uint32_t Alignement in HAL driver
  • HAL update (for STM32F091xC/STM32F098xx)
    • Add new define for HAL IRDA Enveloppe source Selection
    • Add new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()
    • Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)
    • Add new macro __HAL_GET_PENDING_IT()
    • Add new macro __HAL_SYSCFG_IRDA_ENV_SELECTION()
    • Add new macro __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()

  • HAL COMP 

    • Missing assert param IS_COMP_TRIGGERMODE

  • HAL Cortex 

    • remove Macro not supported by cortex-M0 in stm32f0xx.h

  • HAL DMA 

    • Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)
    • Add new defines for DMAx channels remap bit field definition
    • Add new macros: IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()
    • Add new macro: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index
    • Add new macro: __HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index
    • Add new macro: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index
    • Add new macro: __HAL_DMA_GET_FLAG()
    • Add new macro: __HAL_DMA_CLEAR_FLAG()
    • Add new macro: __HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()
    • Bit definition name error for HAL_DMA1_CH2 remap on STM32F091xC
    • HAL_DMA_PollForTransfer updated

  • HAL GPIO 

    • BSRR regsiter should not be split in BSRRH/BSRRL
    • rework GPIO_GET_SOURCE
    • Add new defines for AF functions selection

  • HAL I2S 

    • Supp ClockSource in Init

  • HAL IRDA 

    • Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro

  • HAL IWDG 

    • Use WRITE_REG instead of SET_BIT

  • HAL PWR 

    • Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx

    • PVD feature need falling/rising Event modes
      • Update defines name PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING to PWR_PVD_MODE_NORMAL/PWR_PVD_MODE_IT_RISING/PWR_PVD_MODE_IT_FALLING/PWR_PVD_MODE_IT_RISING_FALLING
      • Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING
      • Update macro IS_PWR_PVD_MODE()
      • change macro name: __HAL_PWR_PVD_EXTI_ENABLE_IT(), __HAL_PWR_PVD_EXTI_DISABLE_IT(), __HAL_PWR_PVD_EXTI_GENERATE_SWIT(), __HAL_PWR_PVD_EXTI_GET_FLAG(),  __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
      • Add -new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(), -__HAL_PWR_PVD_EXTI_DISABLE_EVENT(), -__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(), -__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()
  • HAL RCC 
    • Defect correction:
      • HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode
      • STM32F091xC/STM32F098xx
        • New structure RCC_PeriphCLKInitTypeDef
        • Add -defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1, -RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC, -RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3
        • Add macro IS_RCC_PERIPHCLK()
        • Add -defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1, -RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE, -CC_USART3CLKSOURCE_HSI
        • Add macro IS_RCC_USART3CLKSOURCE()
        • Add macro __HAL_RCC_GET_USART3_SOURCE()
        • Add macro __HAL_RCC_USART3_CONFIG()
        • add clock enable macros for new UART: __USART5_CLK_ENABLE,  __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE
        • add clock disable macros for new UART: __USART5_CLK_DISABLE,  __USART6_CLK_DISABLE, __USART7_CLK_DISABLE, __USART8_CLK_DISABLE
        • add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET
        • add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_RELEASE_RESET, __USART7_RELEASE_RESET, __USART8_RELEASE_RESET 

  • HAL SMARTCARD 

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR

  • HAL SMBUS  

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function

  • HAL SPI 

    • Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC

    • Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready

  • HAL TIM 

    • Missed/Unused assert param to be added/removed
    • Trigger interrupt should be activated when working with a slave mode
    • Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT
    • Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4
    • missing assert in HAL_TIMEx_ConfigBreakDeadTime
    • Add URS_ENABLE/ URS_DISABLE macros

  • HAL UART/USART 

    • Change UART TX-IT implementation to remove WaitOnFlag in ISR
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4
      • Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4

  • HAL USB 

    • Bad IN/OUT EndPoint parameter array size

  • HAL WWDG 

    • improvements from other families

Defect Correction

 - - - - - - - - - - - - - - - - - - - - - - - - -
-

STM32F0xx_HAL_Driver

- 		-

Defect

- 		-

PWR

- 		-

PVD feature need falling/rising Event modes

-
-

STM32F0xx_HAL_Driver

- 		-

Defect

- 		-

COMP

- 		-

Missing assert param IS_COMP_TRIGGERMODE 

-
-

STM32F0xx_HAL_Driver

- 		-

Defect

- 		-

RCC

- 		-

HAL_RCC_OscConfig: HSERDY has to be checked also in by - pass mode

-
-

V1.0.1 -/ 18-June-2014

Main -Changes

-
  • - - - - - - - -

    HAL generic update

    • Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="
    • Fix -on Timeout management, Timeout value set to 0 passed to API -automatically exits the function after checking the flag without any -wait.
    • Add -new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.

  • HAL CEC update

    • Process no more locked during the transmission in interrupt mode. 

  • HAL COMP update

    • Add NonInvertingInput field in the COMP_InitTypeDef structure.
    • Add new defines COMP_NONINVERTINGINPUT_IO1 and COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED

  • HAL DMA update

    • Fix in HAL_DMA_PollForTransfer() to set error code HAL_DMA_ERROR_TE in case of HAL_ERROR status
  • - - - - - - - -

    HAL I2C update

    • Add -management of NACK event in Master transmitter mode and Slave -transmitter/receiver modes (only in polling mode), in that case the -current transfer is stopped.

  • HAL I2S update

    • I2S clock source change: new define I2S_CLOCK_SYSCLK, remove I2S_CLOCK_PLL
    • Improvement done in I2S transfer/receive processes

  • HAL IRDA update

    • Add new enum typedef IRDA_ClockSourceTypeDef
    • Add new macro __HAL_IRDA_GETCLOCKSOURCE
    • Change in HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • -

    HAL PCD update

    -
    • -

      Add new macro __HAL_USB_EXTI_GENERATE_SWIT

      -

  • HAL PWR update

    • Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function

  • HAL RCC update

    • Add USB peripheral and clocking macros for STM32F078xx device.
    • Fix HSI Calibration issue when selected as SYSCLK
  • - - - - - - - -

    HAL SMARTCARD update

    • Change in HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.
    • Process no more locked during the transmission in interrupt mode.

  • HAL SMBUS update

    • Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack

  • HAL TIM update

    • Fix macro __HAL_TIM_PRESCALER

  • HAL TSC update

    • Fix define TSC_ACQ_MODE_SYNCHRO
  • - - - - - - - -

    HAL UART update

    • Change in HAL_LIN_Init() parameter BreakDetectLength to uint32_t
    • Change in HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.

  • HAL USART update

    • Change USART_InitTypeDef fields to uint32_t type
    • Rename __USART_ENABLE and __USART_DISABLE macros to respectively __HAL_USART_ENABLE and __HAL_USART_DISABLE
    • Change in HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
    • Change in HAL_USART_TransmitReceive_DMA() to manage DMA half transfer mode

V1.0.0 -/ 20-May-2014

-

Main -Changes

-
  • First official -release of STM32F0xx HAL drivers for STM32F030x4/x6, STM32F030x8, STM32F031x4/x6,  STM32F051x4/x6/x8,  STM32F071x8/xB,  STM32F042x4/x6, -STM32F072x8/xB,  STM32F038xx, - STM32F048xx, STM32F058xx and STM32F078xx -devices.

License

-
Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- -
-
-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h index 647f238bbf..5c80466c63 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 + * @version V1.8.1 + * @date 14-April-2017 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -138,7 +138,9 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -265,7 +267,6 @@ #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 @@ -457,6 +458,78 @@ * @} */ +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE + + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + + #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX + #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 + #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 + #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + + #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT + #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING + #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING + #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + + +#endif /* STM32H7 */ + + +/** + * @} + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -670,7 +743,6 @@ #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE @@ -678,9 +750,6 @@ #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT @@ -1312,7 +1381,6 @@ #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL @@ -1785,20 +1853,20 @@ #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE @@ -1815,7 +1883,7 @@ #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE @@ -2410,7 +2478,6 @@ #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE @@ -2443,8 +2510,6 @@ #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE @@ -2466,8 +2531,6 @@ #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET @@ -2692,7 +2755,10 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32WB) +#else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL @@ -2788,7 +2854,6 @@ #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c index 2060122aca..bb588b4aa7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -70,10 +68,10 @@ * @{ */ /** - * @brief STM32F0xx HAL Driver version number V1.5.0 + * @brief STM32F0xx HAL Driver version number V1.7.0 */ #define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F0xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ #define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ @@ -232,7 +230,7 @@ __weak void HAL_MspDeInit(void) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __Weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) @@ -307,14 +305,21 @@ __weak uint32_t HAL_GetTick(void) * is incremented. * @note ThiS function is declared as __weak to be overwritten in case of other * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. + * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(__IO uint32_t Delay) { - uint32_t tickstart = 0U; - tickstart = HAL_GetTick(); - while((HAL_GetTick() - tickstart) < Delay) + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a period to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait++; + } + + while((HAL_GetTick() - tickstart) < wait) { } } @@ -379,6 +384,33 @@ uint32_t HAL_GetDEVID(void) return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @brief Enable the Debug Module during STOP mode * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h index 7f02a7db9a..e9747eeadb 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -378,7 +376,7 @@ #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) /** @defgroup HAL_Pin_remap HAL Pin remap * @brief Pin remapping enable/disable macros - * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping + * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping * @{ */ #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ @@ -393,7 +391,7 @@ #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ /** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. * That you can find above these macros. */ #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ @@ -482,7 +480,7 @@ /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register * @note This feature is applicable on STM32F09x - * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL + * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL * @{ */ #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ @@ -532,6 +530,9 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void); diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c index 445e48e966..a94fe6d801 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_adc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -355,7 +353,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma); * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) @@ -581,7 +579,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) * bypassed without error reporting: it can be the intended behaviour in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) @@ -697,7 +695,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /** * @brief Initializes the ADC MSP. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) @@ -712,7 +710,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /** * @brief DeInitializes the ADC MSP. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) @@ -754,7 +752,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) @@ -819,7 +817,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /** * @brief Stop ADC conversion of regular group, disable ADC peripheral. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) @@ -872,8 +870,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -988,12 +986,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /** * @brief Poll for conversion event. - * @param hadc: ADC handle - * @param EventType: the ADC event type. + * @param hadc ADC handle + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watchdog event * @arg ADC_OVR_EVENT: ADC Overrun event - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) @@ -1069,7 +1067,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy * parameter "EOCSelection" * - overrun (if available) * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) @@ -1150,7 +1148,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /** * @brief Stop ADC conversion of regular group, disable interruption of * end-of-conversion, disable ADC peripheral. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) @@ -1201,9 +1199,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) * - DMA half transfer * - overrun * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param hadc ADC handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1292,7 +1290,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable * ADC peripheral. * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) @@ -1374,7 +1372,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) @@ -1391,7 +1389,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /** * @brief Handles ADC interrupt request. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) @@ -1507,7 +1505,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /** * @brief Conversion complete callback in non blocking mode - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) @@ -1522,7 +1520,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Conversion DMA half-transfer callback in non blocking mode - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) @@ -1537,7 +1535,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog callback in non blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) @@ -1553,7 +1551,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief ADC error callback in non blocking mode * (ADC conversion with interruption or transfer by DMA) - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) @@ -1606,8 +1604,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". - * @param hadc: ADC handle - * @param sConfig: Structure of ADC channel for regular group. + * @param hadc ADC handle + * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) @@ -1739,8 +1737,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". - * @param hadc: ADC handle - * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration + * @param hadc ADC handle + * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) @@ -1862,7 +1860,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * For example: * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL state */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) @@ -1876,7 +1874,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) /** * @brief Return the ADC error code - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC Error Code */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) @@ -1906,7 +1904,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * flag ADC_FLAG_RDY is not usable. * Therefore, this function must be called under condition of * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) @@ -1971,7 +1969,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) * @brief Disable the selected ADC. * @note Prerequisite condition to use this function: ADC conversions must be * stopped. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) @@ -2028,7 +2026,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) * @brief Stop ADC conversion. * @note Prerequisite condition to use this function: ADC conversions must be * stopped to disable the ADC. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) @@ -2079,7 +2077,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) @@ -2140,7 +2138,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2154,7 +2152,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h index abb05a25df..9addcb7696 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_adc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention @@ -332,7 +330,6 @@ typedef struct */ #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) -#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ /** * @} */ @@ -463,7 +460,7 @@ typedef struct /** * @brief Enable the ADC peripheral - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) \ @@ -471,7 +468,7 @@ typedef struct /** * @brief Disable the ADC peripheral - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) \ @@ -482,8 +479,8 @@ typedef struct /** * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source @@ -498,8 +495,8 @@ typedef struct /** * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source @@ -513,8 +510,8 @@ typedef struct (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC interrupt source to check + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source @@ -529,8 +526,8 @@ typedef struct /** * @brief Get the selected ADC's flag status. - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag @@ -545,8 +542,8 @@ typedef struct /** * @brief Clear the ADC's pending flags - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag @@ -561,7 +558,7 @@ typedef struct (((__HANDLE__)->Instance->ISR) = (__FLAG__)) /** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ @@ -583,7 +580,7 @@ typedef struct /** * @brief Verification of hardware constraints before ADC can be enabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) */ #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ @@ -594,7 +591,7 @@ typedef struct /** * @brief Verification of hardware constraints before ADC can be disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) */ #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ @@ -604,7 +601,7 @@ typedef struct /** * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ @@ -619,7 +616,7 @@ typedef struct /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ @@ -627,7 +624,7 @@ typedef struct /** * @brief Check if no conversion on going on regular group - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ @@ -637,7 +634,7 @@ typedef struct /** * @brief Returns resolution bits in CFGR1 register: RES[1:0]. * Returned value is among parameters to @ref ADC_Resolution. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) \ @@ -646,7 +643,7 @@ typedef struct /** * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. * Returned value is among parameters to @ref ADC_Resolution. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_SAMPLINGTIME(__HANDLE__) \ @@ -663,7 +660,7 @@ typedef struct /** * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ @@ -672,7 +669,7 @@ typedef struct /** * @brief Configure the channel number into channel selection register - * @param _CHANNEL_: ADC Channel + * @param _CHANNEL_ ADC Channel * @retval None */ /* This function converts ADC channels from numbers (see defgroup ADC_channels) @@ -702,7 +699,7 @@ typedef struct /** * @brief Set the ADC's sample time - * @param _SAMPLETIME_: Sample time parameter. + * @param _SAMPLETIME_ Sample time parameter. * @retval None */ /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ @@ -715,7 +712,7 @@ typedef struct /** * @brief Set the Analog Watchdog 1 channel. - * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1. + * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. * @retval None */ #define ADC_CFGR_AWDCH(_CHANNEL_) \ @@ -723,7 +720,7 @@ typedef struct /** * @brief Enable ADC discontinuous conversion mode for regular group - * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. + * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. * @retval None */ #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ @@ -731,7 +728,7 @@ typedef struct /** * @brief Enable the ADC auto off mode. - * @param _AUTOOFF_: Auto off bit enable or disable. + * @param _AUTOOFF_ Auto off bit enable or disable. * @retval None */ #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ @@ -739,7 +736,7 @@ typedef struct /** * @brief Enable the ADC auto delay mode. - * @param _AUTOWAIT_: Auto delay bit enable or disable. + * @param _AUTOWAIT_ Auto delay bit enable or disable. * @retval None */ #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ @@ -747,7 +744,7 @@ typedef struct /** * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. + * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ @@ -755,7 +752,7 @@ typedef struct /** * @brief Enable ADC overrun mode. - * @param _OVERRUN_MODE_: Overrun mode. + * @param _OVERRUN_MODE_ Overrun mode. * @retval Overun bit setting to be programmed into CFGR register */ /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ @@ -768,7 +765,7 @@ typedef struct /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. - * @param _SCAN_MODE_: Scan conversion mode. + * @param _SCAN_MODE_ Scan conversion mode. * @retval None */ /* Note: Scan mode set using this macro (instead of parameter direct set) */ @@ -782,7 +779,7 @@ typedef struct /** * @brief Enable the ADC DMA continuous request. - * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @param _DMACONTREQ_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ @@ -790,7 +787,7 @@ typedef struct /** * @brief Configure the analog watchdog high threshold into register TR. - * @param _Threshold_: Threshold value + * @param _Threshold_ Threshold value * @retval None */ #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ @@ -804,8 +801,8 @@ typedef struct * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) - * @param __HANDLE__: ADC handle - * @param _Threshold_: Value to be shifted + * @param __HANDLE__ ADC handle + * @param _Threshold_ Value to be shifted * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ @@ -833,8 +830,7 @@ typedef struct ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \ - ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) ) + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c index d3061241fb..a3408d9d4f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c @@ -2,15 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions * ++ Calibration (ADC automatic self-calibration) * Other functions (generic functions) are available in file - * "stm32l1xx_hal_adc.c". + * "stm32f0xx_hal_adc.c". * @verbatim [..] @@ -109,13 +107,14 @@ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @note Calibration factor can be read after calibration, using function * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tickstart=0U; + uint32_t tickstart = 0U; + uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -131,6 +130,15 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); + /* Disable ADC DMA transfer request during calibration */ + /* Note: Specificity of this STM32 serie: Calibration factor is */ + /* available in data register and also transfered by DMA. */ + /* To not insert ADC calibration factor among ADC conversion data */ + /* in array variable, DMA transfer must be disabled during */ + /* calibration. */ + backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + /* Start ADC calibration */ hadc->Instance->CR |= ADC_CR_ADCAL; @@ -153,6 +161,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) } } + /* Restore ADC DMA transfer request after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer); + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h index c7dec724ce..04d2438359 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of ADC HAL Extension module. ****************************************************************************** * @attention @@ -153,7 +151,7 @@ * VrefInt/TempSensor/Vbat * Note: On STM32F0, availability of internal channel Vbat depends on * devices lines. - * @param __CHANNEL__: ADC channel + * @param __CHANNEL__ ADC channel * @retval None */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) @@ -175,7 +173,7 @@ * VrefInt/TempSensor/Vbat. * Note: On STM32F0, availability of internal channel Vbat depends on * devices lines. - * @param __CHANNEL__: ADC channel + * @param __CHANNEL__ ADC channel * @retval Bit of register ADC_CCR */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c index 715f4fbb64..17dede7d5e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_can.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -28,9 +26,13 @@ (#) Initialise and configure the CAN using HAL_CAN_Init() function. (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. - + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. + (#) Receive a CAN frame using HAL_CAN_Receive() function. + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + *** Polling mode IO operation *** ================================= [..] @@ -157,10 +159,10 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); */ /** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) @@ -200,18 +202,18 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) hcan->State = HAL_CAN_STATE_BUSY; /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -221,95 +223,97 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) } /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) { /* Set the time triggered communication mode */ if (hcan->Init.TTCM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_TTCM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } /* Set the automatic bus-off management */ if (hcan->Init.ABOM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_ABOM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } /* Set the automatic wake-up mode */ if (hcan->Init.AWUM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_AWUM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } /* Set the no automatic retransmission */ if (hcan->Init.NART == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_NART; + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); } /* Set the receive FIFO locked mode */ if (hcan->Init.RFLM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_RFLM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } /* Set the transmit FIFO priority */ if (hcan->Init.TXFP == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_TXFP; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1U); + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SJW | + hcan->Init.BS1 | + hcan->Init.BS2 | + (hcan->Init.Prescaler - 1U) )); /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State= HAL_CAN_STATE_TIMEOUT; + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + + return HAL_TIMEOUT; } } /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) { status = CAN_INITSTATUS_SUCCESS; } @@ -339,15 +343,15 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /** * @brief Configures the CAN reception filter according to the specified * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that + * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { - uint32_t filternbrbitpos = 0; + uint32_t filternbrbitpos = 0U; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); @@ -360,81 +364,80 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy filternbrbitpos = (1U) << sFilterConfig->FilterNumber; /* Initialisation mode for the filter */ - hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT; - /* Select the start slave bank */ - hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - hcan->Instance->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); - - /* Filter Deactivation */ - hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos; + MODIFY_REG(hcan->Instance->FMR , + CAN_FMR_CAN2SB , + CAN_FMR_FINIT | + (uint32_t)(sFilterConfig->BankNumber << 8U) ); /* Filter Deactivation */ + CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos); /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { /* 16-bit scale for the filter */ - hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos); /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { /* 32-bit scale for the filter */ - hcan->Instance->FS1R |= filternbrbitpos; + SET_BIT(hcan->Instance->FS1R, filternbrbitpos); + /* 32-bit identifier or First 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { /*Id/Mask mode for the filter*/ - hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos); } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ - hcan->Instance->FM1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->FM1R, filternbrbitpos); } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) { /* FIFO 0 assignation for the filter */ - hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos); } - - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + else { /* FIFO 1 assignation for the filter */ - hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->FFA1R, filternbrbitpos); } /* Filter activation */ if (sFilterConfig->FilterActivation == ENABLE) { - hcan->Instance->FA1R |= filternbrbitpos; + SET_BIT(hcan->Instance->FA1R, filternbrbitpos); } /* Leave the initialisation mode for the filter */ - hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT); + CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT)); /* Return function status */ return HAL_OK; @@ -442,7 +445,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /** * @brief Deinitializes the CANx peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ @@ -475,7 +478,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) /** * @brief Initializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -491,7 +494,7 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) /** * @brief DeInitializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -528,9 +531,9 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) /** * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) @@ -542,37 +545,43 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { + { /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Select one empty transmit mailbox */ + if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) + { + transmitmailbox = CAN_TXMAILBOX_1; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0U; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1U; - } - else - { - transmitmailbox = 2U; + transmitmailbox = CAN_TXMAILBOX_2; } /* Set up the Id */ @@ -580,15 +589,15 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) if (hcan->pTxMsg->IDE == CAN_ID_STD) { assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ + hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); } /* Set up the DLC */ @@ -597,16 +606,17 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4])); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); + /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); /* Get tick */ tickstart = HAL_GetTick(); @@ -617,26 +627,37 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; + + /* Cancel transmission */ + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Process unlocked */ __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - + /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -647,7 +668,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - + /* Return function status */ return HAL_ERROR; } @@ -655,7 +676,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /** * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ @@ -667,7 +688,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) @@ -676,92 +697,94 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) __HAL_LOCK(hcan); /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) { - transmitmailbox = 0U; + transmitmailbox = CAN_TXMAILBOX_0; } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) { - transmitmailbox = 1U; + transmitmailbox = CAN_TXMAILBOX_1; } else { - transmitmailbox = 2U; + transmitmailbox = CAN_TXMAILBOX_2; } /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if(hcan->pTxMsg->IDE == CAN_ID_STD) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ + hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); } - + /* Set up the DLC */ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - + /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hcan); - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); - - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); - - /* Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME); - + /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); } else { /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + hcan->State = HAL_CAN_STATE_ERROR; /* Return function status */ return HAL_ERROR; @@ -772,34 +795,85 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /** * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. - * @param Timeout: Timeout duration. + * @param FIFONumber FIFO number. + * @param Timeout Timeout duration. * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - + /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; } - else + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; } - + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + /* Get tick */ tickstart = HAL_GetTick(); @@ -809,41 +883,54 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; } } } - - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) { - hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; } else { - hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; } - - hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; + pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; + pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; + pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; + pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; + pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; + pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; + pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; /* Release the FIFO */ if(FIFONumber == CAN_FIFO0) @@ -856,16 +943,43 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Release FIFO1 */ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } /* Process unlocked */ @@ -877,69 +991,108 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /** * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. + * @param FIFONumber FIFO number. * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) - { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); - - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + /* Process locked */ + __HAL_LOCK(hcan); + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { /* Process unlocked */ __HAL_UNLOCK(hcan); - if(FIFONumber == CAN_FIFO0) + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) { - /* Enable FIFO 0 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; } - else + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) { - /* Enable FIFO 1 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; } - + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } else { - return HAL_BUSY; + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } /* Return function status */ @@ -948,7 +1101,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber /** * @brief Enters the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status. */ @@ -963,10 +1116,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) hcan->State = HAL_CAN_STATE_BUSY; /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + MODIFY_REG(hcan->Instance->MCR, + CAN_MCR_INRQ , + CAN_MCR_SLEEP ); /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || + HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) { /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -979,7 +1135,8 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || + HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) { if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -1003,7 +1160,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) /** * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral * is in the normal mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status. */ @@ -1018,23 +1175,26 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) hcan->State = HAL_CAN_STATE_BUSY; /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Get tick */ tickstart = HAL_GetTick(); /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) { if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; } } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + + if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) { /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -1055,27 +1215,67 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) /** * @brief Handles CAN interrupt request - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + + /* Check Overrun flag for FIFO1 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + /* Check End of transmission flag */ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) { + /* Check Transmit request completion status */ if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + /* Check Transmit success */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) || + (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) || + (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); } } /* Check End of reception flag for FIFO0 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U)) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO0); @@ -1083,12 +1283,15 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Check End of reception flag for FIFO1 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U)) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO1); } + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + /* Check Error Warning Flag */ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && @@ -1106,7 +1309,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { /* Set CAN error code to EPV error */ hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* No need for clear of Error Passive Flag as read-only */ + /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-Off Flag */ @@ -1155,16 +1358,40 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) } /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); } /* Call the Error call Back in case of Errors */ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) { /* Clear ERRI Flag */ - hcan->Instance->MSR |= CAN_MSR_ERRI; + SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); + /* Set the CAN state ready to be able to start again the process */ hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME ); + /* Call Error callback function */ HAL_CAN_ErrorCallback(hcan); } @@ -1172,7 +1399,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /** * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1188,7 +1415,7 @@ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) /** * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1204,7 +1431,7 @@ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1240,7 +1467,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) /** * @brief return the CAN state - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ @@ -1252,7 +1479,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) /** * @brief Return the CAN error code - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ @@ -1274,9 +1501,10 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) * * @{ */ + /** * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ @@ -1287,33 +1515,36 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) if(hcan->State == HAL_CAN_STATE_BUSY_TX) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - + /* Transmission complete callback */ HAL_CAN_TxCpltCallback(hcan); @@ -1322,84 +1553,122 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /** * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number + * @param FIFONumber Specify the FIFO number * @retval HAL status * @retval None */ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) { - hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; } else { - hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; } - - hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; + pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; + pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; + pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; + pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; + pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; + pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; + pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; + /* Release the FIFO */ /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - /* Disable FIFO 0 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - /* Disable FIFO 1 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1)) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } /* Receive complete callback */ @@ -1408,6 +1677,7 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum /* Return function status */ return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h index 456cf5f885..95a0476d34 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_can.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -59,20 +57,24 @@ /* Exported types ------------------------------------------------------------*/ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ - */ + */ /** * @brief HAL State structures definition */ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ }HAL_CAN_StateTypeDef; @@ -140,7 +142,7 @@ typedef struct second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. @@ -180,7 +182,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. + uint8_t Data[8]; /*!< Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ }CanTxMsgTypeDef; @@ -205,7 +207,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be received. + uint8_t Data[8]; /*!< Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. @@ -227,8 +229,10 @@ typedef struct CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ - + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + HAL_LockTypeDef Lock; /*!< CAN locking object */ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ @@ -250,16 +254,19 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ -#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ -#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */ /** * @} */ @@ -273,10 +280,10 @@ typedef struct * @} */ -/** @defgroup CAN_operating_mode CAN operating mode +/** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -285,10 +292,10 @@ typedef struct */ -/** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -296,10 +303,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1 +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -315,15 +322,14 @@ typedef struct #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ - /** * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2 +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -331,72 +337,65 @@ typedef struct #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ - /** * @} */ -/** @defgroup CAN_filter_mode CAN filter mode +/** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ - /** * @} */ -/** @defgroup CAN_filter_scale CAN filter scale +/** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ - /** * @} */ -/** @defgroup CAN_filter_FIFO CAN filter FIFO +/** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ #define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ - /** * @} */ -/** @defgroup CAN_identifier_type CAN identifier type +/** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ #define CAN_ID_STD (0x00000000U) /*!< Standard Id */ #define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ - /** * @} */ -/** @defgroup CAN_remote_transmission_request CAN remote transmission request +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ #define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ - /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number * @{ */ #define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ - /** * @} */ -/** @defgroup CAN_flags CAN flags +/** @defgroup CAN_flags CAN Flags * @{ */ /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() @@ -423,22 +422,25 @@ typedef struct #define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ -#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ + /** * @} */ -/** @defgroup CAN_interrupts CAN interrupts +/** @defgroup CAN_interrupts CAN Interrupts * @{ */ #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ @@ -465,7 +467,7 @@ typedef struct /** * @} */ - + /** @defgroup CAN_Mailboxes CAN Mailboxes * @{ */ @@ -476,7 +478,7 @@ typedef struct /** * @} */ - + /** * @} */ @@ -485,42 +487,42 @@ typedef struct /** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ - + /** @brief Reset CAN handle state - * @param __HANDLE__: CAN handle. + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** * @brief Enable the specified CAN interrupts. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable the specified CAN interrupts. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) /** * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param __HANDLE__ CAN handle. + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @retval The number of pending message. */ #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: * @arg CAN_TSR_RQCP0: Request MailBox0 Flag * @arg CAN_TSR_RQCP1: Request MailBox1 Flag * @arg CAN_TSR_RQCP2: Request MailBox2 Flag @@ -552,9 +554,9 @@ typedef struct ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: * @arg CAN_TSR_RQCP0: Request MailBox0 Flag * @arg CAN_TSR_RQCP1: Request MailBox1 Flag * @arg CAN_TSR_RQCP2: Request MailBox2 Flag @@ -578,16 +580,16 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ +((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the CAN Handle. - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be one of the following values: * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable @@ -597,21 +599,19 @@ typedef struct /** * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: CAN handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @param __HANDLE__ CAN handle. + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. * @retval The new status of transmission (TRUE or FALSE). */ #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) - - -/** + /** * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param __HANDLE__ CAN handle. + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @retval None */ #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ @@ -619,8 +619,8 @@ typedef struct /** * @brief Cancel a transmit request. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @param __HANDLE__ specifies the CAN Handle. + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. * @retval None */ #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ @@ -630,8 +630,8 @@ typedef struct /** * @brief Enable or disables the DBG Freeze for CAN. - * @param __HANDLE__: specifies the CAN Handle. - * @param __NEWSTATE__: new state of the CAN peripheral. + * @param __HANDLE__ specifies the CAN Handle. + * @param __NEWSTATE__ new state of the CAN peripheral. * This parameter can be: ENABLE (CAN reception/transmission is frozen * during debug. Reception FIFOs can still be accessed/controlled normally) * or DISABLE (CAN is working during debug). @@ -641,14 +641,14 @@ typedef struct ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) /** - * @} - */ - + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup CAN_Exported_Functions CAN Exported Functions * @{ */ - + /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @{ @@ -661,14 +661,13 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); /** - * @} - */ - + * @} + */ + /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + * @brief I/O operation functions * @{ */ - /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); @@ -676,31 +675,28 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, u HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); - void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); - void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); /** - * @} - */ - + * @} + */ + /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions * @brief CAN Peripheral State functions * @{ - */ + */ /* Peripheral State and Error functions ***************************************/ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); - /** - * @} - */ - + * @} + */ + /** - * @} - */ + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types @@ -730,27 +726,37 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ + #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) + #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) + #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) + #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) + +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) + #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) + #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) + #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) + +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) #define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) @@ -759,17 +765,30 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) + #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + /** * @} */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ +/* End of private macros -----------------------------------------------------*/ /** * @} @@ -778,10 +797,6 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** * @} */ - -/** - * @} - */ #endif /* STM32F072xB || STM32F042x6 || STM32F048xx || STM32F078xx || STM32F091xC || STM32F098xx */ @@ -793,4 +808,3 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c index 5c22bb0b40..3c93dc5a6b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cec.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -78,6 +76,13 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" +#ifdef HAL_CEC_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) ||\ + defined(STM32F051x8) || defined(STM32F058xx) ||\ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ + defined(STM32F091xC) || defined (STM32F098xx) + /** @addtogroup STM32F0xx_HAL_Driver * @{ */ @@ -86,12 +91,7 @@ * @brief HAL CEC module driver * @{ */ -#ifdef HAL_CEC_MODULE_ENABLED -#if defined(STM32F042x6) || defined(STM32F048xx) ||\ - defined(STM32F051x8) || defined(STM32F058xx) ||\ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ - defined(STM32F091xC) || defined (STM32F098xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CEC_Private_Constants CEC Private Constants @@ -144,7 +144,7 @@ /** * @brief Initializes the CEC mode according to the specified * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) @@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /** * @brief DeInitializes the CEC peripheral - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) @@ -267,8 +267,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) /** * @brief Initializes the Own Address of the CEC device - * @param hcec: CEC handle - * @param CEC_OwnAddress: The CEC own address. + * @param hcec CEC handle + * @param CEC_OwnAddress The CEC own address. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP Init - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) @@ -328,7 +328,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP DeInit - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) @@ -380,11 +380,11 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief Send data in interrupt mode - * @param hcec: CEC handle - * @param InitiatorAddress: Initiator address - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). + * @param hcec CEC handle + * @param InitiatorAddress Initiator address + * @param DestinationAddress destination logical address + * @param pData pointer to input byte data buffer + * @param Size amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status @@ -440,7 +440,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator /** * @brief Get size of the received frame. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval Frame size */ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) @@ -450,8 +450,8 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) /** * @brief Change Rx Buffer. - * @param hcec: CEC handle - * @param Rxbuffer: Rx Buffer + * @param hcec CEC handle + * @param Rxbuffer Rx Buffer * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ @@ -462,7 +462,7 @@ void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) /** * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) @@ -567,7 +567,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Tx Transfer completed callback - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) @@ -581,8 +581,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Rx Transfer completed callback - * @param hcec: CEC handle - * @param RxFrameSize: Size of frame + * @param hcec CEC handle + * @param RxFrameSize Size of frame * @retval None */ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) @@ -597,7 +597,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize /** * @brief CEC error callbacks - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) @@ -628,7 +628,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize */ /** * @brief return the CEC state - * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC module. * @retval HAL state */ @@ -643,7 +643,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) /** * @brief Return the CEC error code - * @param hcec : pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC. * @retval CEC Error Code */ @@ -659,18 +659,18 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ #endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */ /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ /* defined(STM32F091xC) || defined (STM32F098xx) */ #endif /* HAL_CEC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h index 24acad6179..d3b001ef80 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cec.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention @@ -431,7 +429,7 @@ typedef struct */ /** @brief Reset CEC handle gstate & RxState - * @param __HANDLE__: CEC handle. + * @param __HANDLE__ CEC handle. * @retval None */ #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -440,8 +438,8 @@ typedef struct } while(0) /** @brief Checks whether or not the specified CEC interrupt flag is set. - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the flag to check. * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. @@ -460,8 +458,8 @@ typedef struct #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** @brief Clears the interrupt or status flag when raised (write at 1) - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the interrupt/status flag to clear. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the interrupt/status flag to clear. * This parameter can be one of the following values: * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. @@ -481,8 +479,8 @@ typedef struct #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) /** @brief Enables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to enable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to enable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -502,8 +500,8 @@ typedef struct #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** @brief Disables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to disable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to disable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -523,8 +521,8 @@ typedef struct #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) /** @brief Checks whether or not the specified CEC interrupt is enabled. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to check. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -544,52 +542,52 @@ typedef struct #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) /** @brief Enables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) /** @brief Disables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) /** @brief Set Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) /** @brief Set Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. */ #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) /** @brief Get Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) /** @brief Get Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) /** @brief Clear OAR register - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand - * @param __HANDLE__: specifies the CEC Handle. - * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) + * @param __HANDLE__ specifies the CEC Handle. + * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) * @retval none */ #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) @@ -704,21 +702,21 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); * The message size is the payload size: without counting the header, * it varies from 0 byte (ping operation, one header only, no payload) to * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__: CEC message size. + * @param __SIZE__ CEC message size. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) /** @brief Check CEC device Own Address Register (OAR) setting. * OAR address is written in a 15-bit field within CEC_CFGR register. - * @param __ADDRESS__: CEC own address. + * @param __ADDRESS__ CEC own address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) /** @brief Check CEC initiator or destination logical address setting. * Initiator and destination addresses are coded over 4 bits. - * @param __ADDRESS__: CEC initiator or logical address. + * @param __ADDRESS__ CEC initiator or logical address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c index 61760a3563..a2d9c2d1f2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_comp.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief COMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: @@ -188,7 +186,7 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */ /* CSR register reset value */ #define COMP_CSR_RESET_VALUE (0x00000000U) @@ -230,7 +228,7 @@ * parameters in the COMP_InitTypeDef and create the associated handle. * @note If the selected comparator is locked, initialization can't be performed. * To unlock the configuration, perform a system reset. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) @@ -316,7 +314,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) * @brief DeInitializes the COMP peripheral * @note Deinitialization can't be performed if the COMP configuration is locked. * To unlock the configuration, perform a system reset. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) @@ -357,7 +355,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) /** * @brief Initializes the COMP MSP. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) @@ -372,7 +370,7 @@ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) /** * @brief DeInitializes COMP MSP. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) @@ -406,7 +404,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) /** * @brief Start the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) @@ -438,7 +436,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) hcomp->State = HAL_COMP_STATE_BUSY; /* Delay for COMP startup time */ - wait_loop_index = (LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U)); + wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; @@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /** * @brief Stop the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) @@ -495,7 +493,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) /** * @brief Enables the interrupt and starts the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status. */ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) @@ -542,7 +540,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) /** * @brief Disable the interrupt and Stop the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) @@ -559,7 +557,7 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) /** * @brief Comparator IRQ Handler - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) @@ -598,7 +596,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /** * @brief Lock the selected comparator configuration. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) @@ -643,7 +641,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * voltage than the inverting input * - Comparator output is low when the non-inverting input is at a higher * voltage than the inverting input - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH. * */ @@ -670,7 +668,7 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) /** * @brief Comparator callback. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) @@ -705,7 +703,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) /** * @brief Return the COMP state - * @param hcomp : COMP handle + * @param hcomp COMP handle * @retval HAL state */ uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h index 30c9a98190..ae0df5004f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_comp.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention @@ -262,14 +260,14 @@ typedef struct */ /** @brief Reset COMP handle state - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) /** * @brief Enable the specified comparator. - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ @@ -278,7 +276,7 @@ typedef struct /** * @brief Disable the specified comparator. - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ @@ -287,7 +285,7 @@ typedef struct /** * @brief Lock the specified comparator configuration. - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_LOCK(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ @@ -463,8 +461,8 @@ typedef struct #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) /** @brief Check whether the specified COMP flag is set or not. - * @param __HANDLE__: specifies the COMP Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the COMP Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg COMP_FLAG_LOCK: lock flag * @retval The new state of __FLAG__ (TRUE or FALSE). @@ -564,7 +562,7 @@ uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); */ /** * @brief Get the specified EXTI line for a comparator instance. - * @param __INSTANCE__: specifies the COMP instance. + * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h index 3c256a3385..6baa4090c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_conf.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -85,7 +83,7 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** @@ -93,7 +91,7 @@ * Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -102,7 +100,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -110,14 +108,14 @@ * Timeout value */ #if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */ + #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ #endif /* HSI_STARTUP_TIMEOUT */ /** * @brief Internal High Speed oscillator for ADC (HSI14) value. */ #if !defined (HSI14_VALUE) -#define HSI14_VALUE (14000000U) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + #define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz. The real value may vary depending on the variations in voltage and temperature. */ #endif /* HSI14_VALUE */ @@ -126,7 +124,7 @@ * @brief Internal High Speed oscillator for USB (HSI48) value. */ #if !defined (HSI48_VALUE) -#define HSI48_VALUE (48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz. The real value may vary depending on the variations in voltage and temperature. */ #endif /* HSI48_VALUE */ @@ -135,22 +133,22 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE (40000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + #define LSI_VALUE 40000U +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ /** * @brief Time out for LSE start up value in ms. */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ @@ -161,14 +159,15 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ /* Warning: Must be set to higher priority for HAL_Delay() */ /* and HAL_GetTick() usage under interrupt context */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 -#define INSTRUCTION_CACHE_ENABLE 0 -#define DATA_CACHE_ENABLE 0 +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 0U +#define DATA_CACHE_ENABLE 0U +#define USE_SPI_CRC 1U /* ########################## Assert Selection ############################## */ /** @@ -177,15 +176,6 @@ */ /*#define USE_FULL_ASSERT 1*/ -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c index 8d189d100f..fba72d339d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -140,13 +138,13 @@ /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number . + * @param IRQn External interrupt number . * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) - * @param PreemptPriority: The preemption priority for the IRQn channel. + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 3. * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority the subpriority level for the IRQ channel. * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None @@ -205,7 +203,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -236,7 +234,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None @@ -299,7 +297,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h index 284ac75374..ebea4eab57 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c index 79daa5342d..cd94ee26f4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -13,19 +11,19 @@ * @verbatim =============================================================================== - ##### How to use this driver ##### + ##### How to use this driver ##### =============================================================================== [..] - (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); - (#) Initialize CRC calculator + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator (++)specify generating polynomial (IP default or non-default one) (++)specify initialization value (IP default or non-default one) (++)specify input data format (++)specify input or output data inversion mode if any - (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the input data buffer starting with the previously computed CRC as initialization value - (#) Use HAL_CRC_Calculate() function to compute the CRC value of the + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the input data buffer starting with the defined initialization value (default or non-default) to initiate CRC calculation @@ -57,7 +55,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -67,7 +65,7 @@ * @{ */ -/** @defgroup CRC CRC +/** @defgroup CRC CRC * @brief CRC HAL module driver. * @{ */ @@ -87,34 +85,35 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @} */ - -/* Exported functions ---------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + /** @defgroup CRC_Exported_Functions CRC Exported Functions * @{ */ -/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions +/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions. * @verbatim =============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle (+) DeInitialize the CRC peripheral - (+) Initialize the CRC MSP - (+) DeInitialize CRC MSP + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP @endverbatim * @{ */ /** - * @brief Initializes the CRC according to the specified - * parameters in the CRC_InitTypeDef and creates the associated handle. - * @param hcrc: CRC handle + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and initialize the associated handle. + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) @@ -132,6 +131,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } @@ -181,8 +181,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) } /** - * @brief DeInitializes the CRC peripheral. - * @param hcrc: CRC handle + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) @@ -205,6 +205,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + /* Reset IDR register content */ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; @@ -223,7 +226,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /** * @brief Initializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -237,8 +240,8 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) } /** - * @brief DeInitializes the CRC MSP. - * @param hcrc: CRC handle + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -263,12 +266,12 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - using combination of the previous CRC value and the new one. + (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer + using the combination of the previous CRC value and the new one - or + [..] or - (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer independently of the previous CRC value. @endverbatim @@ -278,16 +281,16 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) @@ -319,9 +322,9 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ case CRC_INPUTDATA_FORMAT_HALFWORDS: temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } /* Change CRC peripheral state */ @@ -338,15 +341,15 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the + * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ @@ -385,9 +388,9 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } /* Change CRC peripheral state */ @@ -399,6 +402,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /* Return the CRC computed value */ return temp; } + /** * @} */ @@ -411,20 +415,20 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. + This subsection permits to get in run-time the status of the peripheral. @endverbatim * @{ */ /** - * @brief Returns the CRC state. - * @param hcrc: CRC handle + * @brief Return the CRC handle state. + * @param hcrc CRC handle * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) { + /* Return CRC handle state */ return hcrc->State; } @@ -436,15 +440,16 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) * @} */ -/** @addtogroup CRC_Private_Functions CRC Private Functions +/** @defgroup CRC_Private_Functions CRC Private Functions * @{ */ + /** * @brief Enter 8-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) @@ -456,23 +461,23 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ * handling by the IP */ for(i = 0U; i < (BufferLength/4U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24U) | ((uint32_t)pBuffer[4*i+1]<<16U) | ((uint32_t)pBuffer[4*i+2]<<8U) | (uint32_t)pBuffer[4*i+3]; + hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3]; } /* last bytes specific handling */ - if ((BufferLength%4) != 0U) + if ((BufferLength%4U) != 0U) { - if (BufferLength%4 == 1U) + if (BufferLength%4U == 1U) { - *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; + *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; } - if (BufferLength%4 == 2U) + if (BufferLength%4U == 2U) { - *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; } - if (BufferLength%4 == 3U) + if (BufferLength%4U == 3U) { - *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1]; - *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; + *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; } } @@ -485,38 +490,35 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ /** * @brief Enter 16-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i = 0U; /* input data buffer index */ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ - for(i = 0; i < (BufferLength/2); i++) + for(i = 0U; i < (BufferLength/2U); i++) { - hcrc->Instance->DR = (pBuffer[2*i]<<16U) | pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1]; } - if ((BufferLength%2) != 0U) + if ((BufferLength%2U) != 0U) { - *(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; } /* Return the CRC computed value */ return hcrc->Instance->DR; } -/** - * @} - */ /** * @} */ - + #endif /* HAL_CRC_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h index 29dc65bc59..620ba76a11 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -224,37 +222,37 @@ typedef struct */ /** @brief Reset CRC handle state - * @param __HANDLE__: CRC handle. + * @param __HANDLE__ CRC handle. * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Reset CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Set CRC INIT non-default value - * @param __HANDLE__ : CRC handle - * @param __INIT__ : 32-bit initial value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value * @retval None. */ #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ 8-bit value to be stored in the ID register * @retval None */ #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval 8-bit value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c index 40ff26f60e..02591701f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CRC peripheral: @@ -96,7 +94,7 @@ /** * @brief Extended initialization to set generating polynomial - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc) @@ -126,8 +124,8 @@ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc) /** * @brief Set the Reverse Input data mode. - * @param hcrc: CRC handle - * @param InputReverseMode: Input Data inversion mode + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode * This parameter can be one of the following values: * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value) * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal @@ -154,8 +152,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t /** * @brief Set the Reverse Output data mode. - * @param hcrc: CRC handle - * @param OutputReverseMode: Output Data inversion mode + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode * This parameter can be one of the following values: * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) @@ -182,12 +180,12 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx) /** * @brief Initializes the CRC polynomial if different from default one. - * @param hcrc: CRC handle - * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long) + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long) * This parameter is written in normal representation, e.g. * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength: CRC polynomial length + * @param PolyLength CRC polynomial length * This parameter can be one of the following values: * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7) * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h index 6f37f054e5..06a518786e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention @@ -133,14 +131,14 @@ /** * @brief Set CRC output reversal - * @param __HANDLE__ : CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) /** * @brief Unset CRC output reversal - * @param __HANDLE__ : CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) @@ -148,8 +146,8 @@ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Set CRC non-default polynomial - * @param __HANDLE__ : CRC handle - * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial * @retval None. */ #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c index fe166f4c61..f3b658d4b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -257,7 +255,7 @@ /** * @brief Initialize the DAC peripheral according to the specified parameters * in the DAC_InitStruct and initialize the associated handle. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -295,7 +293,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) /** * @brief Deinitialize the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -331,7 +329,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /** * @brief Initialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -347,7 +345,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /** * @brief DeInitialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -385,9 +383,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -408,9 +406,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -433,15 +431,15 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -466,9 +464,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Cha /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -531,7 +529,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -546,18 +544,18 @@ __weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) @@ -588,7 +586,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /** * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -604,7 +602,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -620,7 +618,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -636,7 +634,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -671,9 +669,9 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -694,10 +692,10 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -739,7 +737,7 @@ __weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_Chan /** * @brief return the DAC handle state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ @@ -752,7 +750,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h index f249ed1206..3d3263cad7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -180,30 +178,30 @@ typedef struct */ /** @brief Reset DAC handle state - * @param __HANDLE__: specifies the DAC handle. + * @param __HANDLE__ specifies the DAC handle. * @retval None */ #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) /** @brief Enable the DAC channel - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_Channel__: specifies the DAC channel + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) /** @brief Disable the DAC channel - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_Channel__: specifies the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) /** @brief Enable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -212,8 +210,8 @@ typedef struct #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @retval None @@ -221,8 +219,8 @@ typedef struct #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified DAC interrupt source is enabled or not - * @param __HANDLE__: DAC handle - * @param __INTERRUPT__: DAC interrupt source to check + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -231,8 +229,8 @@ typedef struct #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to get. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to get. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @retval None @@ -240,8 +238,8 @@ typedef struct #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @retval None @@ -284,19 +282,19 @@ typedef struct #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) /** @brief Set DHR12R1 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__)) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c index b21cb61cad..7ff936db63 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. @@ -116,10 +114,10 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -171,10 +169,10 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @retval HAL status @@ -226,9 +224,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -259,9 +257,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @retval The selected DAC channel data output value. @@ -292,9 +290,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -345,15 +343,15 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -512,14 +510,14 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -602,7 +600,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -660,7 +658,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -709,7 +707,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -724,7 +722,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -737,7 +735,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -768,7 +766,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -783,7 +781,7 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -796,7 +794,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -870,7 +868,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -894,7 +892,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -915,12 +913,12 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -963,12 +961,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation @@ -1035,15 +1033,15 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status @@ -1103,7 +1101,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /** * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1119,7 +1117,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1135,7 +1133,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1151,7 +1149,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h index 9823515d96..57240ee0c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h index be1eabc487..3e2007617b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_def.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -46,7 +44,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx.h" +#if defined(USE_HAL_LEGACY) #include "stm32_hal_legacy.h" +#endif #include /* Exported types ------------------------------------------------------------*/ @@ -87,7 +87,7 @@ typedef enum #define UNUSED(x) ((void)(x)) /** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. + * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro @@ -124,7 +124,7 @@ typedef enum }while (0) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) && !defined ( __CC_ARM ) +#if defined ( __GNUC__ ) #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c index 29191551fa..9bd69a01fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -149,7 +147,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -217,7 +215,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /** * @brief DeInitialize the DMA peripheral - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -290,11 +288,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Start the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -337,11 +335,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -396,8 +394,8 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /** * @brief Abort the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) @@ -422,8 +420,8 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /** * @brief Abort the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) @@ -466,10 +464,10 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /** * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) @@ -569,7 +567,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /** * @brief Handle DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ @@ -657,11 +655,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /** * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callback function which has pointer to + * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -710,9 +708,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /** * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -788,7 +786,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** * @brief Returns the DMA state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ @@ -799,7 +797,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) /** * @brief Return the DMA error code - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ @@ -822,11 +820,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Set the DMA Transfer parameters. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -837,7 +835,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - /* Peripheral to Memory */ + /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ @@ -846,7 +844,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } - /* Memory to Peripheral */ + /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ @@ -859,7 +857,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /** * @brief set the DMA base address and channel index depending on DMA instance - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h index 1aeabd9009..6a9fb70f44 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -365,21 +363,21 @@ typedef struct __DMA_HandleTypeDef */ /** @brief Reset DMA handle state - * @param __HANDLE__: DMA handle. + * @param __HANDLE__ DMA handle. * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) /** * @brief Disable the specified DMA Channel. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) @@ -389,8 +387,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enables the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -401,8 +399,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disables the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -413,8 +411,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -425,7 +423,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * * @retval The number of remaining data units in the current DMA Channel transfer. */ @@ -433,7 +431,7 @@ typedef struct __DMA_HandleTypeDef #if defined(SYSCFG_CFGR1_DMA_RMP) /** @brief DMA remapping enable/disable macros - * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping + * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping */ #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ SYSCFG->CFGR1 |= (__DMA_REMAP__); \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h index 3153818811..03217b1ca4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DMA HAL Extension module. ****************************************************************************** * @attention @@ -523,7 +521,7 @@ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) /** * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -537,7 +535,7 @@ /** * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -551,7 +549,7 @@ /** * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -565,7 +563,7 @@ /** * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ @@ -579,8 +577,8 @@ /** * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -593,8 +591,8 @@ /** * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -607,7 +605,7 @@ #elif defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -626,7 +624,7 @@ /** * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -645,7 +643,7 @@ /** * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -664,7 +662,7 @@ /** * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ @@ -683,8 +681,8 @@ /** * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -699,8 +697,8 @@ /** * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -715,7 +713,7 @@ #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ /** * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -727,7 +725,7 @@ /** * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -739,7 +737,7 @@ /** * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -751,7 +749,7 @@ /** * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ @@ -763,8 +761,8 @@ /** * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -777,8 +775,8 @@ /** * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c index 72ece2dfa8..167bb4bb66 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -436,7 +434,7 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) @@ -455,7 +453,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which returned an error * - Program: Address which was selected for data program diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h index f3497a2bd0..f2ee2488de 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c index 1999e2c3f3..3c2041cf15 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following @@ -921,26 +919,23 @@ static uint32_t FLASH_OB_GetWRP(void) */ static uint32_t FLASH_OB_GetRDP(void) { - uint32_t readstatus = OB_RDP_LEVEL_0; - uint32_t tmp_reg = 0; + uint32_t tmp_reg = 0U; /* Read RDP level bits */ tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); if (tmp_reg == FLASH_OBR_RDPRT1) { - readstatus = OB_RDP_LEVEL_1; + return OB_RDP_LEVEL_1; } else if (tmp_reg == FLASH_OBR_RDPRT2) { - readstatus = OB_RDP_LEVEL_2; + return OB_RDP_LEVEL_2; } else { - readstatus = OB_RDP_LEVEL_0; + return OB_RDP_LEVEL_0; } - - return readstatus; } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h index 73c96e83aa..0d127e3685 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c index 7e9a8e27f1..2890fccaeb 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -180,8 +178,8 @@ /** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ @@ -305,8 +303,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /** * @brief De-initialize the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -386,8 +384,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /** * @brief Read the specified input port pin. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bit to read. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ @@ -415,10 +413,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -442,8 +440,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggle the specified GPIO pin. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the pin to be toggled. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the pin to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -460,8 +458,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bits to be locked. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ @@ -496,7 +494,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Handle EXTI interrupt request. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -511,7 +509,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) /** * @brief EXTI line detection callback. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h index 31eb6d8d0f..21157f853c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -181,7 +179,7 @@ typedef enum /** * @brief Check whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -189,7 +187,7 @@ typedef enum /** * @brief Clear the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -197,7 +195,7 @@ typedef enum /** * @brief Check whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -205,7 +203,7 @@ typedef enum /** * @brief Clear the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -213,7 +211,7 @@ typedef enum /** * @brief Generate a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h index a6209ad3d0..82169b437f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -76,6 +74,7 @@ #define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ #define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ #define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ /* AF 1 */ #define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ @@ -123,6 +122,7 @@ #define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ #define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ #define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ /* AF 1 */ #define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c index 9547c6b6f5..225b519bdb 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -238,7 +236,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -366,7 +364,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -406,7 +404,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -421,7 +419,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - if(hi2c->State == HAL_I2C_STATE_RESET) + if (hi2c->State == HAL_I2C_STATE_RESET) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; @@ -444,7 +442,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); } @@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { hi2c->Instance->CR2 = (I2C_CR2_ADD10); } @@ -493,7 +491,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -557,7 +555,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * @verbatim =============================================================================== @@ -569,7 +567,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function + The status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. @@ -630,7 +628,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -638,7 +636,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -646,7 +644,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -654,7 +652,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -665,12 +663,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -684,15 +682,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -707,9 +705,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -754,15 +752,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) - { + if (hi2c->State == HAL_I2C_STATE_READY) + { /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -778,7 +776,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -789,12 +787,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -809,15 +807,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -832,9 +830,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -843,7 +841,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -865,7 +863,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /** - * @brief Transmits in slave mode an amount of data in blocking mode. + * @brief Transmits in slave mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -877,15 +875,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -902,7 +900,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -910,13 +908,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -924,26 +922,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -959,16 +957,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } else { @@ -977,10 +975,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1017,9 +1015,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1042,7 +1040,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1050,33 +1048,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferCount--; } - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; } @@ -1092,12 +1090,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1108,10 +1106,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1149,9 +1147,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1168,8 +1166,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1185,7 +1183,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current @@ -1218,9 +1216,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1237,8 +1235,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1252,7 +1250,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1283,7 +1281,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1323,7 +1321,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -1332,7 +1330,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1385,9 +1383,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1404,8 +1402,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1416,7 +1414,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; @@ -1454,7 +1452,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); @@ -1493,9 +1491,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1512,8 +1510,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1524,7 +1522,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; @@ -1541,7 +1539,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1562,7 +1560,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); @@ -1596,12 +1594,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); @@ -1642,7 +1640,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; return HAL_OK; } @@ -1662,12 +1660,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); @@ -1737,9 +1735,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1750,7 +1748,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1765,9 +1763,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1782,7 +1780,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1796,9 +1794,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1813,15 +1811,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1833,13 +1831,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1889,9 +1888,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1902,7 +1901,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1917,9 +1916,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1935,7 +1934,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -1949,7 +1948,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, do { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1959,15 +1958,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1978,13 +1977,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -2033,14 +2033,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2060,8 +2060,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2073,9 +2073,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2090,12 +2090,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ @@ -2132,14 +2132,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2159,8 +2159,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2172,9 +2172,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2230,14 +2230,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2257,8 +2257,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2270,9 +2270,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2346,14 +2346,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2374,7 +2374,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2386,9 +2386,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2416,7 +2416,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2458,9 +2458,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2474,16 +2474,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd do { /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2491,14 +2491,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } - } + } } /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2517,7 +2517,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2535,8 +2535,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2544,7 +2544,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - }while(I2C_Trials < Trials); + } + while (I2C_Trials < Trials); hi2c->State = HAL_I2C_STATE_READY; @@ -2579,7 +2580,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2595,7 +2596,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If size > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2645,7 +2646,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2661,7 +2662,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2673,7 +2674,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, } /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2706,9 +2707,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2718,10 +2719,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); @@ -2741,11 +2742,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2780,9 +2781,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2792,15 +2793,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); } - + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2815,11 +2816,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2847,7 +2848,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->XferISR = I2C_Slave_ISR_IT; @@ -2875,7 +2876,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) uint32_t tmp; /* Disable Address listen mode only if a transfer is not ongoing */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); @@ -2904,7 +2905,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if(hi2c->Mode == HAL_I2C_MODE_MASTER) + if (hi2c->Mode == HAL_I2C_MODE_MASTER) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2923,7 +2924,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -2944,7 +2945,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief This function handles I2C event interrupt request. @@ -2959,7 +2960,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C events treatment -------------------------------------*/ - if(hi2c->XferISR != NULL) + if (hi2c->XferISR != NULL) { hi2c->XferISR(hi2c, itflags, itsources); } @@ -2977,7 +2978,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C Bus error interrupt occurred ------------------------------------*/ - if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -2986,7 +2987,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -2995,7 +2996,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -3004,7 +3005,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -3077,8 +3078,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -3228,7 +3229,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @} - */ + */ /** * @} @@ -3246,14 +3247,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3266,27 +3267,27 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; - hi2c->XferCount--; + hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -3294,7 +3295,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { hi2c->XferSize = hi2c->XferCount; - if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } @@ -3307,7 +3308,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { /* Call TxCpltCallback() if no stop mode is set */ - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSequentialCplt(hi2c); @@ -3320,14 +3321,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Generate a stop condition in case of no transfer option */ - if(hi2c->XferOptions == I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -3347,7 +3348,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3367,26 +3368,26 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } - else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3414,9 +3415,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; @@ -3424,24 +3425,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->XferCount--; } - if((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + if ((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); - } + } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); @@ -3450,7 +3451,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } else { - if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ @@ -3460,7 +3461,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } /* Check if STOPF is set */ - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3480,7 +3481,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; uint32_t xfermode = 0U; @@ -3488,14 +3489,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - + /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ @@ -3504,18 +3505,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if(hi2c->XferCount != 0U) + + if (hi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - + /* Prepare the new XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -3533,7 +3534,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui hi2c->XferCount -= hi2c->XferSize; /* Enable DMA Request */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } @@ -3549,7 +3550,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3569,18 +3570,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3590,17 +3591,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3626,12 +3627,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3642,7 +3643,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3654,9 +3655,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3665,18 +3666,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } -return HAL_OK; + return HAL_OK; } /** @@ -3693,12 +3694,12 @@ return HAL_OK; */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3709,7 +3710,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3721,9 +3722,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3732,17 +3733,17 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -3763,7 +3764,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); @@ -3771,19 +3772,19 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; - if(hi2c->AddrEventCount == 2U) + if (hi2c->AddrEventCount == 2U) { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3885,7 +3886,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3901,7 +3902,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) HAL_I2C_SlaveTxCpltCallback(hi2c); } - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3937,7 +3938,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if((ITFlags & I2C_FLAG_AF) != RESET) + if ((ITFlags & I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3950,16 +3951,16 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); /* Call the corresponding callback to inform upper layer of End of Transfer */ - if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; @@ -3985,7 +3986,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4022,7 +4023,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); @@ -4037,26 +4038,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ - if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); } /* All data are not transferred, so set error code accordingly */ - if(hi2c->XferCount != 0U) + if (hi2c->XferCount != 0U) { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4070,19 +4071,19 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } } - else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; @@ -4094,7 +4095,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) HAL_I2C_ListenCpltCallback(hi2c); } /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4132,12 +4133,12 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4177,9 +4178,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); @@ -4193,10 +4194,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ - if(hi2c->State != HAL_I2C_STATE_ABORT) + if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; @@ -4206,7 +4207,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } /* Abort DMA TX transfer if any */ - if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4218,14 +4219,14 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } /* Abort DMA RX transfer if any */ - else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -4237,16 +4238,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } - else if(hi2c->State == HAL_I2C_STATE_ABORT) + else if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4272,13 +4273,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) { - hi2c->Instance->TXDR = 0x00U; + hi2c->Instance->TXDR = 0x00U; } /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); } @@ -4291,13 +4292,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4309,7 +4310,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4348,13 +4349,13 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4366,7 +4367,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4405,7 +4406,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4417,12 +4418,12 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4432,10 +4433,10 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->hdmarx->XferAbortCallback = NULL; /* Check if come from abort from user */ - if(hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_AbortCpltCallback(hi2c); } @@ -4458,14 +4459,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4487,21 +4488,21 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4524,19 +4525,19 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4558,16 +4559,16 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check if a STOPF is detected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -4576,7 +4577,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4586,10 +4587,10 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4610,18 +4611,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4644,7 +4645,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4690,8 +4691,8 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); /* update CR2 register */ hi2c->Instance->CR2 = tmpreg; @@ -4708,28 +4709,28 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr { uint32_t tmpisr = 0U; - if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -4737,31 +4738,31 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr } else { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } } - + /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ @@ -4781,49 +4782,49 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter { uint32_t tmpisr = 0U; - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h index a3aa63142d..dfdbdec4b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32F0xx_HAL_I2C_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" +#include "stm32f0xx_hal_def.h" /** @addtogroup STM32F0xx_HAL_Driver * @{ @@ -52,7 +50,7 @@ /** @addtogroup I2C * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types @@ -60,13 +58,13 @@ */ /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition + * @brief I2C Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization + This parameter calculated by referring to I2C initialization section in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. @@ -90,9 +88,9 @@ typedef struct uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ -}I2C_InitTypeDef; +} I2C_InitTypeDef; -/** +/** * @} */ @@ -122,7 +120,7 @@ typedef struct * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ - */ + */ typedef enum { HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ @@ -139,7 +137,7 @@ typedef enum HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -}HAL_I2C_StateTypeDef; +} HAL_I2C_StateTypeDef; /** * @} @@ -170,9 +168,9 @@ typedef enum HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -}HAL_I2C_ModeTypeDef; +} HAL_I2C_ModeTypeDef; -/** +/** * @} */ @@ -213,7 +211,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -228,7 +226,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -}I2C_HandleTypeDef; +} I2C_HandleTypeDef; /** * @} */ @@ -313,7 +311,7 @@ typedef struct __I2C_HandleTypeDef /** * @} */ - + /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ @@ -431,7 +429,7 @@ typedef struct __I2C_HandleTypeDef * @retval None */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified I2C interrupt source is enabled or not. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the I2C interrupt source to check. @@ -506,7 +504,7 @@ typedef struct __I2C_HandleTypeDef #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) @@ -527,7 +525,7 @@ typedef struct __I2C_HandleTypeDef */ /* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** @@ -538,7 +536,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); * @{ */ /* IO operation functions ****************************************************/ - /******* Blocking mode: Polling */ +/******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -547,7 +545,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - /******* Non-Blocking mode: Interrupt */ +/******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -563,7 +561,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - /******* Non-Blocking mode: DMA */ +/******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -604,11 +602,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants @@ -617,7 +615,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros @@ -681,7 +679,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions @@ -690,15 +688,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /* Private functions are defined in stm32f0xx_hal_i2c.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c index d8c8e4a8f0..6c24c54b2a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c @@ -2,10 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: * + Extended features functions * @@ -96,7 +94,7 @@ ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Noise Filters + (+) Configure Noise Filters (+) Configure Wake Up Feature @endverbatim @@ -116,7 +114,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -162,7 +160,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -206,12 +204,12 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -245,12 +243,12 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -263,7 +261,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) /* Enable wakeup from stop mode */ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - __HAL_I2C_ENABLE(hi2c); + __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h index cd3ce9d68e..69bc8fb292 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention @@ -40,7 +38,7 @@ #define __STM32F0xx_HAL_I2C_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,7 +50,7 @@ /** @addtogroup I2CEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -64,7 +62,7 @@ /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLE (0x00000000U) +#define I2C_ANALOGFILTER_ENABLE 0x00000000U #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} @@ -73,7 +71,7 @@ /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ -#define I2C_FMP_NOT_SUPPORTED (0xAAAA0000U) /*!< Fast Mode Plus not supported */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ #if defined(SYSCFG_CFGR1_I2C_FMP_PA9) #define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ #define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ @@ -101,7 +99,7 @@ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -154,7 +152,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c index 93e0bdb27a..d0fe3dada4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -212,7 +210,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -331,7 +329,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /** * @brief DeInitializes the I2S peripheral - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -365,7 +363,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP Init - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -381,7 +379,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP DeInit - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -443,15 +441,15 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief Transmit an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -531,15 +529,15 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /** * @brief Receive an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate @@ -612,10 +610,10 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -677,10 +675,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -744,10 +742,10 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u /** * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Transmit data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -825,10 +823,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -915,7 +913,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Pauses the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -943,7 +941,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -978,7 +976,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1019,7 +1017,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1073,7 +1071,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer Half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1089,7 +1087,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1105,7 +1103,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1121,7 +1119,7 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1137,7 +1135,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief I2S error callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1172,7 +1170,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S state - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL state */ @@ -1183,7 +1181,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S error code - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval I2S Error Code */ @@ -1204,7 +1202,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) */ /** * @brief DMA I2S transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1225,7 +1223,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1238,7 +1236,7 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1258,7 +1256,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1271,7 +1269,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1293,7 +1291,7 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1315,7 +1313,7 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) /** * @brief Receive an amount of data in non-blocking mode with Interrupt -* @param hi2s: I2S handle +* @param hi2s I2S handle * @retval None */ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) @@ -1337,11 +1335,11 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S Communication Timeout. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h index fcf0bf67d9..1cf51f2487 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -293,21 +291,21 @@ typedef struct */ /** @brief Reset I2S handle state - * @param __HANDLE__: I2S handle. + * @param __HANDLE__ I2S handle. * @retval None */ #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) /** @brief Enable or disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE)) /** @brief Enable or disable the specified I2S interrupts. - * @param __HANDLE__: specifies the I2S Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -318,9 +316,9 @@ typedef struct #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -330,8 +328,8 @@ typedef struct #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__: specifies the I2S Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag * @arg I2S_FLAG_TXE: Transmit buffer empty flag @@ -345,7 +343,7 @@ typedef struct #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ @@ -355,7 +353,7 @@ typedef struct UNUSED(tmpreg); \ }while(0) /** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c index 17871e7b51..606972ce22 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -266,7 +264,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @brief Initialize the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -319,7 +317,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /** * @brief DeInitialize the IRDA peripheral. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -353,7 +351,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /** * @brief Initialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -369,7 +367,7 @@ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) /** * @brief DeInitialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1653,7 +1651,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -2025,7 +2023,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2055,7 +2053,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h index 06e25afe6c..6df14dd57c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains all the functions prototypes for the IRDA * firmware library. ****************************************************************************** @@ -361,22 +359,10 @@ typedef enum #define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */ #define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */ #define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */ - -/** Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - */ -#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */ - -/** Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - */ -#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */ -#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */ -#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */ +#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */ +#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */ +#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */ +#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */ /** * @} */ @@ -413,7 +399,7 @@ typedef enum */ /** @brief Reset IRDA handle state. - * @param __HANDLE__: IRDA handle. + * @param __HANDLE__ IRDA handle. * @retval None */ #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -422,7 +408,7 @@ typedef enum } while(0) /** @brief Flush the IRDA DR register. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ @@ -432,8 +418,8 @@ typedef enum } while(0) /** @brief Clear the specified IRDA pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref IRDA_CLEAR_PEF * @arg @ref IRDA_CLEAR_FEF @@ -446,39 +432,39 @@ typedef enum #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) /** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) /** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) /** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) /** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) /** @brief Check whether the specified IRDA flag is set or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag @@ -498,8 +484,8 @@ typedef enum /** @brief Enable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -514,8 +500,8 @@ typedef enum ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -531,8 +517,8 @@ typedef enum /** @brief Check whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -547,8 +533,8 @@ typedef enum #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified IRDA interrupt source is enabled or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -563,8 +549,8 @@ typedef enum /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag @@ -578,8 +564,8 @@ typedef enum /** @brief Set a specific IRDA request flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request @@ -590,25 +576,25 @@ typedef enum #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -623,20 +609,20 @@ typedef enum */ /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. - * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False */ #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) /** @brief Ensure that IRDA prescaler value is strictly larger than 0. - * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. + * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. * @retval True or False */ #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) /** * @brief Ensure that IRDA frame parity is valid. - * @param __PARITY__: IRDA frame parity. + * @param __PARITY__ IRDA frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ @@ -645,14 +631,14 @@ typedef enum /** * @brief Ensure that IRDA communication mode is valid. - * @param __MODE__: IRDA communication mode. + * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that IRDA power mode is valid. - * @param __MODE__: IRDA power mode. + * @param __MODE__ IRDA power mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ @@ -660,7 +646,7 @@ typedef enum /** * @brief Ensure that IRDA state is valid. - * @param __STATE__: IRDA state mode. + * @param __STATE__ IRDA state mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ @@ -668,7 +654,7 @@ typedef enum /** * @brief Ensure that IRDA associated UART/USART mode is valid. - * @param __MODE__: IRDA associated UART/USART mode. + * @param __MODE__ IRDA associated UART/USART mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ @@ -676,7 +662,7 @@ typedef enum /** * @brief Ensure that IRDA sampling rate is valid. - * @param __ONEBIT__: IRDA sampling rate. + * @param __ONEBIT__ IRDA sampling rate. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ @@ -684,7 +670,7 @@ typedef enum /** * @brief Ensure that IRDA DMA TX mode is valid. - * @param __DMATX__: IRDA DMA TX mode. + * @param __DMATX__ IRDA DMA TX mode. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ @@ -692,7 +678,7 @@ typedef enum /** * @brief Ensure that IRDA DMA RX mode is valid. - * @param __DMARX__: IRDA DMA RX mode. + * @param __DMARX__ IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ @@ -700,7 +686,7 @@ typedef enum /** * @brief Ensure that IRDA request is valid. - * @param __PARAM__: IRDA request. + * @param __PARAM__ IRDA request. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h index 969406fc53..52df110414 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of IRDA HAL Extended module. ****************************************************************************** * @attention @@ -95,8 +93,8 @@ */ /** @brief Report the IRDA clock source. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ @@ -315,7 +313,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. */ #if defined (STM32F042x6) || defined (STM32F048xx) || \ @@ -389,7 +387,7 @@ /** * @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__: IRDA frame length. + * @param __LENGTH__ IRDA frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c index 9f3e96c615..1899f1f862 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h index 45914d0953..b3f3cd2993 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c index 5b858c4457..a802483a14 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -132,7 +130,7 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @brief Initializes the PCD according to the specified * parameters in the PCD_InitTypeDef and create the associated handle. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) @@ -213,7 +211,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes the PCD peripheral - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) @@ -239,7 +237,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /** * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) @@ -254,7 +252,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) @@ -288,7 +286,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) /** * @brief Start the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) @@ -301,7 +299,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) /** * @brief Stop the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) @@ -323,7 +321,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) /** * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) @@ -401,8 +399,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data out stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -418,8 +416,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data IN stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -434,7 +432,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** * @brief Setup stage callback - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -449,7 +447,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Start Of Frame callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) @@ -464,7 +462,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Reset callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) @@ -479,7 +477,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Suspend event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) @@ -494,7 +492,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Resume event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) @@ -509,8 +507,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO OUT callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -526,8 +524,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO IN callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -543,7 +541,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connection event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) @@ -558,7 +556,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Disconnection event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -591,7 +589,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connect the USB device - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) @@ -607,7 +605,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) /** * @brief Disconnect the USB device - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) @@ -623,8 +621,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) /** * @brief Set the USB Device address - * @param hpcd: PCD handle - * @param address: new device address + * @param hpcd PCD handle + * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) @@ -646,10 +644,10 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) } /** * @brief Open and configure an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packert size - * @param ep_type: endpoint type + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packert size + * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) @@ -754,8 +752,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /** * @brief Deactivate an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -825,10 +823,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Receive an amount of data - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -845,8 +843,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & 0x7FU; - __HAL_LOCK(hpcd); - /* Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { @@ -873,15 +869,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) - __HAL_UNLOCK(hpcd); - return HAL_OK; } /** * @brief Get Received Data Size - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -890,10 +884,10 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** * @brief Send an amount of data - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -910,8 +904,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->is_in = 1U; ep->num = ep_addr & 0x7FU; - __HAL_LOCK(hpcd); - /*Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { @@ -951,16 +943,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) - - __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Set a STALL condition over an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1005,8 +995,8 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Clear a STALL condition over in an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1045,8 +1035,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Flush an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1056,7 +1046,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling -* @param hpcd: PCD handle +* @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1077,7 +1067,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling -* @param hpcd: PCD handle +* @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1116,7 +1106,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD state - * @param hpcd : PCD handle + * @param hpcd PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) @@ -1136,10 +1126,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) */ /** * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx: USB peripheral instance register address. - * @param pbUsrBuf: pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. * @retval None */ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) @@ -1162,28 +1152,37 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u /** * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx: USB peripheral instance register address. + * @param USBx USB peripheral instance register address. * @param pbUsrBuf = pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. * @retval None */ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; + uint32_t n = (uint32_t)wNBytes >> 1U; uint32_t i; uint16_t *pdwVal; + uint32_t temp; pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + for (i = n; i != 0U; i--) { - *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++; - pbUsrBuf++; + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); + *pbUsrBuf++ = ((temp >> 8) & 0xFF); + } + + if (wNBytes % 2) + { + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); } } /** * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) @@ -1241,7 +1240,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); /* SETUP bit kept frozen while CTR_RX = 1*/ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h index a55517f0a3..9f1b753289 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -386,9 +384,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wType: Endpoint Type. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. * @retval None */ #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ @@ -396,8 +394,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Endpoint Type */ #define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD) @@ -406,9 +404,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: Direction + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir Direction * @retval None */ #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ @@ -425,8 +423,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets direction of the double buffered endpoint - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval EP_DBUF_OUT, EP_DBUF_IN, * EP_DBUF_ERR if the endpoint counter not yet programmed. */ @@ -442,9 +440,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ @@ -465,9 +463,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ @@ -489,10 +487,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wStaterx: new state. - * @param wStatetx: new state. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. * @retval None */ #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ @@ -525,8 +523,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] * /STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval status */ #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT) @@ -534,8 +532,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) @@ -543,8 +541,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief checks stall condition in an endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval TRUE = endpoint in stall condition. */ #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ @@ -554,8 +552,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief set & clear EP_KIND bit. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ @@ -565,8 +563,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -574,8 +572,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -583,8 +581,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ @@ -594,8 +592,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ @@ -605,8 +603,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\ @@ -620,9 +618,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bAddr: Address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. * @retval None */ #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ @@ -630,8 +628,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) @@ -644,9 +642,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wAddr: address to be set (must be word aligned). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). * @retval None */ #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) @@ -654,8 +652,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval address of the buffer. */ #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -663,9 +661,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg: Register - * @param wCount: Counter. - * @param wNBlocks: no. of Blocks. + * @param dwReg Register + * @param wCount Counter. + * @param wNBlocks no. of Blocks. * @retval None */ #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ @@ -708,9 +706,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets counter for the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wCount: Counter value. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. * @retval None */ #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) @@ -721,8 +719,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets counter of the tx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Counter value */ #define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) @@ -730,9 +728,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. * @retval Counter value */ #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr))) @@ -740,10 +738,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets addresses in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @param wBuf1Addr = buffer 1 address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @param wBuf1Addr buffer 1 address. * @retval None */ #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ @@ -753,8 +751,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -762,11 +760,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT * EP_DBUF_IN = IN - * @param wCount: Counter value + * @param wCount Counter value * @retval None */ #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ @@ -797,8 +795,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c index 959e7dd1a0..b00d2f8547 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -81,12 +79,12 @@ /** * @brief Configure PMA for EP - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_kind: endpoint Kind + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind * @arg USB_SNG_BUF: Single Buffer used * @arg USB_DBL_BUF: Double Buffer used - * @param pmaadress: EP address in The PMA: In case of single buffer endpoint + * @param pmaadress EP address in The PMA: In case of single buffer endpoint * this parameter is 16-bit value providing the address * in PMA allocated to endpoint. * In case of double buffer endpoint this parameter diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h index 035e8bba83..35a70b6481 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention @@ -36,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L0xx_HAL_PCD_EX_H -#define __STM32L0xx_HAL_PCD_EX_H +#ifndef __STM32F0xx_HAL_PCD_EX_H +#define __STM32F0xx_HAL_PCD_EX_H #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c index 8959920a3f..4eef3d0f4e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -241,7 +239,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. * This parameter can be value of : * @ref PWREx_WakeUp_Pins * @retval None @@ -256,7 +254,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) /** * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. * This parameter can be values of : * @ref PWREx_WakeUp_Pins * @retval None @@ -272,11 +270,11 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) /** * @brief Enters Sleep mode. * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator: Specifies the regulator state in SLEEP mode. + * @param Regulator Specifies the regulator state in SLEEP mode. * On STM32F0 devices, this parameter is a dummy value and it is ignored * as regulator can't be modified in this mode. Parameter is kept for platform * compatibility. - * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. * When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * This parameter can be one of the following values: @@ -317,11 +315,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in STOP mode. + * @param Regulator Specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON - * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h index 302e410fd6..ce9b7dd517 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -104,7 +102,7 @@ */ /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A), @@ -126,7 +124,7 @@ #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c index 4ce4ace5b1..d83817ddef 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -116,7 +114,7 @@ defined (STM32F042x6) || defined (STM32F072xB) /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h index 384cf459ce..ef74a81d77 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c index fd2730f76d..619a481a17 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -986,7 +984,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #endif void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { - GPIO_InitTypeDef gpio = {0U}; + GPIO_InitTypeDef gpio; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); @@ -1068,7 +1066,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, - 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U}; + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; uint32_t sysclockfreq = 0U; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h index 56a62eea43..c9cf5a657c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -68,12 +66,12 @@ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ #if defined(RCC_HSI48_SUPPORT) -#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -83,11 +81,11 @@ * @{ */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00U -#define RCC_CFGR_OFFSET 0x04U -#define RCC_CIR_OFFSET 0x08U -#define RCC_BDCR_OFFSET 0x20U -#define RCC_CSR_OFFSET 0x24U +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x04 +#define RCC_CIR_OFFSET 0x08 +#define RCC_BDCR_OFFSET 0x20 +#define RCC_CSR_OFFSET 0x24 /** * @} @@ -114,30 +112,30 @@ #define RCC_CFGR_HPRE_BITNUMBER 4U #define RCC_CFGR_PPRE_BITNUMBER 8U /* Flags in the CFGR2 register */ -#define RCC_CFGR2_PREDIV_BITNUMBER 0U +#define RCC_CFGR2_PREDIV_BITNUMBER 0 /* Flags in the CR register */ -#define RCC_CR_HSIRDY_BitNumber 1U -#define RCC_CR_HSERDY_BitNumber 17U -#define RCC_CR_PLLRDY_BitNumber 25U +#define RCC_CR_HSIRDY_BitNumber 1 +#define RCC_CR_HSERDY_BitNumber 17 +#define RCC_CR_PLLRDY_BitNumber 25 /* Flags in the CR2 register */ -#define RCC_CR2_HSI14RDY_BitNumber 1U -#define RCC_CR2_HSI48RDY_BitNumber 16U +#define RCC_CR2_HSI14RDY_BitNumber 1 +#define RCC_CR2_HSI48RDY_BitNumber 16 /* Flags in the BDCR register */ -#define RCC_BDCR_LSERDY_BitNumber 1U +#define RCC_BDCR_LSERDY_BitNumber 1 /* Flags in the CSR register */ -#define RCC_CSR_LSIRDY_BitNumber 1U -#define RCC_CSR_V18PWRRSTF_BitNumber 23U -#define RCC_CSR_RMVF_BitNumber 24U -#define RCC_CSR_OBLRSTF_BitNumber 25U -#define RCC_CSR_PINRSTF_BitNumber 26U -#define RCC_CSR_PORRSTF_BitNumber 27U -#define RCC_CSR_SFTRSTF_BitNumber 28U -#define RCC_CSR_IWDGRSTF_BitNumber 29U -#define RCC_CSR_WWDGRSTF_BitNumber 30U -#define RCC_CSR_LPWRRSTF_BitNumber 31U +#define RCC_CSR_LSIRDY_BitNumber 1 +#define RCC_CSR_V18PWRRSTF_BitNumber 23 +#define RCC_CSR_RMVF_BitNumber 24 +#define RCC_CSR_OBLRSTF_BitNumber 25 +#define RCC_CSR_PINRSTF_BitNumber 26 +#define RCC_CSR_PORRSTF_BitNumber 27 +#define RCC_CSR_SFTRSTF_BitNumber 28 +#define RCC_CSR_IWDGRSTF_BitNumber 29 +#define RCC_CSR_WWDGRSTF_BitNumber 30 +#define RCC_CSR_LPWRRSTF_BitNumber 31 /* Flags in the HSITRIM register */ -#define RCC_CR_HSITRIM_BitNumber 3U -#define RCC_HSI14TRIM_BIT_NUMBER 3U +#define RCC_CR_HSITRIM_BitNumber 3 +#define RCC_HSI14TRIM_BIT_NUMBER 3 #define RCC_FLAG_MASK ((uint8_t)0x1FU) /** @@ -244,20 +242,22 @@ typedef struct This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ uint32_t HSI14State; /*!< The new state of the HSI14. This parameter can be a value of @ref RCC_HSI14_Config */ uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ +#if defined(RCC_HSI48_SUPPORT) uint32_t HSI48State; /*!< The new state of the HSI48. This parameter can be a value of @ref RCC_HSI48_Config */ +#endif /* RCC_HSI48_SUPPORT */ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ } RCC_OscInitTypeDef; @@ -352,7 +352,7 @@ typedef struct /** @defgroup RCC_HSI14_Config RCC HSI14 Config * @{ */ -#define RCC_HSI14_OFF ((uint32_t)0x00000000U) +#define RCC_HSI14_OFF (0x00000000U) #define RCC_HSI14_ON RCC_CR2_HSI14ON #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) @@ -641,56 +641,56 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) @@ -744,35 +744,35 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) @@ -818,56 +818,56 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) @@ -1074,7 +1074,7 @@ typedef struct CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ - }while(0) + }while(0U) /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. @@ -1133,7 +1133,7 @@ typedef struct CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ - }while(0) + }while(0U) /** * @} @@ -1267,7 +1267,7 @@ typedef struct do { \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ - } while(0) + } while(0U) /** @brief Get oscillator clock selected as PLL input clock diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c index c4b7ca86fa..a5699bfed8 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -61,9 +59,9 @@ * @{ */ /* Bit position in register */ -#define CRS_CFGR_FELIM_BITNUMBER 16U -#define CRS_CR_TRIM_BITNUMBER 8U -#define CRS_ISR_FECAP_BITNUMBER 16U +#define CRS_CFGR_FELIM_BITNUMBER 16 +#define CRS_CR_TRIM_BITNUMBER 8 +#define CRS_ISR_FECAP_BITNUMBER 16 /** * @} */ @@ -387,7 +385,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { + /* frequency == 0 : means that no available frequency for the peripheral */ uint32_t frequency = 0U; + uint32_t srcclk = 0U; #if defined(USB) uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U; @@ -418,11 +418,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = HSE_VALUE / 32U; } - /* Clock not enabled for RTC*/ - else - { - frequency = 0U; - } break; } case RCC_PERIPHCLK_USART1: @@ -450,11 +445,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for USART1*/ - else - { - frequency = 0U; - } break; } #if defined(RCC_CFGR3_USART2SW) @@ -483,11 +473,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for USART2*/ - else - { - frequency = 0U; - } break; } #endif /* RCC_CFGR3_USART2SW */ @@ -517,11 +502,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for USART3*/ - else - { - frequency = 0U; - } break; } #endif /* RCC_CFGR3_USART3SW */ @@ -540,11 +520,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = HAL_RCC_GetSysClockFreq(); } - /* Clock not enabled for I2C1*/ - else - { - frequency = 0U; - } break; } #if defined(USB) @@ -580,7 +555,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ frequency = (HSI_VALUE / predivfactor) * pllmull; #else - /* HSI used as PLL clock source : frequency = HSI/2 * PLLMUL */ + /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */ frequency = (HSI_VALUE >> 1U) * pllmull; #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ } @@ -592,11 +567,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = HSI48_VALUE; } #endif /* RCC_CR2_HSI48ON */ - /* Clock not enabled for USB*/ - else - { - frequency = 0U; - } break; } #endif /* USB */ @@ -616,11 +586,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for CEC */ - else - { - frequency = 0U; - } break; } #endif /* CEC */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h index c8499b1c15..e86d95010c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -600,14 +598,14 @@ typedef struct typedef struct { uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFF */ + This parameter must be a number between 0 and 0xFFFFU */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ + This parameter must be a number between 0 and 0x3FU */ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFF */ + This parameter must be a number between 0 and 0xFFFFU */ uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. @@ -839,7 +837,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** @@ -849,7 +847,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -864,7 +862,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} @@ -873,7 +871,7 @@ typedef struct /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds +#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} @@ -882,7 +880,7 @@ typedef struct /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value * @{ */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ +#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ /** * @} */ @@ -890,7 +888,7 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ /** @@ -900,7 +898,7 @@ typedef struct /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ /** * @} @@ -962,7 +960,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) @@ -976,7 +974,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) @@ -993,7 +991,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) @@ -1010,7 +1008,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) @@ -1033,7 +1031,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) @@ -1054,7 +1052,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) @@ -1075,7 +1073,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) @@ -1096,14 +1094,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) @@ -1123,7 +1121,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) @@ -1142,7 +1140,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) @@ -1160,21 +1158,21 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) @@ -1192,7 +1190,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) @@ -1208,7 +1206,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ @@ -1222,7 +1220,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) @@ -1236,7 +1234,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) @@ -1258,7 +1256,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) @@ -1275,7 +1273,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) @@ -1289,14 +1287,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART8_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) @@ -1942,7 +1940,7 @@ typedef struct { \ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ } \ - } while(0) + } while(0U) /** * @brief Check whether the specified CRS flag is set or not. @@ -1982,7 +1980,7 @@ typedef struct { \ WRITE_REG(CRS->ICR, (__FLAG__)); \ } \ - } while(0) + } while(0U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c index 6f8fba5e47..c884b7cabd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -146,7 +144,7 @@ /** * @brief Initialize the RTC according to the specified parameters * in the RTC_InitTypeDef structure and initialize the associated handle. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) @@ -205,7 +203,21 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + } + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); @@ -221,7 +233,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /** * @brief DeInitialize the RTC peripheral. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note This function doesn't reset the RTC Backup Data registers. * @retval HAL status */ @@ -339,7 +351,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /** * @brief Initialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) @@ -354,7 +366,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) @@ -387,9 +399,9 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Set RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -473,7 +485,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); @@ -511,12 +523,12 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Get RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned + * @param hrtc RTC handle + * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned * with input format (BIN or BCD), also SubSeconds field returning the * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -566,9 +578,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Set RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -674,9 +686,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /** * @brief Get RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN : Binary data format * @arg RTC_FORMAT_BCD : BCD data format @@ -731,9 +743,9 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** * @brief Set the specified RTC Alarm. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -876,9 +888,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Set the specified RTC Alarm with Interrupt. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -1028,8 +1040,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactivate the specified RTC Alarm. - * @param hrtc: RTC handle - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @retval HAL status @@ -1085,12 +1097,12 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /** * @brief Get the RTC Alarm value and masks. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA - * @param Format: Specifies the format of the entered parameters. + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -1132,7 +1144,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Handle Alarm interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) @@ -1160,7 +1172,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) @@ -1175,8 +1187,8 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle AlarmA Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1235,7 +1247,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) @@ -1279,7 +1291,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ /** * @brief Return the RTC handle state. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL state */ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) @@ -1303,7 +1315,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) * @brief Enter the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) @@ -1334,7 +1346,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) /** * @brief Convert a 2 digit decimal to BCD format. - * @param Value: Byte to be converted + * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) @@ -1352,7 +1364,7 @@ uint8_t RTC_ByteToBcd2(uint8_t Value) /** * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted + * @param Value BCD value to be converted * @retval Converted word */ uint8_t RTC_Bcd2ToByte(uint8_t Value) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h index aaf32fe776..dd1c54f632 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -202,8 +200,8 @@ typedef struct /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 (0x00000000U) -#define RTC_HOURFORMAT_12 (0x00000040U) +#define RTC_HOURFORMAT_24 0x00000000U +#define RTC_HOURFORMAT_12 0x00000040U /** * @} @@ -212,8 +210,8 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH (0x00000000U) -#define RTC_OUTPUT_POLARITY_LOW (0x00100000U) +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U +#define RTC_OUTPUT_POLARITY_LOW 0x00100000U /** * @} */ @@ -221,8 +219,8 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN (0x00000000U) -#define RTC_OUTPUT_TYPE_PUSHPULL (0x00040000U) +#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U +#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U /** * @} */ @@ -230,8 +228,8 @@ typedef struct /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) /** * @} */ @@ -239,9 +237,9 @@ typedef struct /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H (0x00020000U) -#define RTC_DAYLIGHTSAVING_ADD1H (0x00010000U) -#define RTC_DAYLIGHTSAVING_NONE (0x00000000U) +#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U +#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U +#define RTC_DAYLIGHTSAVING_NONE 0x00000000U /** * @} */ @@ -249,8 +247,8 @@ typedef struct /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET (0x00000000U) -#define RTC_STOREOPERATION_SET (0x00040000U) +#define RTC_STOREOPERATION_RESET 0x00000000U +#define RTC_STOREOPERATION_SET 0x00040000U /** * @} */ @@ -258,8 +256,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions * @{ */ -#define RTC_FORMAT_BIN (0x000000000U) -#define RTC_FORMAT_BCD (0x000000001U) +#define RTC_FORMAT_BIN 0x000000000U +#define RTC_FORMAT_BCD 0x000000001U /** * @} */ @@ -268,18 +266,18 @@ typedef struct * @{ */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01U) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) -#define RTC_MONTH_MARCH ((uint8_t)0x03U) -#define RTC_MONTH_APRIL ((uint8_t)0x04U) -#define RTC_MONTH_MAY ((uint8_t)0x05U) -#define RTC_MONTH_JUNE ((uint8_t)0x06U) -#define RTC_MONTH_JULY ((uint8_t)0x07U) -#define RTC_MONTH_AUGUST ((uint8_t)0x08U) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) /** * @} */ @@ -287,13 +285,13 @@ typedef struct /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) /** * @} */ @@ -301,8 +299,8 @@ typedef struct /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE (0x00000000U) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY (0x40000000U) +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U /** * @} */ @@ -310,12 +308,12 @@ typedef struct /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions * @{ */ -#define RTC_ALARMMASK_NONE (0x00000000U) +#define RTC_ALARMMASK_NONE 0x00000000U #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL (0x80808080U) +#define RTC_ALARMMASK_ALL 0x80808080U /** * @} */ @@ -332,38 +330,38 @@ typedef struct /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL (0x00000000U) /*!< All Alarm SS fields are masked. +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 (0x01000000U) /*!< SS[14:1] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 (0x02000000U) /*!< SS[14:2] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 (0x03000000U) /*!< SS[14:3] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 (0x04000000U) /*!< SS[14:4] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 (0x05000000U) /*!< SS[14:5] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 (0x06000000U) /*!< SS[14:6] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 (0x07000000U) /*!< SS[14:7] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 (0x08000000U) /*!< SS[14:8] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 (0x09000000U) /*!< SS[14:9] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 (0x0A000000U) /*!< SS[14:10] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 (0x0B000000U) /*!< SS[14:11] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 (0x0C000000U) /*!< SS[14:12] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 (0x0D000000U) /*!< SS[14:13] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 (0x0E000000U) /*!< SS[14] is don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE (0x0F000000U) /*!< SS[14:0] are compared and must match +#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match to activate alarm. */ /** * @} @@ -372,13 +370,13 @@ typedef struct /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS (0x00008000U) -#define RTC_IT_WUT (0x00004000U) -#define RTC_IT_ALRA (0x00001000U) -#define RTC_IT_TAMP (0x00000004U) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 (0x00020000U) /*only for RTC_ISR flag check*/ -#define RTC_IT_TAMP2 (0x00040000U) /*only for RTC_ISR flag check*/ -#define RTC_IT_TAMP3 (0x00080000U) /*only for RTC_ISR flag check*/ +#define RTC_IT_TS 0x00008000U +#define RTC_IT_WUT 0x00004000U +#define RTC_IT_ALRA 0x00001000U +#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/ /** * @} */ @@ -386,20 +384,20 @@ typedef struct /** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ -#define RTC_FLAG_RECALPF (0x00010000U) -#define RTC_FLAG_TAMP3F (0x00008000U) -#define RTC_FLAG_TAMP2F (0x00004000U) -#define RTC_FLAG_TAMP1F (0x00002000U) -#define RTC_FLAG_TSOVF (0x00001000U) -#define RTC_FLAG_TSF (0x00000800U) -#define RTC_FLAG_WUTF (0x00000400U) -#define RTC_FLAG_ALRAF (0x00000100U) -#define RTC_FLAG_INITF (0x00000040U) -#define RTC_FLAG_RSF (0x00000020U) -#define RTC_FLAG_INITS (0x00000010U) -#define RTC_FLAG_SHPF (0x00000008U) -#define RTC_FLAG_WUTWF (0x00000004U) -#define RTC_FLAG_ALRAWF (0x00000001U) +#define RTC_FLAG_RECALPF 0x00010000U +#define RTC_FLAG_TAMP3F 0x00008000U +#define RTC_FLAG_TAMP2F 0x00004000U +#define RTC_FLAG_TAMP1F 0x00002000U +#define RTC_FLAG_TSOVF 0x00001000U +#define RTC_FLAG_TSF 0x00000800U +#define RTC_FLAG_WUTF 0x00000400U +#define RTC_FLAG_ALRAF 0x00000100U +#define RTC_FLAG_INITF 0x00000040U +#define RTC_FLAG_RSF 0x00000020U +#define RTC_FLAG_INITS 0x00000010U +#define RTC_FLAG_SHPF 0x00000008U +#define RTC_FLAG_WUTWF 0x00000004U +#define RTC_FLAG_ALRAWF 0x00000001U /** * @} */ @@ -414,14 +412,14 @@ typedef struct */ /** @brief Reset RTC handle state - * @param __HANDLE__: RTC handle. + * @param __HANDLE__ RTC handle. * @retval None */ #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) /** * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ @@ -432,7 +430,7 @@ typedef struct /** * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ @@ -442,22 +440,22 @@ typedef struct /** * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -466,8 +464,8 @@ typedef struct /** * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -476,8 +474,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -486,8 +484,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -496,8 +494,8 @@ typedef struct /** * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRAWF @@ -507,8 +505,8 @@ typedef struct /** * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_ALRAF * @retval None @@ -674,10 +672,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK (0x007F7F7FU) -#define RTC_DR_RESERVED_MASK (0x00FFFF3FU) -#define RTC_INIT_MASK (0xFFFFFFFFU) -#define RTC_RSF_MASK (0xFFFFFF5FU) +#define RTC_TR_RESERVED_MASK 0x007F7F7FU +#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU #define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \ RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \ RTC_FLAG_WUTF | RTC_FLAG_ALRAF | \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c index fec90ca471..de88f3ade4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: @@ -136,15 +134,15 @@ /** * @brief Set TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: RTC handle - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @retval HAL status @@ -189,16 +187,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Set TimeStamp with Interrupt. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @retval HAL status @@ -250,7 +248,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivate TimeStamp. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) @@ -287,11 +285,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Get the RTC TimeStamp value. - * @param hrtc: RTC handle + * @param hrtc RTC handle - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -344,8 +342,8 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe /** * @brief Set Tamper * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to Tamper Structure. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) @@ -392,9 +390,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTamper: Pointer to RTC Tamper. + * @param sTamper Pointer to RTC Tamper. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) @@ -449,8 +447,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivate Tamper. - * @param hrtc: RTC handle - * @param Tamper: Selected tamper pin. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. * @retval HAL status */ @@ -476,7 +474,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T /** * @brief Handle TimeStamp interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) @@ -548,7 +546,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief TimeStamp callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) @@ -563,7 +561,7 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 1 callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) @@ -578,7 +576,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 2 callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) @@ -594,7 +592,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Tamper 3 callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) @@ -610,8 +608,8 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle TimeStamp polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -649,8 +647,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** * @brief Handle Tamper 1 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -681,8 +679,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Handle Tamper 2 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -714,8 +712,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Handle Tamper 3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -766,9 +764,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Set wake up timer. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -855,9 +853,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /** * @brief Set wake up timer with interrupt. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -956,7 +954,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /** * @brief Deactivate wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -1008,7 +1006,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Get wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval Counter value */ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -1019,7 +1017,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Handle Wake Up Timer interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) @@ -1047,7 +1045,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief Wake Up Timer callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) @@ -1063,8 +1061,8 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle Wake Up Timer Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1127,11 +1125,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** * @brief Write a data in a specified RTC Backup data register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. + * @param Data Data to be written in the specified RTC Backup data register. * @retval None */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) @@ -1150,8 +1148,8 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /** * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to * specify the register. * @retval Read value @@ -1173,17 +1171,17 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /** * @brief Set the Smooth calibration parameters. - * @param hrtc: RTC handle - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. * This parameter can be can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field @@ -1249,12 +1247,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /** * @brief Configure the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: RTC handle - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. * This parameter can be one of the following values : * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. + * @param ShiftSubFS Select the number of Second Fractions to substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ @@ -1344,8 +1342,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /** * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @param CalibOutput : Select the Calibration output Selection . + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. @@ -1386,7 +1384,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 /** * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) @@ -1415,7 +1413,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) /** * @brief Enable the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) @@ -1464,7 +1462,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Disable the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) @@ -1513,7 +1511,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Enable the Bypass Shadow feature. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status @@ -1545,7 +1543,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Disable the Bypass Shadow feature. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h index 38920de9b9..999844d2d7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention @@ -98,10 +96,10 @@ typedef struct /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition * @{ */ -#define RTC_OUTPUT_DISABLE (0x00000000U) -#define RTC_OUTPUT_ALARMA (0x00200000U) +#define RTC_OUTPUT_DISABLE 0x00000000U +#define RTC_OUTPUT_ALARMA 0x00200000U #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -#define RTC_OUTPUT_WAKEUP (0x00600000U) +#define RTC_OUTPUT_WAKEUP 0x00600000U #endif /** @@ -112,11 +110,11 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition * @{ */ -#define RTC_BKP_DR0 (0x00000000U) -#define RTC_BKP_DR1 (0x00000001U) -#define RTC_BKP_DR2 (0x00000002U) -#define RTC_BKP_DR3 (0x00000003U) -#define RTC_BKP_DR4 (0x00000004U) +#define RTC_BKP_DR0 0x00000000U +#define RTC_BKP_DR1 0x00000001U +#define RTC_BKP_DR2 0x00000002U +#define RTC_BKP_DR3 0x00000003U +#define RTC_BKP_DR4 0x00000004U /** * @} */ @@ -125,8 +123,8 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition * @{ */ -#define RTC_TIMESTAMPEDGE_RISING (0x00000000U) -#define RTC_TIMESTAMPEDGE_FALLING (0x00000008U) +#define RTC_TIMESTAMPEDGE_RISING 0x00000000U +#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U /** * @} @@ -135,7 +133,7 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT (0x00000000U) +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U /** * @} @@ -160,8 +158,8 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE (0x00000000U) -#define RTC_TAMPERTRIGGER_FALLINGEDGE (0x00000002U) +#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE @@ -173,13 +171,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definition * @{ */ -#define RTC_TAMPERFILTER_DISABLE (0x00000000U) /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ -#define RTC_TAMPERFILTER_2SAMPLE (0x00000800U) /*!< Tamper is activated after 2 +#define RTC_TAMPERFILTER_2SAMPLE 0x00000800U /*!< Tamper is activated after 2 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE (0x00001000U) /*!< Tamper is activated after 4 +#define RTC_TAMPERFILTER_4SAMPLE 0x00001000U /*!< Tamper is activated after 4 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE (0x00001800U) /*!< Tamper is activated after 8 +#define RTC_TAMPERFILTER_8SAMPLE 0x00001800U /*!< Tamper is activated after 8 consecutive samples at the active level. */ /** @@ -189,21 +187,21 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 (0x00000000U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 (0x00000100U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 0x00000100U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 (0x00000200U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 0x00000200U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (0x00000300U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 0x00000300U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 (0x00000400U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 0x00000400U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (0x00000500U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 0x00000500U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (0x00000600U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 0x00000600U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (0x00000700U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 0x00000700U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ /** @@ -213,13 +211,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definition * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK (0x00002000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK (0x00004000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (0x00006000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ /** @@ -230,7 +228,7 @@ typedef struct * @{ */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} @@ -239,7 +237,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE (0x00000000U) /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */ /** @@ -250,12 +248,12 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definition * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 (0x00000000U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 (0x00000001U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 (0x00000002U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (0x00000003U) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (0x00000004U) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (0x00000006U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U /** @@ -266,11 +264,11 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definition * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC (0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC (0x00002000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_16SEC 0x00002000U /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC (0x00004000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_8SEC 0x00004000U /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds */ /** @@ -280,10 +278,10 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definition * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET (0x00008000U) /*!< The number of RTCCLK pulses added +#define RTC_SMOOTHCALIB_PLUSPULSES_SET 0x00008000U /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET (0x00000000U) /*!< The number of RTCCLK pulses subbstited +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ /** @@ -292,8 +290,8 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ (0x00000000U) -#define RTC_CALIBOUTPUT_1HZ (0x00080000U) +#define RTC_CALIBOUTPUT_512HZ 0x00000000U +#define RTC_CALIBOUTPUT_1HZ 0x00080000U /** * @} @@ -302,8 +300,8 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definition * @{ */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U) +#define RTC_SHIFTADD1S_RESET 0x00000000U +#define RTC_SHIFTADD1S_SET 0x80000000U /** * @} @@ -325,22 +323,22 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -349,8 +347,8 @@ typedef struct /** * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -359,8 +357,8 @@ typedef struct /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -369,8 +367,8 @@ typedef struct /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -379,8 +377,8 @@ typedef struct /** * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_WUTF * @arg RTC_FLAG_WUTWF @@ -390,8 +388,8 @@ typedef struct /** * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. * This parameter can be: * @arg RTC_FLAG_WUTF * @retval None @@ -489,22 +487,22 @@ typedef struct */ /** * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -513,8 +511,8 @@ typedef struct /** * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -523,8 +521,8 @@ typedef struct /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -533,8 +531,8 @@ typedef struct /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -543,8 +541,8 @@ typedef struct /** * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TSF * @arg RTC_FLAG_TSOVF @@ -554,8 +552,8 @@ typedef struct /** * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag to clear. * This parameter can be: * @arg RTC_FLAG_TSF * @retval None @@ -573,28 +571,28 @@ typedef struct /** * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E)) /** * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E)) /** * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E)) /** * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E)) @@ -602,14 +600,14 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E)) /** * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E)) @@ -617,8 +615,8 @@ typedef struct #endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ /** * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: Tamper interrupt * @retval None @@ -627,8 +625,8 @@ typedef struct /** * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: Tamper interrupt * @retval None @@ -638,8 +636,8 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: * @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt @@ -651,8 +649,8 @@ typedef struct /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: * @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt @@ -664,8 +662,8 @@ typedef struct /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: * @arg RTC_IT_TAMP: Tamper interrupt * @retval None @@ -675,8 +673,8 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -688,8 +686,8 @@ typedef struct /** * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -702,8 +700,8 @@ typedef struct /** * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -714,8 +712,8 @@ typedef struct /** * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -824,36 +822,36 @@ typedef struct /** * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) /** * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) /** * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) /** * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) /** * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_SHPF * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c index 441db9a41c..e111236f30 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -1300,7 +1298,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /** * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1664,7 +1662,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -1759,7 +1757,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1821,7 +1819,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Check the SMARTCARD Idle State. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -2169,7 +2167,7 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Send an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() @@ -2242,7 +2240,7 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /** * @brief Receive an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h index 188b573965..f8c229ce6f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -581,27 +579,27 @@ typedef struct */ /** @brief Reset SMARTCARD handle states. - * @param __HANDLE__: SMARTCARD handle. + * @param __HANDLE__ SMARTCARD handle. * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - } while(0) + } while(0U) /** @brief Flush the Smartcard Data registers. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag @@ -616,39 +614,39 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) /** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) /** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) /** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) /** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) /** @brief Check whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag @@ -669,8 +667,8 @@ typedef struct /** @brief Enable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -682,13 +680,13 @@ typedef struct * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -700,14 +698,14 @@ typedef struct * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT__ specifies the SMARTCARD interrupt to check. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -724,8 +722,8 @@ typedef struct #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt source to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT__ specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -737,14 +735,14 @@ typedef struct * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__IT__)) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \ + (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag @@ -760,8 +758,8 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific SMARTCARD request flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request @@ -771,25 +769,25 @@ typedef struct #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -806,42 +804,42 @@ typedef struct /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on F0 (48 MHz) * divided by the oversampling used on the SMARTCARD (i.e. 16). - * @param __BAUDRATE__: Baud rate set by the configuration function. + * @param __BAUDRATE__ Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 3000001U) /** @brief Check the block length range. * @note The maximum SMARTCARD block length is 0xFF. - * @param __LENGTH__: block length. + * @param __LENGTH__ block length. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) /** @brief Check the receiver timeout value. * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__: receiver timeout value. + * @param __TIMEOUTVALUE__ receiver timeout value. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** @brief Check the SMARTCARD autoretry counter value. * @note The maximum number of retransmissions is 0x7. - * @param __COUNT__: number of retransmissions. + * @param __COUNT__ number of retransmissions. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) /** * @brief Ensure that SMARTCARD frame length is valid. - * @param __LENGTH__: SMARTCARD frame length. + * @param __LENGTH__ SMARTCARD frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) /** * @brief Ensure that SMARTCARD frame number of stop bits is valid. - * @param __STOPBITS__: SMARTCARD frame number of stop bits. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ @@ -849,7 +847,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame parity is valid. - * @param __PARITY__: SMARTCARD frame parity. + * @param __PARITY__ SMARTCARD frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ @@ -857,28 +855,28 @@ typedef struct /** * @brief Ensure that SMARTCARD communication mode is valid. - * @param __MODE__: SMARTCARD communication mode. + * @param __MODE__ SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U)) /** * @brief Ensure that SMARTCARD frame polarity is valid. - * @param __CPOL__: SMARTCARD frame polarity. + * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** * @brief Ensure that SMARTCARD frame phase is valid. - * @param __CPHA__: SMARTCARD frame phase. + * @param __CPHA__ SMARTCARD frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) /** * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. - * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ @@ -886,7 +884,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame sampling is valid. - * @param __ONEBIT__: SMARTCARD frame sampling. + * @param __ONEBIT__ SMARTCARD frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ @@ -894,7 +892,7 @@ typedef struct /** * @brief Ensure that SMARTCARD NACK transmission setting is valid. - * @param __NACK__: SMARTCARD NACK transmission setting. + * @param __NACK__ SMARTCARD NACK transmission setting. * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) */ #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ @@ -902,7 +900,7 @@ typedef struct /** * @brief Ensure that SMARTCARD receiver timeout setting is valid. - * @param __TIMEOUT__: SMARTCARD receiver timeout setting. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ @@ -910,7 +908,7 @@ typedef struct /** * @brief Ensure that SMARTCARD advanced features initialization is valid. - * @param __INIT__: SMARTCARD advanced features initialization. + * @param __INIT__ SMARTCARD advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ @@ -924,7 +922,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame TX inversion setting is valid. - * @param __TXINV__: SMARTCARD frame TX inversion setting. + * @param __TXINV__ SMARTCARD frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ @@ -932,7 +930,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame RX inversion setting is valid. - * @param __RXINV__: SMARTCARD frame RX inversion setting. + * @param __RXINV__ SMARTCARD frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ @@ -940,7 +938,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame data inversion setting is valid. - * @param __DATAINV__: SMARTCARD frame data inversion setting. + * @param __DATAINV__ SMARTCARD frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ @@ -948,7 +946,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. - * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ @@ -956,7 +954,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame overrun setting is valid. - * @param __OVERRUN__: SMARTCARD frame overrun setting. + * @param __OVERRUN__ SMARTCARD frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -964,7 +962,7 @@ typedef struct /** * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. - * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -972,7 +970,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame MSB first setting is valid. - * @param __MSBFIRST__: SMARTCARD frame MSB first setting. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -980,7 +978,7 @@ typedef struct /** * @brief Ensure that SMARTCARD request parameter is valid. - * @param __PARAM__: SMARTCARD request parameter. + * @param __PARAM__ SMARTCARD request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c index 8dd02134bf..3f764d30f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SMARTCARD HAL module driver. * This file provides extended firmware functions to manage the following * functionalities of the SmartCard. @@ -101,9 +99,9 @@ /** * @brief Update on the fly the SMARTCARD block length in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @param BlockLength SMARTCARD block length (8-bit long at most) * @retval None */ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) @@ -113,9 +111,9 @@ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uin /** * @brief Update on the fly the receiver timeout value in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout * value must be less or equal to 0x0FFFFFFFF. * @retval None */ @@ -127,7 +125,7 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ /** * @brief Enable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -159,7 +157,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @brief Disable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h index 8d9e8b248c..ce806d4c55 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention @@ -65,8 +63,8 @@ */ /** @brief Report the SMARTCARD clock source. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__ output variable. * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F031x6) || defined(STM32F038xx) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c index 2ecc371bab..c693b6e8b4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c @@ -2,25 +2,23 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SMBUS HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, * based on I2C principles of operation : * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The SMBUS HAL driver can be used as follows: - + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: - SMBUS_HandleTypeDef hsmbus; + SMBUS_HandleTypeDef hsmbus; (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock @@ -28,7 +26,7 @@ (+++) Enable the clock for the SMBUS GPIOs (+++) Configure SMBUS pins as alternate function open-drain (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SMBUSx interrupt priority + (+++) Configure the SMBUSx interrupt priority (+++) Enable the NVIC SMBUS IRQ Channel (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, @@ -92,7 +90,7 @@ [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention @@ -121,8 +119,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -156,7 +154,7 @@ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -170,6 +168,10 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); + +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); + static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} @@ -182,19 +184,19 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and + [..] This subsection provides a set of functions allowing to initialize and deinitialize the SMBUSx peripheral: - (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, IT and NVIC ). - (+) Call the function HAL_SMBUS_Init() to configure the selected device with + (+) Call the function HAL_SMBUS_Init() to configure the selected device with the selected configuration: (++) Clock Timing (++) Bus Timeout @@ -210,28 +212,31 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre (++) Peripheral mode - (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration - of the selected SMBUSx peripheral. + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx peripheral. + + (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and + HAL_SMBUS_ConfigDigitalFilter(). @endverbatim * @{ */ /** - * @brief Initialize the SMBUS according to the specified parameters + * @brief Initialize the SMBUS according to the specified parameters * in the SMBUS_InitTypeDef and initialize the associated handle. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) -{ +{ /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); @@ -245,7 +250,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); - if(hsmbus->State == HAL_SMBUS_STATE_RESET) + if (hsmbus->State == HAL_SMBUS_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; @@ -253,17 +258,17 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); } - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); - - /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ /* Configure SMBUSx: Frequency range */ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ /* Configure SMBUSx: Bus Timeout */ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; @@ -272,10 +277,10 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - if(hsmbus->Init.OwnAddress1 != 0U) + + if (hsmbus->Init.OwnAddress1 != 0U) { - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); } @@ -287,41 +292,41 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ /* Configure SMBUSx: Addressing Master mode */ - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) { hsmbus->Instance->CR2 = (I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ /* AUTOEND and NACK bit will be manage during Transfer process */ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); - + /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) + && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } /* Enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitialize the SMBUS peripheral. + * @brief DeInitialize the SMBUS peripheral. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -329,29 +334,29 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the SMBUS Peripheral Clock */ __HAL_SMBUS_DISABLE(hsmbus); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_SMBUS_MspDeInit(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; hsmbus->State = HAL_SMBUS_STATE_RESET; - - /* Release Lock */ + + /* Release Lock */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } @@ -361,14 +366,14 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspInit could be implemented in the user file - */ + */ } /** @@ -377,14 +382,112 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspDeInit could be implemented in the user file - */ + */ +} + +/** + * @brief Configure Analog noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref SMBUS_ANALOGFILTER_ENABLE + * @arg @ref SMBUS_ANALOGFILTER_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Reset ANOFF bit */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hsmbus->Instance->CR1 |= AnalogFilter; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure Digital noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Get the old register value */ + tmpreg = hsmbus->Instance->CR1; + + /* Reset I2C DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos; + + /* Store the new register value */ + hsmbus->Instance->CR1 = tmpreg; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } } /** @@ -392,14 +495,14 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the SMBUS data + This subsection provides a set of functions allowing to manage the SMBUS data transfers. (#) Blocking mode function to check if device is ready for usage is : @@ -408,7 +511,7 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) (#) There is only one mode of transfer: (++) Non-Blocking mode : The communication is performed using Interrupts. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the + The end of the data processing will be indicated through the dedicated SMBUS IRQ when using Interrupt mode. (#) Non-Blocking mode functions with Interrupt are : @@ -446,15 +549,15 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ +{ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Prepare transfer parameters */ @@ -464,12 +567,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -477,50 +580,54 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint { hsmbus->XferSize = Size; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); - + return HAL_OK; } else { return HAL_BUSY; - } + } } /** @@ -539,27 +646,27 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Prepare transfer parameters */ hsmbus->pBuffPtr = pData; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - + /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - - if(Size > MAX_NBYTE_SIZE) + + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -567,42 +674,46 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 { hsmbus->XferSize = Size; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -616,18 +727,18 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) { - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + /* Keep the same state as previous */ /* to perform as well the call of the corresponding end of transfer callback */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; } - else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; } @@ -638,32 +749,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ return HAL_ERROR; } hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); } - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -680,11 +791,11 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -692,10 +803,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -704,11 +815,13 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Prepare transfer parameters */ hsmbus->pBuffPtr = pData; - hsmbus->XferSize = Size; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - if(Size > MAX_NBYTE_SIZE) + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -718,32 +831,32 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - + /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -753,8 +866,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } else { - return HAL_ERROR; - } + return HAL_ERROR; + } } /** @@ -771,22 +884,22 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -798,13 +911,16 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ hsmbus->XferSize = Size; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + /* Set NBYTE to receive */ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -815,12 +931,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -830,7 +946,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ } else { - return HAL_ERROR; + return HAL_ERROR; } } @@ -843,10 +959,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) { hsmbus->State = HAL_SMBUS_STATE_LISTEN; - + /* Enable the Address Match interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } @@ -859,13 +975,13 @@ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) { /* Disable Address listen mode only if a transfer is not ongoing */ - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Disable the Address Match interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } else @@ -883,7 +999,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; /* Clear ALERT flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); @@ -891,7 +1007,7 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) /* Enable Alert Interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** * @brief Disable the SMBUS alert mode with Interrupt. @@ -902,16 +1018,16 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; - + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + /* Disable Alert Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** - * @brief Check if target device is ready for communication. + * @brief Check if target device is ready for communication. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value @@ -921,72 +1037,72 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ +{ uint32_t tickstart = 0U; - + __IO uint32_t SMBUS_Trials = 0U; - - if(hsmbus->State == HAL_SMBUS_STATE_READY) + + if (hsmbus->State == HAL_SMBUS_STATE_READY) { - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + do { /* Generate Start */ - hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); - + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); return HAL_TIMEOUT; } - } + } } - + /* Check if the NACKF flag has not been set */ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } else { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -997,31 +1113,32 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Clear STOP Flag, auto generated with autoend*/ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - + /* Check if the maximum allowed number of trials has been reached */ if (SMBUS_Trials++ == Trials) { /* Generate Stop */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - }while(SMBUS_Trials < Trials); + } + } + while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; - } + } else { return HAL_BUSY; @@ -1044,28 +1161,28 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t tmpisrvalue = 0U; - + /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); - + /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) - { + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Master_ISR(hsmbus); } } - + /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1073,15 +1190,15 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Master_ISR(hsmbus); } - } - - /* SMBUS in mode Listener Only --------------------------------------------------*/ + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) - && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { @@ -1098,79 +1215,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) */ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); - } - - /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); - } - - /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); - } - - /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; - - /* Clear TIMEOUT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); - } - - /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; - - /* Clear ALERT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); - } - - /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; - - /* Clear PEC error flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); - } - - /* Call the Error Callback in case of Error detected */ - if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) - { - /* Do not Reset the HAL state in case of ALERT error */ - if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) - { - if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) - { - /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ - /* keep HAL_SMBUS_STATE_LISTEN if set */ - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_LISTEN; - } - } - - /* Call the Error callback to prevent upper layer */ - HAL_SMBUS_ErrorCallback(hsmbus); - } + SMBUS_ITErrorHandler(hsmbus); } /** @@ -1179,14 +1224,14 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1210,14 +1255,14 @@ __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1240,8 +1285,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @brief Slave Address Match callback. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param TransferDirection: Master request Transfer Direction (Write/Read) - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -1267,7 +1312,7 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file */ } @@ -1278,29 +1323,29 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_ErrorCallback() could be implemented in the user file - */ + */ } /** * @} - */ + */ -/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1332,14 +1377,14 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) /** * @} - */ + */ /** * @} - */ + */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1349,42 +1394,45 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) { uint16_t DevAddress; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - + /* Set corresponding Error Code */ /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); @@ -1394,21 +1442,21 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + /* REenable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1420,64 +1468,64 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) - { + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferSize--; - hsmbus->XferCount--; + hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); - - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } } - else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U)) + else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ - if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1486,10 +1534,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1497,30 +1545,30 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Specific use case for Quick command */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { /* Generate a Stop command */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; } /* Call TxCpltCallback() if no stop mode is set */ - else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ - + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1529,10 +1577,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1540,39 +1588,39 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { uint8_t TransferDirection = 0U; uint16_t SlaveAddrCode = 0U; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Check that SMBUS transfer finished */ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1594,58 +1642,58 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) { TransferDirection = SMBUS_GET_DIR(hsmbus); SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); - + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ /* Other ADDRInterrupt will be treat in next Listen usecase */ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); /* Call Slave Addr callback */ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); } - else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) { - if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; - if(hsmbus->XferCount == 1U) + if (hsmbus->XferCount == 1U) { /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } - else if(hsmbus->XferCount == 0U) + else if (hsmbus->XferCount == 0U) { /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ hsmbus->PreviousState = hsmbus->State; hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1660,13 +1708,13 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; } - } - else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + } + else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -1676,7 +1724,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1685,21 +1733,21 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hsmbus->XferCount > 0U) + if (hsmbus->XferCount > 0U) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferCount--; hsmbus->XferSize--; } - - if(hsmbus->XferCount == 0U) + + if (hsmbus->XferCount == 0U) { /* Last Byte is Transmitted */ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ @@ -1716,17 +1764,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } /* Check if STOPF is set */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1744,30 +1792,30 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Clear ADDR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); hsmbus->XferOptions = 0U; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ HAL_SMBUS_ListenCpltCallback(hsmbus); } } /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + + return HAL_OK; +} /** * @brief Manage the enabling of Interrupts. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -1775,40 +1823,40 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { /* Enable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Enable ERR, TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Enable ERR, TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; } - + /* Enable interrupts only at the end */ /* to avoid the risk of SMBUS interrupt handle execution before */ /* all interrupts requested done */ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); - return HAL_OK; + return HAL_OK; } /** * @brief Manage the disabling of Interrupts. @@ -1817,60 +1865,60 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) + if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Disable TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) - { - /* Disable ERR interrupt */ - tmpisr |= SMBUS_IT_ERRI; - } - - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) - { - /* Disable STOPI, NACKI */ - tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; - } - } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) - { - /* Disable TC, STOP, NACK, RXI interrupt */ - tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Disable TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOPI, NACKI */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1881,9 +1929,95 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); - + return HAL_OK; } + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t itflags = READ_REG(hsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Call the Error Callback in case of Error detected */ + if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } +} + /** * @brief Handle SMBUS Communication Timeout. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -1893,26 +2027,26 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ uint32_t tickstart = HAL_GetTick(); - + /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + if (Status == RESET) + { + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } @@ -1920,25 +2054,25 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu } else { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } } } - return HAL_OK; + return HAL_OK; } /** @@ -1964,25 +2098,64 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { uint32_t tmpreg = 0U; - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); - + /* Get the CR2 register value */ tmpreg = hsmbus->Instance->CR2; - + /* clear tmpreg specific bits */ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); - + /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); + /* update CR2 register */ - hsmbus->Instance->CR2 = tmpreg; -} + hsmbus->Instance->CR2 = tmpreg; +} + +/** + * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) +{ + /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME */ + if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME; + } + /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ + else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; + } +} /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h index 8c71042223..4a499bcef6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32F0xx_HAL_SMBUS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" +#include "stm32f0xx_hal_def.h" /** @addtogroup STM32F0xx_HAL_Driver * @{ @@ -52,25 +50,25 @@ /** @addtogroup SMBUS * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Types SMBUS Exported Types * @{ - */ - + */ + /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition - * @brief SMBUS Configuration Structure definition + * @brief SMBUS Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization + This parameter calculated by referring to SMBUS initialization section in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. This parameter can be a value of @ref SMBUS_Analog_Filter */ - + uint32_t OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ @@ -99,51 +97,51 @@ typedef struct This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section in Reference manual */ } SMBUS_InitTypeDef; -/** +/** * @} */ /** @defgroup HAL_state_definition HAL state definition - * @brief HAL State definition + * @brief HAL State definition * @{ - */ + */ #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ -/** +/** * @} */ /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition - * @brief SMBUS Error Code definition + * @brief SMBUS Error Code definition * @{ - */ + */ #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ -/** +/** * @} */ -/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition - * @brief SMBUS handle Structure definition +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition + * @brief SMBUS handle Structure definition * @{ */ typedef struct @@ -168,11 +166,11 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ -}SMBUS_HandleTypeDef; +} SMBUS_HandleTypeDef; /** * @} */ - + /** * @} */ @@ -292,12 +290,24 @@ typedef struct * @{ */ +/* List of XferOptions in usage of : + * 1- Restart condition when direction change + * 2- No Restart condition in other use cases + */ #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) -#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) +#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) +#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) +#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) /** * @} */ @@ -328,7 +338,7 @@ typedef struct * Elements values convention: 0xXXXXYYYY * - XXXXXXXX : Flag mask * @{ - */ + */ #define SMBUS_FLAG_TXE I2C_ISR_TXE #define SMBUS_FLAG_TXIS I2C_ISR_TXIS @@ -357,8 +367,8 @@ typedef struct /* Exported macros ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros * @{ - */ - + */ + /** @brief Reset SMBUS handle state. * @param __HANDLE__ specifies the SMBUS Handle. * @retval None @@ -376,7 +386,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) @@ -392,11 +402,11 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified SMBUS interrupt source is enabled or not. * @param __HANDLE__ specifies the SMBUS Handle. * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. @@ -408,7 +418,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) @@ -417,69 +427,69 @@ typedef struct * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag - * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) - * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert * @arg @ref SMBUS_FLAG_BUSY Bus busy * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) - * + * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) - + /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert - * + * * @retval None */ #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - + /** @brief Enable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} - */ - - + */ + + /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -490,6 +500,8 @@ typedef struct #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) +#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) @@ -503,7 +515,7 @@ typedef struct ((MASK) == SMBUS_OA2_MASK04) || \ ((MASK) == SMBUS_OA2_MASK05) || \ ((MASK) == SMBUS_OA2_MASK06) || \ - ((MASK) == SMBUS_OA2_MASK07)) + ((MASK) == SMBUS_OA2_MASK07)) #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ ((CALL) == SMBUS_GENERALCALL_ENABLE)) @@ -521,12 +533,13 @@ typedef struct #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ ((MODE) == SMBUS_AUTOEND_MODE) || \ ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) - - + + #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ ((REQUEST) == SMBUS_GENERATE_START_READ) || \ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ @@ -538,7 +551,13 @@ typedef struct ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ + IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) @@ -560,16 +579,7 @@ typedef struct /** * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup SMBUS_Private_Functions SMBUS Private Functions - * @{ */ -/* Private functions are defined in stm32f0xx_hal_smbus.c file */ -/** - * @} - */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions @@ -579,12 +589,14 @@ typedef struct /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - + /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); /** * @} @@ -593,7 +605,7 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions * @{ */ - + /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling * @{ @@ -640,7 +652,7 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); * @} */ -/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions * @{ */ @@ -654,7 +666,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup SMBUS_Private_Functions SMBUS Private Functions @@ -663,23 +675,19 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /* Private functions are defined in stm32f0xx_hal_smbus.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ - -/** - * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c index d7a4f6b96f..1fc6912ecb 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -60,9 +58,24 @@ (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() [..] - Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, - the following table resume the max SPI frequency reached with data size 8bits/16bits, - according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI + modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the + maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on + the APBx peripheral clock frequency (fPCLK) used by the SPI instance. + + [..] + Data buffer address alignment restriction: + (#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer. + But there is no support for unaligned accesses on the Cortex-M0 processor. + So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for: + (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT() + (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT() + (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA() + and HAL_SPI_TransmitReceive_DMA(). + + @endverbatim + + Additional table : DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ @@ -120,7 +133,6 @@ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - @endverbatim ****************************************************************************** * @attention * @@ -262,7 +274,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -349,7 +361,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, - Communication speed, First bit, CRC calculation state */ + Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); @@ -361,7 +373,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } #endif /* USE_SPI_CRC */ - /* Configure : NSS management, TI Mode and Rx Fifo Threshold */ + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); @@ -387,7 +399,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -421,7 +433,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -437,7 +449,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -490,11 +502,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -502,6 +514,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -561,7 +580,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) { hspi->Instance->DR = *((uint16_t *)pData); pData += sizeof(uint16_t); @@ -591,7 +610,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ else { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) { if (hspi->TxXferCount > 1U) { @@ -669,11 +688,11 @@ error: /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -684,6 +703,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -733,7 +759,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ - /* Set the Rx Fido threshold */ + /* Set the Rx FiFo threshold */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* set fiforxthresold according the reception data length: 16bit */ @@ -899,12 +925,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, @@ -919,6 +945,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD uint32_t txallowed = 1U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -971,8 +1005,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } #endif /* USE_SPI_CRC */ - /* Set the Rx Fido threshold */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) { /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1191,16 +1225,23 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1274,16 +1315,23 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1319,16 +1367,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui hspi->TxXferCount = 0U; hspi->TxISR = NULL; - /* check the data size to adapt Rx threshold and the set the function for IT treatment */ + /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* Set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* Set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } @@ -1378,11 +1426,11 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1390,6 +1438,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1456,15 +1512,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } #endif /* USE_SPI_CRC */ - /* check if packing mode is enabled and if there is more than 2 data to receive */ + /* Check if packing mode is enabled and if there is more than 2 data to receive */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* Set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* Set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1486,16 +1542,19 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + /* check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1555,7 +1614,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, hspi->hdmatx->XferAbortCallback = NULL; CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - /* packing mode is enabled only if the DMA setting is HALWORD */ + /* Packing mode is enabled only if the DMA setting is HALWORD */ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Check the even/odd of the data size + crc if enabled */ @@ -1595,20 +1654,28 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + /* check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } @@ -1656,7 +1723,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u #endif /* USE_SPI_CRC */ #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx) - /* packing mode management is enabled by the DMA settings */ + /* Packing mode management is enabled by the DMA settings */ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Restriction the DMA data received is not allowed in this mode */ @@ -1668,14 +1735,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { /* set fiforxthresold according the reception data length: 16bit */ @@ -1730,12 +1797,12 @@ error: /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, @@ -1744,6 +1811,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + /* check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1802,18 +1873,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } #endif + /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); - /* the packing mode management is enabled by the DMA settings according the spi data size */ + /* The packing mode management is enabled by the DMA settings according the spi data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthreshold according the reception data length: 16bit */ + /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) @@ -1832,7 +1904,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -1918,25 +1990,46 @@ error : HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; + __IO uint32_t count, resetcount; /* Initialized local variable */ errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { hspi->TxISR = SPI_AbortTx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) { hspi->RxISR = SPI_AbortRx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } /* Clear ERRIE interrupts in case of DMA Mode */ @@ -2052,26 +2145,47 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; uint32_t abortcplt ; + __IO uint32_t count, resetcount; /* Initialized local variable */ errorcode = HAL_OK; abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { hspi->TxISR = SPI_AbortTx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) { hspi->RxISR = SPI_AbortRx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } /* Clear ERRIE interrupts in case of DMA Mode */ @@ -2213,7 +2327,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2233,7 +2347,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2253,7 +2367,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) /** * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2284,7 +2398,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2380,7 +2494,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2396,7 +2510,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2412,7 +2526,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2428,7 +2542,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2444,7 +2558,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2460,7 +2574,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2476,7 +2590,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2529,7 +2643,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2541,7 +2655,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2566,7 +2680,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2613,7 +2727,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2704,7 +2818,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2789,7 +2903,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2802,7 +2916,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2815,7 +2929,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2828,7 +2942,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2986,7 +3100,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3036,7 +3150,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3068,7 +3182,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3114,7 +3228,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3148,7 +3262,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3172,7 +3286,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3210,7 +3324,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3235,7 +3349,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3268,7 +3382,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3291,7 +3405,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3324,7 +3438,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3348,7 +3462,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3374,12 +3488,12 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, @@ -3426,12 +3540,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle SPI FIFO Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Fifo: Fifo to check - * @param State: Fifo state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, @@ -3487,10 +3601,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle the check of the RX transaction complete. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3524,9 +3638,9 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t /** * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3537,18 +3651,26 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } return HAL_OK; } /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3605,7 +3727,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3647,7 +3769,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3686,21 +3808,32 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { + __IO uint32_t count; + /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + /* Check RXNEIE is disabled */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) @@ -3719,18 +3852,29 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx/Tx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) { + __IO uint32_t count; + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + /* Check TXEIE is disabled */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h index 109a19e2ee..4c62440bad 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -99,7 +97,7 @@ typedef struct This parameter can be a value of @ref SPI_CRC_Calculation */ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size @@ -253,7 +251,7 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_NSS_SOFT SPI_CR1_SSM #define SPI_NSS_HARD_INPUT (0x00000000U) -#define SPI_NSS_HARD_OUTPUT (0x00040000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) /** * @} */ @@ -271,13 +269,13 @@ typedef struct __SPI_HandleTypeDef * @{ */ #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) -#define SPI_BAUDRATEPRESCALER_4 (0x00000008U) -#define SPI_BAUDRATEPRESCALER_8 (0x00000010U) -#define SPI_BAUDRATEPRESCALER_16 (0x00000018U) -#define SPI_BAUDRATEPRESCALER_32 (0x00000020U) -#define SPI_BAUDRATEPRESCALER_64 (0x00000028U) -#define SPI_BAUDRATEPRESCALER_128 (0x00000030U) -#define SPI_BAUDRATEPRESCALER_256 (0x00000038U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /** * @} */ @@ -368,10 +366,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level * @{ */ -#define SPI_FTLVL_EMPTY (0x00000000U) -#define SPI_FTLVL_QUARTER_FULL (0x00000800U) -#define SPI_FTLVL_HALF_FULL (0x00001000U) -#define SPI_FTLVL_FULL (0x00001800U) +#define SPI_FTLVL_EMPTY (0x00000000U) +#define SPI_FTLVL_QUARTER_FULL (0x00000800U) +#define SPI_FTLVL_HALF_FULL (0x00001000U) +#define SPI_FTLVL_FULL (0x00001800U) /** * @} @@ -380,10 +378,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level * @{ */ -#define SPI_FRLVL_EMPTY (0x00000000U) -#define SPI_FRLVL_QUARTER_FULL (0x00000200U) -#define SPI_FRLVL_HALF_FULL (0x00000400U) -#define SPI_FRLVL_FULL (0x00000600U) +#define SPI_FRLVL_EMPTY (0x00000000U) +#define SPI_FRLVL_QUARTER_FULL (0x00000200U) +#define SPI_FRLVL_HALF_FULL (0x00000400U) +#define SPI_FRLVL_FULL (0x00000600U) /** * @} */ @@ -391,36 +389,47 @@ typedef struct __SPI_HandleTypeDef /** * @} */ - + /* Exported macros -----------------------------------------------------------*/ /** @defgroup SPI_Exported_Macros SPI Exported Macros * @{ */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -/** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -430,9 +439,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -448,27 +457,27 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_modf = 0x00U; \ - tmpreg_modf = (__HANDLE__)->Instance->SR; \ - (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ - UNUSED(tmpreg_modf); \ - } while(0) +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -478,10 +487,10 @@ typedef struct __SPI_HandleTypeDef tmpreg_ovr = (__HANDLE__)->Instance->DR; \ tmpreg_ovr = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_ovr); \ - } while(0) + } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -490,21 +499,21 @@ typedef struct __SPI_HandleTypeDef __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0) + }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** * @} @@ -516,26 +525,26 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ - (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) @@ -600,6 +609,10 @@ typedef struct __SPI_HandleTypeDef #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) +#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL) + +#define IS_SPI_16BIT_ALIGNED_ADDRESS(DATA) (((uint32_t)(DATA) % 2U) == 0U) + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c index 52fe0e2287..2ae2a39ed6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended SPI HAL module driver. * This file provides firmware functions to manage the following * SPI peripheral extended functionalities : @@ -57,7 +55,7 @@ /** @defgroup SPIEx_Private_Constants SPIEx Private Constants * @{ */ -#define SPI_FIFO_SIZE 4U +#define SPI_FIFO_SIZE 4 /** * @} */ @@ -72,8 +70,8 @@ */ /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -91,7 +89,7 @@ /** * @brief Flush the RX fifo. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h index 58632d9538..776447667d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h @@ -1,39 +1,37 @@ /** - ****************************************************************************** - * @file stm32f0xx_hal_spi_ex.h - * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 - * @brief Header file of SPI HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32f0xx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_SPI_EX_H @@ -56,7 +54,7 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/* Exported macros ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SPIEx_Exported_Functions * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c index 7f8980566a..459f3624e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -199,7 +197,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM Base handle + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) @@ -239,7 +237,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM Base peripheral - * @param htim : TIM Base handle + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) @@ -266,7 +264,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -281,7 +279,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Base MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -297,7 +295,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) @@ -320,7 +318,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) @@ -343,7 +341,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) @@ -363,7 +361,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) @@ -382,9 +380,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim : TIM handle - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to peripheral. + * @param htim TIM handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -428,7 +426,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) @@ -477,7 +475,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM Output Compare handle + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) @@ -517,7 +515,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitializes the TIM peripheral - * @param htim : TIM Output Compare handle + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) @@ -544,7 +542,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -559,7 +557,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Output Compare MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -574,8 +572,8 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -606,8 +604,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -638,8 +636,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -704,8 +702,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -770,15 +768,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -889,8 +887,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -984,7 +982,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) @@ -1024,7 +1022,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1051,7 +1049,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1066,7 +1064,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM PWM MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1081,8 +1079,8 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1113,8 +1111,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1148,8 +1146,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1214,8 +1212,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1280,15 +1278,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1399,8 +1397,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1494,7 +1492,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM Input Capture handle + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) @@ -1534,7 +1532,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim : TIM Input Capture handle + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) @@ -1561,7 +1559,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Input Capture MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1576,7 +1574,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Input Capture MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) @@ -1591,8 +1589,8 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1617,8 +1615,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1643,8 +1641,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1702,8 +1700,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1762,15 +1760,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The destination Buffer address. - * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1877,8 +1875,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1966,8 +1964,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM OnePulse handle - * @param OnePulseMode : Select the One pulse mode. + * @param htim TIM OnePulse handle + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. @@ -2017,7 +2015,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitializes the TIM One Pulse - * @param htim : TIM One Pulse handle + * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) @@ -2044,7 +2042,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2059,7 +2057,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM One Pulse MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2074,8 +2072,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2107,8 +2105,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be disable + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2140,8 +2138,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2179,8 +2177,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2242,8 +2240,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim : TIM Encoder Interface handle - * @param sConfig : TIM Encoder Interface configuration structure + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2336,7 +2334,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitializes the TIM Encoder interface - * @param htim : TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2363,7 +2361,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2378,7 +2376,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2393,8 +2391,8 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2435,8 +2433,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2479,8 +2477,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2527,8 +2525,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2578,15 +2576,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 : The destination Buffer address for IC1. - * @param pData2 : The destination Buffer address for IC2. - * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2698,8 +2696,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2765,7 +2763,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) @@ -2921,9 +2919,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim : TIM Output Compare handle - * @param sConfig : TIM Output Compare configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2990,9 +2988,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim : TIM IC handle - * @param sConfig : TIM Input Capture configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3086,9 +3084,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim : TIM handle - * @param sConfig : TIM PWM configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3184,13 +3182,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim : TIM One Pulse handle - * @param sConfig : TIM One Pulse configuration structure - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel : TIM Channels to be enabled + * @param InputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3296,8 +3294,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim : TIM handle - * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3318,7 +3316,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc : TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3327,19 +3325,66 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer : The Buffer address. - * @param BurstLength : DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) + uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -3367,7 +3412,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC1: @@ -3379,7 +3424,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC2: @@ -3391,7 +3436,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC3: @@ -3403,7 +3448,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC4: @@ -3415,7 +3460,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_COM: @@ -3427,7 +3472,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_TRIGGER: @@ -3439,7 +3484,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; default: @@ -3459,8 +3504,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim : TIM handle - * @param BurstRequestSrc : TIM DMA Request sources to disable + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3519,8 +3564,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim : TIM handle - * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3541,7 +3586,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc : TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3550,19 +3595,66 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer : The Buffer address. - * @param BurstLength : DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -3590,7 +3682,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC1: @@ -3602,7 +3694,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC2: @@ -3614,7 +3706,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC3: @@ -3626,7 +3718,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC4: @@ -3638,7 +3730,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_COM: @@ -3650,7 +3742,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_TRIGGER: @@ -3662,7 +3754,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; default: @@ -3683,8 +3775,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim : TIM handle - * @param BurstRequestSrc : TIM DMA Request sources to disable. + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3743,8 +3835,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim : TIM handle - * @param EventSource : specifies the event source. + * @param htim TIM handle + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3785,10 +3877,10 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim : TIM handle - * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel : specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 @@ -3919,8 +4011,8 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C /** * @brief Configures the clock source to be used - * @param htim : TIM handle - * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4089,8 +4181,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim : TIM handle. - * @param TI1_Selection : Indicate whether or not channel 1 is connected to the + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4123,8 +4215,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim : TIM handle. - * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4158,8 +4250,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4194,8 +4286,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, /** * @brief Read the captured value from Capture Compare unit - * @param htim : TIM handle. - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1 : TIM Channel 1 selected * @arg TIM_CHANNEL_2 : TIM Channel 2 selected @@ -4287,7 +4379,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) @@ -4302,7 +4394,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non blocking mode - * @param htim : TIM OC handle + * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) @@ -4316,7 +4408,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Input Capture callback in non blocking mode - * @param htim : TIM IC handle + * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) @@ -4331,7 +4423,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) @@ -4346,7 +4438,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) @@ -4361,7 +4453,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) @@ -4395,7 +4487,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base state - * @param htim : TIM Base handle + * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) @@ -4405,7 +4497,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC state - * @param htim : TIM Ouput Compare handle + * @param htim TIM Ouput Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4415,7 +4507,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM state - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) @@ -4425,7 +4517,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture state - * @param htim : TIM IC handle + * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) @@ -4435,7 +4527,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode state - * @param htim : TIM OPM handle + * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) @@ -4445,7 +4537,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode state - * @param htim : TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4467,7 +4559,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA error callback - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) @@ -4481,7 +4573,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) @@ -4513,7 +4605,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) } /** * @brief TIM DMA Capture complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) @@ -4546,7 +4638,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) @@ -4560,7 +4652,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) @@ -4574,8 +4666,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Base configuration - * @param TIMx : TIM periheral - * @param Structure : TIM Base configuration structure + * @param TIMx TIM periheral + * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4623,7 +4715,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Time Ouput Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4697,7 +4789,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4773,7 +4865,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4847,7 +4939,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -5029,17 +5121,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 @@ -5084,12 +5176,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5119,17 +5211,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 @@ -5167,12 +5259,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5202,17 +5294,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 @@ -5250,17 +5342,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be @@ -5298,7 +5390,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param InputTriggerSource : The Input Trigger source. + * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0 : Internal Trigger 0 * @arg TIM_TS_ITR1 : Internal Trigger 1 @@ -5326,17 +5418,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity : The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter : External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ @@ -5360,13 +5452,13 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel : specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1 : TIM Channel 1 * @arg TIM_CHANNEL_2 : TIM Channel 2 * @arg TIM_CHANNEL_3 : TIM Channel 3 * @arg TIM_CHANNEL_4 : TIM Channel 4 - * @param ChannelState : specifies the TIM Channel CCxE bit new state. + * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h index 88f1edfcb3..410138aee6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -1094,12 +1092,14 @@ typedef struct ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) /** @brief Set TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @param __ICPSC__: specifies the prescaler value. + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __ICPSC__ specifies the prescaler value. * @retval None */ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ @@ -1109,8 +1109,8 @@ typedef struct ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) /** @brief Reset TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel * @retval None */ #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ @@ -1121,9 +1121,9 @@ typedef struct /** @brief Set TIM IC polarity - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @param __POLARITY__: specifies TIM Channel Polarity + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __POLARITY__ specifies TIM Channel Polarity * @retval None */ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ @@ -1133,8 +1133,8 @@ typedef struct ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U))) /** @brief Reset TIM IC polarity - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel * @retval None */ #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ @@ -1168,28 +1168,28 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat */ /** @brief Reset TIM handle state - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -1206,7 +1206,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat channels have been disabled */ /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ @@ -1221,10 +1221,19 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat } \ } while(0) +/* The Main Output Enable of a timer instance is disabled unconditionally */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled uncondiotionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + /** * @brief Enables the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1240,8 +1249,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Disables the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1257,8 +1266,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Enables the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1273,8 +1282,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Disables the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1289,8 +1298,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Checks whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to check. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1310,8 +1319,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Clears the specified TIM interrupt flag. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to clear. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1331,23 +1340,23 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Checks whether the specified TIM interrupt has occurred or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. * @retval The state of TIM_IT (SET or RESET). */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Clear the TIM interrupt pending bits - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** * @brief Indicates whether or not the TIM Counter is used as downcounter - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. @@ -1356,8 +1365,8 @@ mode. /** * @brief Sets the TIM active prescaler register value on update event. - * @param __HANDLE__: TIM handle. - * @param __PRESC__: specifies the active prescaler register new value. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the active prescaler register new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) @@ -1365,14 +1374,14 @@ mode. /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -1380,30 +1389,30 @@ mode. /** * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval None + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) /** * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ ((__HANDLE__)->Instance->CNT) @@ -1411,8 +1420,8 @@ mode. /** * @brief Sets the TIM Autoreload Register value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ @@ -1423,8 +1432,8 @@ mode. /** * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ ((__HANDLE__)->Instance->ARR) @@ -1432,12 +1441,12 @@ mode. /** * @brief Sets the TIM Clock Division value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1 - * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ @@ -1449,16 +1458,19 @@ mode. /** * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Sets the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1474,8 +1486,8 @@ mode. /** * @brief Resets the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1493,14 +1505,14 @@ mode. /** * @brief Sets the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1516,14 +1528,18 @@ mode. /** * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ @@ -1533,7 +1549,7 @@ mode. /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) @@ -1544,7 +1560,7 @@ mode. /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): @@ -1558,14 +1574,14 @@ mode. /** * @brief Sets the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge @@ -1739,9 +1755,13 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c index 12ce47214c..9bf2c75d28 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -153,8 +151,8 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim : TIM Encoder Interface handle - * @param sConfig : TIM Hall Sensor configuration structure + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -233,7 +231,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitializes the TIM Hall Sensor interface - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -260,7 +258,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -275,7 +273,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -290,7 +288,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) @@ -311,7 +309,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) @@ -332,7 +330,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) @@ -356,7 +354,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) @@ -380,9 +378,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM Hall Sensor handle - * @param pData : The destination Buffer address. - * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @param htim TIM Hall Sensor handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -429,7 +427,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) @@ -479,8 +477,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -509,8 +507,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -539,8 +537,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -606,8 +604,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -679,15 +677,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -796,8 +794,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -896,8 +894,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -925,8 +923,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -955,8 +953,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1022,8 +1020,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1095,15 +1093,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1212,8 +1210,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1301,8 +1299,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complemetary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1326,8 +1324,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1355,8 +1353,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1386,8 +1384,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1445,15 +1443,15 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim : TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1494,15 +1492,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim : TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1547,15 +1545,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim : TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1599,8 +1597,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim : TIM handle. - * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1636,8 +1634,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim : TIM handle - * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1686,8 +1684,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM14 Remapping input capabilities. - * @param htim : TIM handle. - * @param Remap : specifies the TIM remapping source. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. * This parameter can be one of the following values: * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock @@ -1725,10 +1723,10 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) defined(STM32F091xC) || defined (STM32F098xx) /** * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 @@ -1890,7 +1888,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /** * @brief Hall commutation changed callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) @@ -1905,7 +1903,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) @@ -1920,7 +1918,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) @@ -1953,7 +1951,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Return the TIM Hall Sensor interface state - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) @@ -1976,12 +1974,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel : specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 - * @param ChannelNState : specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h index 3e614681ae..a504794e8c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c index 493b963f3d..eaf1697a91 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and DeInitialization @@ -153,7 +151,7 @@ static uint32_t TSC_extract_groups(uint32_t iomask); /** * @brief Initializes the TSC peripheral according to the specified parameters * in the TSC_InitTypeDef structure. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) @@ -241,7 +239,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) /** * @brief Deinitializes the TSC peripheral registers to their default reset values. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) @@ -273,7 +271,7 @@ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) /** * @brief Initializes the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -289,7 +287,7 @@ __weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc) /** * @brief DeInitializes the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -327,7 +325,7 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc) /** * @brief Starts the acquisition. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ @@ -370,7 +368,7 @@ HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc) /** * @brief Enables the interrupt and starts the acquisition - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status. */ @@ -424,7 +422,7 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) /** * @brief Stops the acquisition previously launched in polling mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ @@ -457,7 +455,7 @@ HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc) /** * @brief Stops the acquisition previously launched in interrupt mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ @@ -493,9 +491,9 @@ HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc) /** * @brief Gets the acquisition status for a group - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Group status */ TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index) @@ -510,9 +508,9 @@ TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t /** * @brief Gets the acquisition measure for a group - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Acquisition measure */ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) @@ -545,9 +543,9 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) /** * @brief Configures TSC IOs - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param config: pointer to the configuration structure. + * @param config pointer to the configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config) @@ -582,9 +580,9 @@ HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* /** * @brief Discharge TSC IOs - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param choice: enable or disable + * @param choice enable or disable * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) @@ -634,7 +632,7 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) /** * @brief Return the TSC state - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ @@ -670,7 +668,7 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) * @brief Start acquisition and wait until completion * @note There is no need of a timeout parameter as the max count error is already * managed by the TSC peripheral. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ @@ -696,7 +694,7 @@ HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc) /** * @brief Handles TSC interrupt request - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -742,7 +740,7 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /** * @brief Acquisition completed callback in non blocking mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -758,7 +756,7 @@ __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc) /** * @brief Error callback in non blocking mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -786,7 +784,7 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) /** * @brief Utility function used to set the acquired groups mask - * @param iomask: Channels IOs mask + * @param iomask Channels IOs mask * @retval Acquired groups mask */ static uint32_t TSC_extract_groups(uint32_t iomask) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h index 677d1bd721..8972469eb5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains all the functions prototypes for the TSC firmware * library. ****************************************************************************** @@ -439,189 +437,189 @@ typedef struct */ /** @brief Reset TSC handle state - * @param __HANDLE__: TSC handle. + * @param __HANDLE__ TSC handle. * @retval None */ #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) /** * @brief Enable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) /** * @brief Disable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) /** * @brief Start acquisition - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) /** * @brief Stop acquisition - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) /** * @brief Set IO default mode to output push-pull low - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) /** * @brief Set IO default mode to input floating - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) /** * @brief Set synchronization polarity to falling edge - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) /** * @brief Set synchronization polarity to rising edge and high level - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) /** * @brief Enable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** * @brief Disable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) /** @brief Check if the specified TSC interrupt source is enabled or disabled. - * @param __HANDLE__: TSC Handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC Handle + * @param __INTERRUPT__ TSC interrupt * @retval SET or RESET */ #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Get the selected TSC's flag status. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval SET or RESET */ #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** * @brief Clear the TSC's pending flag. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval None */ #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enable schmitt trigger hysteresis on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) /** * @brief Disable schmitt trigger hysteresis on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Open analog switch on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Close analog switch on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) /** * @brief Enable a group of IOs in channel mode - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of channel IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Enable a group of IOs in sampling mode - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of sampling IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Enable acquisition groups - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) /** * @brief Disable acquisition groups - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) /** @brief Gets acquisition group status - * @param __HANDLE__: TSC Handle - * @param __GX_INDEX__: Group index + * @param __HANDLE__ TSC Handle + * @param __GX_INDEX__ Group index * @retval SET or RESET */ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c index b9bed69982..564e2a67d1 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -287,7 +285,7 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); /** * @brief Initialize the UART mode according to the specified * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -366,7 +364,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -439,9 +437,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the multiprocessor mode according to the specified * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. - * @param Address: UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod: specifies the UART wakeup method. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod specifies the UART wakeup method. * This parameter can be one of the following values: * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark @@ -531,7 +529,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief DeInitialize the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -569,7 +567,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief Initialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) @@ -584,7 +582,7 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) /** * @brief DeInitialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) @@ -680,10 +678,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Send an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, @@ -764,10 +762,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @param Timeout Timeout duration. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled using u16 pointer cast). Depending on compilation chain, @@ -851,9 +849,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, @@ -907,9 +905,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled using u16 pointer cast). Depending on compilation chain, @@ -969,9 +967,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, @@ -1044,9 +1042,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, @@ -1121,7 +1119,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pause the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) @@ -1154,7 +1152,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /** * @brief Resume the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) @@ -1188,7 +1186,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /** * @brief Stop the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) @@ -1652,7 +1650,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /** * @brief Handle UART interrupt request. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) @@ -1806,7 +1804,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) @@ -1821,7 +1819,7 @@ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1836,7 +1834,7 @@ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) @@ -1851,7 +1849,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1866,7 +1864,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -1949,7 +1947,7 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) @@ -1970,7 +1968,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) /** * @brief Disable UART mute mode (does not mean the UART actually exits mute mode * as it may not have been in mute mode at this very moment). - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) @@ -1991,7 +1989,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) /** * @brief Enter UART mute mode (means UART actually enters mute mode). * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) @@ -2001,7 +1999,7 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) @@ -2025,7 +2023,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) @@ -2105,7 +2103,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) @@ -2210,7 +2208,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral advanced features. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h index 4731c435de..b6ac309cce 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -408,19 +406,16 @@ typedef struct */ /** @defgroup UART_IT UART IT - * Elements values convention: 000000000XXYYYYYb + * Elements values convention: 0000ZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) * - 01: CR1 register * - 10: CR2 register * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ #define UART_IT_ERR (0x0060U) /*!< UART error interruption */ - -/** Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - */ #define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */ #define UART_IT_NE (0x0200U) /*!< UART noise error interruption */ #define UART_IT_FE (0x0100U) /*!< UART frame error interruption */ @@ -585,7 +580,7 @@ typedef struct */ /** @brief Reset UART handle states. - * @param __HANDLE__: UART handle. + * @param __HANDLE__ UART handle. * @retval None */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -594,8 +589,8 @@ typedef struct } while(0) /** @brief Clear the specified UART pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag @@ -635,38 +630,38 @@ typedef struct #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) /** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) /** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) /** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) /** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -722,8 +717,8 @@ typedef struct #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -757,8 +752,8 @@ typedef struct /** @brief Disable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -791,8 +786,8 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT__ specifies the UART interrupt to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -825,8 +820,8 @@ typedef struct #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt source to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -858,8 +853,8 @@ typedef struct (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK))) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag @@ -900,8 +895,8 @@ typedef struct #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific UART request flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref UART_SENDBREAK_REQUEST Send Break Request @@ -920,25 +915,25 @@ typedef struct #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) /** @brief Enable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -952,7 +947,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ @@ -970,7 +965,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ @@ -988,7 +983,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ @@ -1006,7 +1001,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ @@ -1025,21 +1020,21 @@ typedef struct */ /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check UART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. + * @param __BAUDRATE__ Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) @@ -1047,20 +1042,20 @@ typedef struct #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U) /** @brief Check UART assertion time. - * @param __TIME__: 5-bit value assertion time. + * @param __TIME__ 5-bit value assertion time. * @retval Test result (TRUE or FALSE). */ #define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) /** @brief Check UART deassertion time. - * @param __TIME__: 5-bit value deassertion time. + * @param __TIME__ 5-bit value deassertion time. * @retval Test result (TRUE or FALSE). */ #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) /** * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__: UART frame number of stop bits. + * @param __STOPBITS__ UART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #ifdef USART_SMARTCARD_SUPPORT @@ -1075,7 +1070,7 @@ typedef struct /** * @brief Ensure that UART frame parity is valid. - * @param __PARITY__: UART frame parity. + * @param __PARITY__ UART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ @@ -1084,7 +1079,7 @@ typedef struct /** * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__: UART hardware flow control. + * @param __CONTROL__ UART hardware flow control. * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ @@ -1095,14 +1090,14 @@ typedef struct /** * @brief Ensure that UART communication mode is valid. - * @param __MODE__: UART communication mode. + * @param __MODE__ UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. - * @param __STATE__: UART state. + * @param __STATE__ UART state. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ @@ -1110,7 +1105,7 @@ typedef struct /** * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__: UART oversampling. + * @param __SAMPLING__ UART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) */ #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ @@ -1118,7 +1113,7 @@ typedef struct /** * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__: UART frame sampling. + * @param __ONEBIT__ UART frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ @@ -1126,7 +1121,7 @@ typedef struct /** * @brief Ensure that Address Length detection parameter is valid. - * @param __ADDRESS__: UART Adress length value. + * @param __ADDRESS__ UART Adress length value. * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) */ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ @@ -1134,7 +1129,7 @@ typedef struct /** * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__: UART receiver timeout setting. + * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ @@ -1142,7 +1137,7 @@ typedef struct /** * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__: UART DMA TX state. + * @param __DMATX__ UART DMA TX state. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ @@ -1150,7 +1145,7 @@ typedef struct /** * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__: UART DMA RX state. + * @param __DMARX__ UART DMA RX state. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ @@ -1158,7 +1153,7 @@ typedef struct /** * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__: UART half-duplex state. + * @param __HDSEL__ UART half-duplex state. * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) */ #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ @@ -1166,7 +1161,7 @@ typedef struct /** * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__: UART wake-up method . + * @param __WAKEUP__ UART wake-up method . * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) */ #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ @@ -1174,7 +1169,7 @@ typedef struct /** * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__: UART advanced features initialization. + * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ @@ -1189,7 +1184,7 @@ typedef struct /** * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__: UART frame TX inversion setting. + * @param __TXINV__ UART frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ @@ -1197,7 +1192,7 @@ typedef struct /** * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__: UART frame RX inversion setting. + * @param __RXINV__ UART frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ @@ -1205,7 +1200,7 @@ typedef struct /** * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__: UART frame data inversion setting. + * @param __DATAINV__ UART frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ @@ -1213,7 +1208,7 @@ typedef struct /** * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__: UART frame RX/TX pins swap setting. + * @param __SWAP__ UART frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ @@ -1221,7 +1216,7 @@ typedef struct /** * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__: UART frame overrun setting. + * @param __OVERRUN__ UART frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -1229,7 +1224,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__: UART auto Baud rate state. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ @@ -1237,7 +1232,7 @@ typedef struct /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__: UART DMA enabling or disabling on error setting. + * @param __DMA__ UART DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -1245,7 +1240,7 @@ typedef struct /** * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__: UART frame MSB first setting. + * @param __MSBFIRST__ UART frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -1253,7 +1248,7 @@ typedef struct /** * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__: UART mute mode state. + * @param __MUTE__ UART mute mode state. * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ @@ -1261,7 +1256,7 @@ typedef struct /** * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__: UART driver enable polarity. + * @param __POLARITY__ UART driver enable polarity. * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) */ #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c index 448174330d..d9fcb1f877 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -165,16 +163,16 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. - * @param Polarity: select the driver enable polarity. + * @param huart UART handle. + * @param Polarity select the driver enable polarity. * This parameter can be one of the following values: * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime: Driver Enable assertion time: + * @param AssertionTime Driver Enable assertion time: * 5-bit value defining the time between the activation of the DE (Driver Enable) * signal and the beginning of the start bit. It is expressed in sample time * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime: Driver Enable deassertion time: + * @param DeassertionTime Driver Enable deassertion time: * 5-bit value defining the time between the end of the last stop bit, in a * transmitted message, and the de-activation of the DE (Driver Enable) signal. * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the @@ -249,8 +247,8 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /** * @brief Initialize the LIN mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle. - * @param BreakDetectLength: specifies the LIN break detection length. + * @param huart UART handle. + * @param BreakDetectLength specifies the LIN break detection length. * This parameter can be one of the following values: * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection @@ -349,7 +347,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief UART wakeup from Stop mode callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) @@ -393,8 +391,8 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief Set Wakeup from Stop mode interrupt flag selection. - * @param huart: UART handle. - * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. + * @param huart UART handle. + * @param WakeUpSelection address match, Start Bit detection or RXNE bit status. * This parameter can be one of the following values: * @arg @ref UART_WAKEUP_ON_ADDRESS * @arg @ref UART_WAKEUP_ON_STARTBIT @@ -454,7 +452,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /** * @brief Enable UART Stop Mode. * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) @@ -480,7 +478,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) /** * @brief Disable UART Stop Mode. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) @@ -512,8 +510,8 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) * long). * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart: UART handle. - * @param AddressLength: this parameter can be one of the following values: + * @param huart UART handle. + * @param AddressLength this parameter can be one of the following values: * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status @@ -548,7 +546,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief Transmit break characters. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) @@ -588,8 +586,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart: UART handle. - * @param WakeUpSelection: UART wake up from stop mode parameters. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. * @retval None */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h index 68ef6fdea7..916a98e96a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of UART HAL Extended module. ****************************************************************************** * @attention @@ -283,7 +281,7 @@ typedef struct */ /** @brief Flush the UART Data registers. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #if !defined(STM32F030x6) && !defined(STM32F030x8) @@ -309,8 +307,8 @@ typedef struct */ /** @brief Report the UART clock source. - * @param __HANDLE__: specifies the UART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) @@ -619,7 +617,7 @@ typedef struct * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -693,7 +691,7 @@ typedef struct /** * @brief Ensure that UART frame length is valid. - * @param __LENGTH__: UART frame length. + * @param __LENGTH__ UART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -711,7 +709,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__: UART auto Baud rate detection mode. + * @param __MODE__ UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -732,7 +730,7 @@ typedef struct #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** * @brief Ensure that UART LIN state is valid. - * @param __LIN__: UART LIN state. + * @param __LIN__ UART LIN state. * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) */ #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ @@ -740,7 +738,7 @@ typedef struct /** * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__: UART LIN break detection length. + * @param __LENGTH__ UART LIN break detection length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ @@ -749,7 +747,7 @@ typedef struct /** * @brief Ensure that UART request parameter is valid. - * @param __PARAM__: UART request parameter. + * @param __PARAM__ UART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) @@ -768,7 +766,7 @@ typedef struct #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__: UART stop mode state. + * @param __STOPMODE__ UART stop mode state. * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) */ #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ @@ -776,7 +774,7 @@ typedef struct /** * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__: UART wake-up selection. + * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c index 456ebd97e4..ad262a931c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter @@ -369,7 +367,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief Initialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) @@ -384,7 +382,7 @@ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) /** * @brief DeInitialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) @@ -1108,7 +1106,6 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Enable the USART transmit DMA channel: the transmit channel is used in order to generate in the non-blocking mode the clock to the slave device, this mode isn't a simplex receive mode but a full-duplex receive mode */ - tmp = (uint32_t*)&pRxData; /* Set the USART DMA Tx Complete and Error callback to Null */ husart->hdmatx->XferErrorCallback = NULL; husart->hdmatx->XferHalfCpltCallback = NULL; @@ -1720,7 +1717,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Tx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) @@ -1735,7 +1732,7 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1750,7 +1747,7 @@ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) @@ -1765,7 +1762,7 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1780,7 +1777,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) @@ -1795,7 +1792,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief USART error callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) @@ -1846,7 +1843,7 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) /** * @brief Return the USART handle state. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle state */ @@ -1857,7 +1854,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) /** * @brief Return the USART error code. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle Error Code */ @@ -2014,7 +2011,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMAError(DMA_HandleTypeDef *hdma) @@ -2166,7 +2163,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief Configure the USART peripheral. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) @@ -2244,7 +2241,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /** * @brief Check the USART Idle State. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) @@ -2430,7 +2427,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_TransmitReceive_IT(). - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h index c996457c12..30a6e59d24 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -308,14 +306,14 @@ typedef struct */ /** @brief Reset USART handle state. - * @param __HANDLE__: USART handle. + * @param __HANDLE__ USART handle. * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) /** @brief Check whether the specified USART flag is set or not. - * @param __HANDLE__: specifies the USART Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -341,8 +339,8 @@ typedef struct #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified USART pending flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref USART_CLEAR_PEF * @arg @ref USART_CLEAR_FEF @@ -356,38 +354,38 @@ typedef struct #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the USART PE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) /** @brief Clear the USART FE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) /** @brief Clear the USART NE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) /** @brief Clear the USART ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) /** @brief Clear the USART IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) /** @brief Enable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to enable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -397,13 +395,13 @@ typedef struct * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to disable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -413,14 +411,14 @@ typedef struct * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -435,8 +433,8 @@ typedef struct #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified USART interrupt source is enabled or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -454,8 +452,8 @@ typedef struct /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag @@ -470,8 +468,8 @@ typedef struct #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific USART request flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __REQ__: specifies the request flag to set. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. * This parameter can be one of the following values: * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request @if STM32F030x6 @@ -488,25 +486,25 @@ typedef struct #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -521,7 +519,7 @@ typedef struct */ /** @brief Check USART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. + * @param __BAUDRATE__ Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval Test result (TRUE or FALSE). @@ -530,7 +528,7 @@ typedef struct /** * @brief Ensure that USART frame number of stop bits is valid. - * @param __STOPBITS__: USART frame number of stop bits. + * @param __STOPBITS__ USART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #ifdef USART_SMARTCARD_SUPPORT @@ -545,7 +543,7 @@ typedef struct /** * @brief Ensure that USART frame parity is valid. - * @param __PARITY__: USART frame parity. + * @param __PARITY__ USART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ @@ -554,14 +552,14 @@ typedef struct /** * @brief Ensure that USART communication mode is valid. - * @param __MODE__: USART communication mode. + * @param __MODE__ USART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that USART clock state is valid. - * @param __CLOCK__: USART clock state. + * @param __CLOCK__ USART clock state. * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) */ #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ @@ -569,21 +567,21 @@ typedef struct /** * @brief Ensure that USART frame polarity is valid. - * @param __CPOL__: USART frame polarity. + * @param __CPOL__ USART frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) /** * @brief Ensure that USART frame phase is valid. - * @param __CPHA__: USART frame phase. + * @param __CPHA__ USART frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) /** * @brief Ensure that USART frame last bit clock pulse setting is valid. - * @param __LASTBIT__: USART frame last bit clock pulse setting. + * @param __LASTBIT__ USART frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h index f21d16a29e..942fe1ed4e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of USART HAL Extended module. ****************************************************************************** * @attention @@ -125,7 +123,7 @@ */ /** @brief Flush the USART Data registers. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) @@ -151,8 +149,8 @@ */ /** @brief Report the USART clock source. - * @param __HANDLE__: specifies the USART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) @@ -460,7 +458,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -535,7 +533,7 @@ /** * @brief Ensure that USART frame length is valid. - * @param __LENGTH__: USART frame length. + * @param __LENGTH__ USART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -553,7 +551,7 @@ /** * @brief Ensure that USART request parameter is valid. - * @param __PARAM__: USART request parameter. + * @param __PARAM__ USART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c index 167dc6e2d1..ae48b997b8 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h index 3ceddb8fcf..a164d85390 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -176,7 +174,7 @@ typedef struct /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c index 298efd58dc..7db18a6a21 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_adc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief ADC LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h index 29c9afd5fd..2a7f519587 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_adc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -87,8 +85,8 @@ extern "C" { ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) /* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */ @@ -100,18 +98,18 @@ extern "C" { /* GPIO pins) and internal channels (connected to internal paths) */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ /* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U) +#define ADC_CHANNEL_0_NUMBER (0x00000000U) #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0) #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 ) #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) @@ -161,7 +159,7 @@ extern "C" { /* selection of ADC group (ADC group regular). */ /* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) +#define ADC_AWD_CR1_REGOFFSET (0x00000000U) #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) @@ -174,28 +172,28 @@ extern "C" { /* ADC registers bits positions */ -#define ADC_CFGR1_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */ -#define ADC_CFGR1_AWDSGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */ -#define ADC_TR_HT_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ -#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */ -#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ((uint32_t) 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */ -#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */ -#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */ -#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */ -#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */ -#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */ -#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */ -#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */ -#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ((uint32_t) 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */ -#define ADC_CHSELR_CHSEL10_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */ -#define ADC_CHSELR_CHSEL11_BITOFFSET_POS ((uint32_t)11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */ -#define ADC_CHSELR_CHSEL12_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */ -#define ADC_CHSELR_CHSEL13_BITOFFSET_POS ((uint32_t)13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */ -#define ADC_CHSELR_CHSEL14_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */ -#define ADC_CHSELR_CHSEL15_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */ -#define ADC_CHSELR_CHSEL16_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */ -#define ADC_CHSELR_CHSEL17_BITOFFSET_POS ((uint32_t)17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */ -#define ADC_CHSELR_CHSEL18_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */ +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */ +#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */ /* ADC registers bits groups */ @@ -204,14 +202,14 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ /** @@ -219,19 +217,6 @@ extern "C" { */ -#if defined(USE_FULL_LL_DRIVER) -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Macros ADC Private Macros - * @{ - */ - - -/** - * @} - */ - -#endif - /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure @@ -384,7 +369,7 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ /** * @} */ @@ -397,7 +382,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement pathes all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ #if defined(ADC_CCR_VBATEN) @@ -412,7 +397,7 @@ typedef struct */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ -#define LL_ADC_CLOCK_ASYNC ((uint32_t)0x00000000U) /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */ +#define LL_ADC_CLOCK_ASYNC (0x00000000U) /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */ /** * @} */ @@ -420,7 +405,7 @@ typedef struct /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ -#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */ #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */ #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */ @@ -431,7 +416,7 @@ typedef struct /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ -#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ /** * @} @@ -440,7 +425,7 @@ typedef struct /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ -#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. */ #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ @@ -451,7 +436,7 @@ typedef struct /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ -#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ /** * @} */ @@ -490,7 +475,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ -#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ @@ -513,7 +498,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ -#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} @@ -522,7 +507,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** @@ -532,7 +517,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} @@ -541,7 +526,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD ((uint32_t)0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */ #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */ /** * @} @@ -550,7 +535,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} @@ -559,7 +544,7 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 28.5 ADC clock cycles */ @@ -582,7 +567,7 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ @@ -654,13 +639,13 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ @@ -669,7 +654,7 @@ typedef struct /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2U) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} @@ -821,7 +806,7 @@ typedef struct * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1190,7 +1175,7 @@ typedef struct * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) + (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) /** * @brief Helper macro to convert the ADC conversion data from @@ -1255,7 +1240,7 @@ typedef struct * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -2701,7 +2686,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) @@ -2712,7 +2697,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* data is not shifted. */ MODIFY_REG(ADCx->TR, AWDThresholdsHighLow, - AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U))); + AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U)); } /** @@ -2747,7 +2732,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ /* both thresholds), data is not shifted. */ return (uint32_t)(READ_BIT(ADCx->TR, (AWDThresholdsHighLow | ADC_TR_LT)) - >> ((~AWDThresholdsHighLow) & ((uint32_t)0x00000010U)) + >> ((~AWDThresholdsHighLow) & 0x00000010U) ); } @@ -2896,7 +2881,8 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular. + * without conversion stop command on going on group regular, + * without ADC disable command on going. * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h index fe6afd8390..405915981e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_bus.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of BUS LL module. @verbatim diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c index 2e153104d5..0a4f6f9cbc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_comp.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief COMP LL module driver ****************************************************************************** * @attention @@ -295,7 +293,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /** * @brief Set each @ref LL_COMP_InitTypeDef field to default value. - * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure + * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h index fd0025a443..ceb1a5d82c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_comp.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of COMP LL module. ****************************************************************************** * @attention @@ -716,7 +714,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) * to reach reach propagation delay specification. * Refer to device datasheet, parameter "tSTART". * @rmtoll CSR COMP1EN LL_COMP_Enable\n - * COMP2EN LL_COMP_Enable + * CSR COMP2EN LL_COMP_Enable * @param COMPx Comparator instance * @retval None */ @@ -728,7 +726,7 @@ __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx) /** * @brief Disable comparator instance. * @rmtoll CSR COMP1EN LL_COMP_Disable\n - * COMP2EN LL_COMP_Disable + * CSR COMP2EN LL_COMP_Disable * @param COMPx Comparator instance * @retval None */ @@ -741,7 +739,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @brief Get comparator enable state * (0: COMP is disabled, 1: COMP is enabled) * @rmtoll CSR COMP1EN LL_COMP_IsEnabled\n - * COMP2EN LL_COMP_IsEnabled + * CSR COMP2EN LL_COMP_IsEnabled * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ @@ -755,7 +753,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) * @note Once locked, comparator configuration can be accessed in read-only. * @note The only way to unlock the comparator is a device hardware reset. * @rmtoll CSR COMP1LOCK LL_COMP_Lock\n - * COMP2LOCK LL_COMP_Lock + * CSR COMP2LOCK LL_COMP_Lock * @param COMPx Comparator instance * @retval None */ @@ -770,7 +768,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @note Once locked, comparator configuration can be accessed in read-only. * @note The only way to unlock the comparator is a device hardware reset. * @rmtoll CSR COMP1LOCK LL_COMP_IsLocked\n - * COMP2LOCK LL_COMP_IsLocked + * CSR COMP2LOCK LL_COMP_IsLocked * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ @@ -794,7 +792,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * - Comparator output is low when the input plus * is at a higher voltage than the input minus * @rmtoll CSR COMP1OUT LL_COMP_ReadOutputLevel\n - * COMP2OUT LL_COMP_ReadOutputLevel + * CSR COMP2OUT LL_COMP_ReadOutputLevel * @param COMPx Comparator instance * @retval Returned value can be one of the following values: * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h index 2d7818c034..4044db1d1e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_cortex.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of CORTEX LL module. @verbatim ============================================================================== @@ -83,8 +81,8 @@ extern "C" { /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source * @{ */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c index 43eddd6a23..c634603c65 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief CRC LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h index f32740975f..949201e135 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of CRC LL module. ****************************************************************************** * @attention @@ -71,7 +69,7 @@ extern "C" { /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length * @{ */ -#define LL_CRC_POLYLENGTH_32B (uint32_t)0x00000000U /*!< 32 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ #define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ #define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ #define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ @@ -83,7 +81,7 @@ extern "C" { /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse * @{ */ -#define LL_CRC_INDATA_REVERSE_NONE (uint32_t)0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ #define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ #define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ #define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ @@ -94,7 +92,7 @@ extern "C" { /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse * @{ */ -#define LL_CRC_OUTDATA_REVERSE_NONE (uint32_t)0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ #define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ /** * @} @@ -106,7 +104,7 @@ extern "C" { * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . * @{ */ -#define LL_CRC_DEFAULT_CRC32_POLY (uint32_t)0x04C11DB7U /*!< Default CRC generating polynomial value */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ /** * @} */ @@ -115,7 +113,7 @@ extern "C" { /** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value * @{ */ -#define LL_CRC_DEFAULT_CRC_INITVALUE (uint32_t)0xFFFFFFFFU /*!< Default CRC computation initialization value */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c index ed454370c3..845f94e4dd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crs.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief CRS LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h index a5ee1bdc71..4f154c142b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crs.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of CRS LL module. ****************************************************************************** * @attention @@ -58,23 +56,7 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ -/** @defgroup CRS_LL_Private_Constants CRS Private Constants - * @{ - */ - -/* Defines used for the bit position in the register and perform offsets*/ -#define CRS_POSITION_TRIM (uint32_t)8U /* bit position in CR reg */ -#define CRS_POSITION_FECAP (uint32_t)16U /* bit position in ISR reg */ -#define CRS_POSITION_RELOAD (uint32_t)0U /* bit position in CFGR reg */ -#define CRS_POSITION_FELIM (uint32_t)16U /* bit position in CFGR reg */ - - -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ @@ -317,7 +299,7 @@ __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) */ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) { - MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM); + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); } /** @@ -327,7 +309,7 @@ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) */ __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) { - return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM); + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); } /** @@ -362,7 +344,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) */ __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) { - MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); } /** @@ -372,7 +354,7 @@ __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) */ __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) { - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM); + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); } /** @@ -484,10 +466,10 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) */ __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) { - MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, - ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings); + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); } /** @@ -528,7 +510,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) */ __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) { - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP); + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c index c3636ff345..b4596d1c19 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dac.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief DAC LL module driver ****************************************************************************** * @attention @@ -40,7 +38,7 @@ #include "stm32f0xx_ll_dac.h" #include "stm32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h index 67b02d2001..9e060fb71c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dac.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -70,8 +68,8 @@ extern "C" { /* - channel bits position into register SWTRIG */ /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ -#define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ -#define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ @@ -82,43 +80,43 @@ extern "C" { #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ -#define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U) -#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U) -#define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U) +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) -#define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */ +#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) #else #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_REGOFFSET_MASK_POSBIT0 ((uint32_t)0x0000000FU) /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */ +#define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */ -#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS ((uint32_t)16U) /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ -#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS ((uint32_t)20U) /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS ((uint32_t)24U) /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS ((uint32_t)28U) /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */ /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ -#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ -#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ #endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ +#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ /** * @} @@ -238,7 +236,7 @@ typedef struct #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ @@ -249,7 +247,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode * @{ */ -#define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ /** @@ -259,7 +257,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits * @{ */ -#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ @@ -278,7 +276,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude * @{ */ -#define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ @@ -297,7 +295,7 @@ typedef struct /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer * @{ */ -#define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ /** * @} @@ -307,8 +305,8 @@ typedef struct /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ -#define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */ -#define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */ +#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ /** * @} */ @@ -346,7 +344,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ -#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ @@ -359,7 +357,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 12U) /*!< Delay for DAC channel voltage settling time */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ /** * @} */ @@ -479,7 +477,7 @@ typedef struct * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U)) + ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) /** * @brief Helper macro to calculate the DAC conversion data (unit: digital diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c index 376e824029..ac2a89c3a3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dma.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief DMA LL module driver. ****************************************************************************** * @attention @@ -83,7 +81,7 @@ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) -#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ @@ -359,7 +357,7 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) /*--------------------------- DMAx CSELR Configuration ----------------------- - * Configure the peripheral base address with parameter : + * Configure the DMA request for DMA instance on Channel x with parameter : * - PeriphRequest: DMA_CSELR[31:0] bits */ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); @@ -376,15 +374,15 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) { /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; - DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct->NbData = (uint32_t)0x00000000U; + DMA_InitStruct->NbData = 0x00000000U; #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h index 09a2851d5e..9d9eb976a6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dma.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of DMA LL module. ****************************************************************************** * @attention @@ -280,19 +278,19 @@ typedef struct /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ -#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ #if defined(DMA1_Channel6) -#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ #endif #if defined(DMA1_Channel7) -#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ #endif #if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} @@ -301,7 +299,7 @@ typedef struct /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction * @{ */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** @@ -311,7 +309,7 @@ typedef struct /** @defgroup DMA_LL_EC_MODE Transfer mode * @{ */ -#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ /** * @} @@ -321,7 +319,7 @@ typedef struct * @{ */ #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ @@ -330,7 +328,7 @@ typedef struct * @{ */ #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ @@ -338,7 +336,7 @@ typedef struct /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment * @{ */ -#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** @@ -348,7 +346,7 @@ typedef struct /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment * @{ */ -#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** @@ -358,7 +356,7 @@ typedef struct /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level * @{ */ -#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ @@ -370,22 +368,22 @@ typedef struct /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request * @{ */ -#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */ -#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */ -#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */ -#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */ -#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */ -#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */ -#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */ -#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */ -#define LL_DMA_REQUEST_8 ((uint32_t)0x00000008U) /*!< DMA peripheral request 8 */ -#define LL_DMA_REQUEST_9 ((uint32_t)0x00000009U) /*!< DMA peripheral request 9 */ -#define LL_DMA_REQUEST_10 ((uint32_t)0x0000000AU) /*!< DMA peripheral request 10 */ -#define LL_DMA_REQUEST_11 ((uint32_t)0x0000000BU) /*!< DMA peripheral request 11 */ -#define LL_DMA_REQUEST_12 ((uint32_t)0x0000000CU) /*!< DMA peripheral request 12 */ -#define LL_DMA_REQUEST_13 ((uint32_t)0x0000000DU) /*!< DMA peripheral request 13 */ -#define LL_DMA_REQUEST_14 ((uint32_t)0x0000000EU) /*!< DMA peripheral request 14 */ -#define LL_DMA_REQUEST_15 ((uint32_t)0x0000000FU) /*!< DMA peripheral request 15 */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ +#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ +#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ +#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ +#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ +#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ +#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ +#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ /** * @} */ @@ -1054,7 +1052,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe /** * @brief Configure the Source and Destination addresses. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr) + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance @@ -1080,24 +1079,21 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - SrcAddress); - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); } /* Direction Periph to Memory and Memory to Memory */ else { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - SrcAddress); - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); } } /** * @brief Set the Memory address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetMemoryAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1113,13 +1109,13 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** * @brief Set the Peripheral address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetPeriphAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1135,8 +1131,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - PeriphAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); } /** @@ -1156,8 +1151,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, - DMA_CMAR_MA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } /** @@ -1177,13 +1171,13 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, - DMA_CPAR_PA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** * @brief Set the Memory to Memory Source address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1199,13 +1193,13 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); } /** * @brief Set the Memory to Memory Destination address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1221,8 +1215,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** @@ -1242,8 +1235,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, - DMA_CPAR_PA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** @@ -1263,8 +1255,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, - DMA_CMAR_MA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) @@ -1695,7 +1686,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } /** @@ -1706,7 +1697,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } /** @@ -1717,7 +1708,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } /** @@ -1728,7 +1719,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } /** @@ -1739,7 +1730,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } #if defined(DMA1_Channel6) @@ -1751,7 +1742,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } #endif @@ -1764,7 +1755,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } #endif @@ -1776,7 +1767,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } /** @@ -1787,7 +1778,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } /** @@ -1798,7 +1789,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } /** @@ -1809,7 +1800,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } /** @@ -1820,7 +1811,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } #if defined(DMA1_Channel6) @@ -1832,7 +1823,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } #endif @@ -1845,7 +1836,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } #endif @@ -1857,7 +1848,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } /** @@ -1868,7 +1859,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } /** @@ -1879,7 +1870,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } /** @@ -1890,7 +1881,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } /** @@ -1901,7 +1892,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } #if defined(DMA1_Channel6) @@ -1913,7 +1904,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } #endif @@ -1926,7 +1917,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } #endif @@ -1938,7 +1929,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } /** @@ -1949,7 +1940,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } /** @@ -1960,7 +1951,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } /** @@ -1971,7 +1962,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } /** @@ -1982,7 +1973,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } #if defined(DMA1_Channel6) @@ -1994,7 +1985,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } #endif @@ -2007,7 +1998,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c index 39cc36eaf0..d9e42531ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_exti.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief EXTI LL module driver. ****************************************************************************** * @attention @@ -115,7 +113,7 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FTSR, 0x00000000U); /* Software interrupt event register set to default reset values */ LL_EXTI_WriteReg(SWIER, 0x00000000U); - /* Pending register set to default reset values */ + /* Pending register clear */ LL_EXTI_WriteReg(PR, 0x007BFFFFU); return SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h index a80702ae60..647409c673 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_exti.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention @@ -122,7 +120,9 @@ typedef struct #define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ #endif #define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) #define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif #define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ #if defined(EXTI_IMR_IM20) #define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ @@ -161,10 +161,10 @@ typedef struct #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ -#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ #if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ #endif /*USE_FULL_LL_DRIVER*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c index 6f2f937b66..3fae50cc9a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_gpio.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief GPIO LL module driver. ****************************************************************************** * @attention @@ -62,7 +60,7 @@ /** @addtogroup GPIO_LL_Private_Macros * @{ */ -#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ @@ -74,8 +72,7 @@ #define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) #define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ ((__VALUE__) == LL_GPIO_PULL_UP) ||\ @@ -166,7 +163,7 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -243,7 +240,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -280,4 +277,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h index 0930221fe3..2782b069a9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_gpio.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention @@ -152,7 +150,7 @@ typedef struct /** @defgroup GPIO_LL_EC_MODE Mode * @{ */ -#define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ @@ -163,7 +161,7 @@ typedef struct /** @defgroup GPIO_LL_EC_OUTPUT Output Type * @{ */ -#define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ /** * @} @@ -172,23 +170,20 @@ typedef struct /** @defgroup GPIO_LL_EC_SPEED Output Speed * @{ */ -#define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0_1 /*!< Select I/O fast output speed */ -#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ /** * @} */ #define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW #define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM -#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH -#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH - +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down * @{ */ -#define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ /** @@ -198,14 +193,14 @@ typedef struct /** @defgroup GPIO_LL_EC_AF Alternate Function * @{ */ -#define LL_GPIO_AF_0 ((uint32_t)0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 ((uint32_t)0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 ((uint32_t)0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 ((uint32_t)0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 ((uint32_t)0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 ((uint32_t)0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 ((uint32_t)0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 ((uint32_t)0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ /** * @} */ @@ -422,7 +417,6 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t * @arg @ref LL_GPIO_SPEED_FREQ_LOW * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) @@ -459,7 +453,6 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_LOW * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) { @@ -559,7 +552,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0), + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), ((((Pin * Pin) * Pin) * Pin) * Alternate)); } @@ -589,7 +582,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], - ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0)) / (((Pin * Pin) * Pin) * Pin)); + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); } /** @@ -620,7 +613,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0), + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); } @@ -651,7 +644,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0)) / ((((Pin >> 8U) * + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c index 754d8e72c2..5d886404a0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_i2c.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief I2C LL module driver. ****************************************************************************** * @attention @@ -73,7 +71,7 @@ #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) -#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= (uint32_t)0x000003FFU) +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ ((__VALUE__) == LL_I2C_NACK)) @@ -184,7 +182,12 @@ uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) */ LL_I2C_DisableOwnAddress1(I2Cx); LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); - LL_I2C_EnableOwnAddress1(I2Cx); + + /* OwnAdress1 == 0 is reserved for General Call address */ + if (I2C_InitStruct->OwnAddress1 != 0U) + { + LL_I2C_EnableOwnAddress1(I2Cx); + } /*---------------------------- I2Cx MODE Configuration ----------------------- * Configure I2Cx peripheral mode with parameter : diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h index c1b5cb8aae..fbe9e01fc1 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_i2c.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of I2C LL module. ****************************************************************************** * @attention @@ -63,16 +61,6 @@ extern "C" { /** @defgroup I2C_LL_Private_Constants I2C Private Constants * @{ */ -/* Defines used for the bit position in the register and perform offsets */ -#define I2C_POSITION_CR1_DNF (uint32_t)8U -#define I2C_POSITION_CR2_NBYTES (uint32_t)16U -#define I2C_POSITION_TIMINGR_PRESC (uint32_t)28U -#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)20U -#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)16U -#define I2C_POSITION_TIMINGR_SCLH (uint32_t)8U -#define I2C_POSITION_TIMINGR_SCLL (uint32_t)0U -#define I2C_POSITION_ISR_ADDCODE (uint32_t)17U -#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)16U /** * @} */ @@ -198,9 +186,9 @@ typedef struct /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode * @{ */ -#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ /** * @} @@ -209,7 +197,7 @@ typedef struct /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection * @{ */ -#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ /** * @} @@ -218,7 +206,7 @@ typedef struct /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode * @{ */ -#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ /** * @} @@ -227,7 +215,7 @@ typedef struct /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length * @{ */ -#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ /** * @} @@ -251,7 +239,7 @@ typedef struct /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation * @{ */ -#define LL_I2C_ACK ((uint32_t) 0x00000000U) /*!< ACK is sent after current received byte. */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ /** * @} @@ -260,7 +248,7 @@ typedef struct /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length * @{ */ -#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ /** * @} @@ -269,7 +257,7 @@ typedef struct /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction * @{ */ -#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ /** * @} @@ -280,7 +268,7 @@ typedef struct */ #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /*!< Enable I2C Software end mode with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ @@ -293,7 +281,7 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ #define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */ #define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ #define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */ @@ -308,7 +296,7 @@ typedef struct /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /*!< Write transfer request by master, slave enters receiver mode. */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ /** * @} @@ -317,8 +305,8 @@ typedef struct /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /*!< Get address of data register used for transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /*!< Get address of data register used for reception */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ @@ -326,7 +314,7 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /*!< TimeoutA is used to detect SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ /** * @} @@ -388,11 +376,11 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_POSITION_TIMINGR_PRESC) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_POSITION_TIMINGR_SCLL) & I2C_TIMINGR_SCLL)) + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -463,7 +451,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) { - MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_POSITION_CR1_DNF)); + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); } /** @@ -479,7 +467,7 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt */ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) { - MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF); + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); } /** @@ -490,7 +478,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital */ __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF); + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } /** @@ -922,7 +910,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) */ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } /** @@ -933,7 +921,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } /** @@ -944,7 +932,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } /** @@ -955,7 +943,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } /** @@ -966,7 +954,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } /** @@ -1114,7 +1102,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo uint32_t TimeoutB) { MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, - TimeoutA | TimeoutAMode | (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB)); + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); } /** @@ -1189,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) { - WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB); + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); } /** @@ -1202,7 +1190,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout */ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB); + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } /** @@ -1938,7 +1926,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES); + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); } /** @@ -1949,7 +1937,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer */ __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES); + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } /** @@ -2122,7 +2110,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr { MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | TransferSize << I2C_POSITION_CR2_NBYTES | EndMode | Request); + SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); } /** @@ -2148,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1); + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h index 21a111bd58..7a2086e76d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_iwdg.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention @@ -64,10 +62,10 @@ extern "C" { * @{ */ -#define LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU) /*!< IWDG Reload Counter Enable */ -#define LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU) /*!< IWDG Peripheral Enable */ -#define LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U) /*!< IWDG KR Write Access Enable */ -#define LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U) /*!< IWDG KR Write Access Disable */ +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ /** * @} @@ -96,7 +94,7 @@ extern "C" { /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider * @{ */ -#define LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U) /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c index 14df679af9..b4bf66509a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_pwr.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief PWR LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h index 64b314504f..3a6449d8cb 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_pwr.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of PWR LL module. ****************************************************************************** * @attention @@ -58,11 +56,8 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ - /* Private macros ------------------------------------------------------------*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants @@ -85,30 +80,30 @@ extern "C" { */ #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ -#endif -#if defined (PWR_CSR_VREFINTRDYF) +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ -#endif +#endif /* PWR_CSR_VREFINTRDYF */ #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ -#if defined (PWR_CSR_EWUP3) +#if defined(PWR_CSR_EWUP3) #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ #endif /* PWR_CSR_EWUP3 */ -#if defined (PWR_CSR_EWUP4) +#if defined(PWR_CSR_EWUP4) #define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ #endif /* PWR_CSR_EWUP4 */ -#if defined (PWR_CSR_EWUP5) +#if defined(PWR_CSR_EWUP5) #define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ #endif /* PWR_CSR_EWUP5 */ -#if defined (PWR_CSR_EWUP6) +#if defined(PWR_CSR_EWUP6) #define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ #endif /* PWR_CSR_EWUP6 */ -#if defined (PWR_CSR_EWUP7) +#if defined(PWR_CSR_EWUP7) #define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ #endif /* PWR_CSR_EWUP7 */ -#if defined (PWR_CSR_EWUP8) +#if defined(PWR_CSR_EWUP8) #define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ #endif /* PWR_CSR_EWUP8 */ /** @@ -119,9 +114,9 @@ extern "C" { /** @defgroup PWR_LL_EC_MODE_PWR Mode Power * @{ */ -#define LL_PWR_MODE_STOP_MAINREGU ((uint32_t)0x00000000U) /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ /** * @} */ @@ -130,14 +125,14 @@ extern "C" { /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode * @{ */ -#define LL_PWR_REGU_DSMODE_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ /** - * @} - */ + * @} + */ #endif /* PWR_CR_LPDS */ -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level * @{ */ @@ -152,29 +147,28 @@ extern "C" { /** * @} */ -#endif - +#endif /* PWR_PVD_SUPPORT */ /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins -* @{ -*/ + * @{ + */ #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ -#if defined (PWR_CSR_EWUP3) +#if defined(PWR_CSR_EWUP3) #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ #endif /* PWR_CSR_EWUP3 */ -#if defined (PWR_CSR_EWUP4) +#if defined(PWR_CSR_EWUP4) #define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ #endif /* PWR_CSR_EWUP4 */ -#if defined (PWR_CSR_EWUP5) +#if defined(PWR_CSR_EWUP5) #define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ #endif /* PWR_CSR_EWUP5 */ -#if defined (PWR_CSR_EWUP6) +#if defined(PWR_CSR_EWUP6) #define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ #endif /* PWR_CSR_EWUP6 */ -#if defined (PWR_CSR_EWUP7) +#if defined(PWR_CSR_EWUP7) #define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ #endif /* PWR_CSR_EWUP7 */ -#if defined (PWR_CSR_EWUP8) +#if defined(PWR_CSR_EWUP8) #define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ #endif /* PWR_CSR_EWUP8 */ /** @@ -217,7 +211,6 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions * @{ @@ -227,7 +220,6 @@ extern "C" { * @{ */ - /** * @brief Enable access to the backup domain * @rmtoll CR DBP LL_PWR_EnableBkUpAccess @@ -260,7 +252,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) #if defined(PWR_CR_LPDS) /** - * @brief Set voltage regulator mode during deep sleep mode + * @brief Set voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_SetRegulModeDS * @param RegulMode This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN @@ -273,7 +265,7 @@ __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) } /** - * @brief Get voltage regulator mode during deep sleep mode + * @brief Get voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_GetRegulModeDS * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN @@ -286,9 +278,9 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) #endif /* PWR_CR_LPDS */ /** - * @brief Set power down mode when CPU enters deepsleep + * @brief Set Power Down mode when CPU enters deepsleep * @rmtoll CR PDDS LL_PWR_SetPowerMode\n - * CR LPDS LL_PWR_SetPowerMode + * @rmtoll CR LPDS LL_PWR_SetPowerMode * @param PDMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU @@ -301,9 +293,9 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) } /** - * @brief Get power down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_GetPowerMode - * CR LPDS LL_PWR_SetPowerMode + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU @@ -314,7 +306,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); } -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** * @brief Configure the voltage threshold detected by the Power Voltage Detector * @rmtoll CR PLS LL_PWR_SetPVDLevel @@ -381,13 +373,18 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) { return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); } -#endif +#endif /* PWR_PVD_SUPPORT */ /** * @brief Enable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n - * CSR EWUP2 LL_PWR_EnableWakeUpPin\n - * CSR EWUP3 LL_PWR_EnableWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -409,8 +406,13 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) /** * @brief Disable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n - * CSR EWUP2 LL_PWR_DisableWakeUpPin\n - * CSR EWUP3 LL_PWR_DisableWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -432,8 +434,13 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) /** * @brief Check if the WakeUp PINx functionality is enabled * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n - * CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n - * CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -452,6 +459,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); } + /** * @} */ @@ -480,7 +488,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); } -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** * @brief Indicate whether VDD voltage is below the selected PVD threshold * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO @@ -490,9 +498,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) { return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); } -#endif +#endif /* PWR_PVD_SUPPORT */ -#if defined (PWR_CSR_VREFINTRDYF) +#if defined(PWR_CSR_VREFINTRDYF) /** * @brief Get Internal Reference VrefInt Flag * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY @@ -502,10 +510,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) { return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); } -#endif - - - +#endif /* PWR_CSR_VREFINTRDYF */ /** * @brief Clear Standby Flag * @rmtoll CR CSBF LL_PWR_ClearFlag_SB @@ -526,6 +531,9 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) SET_BIT(PWR->CR, PWR_CR_CWUF); } +/** + * @} + */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function @@ -545,10 +553,6 @@ ErrorStatus LL_PWR_DeInit(void); * @} */ -/** - * @} - */ - #endif /* defined(PWR) */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c index 83058763f3..6a244fdd50 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rcc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief RCC LL module driver. ****************************************************************************** * @attention @@ -148,7 +146,7 @@ ErrorStatus LL_RCC_DeInit(void) /* Reset HSEBYP bit */ LL_RCC_HSE_DisableBypass(); - + /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); @@ -499,6 +497,12 @@ uint32_t RCC_GetSystemClockFreq(void) frequency = RCC_PLL_GetFreqDomain_SYS(); break; +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ + frequency = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + default: frequency = HSI_VALUE; break; @@ -548,15 +552,15 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) pllinputfreq = HSI_VALUE; #else case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE / 2; + pllinputfreq = HSI_VALUE / 2U; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; -#if defined(RCC_CFGR_SW_HSI48) +#if defined(RCC_HSI48_SUPPORT) case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ pllinputfreq = HSI48_VALUE; break; -#endif /* RCC_CFGR_SW_HSI48 */ +#endif /* RCC_HSI48_SUPPORT */ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllinputfreq = HSE_VALUE; @@ -566,7 +570,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) pllinputfreq = HSI_VALUE; #else - pllinputfreq = HSI_VALUE / 2; + pllinputfreq = HSI_VALUE / 2U; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h index 974329afb5..50bba6b2b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rcc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of RCC LL module. ****************************************************************************** * @attention @@ -58,14 +56,6 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_LL_Private_Constants RCC Private Constants * @{ @@ -139,24 +129,24 @@ typedef struct * @{ */ #if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */ +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ #endif /* HSI_VALUE */ #if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ #if defined(RCC_HSI48_SUPPORT) #if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */ +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ #endif /* RCC_HSI48_SUPPORT */ /** @@ -333,8 +323,8 @@ typedef struct /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency * @{ */ -#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ /** * @} */ @@ -445,7 +435,7 @@ typedef struct /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ -#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ @@ -571,7 +561,7 @@ typedef struct * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() * , @ref LL_RCC_PLL_GetPrediv()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) - * @param __PLLMUL__: This parameter can be one of the following values: + * @param __PLLMUL__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 @@ -587,7 +577,7 @@ typedef struct * @arg @ref LL_RCC_PLL_MUL_14 * @arg @ref LL_RCC_PLL_MUL_15 * @arg @ref LL_RCC_PLL_MUL_16 - * @param __PLLPREDIV__: This parameter can be one of the following values: + * @param __PLLPREDIV__ This parameter can be one of the following values: * @arg @ref LL_RCC_PREDIV_DIV_1 * @arg @ref LL_RCC_PREDIV_DIV_2 * @arg @ref LL_RCC_PREDIV_DIV_3 @@ -614,7 +604,7 @@ typedef struct * @brief Helper macro to calculate the PLLCLK frequency * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) - * @param __PLLMUL__: This parameter can be one of the following values: + * @param __PLLMUL__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 @@ -640,7 +630,7 @@ typedef struct * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__: This parameter can be one of the following values: + * @param __AHBPRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 @@ -652,14 +642,14 @@ typedef struct * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval HCLK clock frequency (in Hz) */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) /** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__: This parameter can be one of the following values: + * @param __APB1PRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 @@ -667,7 +657,7 @@ typedef struct * @arg @ref LL_RCC_APB1_DIV_16 * @retval PCLK1 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) /** * @} @@ -804,7 +794,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) { - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL); + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); } /** @@ -818,7 +808,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) */ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) { - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM); + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); } /** @@ -828,7 +818,7 @@ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) { - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM); + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c index e3feddb32d..6c1ba8e075 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rtc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief RTC LL module driver. ****************************************************************************** * @attention @@ -62,12 +60,12 @@ * @{ */ /* Default values used for prescaler */ -#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU) -#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU) +#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU +#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU /* Values used for timeout */ -#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ -#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */ /** * @} */ @@ -80,9 +78,9 @@ #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) -#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FU) +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) -#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FFFU) +#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ || ((__VALUE__) == LL_RTC_FORMAT_BCD)) @@ -103,7 +101,7 @@ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) -#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U)) +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ @@ -369,7 +367,7 @@ void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) * @param RTC_Format This parameter can be one of the following values: * @arg @ref LL_RTC_FORMAT_BIN * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Day register is configured diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h index 710e92af16..b7cfbe6f49 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rtc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of RTC LL module. ****************************************************************************** * @attention @@ -63,49 +61,20 @@ extern "C" { * @{ */ /* Masks Definition */ -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU /* Write protection defines */ #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU) #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U) -/* Defines used for the bit position in the register and perform offsets */ -#define RTC_POSITION_TR_HT (uint32_t)20U -#define RTC_POSITION_TR_HU (uint32_t)16U -#define RTC_POSITION_TR_MT (uint32_t)12U -#define RTC_POSITION_TR_MU (uint32_t)8U -#define RTC_POSITION_TR_ST (uint32_t)4U -#define RTC_POSITION_TR_SU (uint32_t)0U -#define RTC_POSITION_DR_YT (uint32_t)20U -#define RTC_POSITION_DR_YU (uint32_t)16U -#define RTC_POSITION_DR_MT (uint32_t)12U -#define RTC_POSITION_DR_MU (uint32_t)8U -#define RTC_POSITION_DR_DT (uint32_t)4U -#define RTC_POSITION_DR_DU (uint32_t)0U -#define RTC_POSITION_DR_WDU (uint32_t)13U -#define RTC_POSITION_ALMA_DT (uint32_t)28U -#define RTC_POSITION_ALMA_DU (uint32_t)24U -#define RTC_POSITION_ALMA_HT (uint32_t)20U -#define RTC_POSITION_ALMA_HU (uint32_t)16U -#define RTC_POSITION_ALMA_MT (uint32_t)12U -#define RTC_POSITION_ALMA_MU (uint32_t)8U -#define RTC_POSITION_ALMA_SU (uint32_t)0U -#define RTC_POSITION_ALMA_ST (uint32_t)4U -#define RTC_POSITION_PRER_PREDIV_A (uint32_t)16U -#define RTC_POSITION_ALMA_MASKSS (uint32_t)24U -#define RTC_POSITION_TS_HU (uint32_t)16U -#define RTC_POSITION_TS_MNU (uint32_t)8U -#define RTC_POSITION_TS_WDU (uint32_t)13U -#define RTC_POSITION_TS_MU (uint32_t)8U - /* Defines used to combine date & time */ -#define RTC_OFFSET_WEEKDAY (uint32_t)24U -#define RTC_OFFSET_DAY (uint32_t)16U -#define RTC_OFFSET_MONTH (uint32_t)8U -#define RTC_OFFSET_HOUR (uint32_t)16U -#define RTC_OFFSET_MINUTE (uint32_t)8U +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U /** * @} @@ -248,8 +217,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN ((uint32_t)0x000000000U) /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD ((uint32_t)0x000000001U) /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ /** * @} */ @@ -257,7 +226,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay * @{ */ -#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ /** * @} @@ -335,7 +304,7 @@ typedef struct /** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT * @{ */ -#define LL_RTC_HOURFORMAT_24HOUR (uint32_t)0x00000000U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ #define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ /** * @} @@ -344,7 +313,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT * @{ */ -#define LL_RTC_ALARMOUT_DISABLE ((uint32_t)0x00000000U) /*!< Output disabled */ +#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ #define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ #define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ #define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ @@ -355,7 +324,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN (uint32_t)0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ /** * @} @@ -374,7 +343,7 @@ typedef struct /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN * @{ */ -#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ #define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ /** * @} @@ -383,7 +352,7 @@ typedef struct /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT * @{ */ -#define LL_RTC_TIME_FORMAT_AM_OR_24 (uint32_t)0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ #define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ /** * @} @@ -392,7 +361,7 @@ typedef struct /** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND * @{ */ -#define LL_RTC_SHIFT_SECOND_DELAY (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ #define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ /** * @} @@ -401,7 +370,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK * @{ */ -#define LL_RTC_ALMA_MASK_NONE ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A*/ +#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ #define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ #define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ #define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ @@ -414,7 +383,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT * @{ */ -#define LL_RTC_ALMA_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ #define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ /** * @} @@ -423,7 +392,7 @@ typedef struct /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE * @{ */ -#define LL_RTC_TIMESTAMP_EDGE_RISING (uint32_t)0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ #define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ /** * @} @@ -432,7 +401,7 @@ typedef struct /** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT * @{ */ -#define LL_RTC_TS_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ #define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ /** * @} @@ -490,7 +459,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION * @{ */ -#define LL_RTC_TAMPER_DURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ @@ -503,7 +472,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER * @{ */ -#define LL_RTC_TAMPER_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ #define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ #define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ #define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ @@ -516,7 +485,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER * @{ */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ #define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ @@ -548,7 +517,7 @@ typedef struct /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV * @{ */ -#define LL_RTC_WAKEUPCLOCK_DIV_16 ((uint32_t)0x00000000U) /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ @@ -562,11 +531,11 @@ typedef struct /** @defgroup RTC_LL_EC_BKP BACKUP * @{ */ -#define LL_RTC_BKP_DR0 ((uint32_t)0x00000000U) -#define LL_RTC_BKP_DR1 ((uint32_t)0x00000001U) -#define LL_RTC_BKP_DR2 ((uint32_t)0x00000002U) -#define LL_RTC_BKP_DR3 ((uint32_t)0x00000003U) -#define LL_RTC_BKP_DR4 ((uint32_t)0x00000004U) +#define LL_RTC_BKP_DR0 0x00000000U +#define LL_RTC_BKP_DR1 0x00000001U +#define LL_RTC_BKP_DR2 0x00000002U +#define LL_RTC_BKP_DR3 0x00000003U +#define LL_RTC_BKP_DR4 0x00000004U /** * @} */ @@ -575,9 +544,9 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output * @{ */ -#define LL_RTC_CALIB_OUTPUT_NONE (uint32_t)0x00000000U /*!< Calibration output disabled */ -#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */ -#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */ /** * @} */ @@ -585,7 +554,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion * @{ */ -#define LL_RTC_CALIB_INSERTPULSE_NONE (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ #define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ /** * @} @@ -594,7 +563,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period * @{ */ -#define LL_RTC_CALIB_PERIOD_32SEC (uint32_t)0x00000000U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ #define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ #define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ /** @@ -1041,7 +1010,7 @@ __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) { - MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A); + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); } /** @@ -1064,7 +1033,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP */ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A); + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } /** @@ -1156,7 +1125,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) { MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), - (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU))); + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); } /** @@ -1177,7 +1146,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); - return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC_POSITION_TR_HU)); + return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)); } /** @@ -1194,7 +1163,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) { MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), - (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU))); + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); } /** @@ -1215,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); - return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> RTC_POSITION_TR_MU)); + return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)); } /** @@ -1232,7 +1201,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) { MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), - (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU))); + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); } /** @@ -1253,7 +1222,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); - return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC_POSITION_TR_SU)); + return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)); } /** @@ -1282,9 +1251,9 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, register uint32_t temp = 0U; temp = Format12_24 | \ - (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) | \ - (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)) | \ - (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU)); + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); } @@ -1307,42 +1276,47 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); } /** * @brief Memorize whether the daylight saving time change has been performed * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BCK LL_RTC_TIME_EnableDayLightStore + * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) { - SET_BIT(RTCx->CR, RTC_CR_BCK); + SET_BIT(RTCx->CR, RTC_CR_BKP); } /** * @brief Disable memorization whether the daylight saving time change has been performed. * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BCK LL_RTC_TIME_DisableDayLightStore + * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) { - CLEAR_BIT(RTCx->CR, RTC_CR_BCK); + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); } /** * @brief Check if RTC Day Light Saving stored operation has been enabled or not - * @rmtoll CR BCK LL_RTC_TIME_IsDayLightStoreEnabled + * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK)); + return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)); } /** @@ -1426,7 +1400,7 @@ __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSe __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) { MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), - (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU))); + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); } /** @@ -1444,7 +1418,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); - return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC_POSITION_DR_YU)); + return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)); } /** @@ -1463,7 +1437,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) { - MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU); + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); } /** @@ -1483,7 +1457,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU); + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } /** @@ -1510,7 +1484,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) { MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), - (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU))); + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); } /** @@ -1540,7 +1514,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); - return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC_POSITION_DR_MU)); + return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)); } /** @@ -1555,7 +1529,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) { MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), - (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU))); + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); } /** @@ -1573,7 +1547,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); - return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC_POSITION_DR_DU)); + return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)); } /** @@ -1615,10 +1589,10 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin { register uint32_t temp = 0U; - temp = (WeekDay << RTC_POSITION_DR_WDU) | \ - (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) | \ - (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) | \ - (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)); + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); } @@ -1641,7 +1615,13 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); } /** @@ -1751,7 +1731,7 @@ __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), - (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_DU))); + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); } /** @@ -1767,7 +1747,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); - return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU)); + return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos)); } /** @@ -1786,7 +1766,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) { - MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU); + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); } /** @@ -1804,7 +1784,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU); + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } /** @@ -1846,7 +1826,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), - (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU))); + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); } /** @@ -1862,7 +1842,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); - return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_POSITION_ALMA_HU)); + return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos)); } /** @@ -1877,7 +1857,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), - (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU))); + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); } /** @@ -1893,7 +1873,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); - return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_POSITION_ALMA_MU)); + return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos)); } /** @@ -1908,7 +1888,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), - (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU))); + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); } /** @@ -1924,7 +1904,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_POSITION_ALMA_SU)); + return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos)); } /** @@ -1949,9 +1929,9 @@ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 { register uint32_t temp = 0U; - temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)) | \ - (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)) | \ - (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU)); + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); } @@ -1985,7 +1965,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) { - MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS); + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); } /** @@ -1996,7 +1976,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS); + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } /** @@ -2107,7 +2087,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU); + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } /** @@ -2120,7 +2100,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU); + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } /** @@ -2170,7 +2150,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU); + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } /** @@ -2195,7 +2175,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU); + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c index 07cd385fdd..3005490285 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_spi.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief SPI LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h index 6a8581e1f2..d3a638158f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_spi.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of SPI LL module. ****************************************************************************** * @attention @@ -141,7 +139,6 @@ typedef struct #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ -#define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */ #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ @@ -165,7 +162,7 @@ typedef struct * @{ */ #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ -#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ /** * @} */ @@ -173,7 +170,7 @@ typedef struct /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol * @{ */ -#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ /** * @} @@ -182,7 +179,7 @@ typedef struct /** @defgroup SPI_LL_EC_PHASE Clock Phase * @{ */ -#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ /** * @} @@ -191,7 +188,7 @@ typedef struct /** @defgroup SPI_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ /** * @} @@ -200,7 +197,7 @@ typedef struct /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler * @{ */ -#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ @@ -216,7 +213,7 @@ typedef struct * @{ */ #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ -#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/received with the MSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ /** * @} */ @@ -224,7 +221,7 @@ typedef struct /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode * @{ */ -#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ @@ -236,7 +233,7 @@ typedef struct * @{ */ #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ -#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ /** * @} @@ -266,7 +263,7 @@ typedef struct /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation * @{ */ -#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ /** * @} @@ -276,7 +273,7 @@ typedef struct /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length * @{ */ -#define LL_SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< 8-bit CRC length */ +#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ /** * @} @@ -285,7 +282,7 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold * @{ */ -#define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ /** * @} @@ -294,7 +291,7 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level * @{ */ -#define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ @@ -305,7 +302,7 @@ typedef struct /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level * @{ */ -#define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ @@ -316,8 +313,8 @@ typedef struct /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity * @{ */ -#define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Select DMA parity Even */ -#define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U) /*!< Select DMA parity Odd */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ /** * @} @@ -1283,7 +1280,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) { - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << 13U)); + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); } /** @@ -1296,7 +1293,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) */ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) { - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> 13U); + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } /** @@ -1310,7 +1307,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) { - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << 14U)); + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); } /** @@ -1323,7 +1320,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) */ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) { - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> 14U); + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } /** @@ -1490,7 +1487,7 @@ typedef struct #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ -#define LL_I2S_SR_UDR LL_SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ /** @@ -1511,7 +1508,7 @@ typedef struct /** @defgroup I2S_LL_EC_DATA_FORMAT Data format * @{ */ -#define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /*!< Data length 16 bits, Channel lenght 16bit */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ @@ -1522,7 +1519,7 @@ typedef struct /** @defgroup I2S_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ /** * @} @@ -1531,7 +1528,7 @@ typedef struct /** @defgroup I2S_LL_EC_STANDARD I2s Standard * @{ */ -#define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /*!< I2S standard philips */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ @@ -1543,7 +1540,7 @@ typedef struct /** @defgroup I2S_LL_EC_MODE Operation Mode * @{ */ -#define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ @@ -1554,7 +1551,7 @@ typedef struct /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor * @{ */ -#define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ /** * @} @@ -1565,7 +1562,7 @@ typedef struct /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output * @{ */ -#define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ /** * @} @@ -1575,16 +1572,16 @@ typedef struct * @{ */ -#define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /*!< Audio Frequency configuration 192000 Hz */ -#define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /*!< Audio Frequency configuration 96000 Hz */ -#define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /*!< Audio Frequency configuration 48000 Hz */ -#define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /*!< Audio Frequency configuration 44100 Hz */ -#define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /*!< Audio Frequency configuration 32000 Hz */ -#define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /*!< Audio Frequency configuration 22050 Hz */ -#define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /*!< Audio Frequency configuration 16000 Hz */ -#define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /*!< Audio Frequency configuration 11025 Hz */ -#define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /*!< Audio Frequency configuration 8000 Hz */ -#define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /*!< Audio Freq not specified. Register I2SDIV = 2 */ +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h index 870497991c..65af161464 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_system.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -76,9 +74,6 @@ extern "C" { * @{ */ -/* Defines used for position in the register */ -#define DBGMCU_REVID_POSITION (uint32_t)16U - /** * @} */ @@ -337,7 +332,7 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY * @{ */ -#define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ /** * @} @@ -1635,7 +1630,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c index 3393d5ec4b..fa745e1190 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_tim.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief TIM LL module driver. ****************************************************************************** * @attention @@ -127,6 +125,26 @@ #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** * @} */ @@ -265,7 +283,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) /* Set the default configuration */ TIM_InitStruct->Prescaler = (uint16_t)0x0000U; TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; - TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; } @@ -335,7 +353,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U; + TIM_OC_InitStruct->CompareValue = 0x00000000U; TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; @@ -528,7 +546,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_HallSensorInitStruct->CommutationDelay = (uint32_t)0U; + TIM_HallSensorInitStruct->CommutationDelay = 0U; } /** @@ -623,6 +641,68 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType return SUCCESS; } +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked + * depending on the LOCK configuration, it can be necessary to configure all of + * them during the first write access to the TIMx_BDTR register. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h index 7c4974ecbf..85ebdf1b6a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_tim.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of TIM LL module. ****************************************************************************** * @attention @@ -126,9 +124,9 @@ static const uint8_t SHIFT_TAB_OISx[] = */ -#define TIMx_OR_RMP_SHIFT ((uint32_t)16U) -#define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU) -#define TIM14_OR_RMP_MASK ((uint32_t)(TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)) +#define TIMx_OR_RMP_SHIFT 16U +#define TIMx_OR_RMP_MASK 0x0000FFFFU +#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ #define DT_DELAY_1 ((uint8_t)0x7FU) @@ -147,7 +145,6 @@ static const uint8_t SHIFT_TAB_OISx[] = * @} */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_LL_Private_Macros TIM Private Macros * @{ @@ -209,7 +206,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ - uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. @@ -267,6 +264,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. @@ -390,6 +388,61 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +} LL_TIM_BDTR_InitTypeDef; + /** * @} */ @@ -420,6 +473,26 @@ typedef struct * @} */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + /** @defgroup TIM_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. * @{ @@ -439,8 +512,8 @@ typedef struct /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source * @{ */ -#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ -#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ /** * @} */ @@ -448,8 +521,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ /** * @} */ @@ -457,11 +530,11 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!TIMx_CCRy else active.*/ #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ @@ -557,7 +630,7 @@ typedef struct /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity * @{ */ -#define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /*!< OCxactive high*/ +#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ /** * @} @@ -566,7 +639,7 @@ typedef struct /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State * @{ */ -#define LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U) /*!> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) /** @@ -1005,7 +1077,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) { - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** @@ -1016,18 +1088,18 @@ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) { - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** * @brief Indicates whether update event generation is enabled. * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent * @param TIMx Timer instance - * @retval State of bit (1 or 0). + * @retval Inverted state of bit (0 or 1). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); } /** @@ -2709,7 +2781,13 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u */ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) { + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); + + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); } /** @@ -2722,7 +2800,13 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) { + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); + + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); } /** @@ -2738,7 +2822,13 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) { + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); + + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); } /** @@ -2932,15 +3022,14 @@ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) * @} */ -#if defined(TIM_SMCR_OCCS) /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management * @{ */ /** - * @brief Set the OCREF clear source + * @brief Set the OCREF clear input source * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT * @note This function can only be used in Output compare and PWM modes. - * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource * @param TIMx Timer instance * @param OCRefClearInputSource This parameter can be one of the following values: * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR @@ -2955,7 +3044,6 @@ __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t * @} */ -#endif /* TIM_SMCR_OCCS */ /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management * @{ */ @@ -3847,6 +3935,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ @@ -3871,5 +3961,4 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType #endif #endif /* __STM32F0xx_LL_TIM_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c index d6de97daae..d671b293b2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_usart.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief USART LL module driver. ****************************************************************************** * @attention @@ -77,6 +75,12 @@ * divided by the smallest oversampling used on the USART (i.e. 8) */ #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U) +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ +#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -247,7 +251,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance - * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure * that contains the configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are initialized according to USART_InitStruct content @@ -275,7 +279,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR1 Configuration ----------------------- + /*---------------------------- USART CR1 Configuration --------------------- * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value @@ -288,20 +292,20 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini (USART_InitStruct->DataWidth | USART_InitStruct->Parity | USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); - /*---------------------------- USART CR2 Configuration ----------------------- + /*---------------------------- USART CR2 Configuration --------------------- * Configure USARTx CR2 (Stop bits) with parameters: * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). */ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); - /*---------------------------- USART CR3 Configuration ----------------------- + /*---------------------------- USART CR3 Configuration --------------------- * Configure USARTx CR3 (Hardware Flow Control) with parameters: * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. */ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); - /*---------------------------- USART BRR Configuration ----------------------- + /*---------------------------- USART BRR Configuration --------------------- * Retrieve Clock frequency used for USART Peripheral */ if (USARTx == USART1) @@ -389,6 +393,12 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini periphclk, USART_InitStruct->OverSampling, USART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -398,7 +408,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /** * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -421,7 +431,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content @@ -482,7 +492,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef /** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h index b3f2911d12..e8f00fb8de 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_usart.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of USART LL module. ****************************************************************************** * @attention @@ -63,16 +61,6 @@ extern "C" { /** @defgroup USART_LL_Private_Constants USART Private Constants * @{ */ - -/* Defines used for the bit position in the register and perform offsets*/ -#define USART_POSITION_CR1_DEDT (uint32_t)16 -#define USART_POSITION_CR1_DEAT (uint32_t)21 -#define USART_POSITION_CR2_ADD (uint32_t)24 -#if defined(USART_SMARTCARD_SUPPORT) -#define USART_POSITION_CR3_SCARCNT (uint32_t)17 -#define USART_POSITION_RTOR_BLEN (uint32_t)24 -#define USART_POSITION_GTPR_GT (uint32_t)8 -#endif /** * @} */ @@ -268,7 +256,7 @@ typedef struct /** @defgroup USART_LL_EC_DIRECTION Communication Direction * @{ */ -#define LL_USART_DIRECTION_NONE (uint32_t)0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ @@ -279,7 +267,7 @@ typedef struct /** @defgroup USART_LL_EC_PARITY Parity Control * @{ */ -#define LL_USART_PARITY_NONE (uint32_t)0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ /** @@ -289,7 +277,7 @@ typedef struct /** @defgroup USART_LL_EC_WAKEUP Wakeup * @{ */ -#define LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ /** * @} @@ -300,10 +288,10 @@ typedef struct */ #if defined(USART_7BITS_SUPPORT) #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ #else -#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ #define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ #endif /** @@ -313,7 +301,7 @@ typedef struct /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling * @{ */ -#define LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ /** * @} @@ -324,7 +312,7 @@ typedef struct * @{ */ -#define LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ /** * @} @@ -334,7 +322,7 @@ typedef struct /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse * @{ */ -#define LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ /** * @} @@ -343,7 +331,7 @@ typedef struct /** @defgroup USART_LL_EC_PHASE Clock Phase * @{ */ -#define LL_USART_PHASE_1EDGE (uint32_t)0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ /** * @} @@ -352,7 +340,7 @@ typedef struct /** @defgroup USART_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_USART_POLARITY_LOW (uint32_t)0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ /** * @} @@ -364,7 +352,7 @@ typedef struct #if defined(USART_SMARTCARD_SUPPORT) #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ #endif -#define LL_USART_STOPBITS_1 (uint32_t)0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ #if defined(USART_SMARTCARD_SUPPORT) #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ #endif @@ -376,7 +364,7 @@ typedef struct /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap * @{ */ -#define LL_USART_TXRX_STANDARD (uint32_t)0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ /** * @} @@ -385,7 +373,7 @@ typedef struct /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion * @{ */ -#define LL_USART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ /** * @} @@ -394,7 +382,7 @@ typedef struct /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion * @{ */ -#define LL_USART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ /** * @} @@ -403,7 +391,7 @@ typedef struct /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion * @{ */ -#define LL_USART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ /** * @} @@ -412,7 +400,7 @@ typedef struct /** @defgroup USART_LL_EC_BITORDER Bit Order * @{ */ -#define LL_USART_BITORDER_LSBFIRST (uint32_t)0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ /** * @} @@ -421,7 +409,7 @@ typedef struct /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection * @{ */ -#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT (uint32_t)0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ #if defined(USART_FABR_SUPPORT) #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ @@ -434,7 +422,7 @@ typedef struct /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection * @{ */ -#define LL_USART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ /** * @} @@ -443,7 +431,7 @@ typedef struct /** @defgroup USART_LL_EC_HWCONTROL Hardware Control * @{ */ -#define LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ @@ -455,7 +443,7 @@ typedef struct /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ -#define LL_USART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ /** @@ -467,7 +455,7 @@ typedef struct /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power * @{ */ -#define LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ /** * @} @@ -478,7 +466,7 @@ typedef struct /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length * @{ */ -#define LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ /** * @} @@ -488,7 +476,7 @@ typedef struct /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity * @{ */ -#define LL_USART_DE_POLARITY_HIGH (uint32_t)0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ /** * @} @@ -497,8 +485,8 @@ typedef struct /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_USART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /*!< Get address of data register used for transmission */ -#define LL_USART_DMA_REG_DATA_RECEIVE (uint32_t)1U /*!< Get address of data register used for reception */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ @@ -1400,7 +1388,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) { MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, - (uint32_t)(AddressLen | (NodeAddress << USART_POSITION_CR2_ADD))); + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); } /** @@ -1415,7 +1403,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_POSITION_CR2_ADD); + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } /** @@ -1627,6 +1615,7 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values * @note Peripheral clock and Baud rate values provided as function parameters should be valid * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. * @rmtoll BRR BRR LL_USART_SetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock @@ -1659,6 +1648,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @brief Return current Baud Rate value, according to USARTDIV present in BRR register * (full BRR content), and to used Peripheral Clock and Oversampling mode values * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. * @rmtoll BRR BRR LL_USART_GetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock @@ -1725,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) { - MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_POSITION_RTOR_BLEN); + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); } /** @@ -1736,7 +1726,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo */ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_POSITION_RTOR_BLEN); + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); } #endif @@ -1952,7 +1942,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) { - MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_POSITION_CR3_SCARCNT); + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); } /** @@ -1965,7 +1955,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, */ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_POSITION_CR3_SCARCNT); + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); } /** @@ -2009,7 +1999,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos); } /** @@ -2023,7 +2013,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 */ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); } /** @@ -2173,7 +2163,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) { - MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_POSITION_CR1_DEDT); + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); } /** @@ -2186,7 +2176,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 */ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_POSITION_CR1_DEDT); + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } /** @@ -2200,7 +2190,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) { - MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_POSITION_CR1_DEAT); + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); } /** @@ -2213,7 +2203,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_POSITION_CR1_DEAT); + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c index 49942c5f02..836204a08c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_utils.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief UTILS LL module driver. ****************************************************************************** * @attention @@ -60,15 +58,15 @@ */ /* Defines used for PLL range */ -#define UTILS_PLL_OUTPUT_MIN ((uint32_t)16000000U) /*!< Frequency min for PLL output, in Hz */ -#define UTILS_PLL_OUTPUT_MAX ((uint32_t)48000000U) /*!< Frequency max for PLL output, in Hz */ +#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */ +#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ /* Defines used for HSE range */ -#define UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000U) /*!< Frequency min for HSE frequency, in Hz */ -#define UTILS_HSE_FREQUENCY_MAX ((uint32_t)32000000U) /*!< Frequency max for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to SYSCLK Frequency */ -#define UTILS_LATENCY1_FREQ ((uint32_t)24000000U) /*!< SYSCLK frequency to set FLASH latency 1 */ +#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ /** * @} */ @@ -133,7 +131,9 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +#if defined(FLASH_ACR_LATENCY) static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -268,7 +268,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS /* Force PREDIV value to 2 */ UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - /* Calculate the new PLL output frequency */ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); @@ -426,7 +425,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); #else - LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); + LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ /* Enable PLL and switch system clock to PLL */ @@ -460,6 +459,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa * - SUCCESS: Latency has been modified * - ERROR: Latency cannot be modified */ +#if defined(FLASH_ACR_LATENCY) static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) { ErrorStatus status = SUCCESS; @@ -491,6 +491,7 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) } return status; } +#endif /* FLASH_ACR_LATENCY */ /** * @brief Function to check that PLL can be modified @@ -536,7 +537,6 @@ static ErrorStatus UTILS_PLL_IsBusy(void) status = ERROR; } - return status; } @@ -558,7 +558,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); /* Calculate current SYSCLK frequency */ - sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]); + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); /* Increasing the number of wait states because of higher CPU frequency */ if (sysclk_frequency_current < SYSCLK_Frequency) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h index 0eeaeda6fd..ca5ed3eba6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_utils.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of UTILS LL module. @verbatim ============================================================================== @@ -75,7 +73,7 @@ extern "C" { */ /* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY (uint32_t)0xFFFFFFFFU +#define LL_MAX_DELAY 0xFFFFFFFFU /** * @brief Unique device ID register base address @@ -158,8 +156,8 @@ typedef struct /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation * @{ */ -#define LL_UTILS_HSEBYPASS_OFF (uint32_t)0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON (uint32_t)0x00000001U /*!< HSE Bypass is enabled */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ /** * @} */ @@ -217,6 +215,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h index 5fb27831ee..3a6d707e70 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_wwdg.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention @@ -82,7 +80,7 @@ extern "C" { /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER * @{ */ -#define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c b/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c index 688f9fe1d1..9f77316090 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.c * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from diff --git a/targets/TARGET_STM/hal_tick_32b.c b/targets/TARGET_STM/hal_tick_32b.c index 7e84f34418..2fb605413f 100644 --- a/targets/TARGET_STM/hal_tick_32b.c +++ b/targets/TARGET_STM/hal_tick_32b.c @@ -42,7 +42,7 @@ void timer_irq_handler(void) if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) { if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) { __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); - uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + uint32_t val = __HAL_TIM_GET_COUNTER(&TimMasterHandle); if ((val - PreviousVal) >= HAL_TICK_DELAY) { // Increment HAL variable HAL_IncTick(); @@ -114,7 +114,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) // Channel 2 for HAL tick HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); - PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + PreviousVal = __HAL_TIM_GET_COUNTER(&TimMasterHandle); __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 31330863d8..b757e3b005 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -413,7 +413,7 @@ void i2c_frequency(i2c_t *obj, int hz) #ifdef I2C_ANALOGFILTER_ENABLE /* Enable the Analog I2C Filter */ - HAL_I2CEx_AnalogFilter_Config(handle,I2C_ANALOGFILTER_ENABLE); + HAL_I2CEx_ConfigAnalogFilter(handle,I2C_ANALOGFILTER_ENABLE); #endif // I2C configuration From f5ac72f6c0a48cd7d3b4d8bca3e7568b7fcbd662 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 20 Dec 2017 16:13:06 +0000 Subject: [PATCH 104/118] BLE: Introduce pal client adaptation layer for nordic targets. --- .../TARGET_NRF5/source/nRF5XPalGattClient.cpp | 1616 +++++++++++++++++ .../TARGET_NRF5/source/nRF5XPalGattClient.h | 257 +++ 2 files changed, 1873 insertions(+) create mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp create mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp new file mode 100644 index 0000000000..23b352c440 --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp @@ -0,0 +1,1616 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "nRF5XPalGattClient.h" + +#include "ble/pal/PalGattClient.h" +#include "ble/pal/SimpleAttServerMessage.h" + +#include "nrf_ble_gatt.h" +#include "nrf_ble.h" +#include "nrf_ble_types.h" +#include "nrf_ble_err.h" + +namespace ble { +namespace pal { +namespace vendor { +namespace nordic { + +namespace { + +/** + * Extract an uint16_t value from a memory location. + */ +static uint16_t bytes_to_u16(const void* b) +{ + uint16_t res; + memcpy(&res, b, sizeof(uint16_t)); + return res; +} + +/** + * Push an uint16_t value into a byte stream. + * + * @note it is incremented. + */ +static void u16_to_stream(uint8_t *&it, uint16_t v) +{ + memcpy(it, &v, sizeof(uint16_t)); + it += 2; +} + +/** + * Convert a pal::attribute_handle_range_t into a ble_gattc_handle_range_t. + */ +static ble_gattc_handle_range_t to_nordic_handle_range(const attribute_handle_range_t &range) +{ + ble_gattc_handle_range_t result = { + range.begin, + range.end + }; + return result; +} + +/** + * Convert a ble_gattc_handle_range_t into a pal::attribute_handle_range_t. + */ +static attribute_handle_range_t to_ble_handle_range(const ble_gattc_handle_range_t &range) +{ + attribute_handle_range_t result = { + range.start_handle, + range.end_handle + }; + return result; +} + +/** + * Convert a UUID into a ble_uuid_t . + * If the UUID is a 128 bit one then it is registered into the softdevice. + */ +static ble_error_t to_nordic_uuid(const UUID &uuid, ble_uuid_t &nordic_uuid) +{ + if (uuid.getLen() == UUID::LENGTH_OF_LONG_UUID) { + // first try to get the long UUID in the table of UUIDs + uint32_t err = sd_ble_uuid_decode( + uuid.getLen(), + uuid.getBaseUUID(), + &nordic_uuid + ); + + // UUID found and filed, return. + if (err == NRF_SUCCESS) { + return BLE_ERROR_NONE; + } + + ble_uuid128_t uuid128; + memcpy(uuid128.uuid128, uuid.getBaseUUID(), sizeof(uuid128.uuid128)); + + // UUID not found, try to register it + err = sd_ble_uuid_vs_add( + &uuid128, + &nordic_uuid.type + ); + + switch (err) { + case NRF_SUCCESS: + nordic_uuid.uuid = bytes_to_u16(uuid.getBaseUUID() + 12); + return BLE_ERROR_NONE; + case NRF_ERROR_INVALID_ADDR: + return BLE_ERROR_INVALID_PARAM; + case NRF_ERROR_NO_MEM: + return BLE_ERROR_NO_MEM; + default: + return BLE_ERROR_UNSPECIFIED; + } + } else { + nordic_uuid.type = BLE_UUID_TYPE_BLE; + nordic_uuid.uuid = uuid.getShortUUID(); + return BLE_ERROR_NONE; + } +} + +/** + * Convert an error from the softdevice into a ble_error_t + */ +static ble_error_t convert_sd_error(uint32_t err) +{ + switch (err) { + case NRF_SUCCESS: + return BLE_ERROR_NONE; + case NRF_ERROR_INVALID_PARAM: + case BLE_ERROR_INVALID_CONN_HANDLE: + case NRF_ERROR_INVALID_ADDR: + return BLE_ERROR_INVALID_PARAM; + case NRF_ERROR_INVALID_STATE: + return BLE_ERROR_INVALID_STATE; + case NRF_ERROR_DATA_SIZE: + return BLE_ERROR_PARAM_OUT_OF_RANGE; + case BLE_ERROR_NO_TX_PACKETS: + return BLE_ERROR_NO_MEM; + case NRF_ERROR_BUSY: + return BLE_STACK_BUSY; + default: + return BLE_ERROR_UNSPECIFIED; + } +} + +/** + * Convert an attribute error code from the softdevice into a valid ATT error. + */ +static uint8_t convert_sd_att_error_code(uint16_t err) +{ + if (err < 0x101 || err > 0x1FF) { + return AttErrorResponse::UNLIKELY_ERROR; + } else { + return err & 0xFF; + } +} + +} // end of anonymous namespace + +nRF5XGattClient::nRF5XGattClient() : + ble::pal::GattClient(), + _procedures() +{ +} + +nRF5XGattClient::~nRF5XGattClient() +{ + terminate(); +} + +ble_error_t nRF5XGattClient::initialize() +{ + return BLE_ERROR_NONE; +} + +ble_error_t nRF5XGattClient::exchange_mtu(connection_handle_t connection) +{ + // Note: Not supported by the current softdevice + return BLE_ERROR_NOT_IMPLEMENTED; +} + +ble_error_t nRF5XGattClient::get_mtu_size( + connection_handle_t connection_handle, uint16_t& mtu_size +) { + mtu_size = GATT_RX_MTU; + return BLE_ERROR_NONE; +} + +ble_error_t nRF5XGattClient::discover_primary_service( + connection_handle_t connection, + attribute_handle_t discovery_range_begining +) { + return launch_procedure( + connection, discovery_range_begining + ); +} + +ble_error_t nRF5XGattClient::discover_primary_service_by_service_uuid( + connection_handle_t connection_handle, + attribute_handle_t discovery_range_beginning, + const UUID& uuid +) { + return launch_procedure( + connection_handle, discovery_range_beginning, uuid + ); +} + +ble_error_t nRF5XGattClient::find_included_service( + connection_handle_t connection_handle, + attribute_handle_range_t service_range +) { + return launch_procedure( + connection_handle, service_range + ); +} + +ble_error_t nRF5XGattClient::discover_characteristics_of_a_service( + connection_handle_t connection_handle, + attribute_handle_range_t discovery_range +) { + return launch_procedure( + connection_handle, discovery_range + ); +} + +ble_error_t nRF5XGattClient::discover_characteristics_descriptors( + connection_handle_t connection_handle, + attribute_handle_range_t descriptors_discovery_range +) { + return launch_procedure( + connection_handle, descriptors_discovery_range + ); +} + +ble_error_t nRF5XGattClient::read_attribute_value( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle +) { + return launch_procedure( + connection_handle, attribute_handle + ); +} + +ble_error_t nRF5XGattClient::read_using_characteristic_uuid( + connection_handle_t connection_handle, + attribute_handle_range_t read_range, + const UUID& uuid +) { + return launch_procedure( + connection_handle, read_range, uuid + ); +} + +ble_error_t nRF5XGattClient::read_attribute_blob( + connection_handle_t connection, + attribute_handle_t attribute_handle, + uint16_t offset +) { + return launch_procedure( + connection, attribute_handle, offset + ); +} + +ble_error_t nRF5XGattClient::read_multiple_characteristic_values( + connection_handle_t connection, + const ArrayView& characteristic_handles +) { + return launch_procedure( + connection, characteristic_handles + ); +} + +ble_error_t nRF5XGattClient::write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value +) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_WRITE_CMD, + /* exec flags */ 0, + characteristic_value_handle, + /* offset */ 0, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); +} + +ble_error_t nRF5XGattClient::signed_write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value +) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_SIGN_WRITE_CMD, + /* exec flags */ 0, + characteristic_value_handle, + /* offset */ 0, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); +} + +ble_error_t nRF5XGattClient::write_attribute( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle, + const ArrayView& value +) { + return launch_procedure( + connection_handle, attribute_handle, value + ); +} + +ble_error_t nRF5XGattClient::queue_prepare_write( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value, + uint16_t offset +) { + return launch_procedure( + connection_handle, characteristic_value_handle, value, offset + ); +} + +ble_error_t nRF5XGattClient::execute_write_queue( + connection_handle_t connection_handle, + bool execute +) { + return launch_procedure( + connection_handle, execute + ); +} + + +/** + * Base definition of a GATT procedure. + * + * Nordic implementation of discovery procedures requires more than a single + * request to the BLE peer when it involves 128bit UUID. As a consequence it is + * necessary to reserve the connection slot, maintain state between requests and + * interpret responses depending on the context. + * + * The concept of procedures for Gatt operations formalize the process. A + * procedure lifecycle is defined by three function: + * - start: Launch of the procedure. It initiate the first request to send to + * the peer. It must be implemented by Procedure childs. + * - handle: Event handler that process ble events comming from the softdevice. + * This function drive the procedure flow and must be implemented by + * Procedure childs. + * - terminate: end the procedure and forward the result to the GattClient + * event handle. + * + * @note Commands such as write without response or signed write without response + * are not procedures. + */ +struct nRF5XGattClient::GattProcedure { + /** + * Initialize the procedure. + * + * @param connection Handle representing the connection used by the procedure. + * @param op Opcode of the procedure. + */ + GattProcedure(connection_handle_t connection, AttributeOpcode op) : + connection_handle(connection), procedure_opcode(op) { } + + /** + * To overide in child if necessary. + */ + virtual ~GattProcedure() { } + + /** + * Handle events targeting the connection. + */ + virtual void handle(const ble_evt_t &evt) = 0; + + /** + * Terminate the execution of the procedure and forward msg to the handler + * registered in the client. + * + * @note delete this. + */ + void terminate(const AttServerMessage &msg) + { + get_client().remove_procedure(this); + get_client().on_server_event(connection_handle, msg); + delete this; + } + + /** + * Terminate the procedure with an unlikely error. + */ + void abort() + { + terminate(AttErrorResponse( + procedure_opcode, AttErrorResponse::UNLIKELY_ERROR + )); + } + + const connection_handle_t connection_handle; + const AttributeOpcode procedure_opcode; +}; + + +/** + * A regular procedure is a procedure that follows Gatt specification. + * + * It initiate a single request to the peer and except a single response. This + * kind of procedure doesn't requires extra processing step. + * + * Given that such procedure expect a single event type from the soft device, + * error handling can be generalized. + */ +struct nRF5XGattClient::RegularGattProcedure : GattProcedure { + + /** + * Construct a RegularGattProcedure. + * + * @param connection Handle of the connection used by the procedure. + * @param op Attribute operation code + * @param event_type Type of event expected by the stack. + */ + RegularGattProcedure( + connection_handle_t connection, AttributeOpcode op, BLE_GATTC_EVTS event_type + ) : GattProcedure(connection, op), _event_type(event_type) { } + + /** + * Handle events from the BLE stack; do not overide in child. + * + * @note This function offload error handling from user error handler. If + * the event in input match the expected event type and does not carry error + * then it is forwarded to the do_handle function. Otherwise the procedure + * is terminated and an error is forwarded to the client event handler. + */ + virtual void handle(const ble_evt_t &evt) + { + if (evt.header.evt_id == _event_type) { + const ble_gattc_evt_t &gattc_evt = evt.evt.gattc_evt; + if (gattc_evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + procedure_opcode, + gattc_evt.error_handle, + convert_sd_att_error_code(gattc_evt.gatt_status) + )); + return; + } else { + do_handle(gattc_evt); + } + } else { + abort(); + } + } + + /** + * Handle gatt event received from the stack. + * + * @note The event passed in parameter is valid. + */ + virtual void do_handle(const ble_gattc_evt_t &evt) = 0; + +protected: + BLE_GATTC_EVTS _event_type; +}; + + +/** + * Procedure that handle discovery of primary services. + * + * The softdevice doesn't forward to user UUID of services that are 128 bit long. + * In such case a read request is issued for each service attribute handle + * to extract that information. + */ +struct nRF5XGattClient::DiscoverPrimaryServiceProcedure : GattProcedure { + + typedef ArrayView services_array_t; + + DiscoverPrimaryServiceProcedure(connection_handle_t connection) : + GattProcedure(connection, AttributeOpcode::READ_BY_GROUP_TYPE_REQUEST), + response(NULL), count(0), idx(0) { } + + virtual ~DiscoverPrimaryServiceProcedure() + { + if (response) { + delete[] response; + } + } + + ble_error_t start(attribute_handle_t begining) + { + uint32_t err = sd_ble_gattc_primary_services_discover( + connection_handle, begining, /* p_srvc_uuid */ NULL + ); + return convert_sd_error(err); + } + + /** + * Dispatch responses either to service discovery handler or attribute read + * handler. + */ + virtual void handle(const ble_evt_t &evt) + { + switch (evt.header.evt_id) { + case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: + handle_service_discovered(evt.evt.gattc_evt); + return; + case BLE_GATTC_EVT_READ_RSP: + handle_uuid_read(evt.evt.gattc_evt); + return; + default: + abort(); + return; + } + } + + /** + * Dispatch service discovery response either to the short UUID handler or + * the long UUID handler. + */ + void handle_service_discovered(const ble_gattc_evt_t &evt) + { + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_BY_GROUP_TYPE_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + services_array_t services( + evt.params.prim_srvc_disc_rsp.services, + evt.params.prim_srvc_disc_rsp.count + ); + + // note 128 bit and 16 bits UUID cannot be mixed up + if (services[0].uuid.type == BLE_UUID_TYPE_BLE) { + handle_16bit_services_discovered(services); + } else { + handle_128bit_services_discovered(services); + } + } + + /** + * Handle discovery of services with a 16 bit UUID. + * + * The procedure ends here. + */ + void handle_16bit_services_discovered(const services_array_t &services) + { + /** + * Custom implementation of AttReadByGroupTypeResponse that can be used + * with data returned by the nordic stack. + */ + struct CustomAttReadByGroupTypeResponse : AttReadByGroupTypeResponse { + CustomAttReadByGroupTypeResponse(const services_array_t &s) : + AttReadByGroupTypeResponse(), services(s) { + } + + virtual size_t size() const + { + return services.size(); + } + + virtual attribute_data_t operator[](size_t i) const + { + attribute_data_t result = { + to_ble_handle_range(services[i].handle_range), + make_const_ArrayView( + reinterpret_cast(&services[i].uuid.uuid), + sizeof(uint16_t) + ) + }; + return result; + } + + const services_array_t &services; + }; + + terminate(CustomAttReadByGroupTypeResponse(services)); + } + + /** + * Handle discovery of services with a 128 UUID. + * + * Handle of the services discovered will be stored locally then the + * procedure sequentially initiate a read request of each of these attribute + * handle to acquire the value of the UUID of the service. + * + * The procedure ends once all the informations initially sent by the peer + * has been reconstructed and forwarded to the registered client handler. + */ + void handle_128bit_services_discovered(const services_array_t &services) + { + response = new(std::nothrow) packed_discovery_response_t[services.size()]; + if (!response) { + abort(); + return; + } + + count = services.size(); + idx = 0; + for (size_t i = 0; i < count; ++i) { + uint8_t *it = &response[i][0]; + u16_to_stream(it, services[i].handle_range.start_handle); + u16_to_stream(it, services[i].handle_range.end_handle); + } + + read_service_uuid(); + } + + /** + * Initiate the read request of the next service attribute handle. + */ + void read_service_uuid(void) + { + // note: use read multiple once different mtu size are supported ? + uint16_t attribute_handle = bytes_to_u16(&response[idx][0]); + + uint32_t err = sd_ble_gattc_read(connection_handle, attribute_handle, 0); + if (err) { + abort(); + } + } + + /** + * Handle reception of a service (long) UUID. + */ + void handle_uuid_read(const ble_gattc_evt_t &evt) + { + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + const ble_gattc_evt_read_rsp_t &rsp = evt.params.read_rsp; + + uint16_t expected_handle = bytes_to_u16(&response[idx][0]); + + if (rsp.handle != expected_handle || rsp.offset != 0 || rsp.len != 16) { + abort(); + } + + memcpy(&response[idx][4], rsp.data, rsp.len); + + ++idx; + + if (idx == count) { + terminate(SimpleAttReadByGroupTypeResponse( + sizeof(packed_discovery_response_t), + make_const_ArrayView( + reinterpret_cast(response), + count * sizeof(packed_discovery_response_t) + )) + ); + } else { + read_service_uuid(); + } + } + + typedef uint8_t packed_discovery_response_t[20]; + + packed_discovery_response_t* response; + uint16_t count; + uint16_t idx; +}; + + +/** + * Procedure that manage Discover Primary Service by Service UUID transactions. + * + * @note Even if the softdevice doesn't forward the complete content of the peer + * response it is possible to reconstruct it by keeping a copy of the UUID to + * find. + */ +struct nRF5XGattClient::DiscoverPrimaryServiceByUUIDProcedure : RegularGattProcedure { + + typedef ArrayView services_array_t; + + DiscoverPrimaryServiceByUUIDProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::FIND_BY_TYPE_VALUE_REQUEST, + BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP + ), + _service_uuid() { } + + ble_error_t start(attribute_handle_t begining, const UUID &uuid) + { + ble_uuid_t nordic_uuid; + ble_error_t ble_err = to_nordic_uuid(uuid, nordic_uuid); + if (ble_err) { + return ble_err; + } + + uint32_t err = sd_ble_gattc_primary_services_discover( + connection_handle, begining, &nordic_uuid + ); + if (!err) { + _service_uuid = uuid; + } + + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + services_array_t services( + evt.params.prim_srvc_disc_rsp.services, + evt.params.prim_srvc_disc_rsp.count + ); + + /** + * Implementation of AttReadByGroupTypeResponse that addapt Nordic data + * structure. + */ + struct CustomAttReadByGroupTypeResponse : AttReadByGroupTypeResponse { + CustomAttReadByGroupTypeResponse(const services_array_t &s, const UUID &u) : + AttReadByGroupTypeResponse(), services(s), uuid(u) { + } + + virtual size_t size() const + { + return services.size(); + } + + virtual attribute_data_t operator[](size_t i) const + { + attribute_data_t result = { + to_ble_handle_range(services[i].handle_range), + make_ArrayView(uuid.getBaseUUID(), uuid.getLen()) + }; + return result; + } + + const services_array_t &services; + const UUID &uuid; + }; + + terminate(CustomAttReadByGroupTypeResponse(services, _service_uuid)); + } + + UUID _service_uuid; +}; + + +/** + * Procedure that manage Find Included Services transactions. + */ +struct nRF5XGattClient::FindIncludedServicesProcedure : RegularGattProcedure { + + typedef ArrayView services_array_t; + + FindIncludedServicesProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::READ_BY_TYPE_REQUEST, + BLE_GATTC_EVT_REL_DISC_RSP + ) { } + + ble_error_t start(attribute_handle_range_t service_range) + { + ble_gattc_handle_range_t range = to_nordic_handle_range(service_range); + uint32_t err = sd_ble_gattc_relationships_discover( + connection_handle, &range + ); + + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + // recompose the message into a raw att read by type response. + const ble_gattc_evt_rel_disc_rsp_t &resp = evt.params.rel_disc_rsp; + + bool contain_short_uuid = + (resp.includes[0].included_srvc.uuid.type == BLE_UUID_TYPE_BLE); + + uint8_t element_size = 6; + if (contain_short_uuid) { + element_size += 2; + } + + // It would be more efficient to use an API like alloca but it is + // unavailable and unsafe. Another alternative would be to have a fixed + // size stack buffer since the size of the MTU is fixed however once new + // softdevices lands could would have to be rewritten because they support + // variable MTU size. + size_t buffer_size = element_size * resp.count; + uint8_t* buffer = new(std::nothrow) uint8_t[buffer_size]; + if (!buffer) { + abort(); + } + + uint8_t *it = buffer; + for(size_t i = 0; i < resp.count; ++i) { + u16_to_stream(it, resp.includes[i].handle); + u16_to_stream(it, resp.includes[i].included_srvc.handle_range.start_handle); + u16_to_stream(it, resp.includes[i].included_srvc.handle_range.end_handle); + if (contain_short_uuid) { + u16_to_stream(it, resp.includes[i].included_srvc.uuid.uuid); + } + } + + terminate(SimpleAttReadByTypeResponse( + element_size, + make_const_ArrayView(buffer, buffer_size) + )); + + delete[] buffer; + } + + UUID _service_uuid; +}; + + +/** + * Procedure that handle Discover All Characteristics of a Service transactions. + * + * The softdevice doesn't forward to user UUID of services that are 128 bit long. + * In such case a read request is issued for each attribute handle of + * characteristics that exposes a long UUID. + */ +struct nRF5XGattClient::DiscoverCharacteristicsProcedure : GattProcedure { + /** + * Data structure returned by the function flatten_response. + */ + struct read_by_type_response_t { + uint16_t count; + uint16_t element_size; + uint8_t* buffer; + }; + + DiscoverCharacteristicsProcedure(connection_handle_t connection) : + GattProcedure(connection, AttributeOpcode::READ_BY_TYPE_REQUEST), + _response(), _idx(0) { } + + virtual ~DiscoverCharacteristicsProcedure() + { + if (_response.buffer) { + delete[] _response.buffer; + } + } + + ble_error_t start(attribute_handle_range_t discovery_range) + { + ble_gattc_handle_range_t range = to_nordic_handle_range(discovery_range); + uint32_t err = sd_ble_gattc_characteristics_discover( + connection_handle, + &range + ); + + return convert_sd_error(err); + } + + /** + * Dispatch ble events to the appropriate handler: + * - handle_characteristic_discovered: For a discovery response. + * - handle_uuid_read: For a read response. + */ + virtual void handle(const ble_evt_t &evt) + { + switch (evt.header.evt_id) { + case BLE_GATTC_EVT_CHAR_DISC_RSP: + handle_characteristic_discovered(evt.evt.gattc_evt); + return; + case BLE_GATTC_EVT_READ_RSP: + handle_uuid_read(evt.evt.gattc_evt); + return; + default: + abort(); + return; + } + } + + void handle_characteristic_discovered(const ble_gattc_evt_t &evt) + { + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_BY_TYPE_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + // layout the data structure into a flat byte array. + _response = flatten_response(evt.params.char_disc_rsp); + if (!_response.buffer) { + abort(); + } + + // If element size is equal to 7 then the characteristic discovered + // have 16 bit UUID. It is not necessary to read their characteristic + // declaration attribute. + if (_response.element_size == 7) { + forward_response_and_terminate(); + } else { + // 128 bit UUID. + // read sequentially each characteristic declaration attribute + // discovered. + _idx = 0; + read_characteristic_uuid(); + } + } + + /** + * Initiate read of the next characteristic declaration attribute. + */ + void read_characteristic_uuid(void) + { + // note: use read multiple once different mtu size are supported ? + uint16_t attribute_handle = + bytes_to_u16(&_response.buffer[_idx * _response.element_size]); + + uint32_t err = sd_ble_gattc_read(connection_handle, attribute_handle, 0); + if (err) { + abort(); + } + } + + /** + * Handle read response of a characteristic declaration attribute. + * It add the data in the response then initiate the read of the next + * attribute or terminate the procedure if all characteristic declaration + * attributes have been read. + */ + void handle_uuid_read(const ble_gattc_evt_t &evt) + { + // should never happen + if (!_response.buffer) { + abort(); + } + + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + const ble_gattc_evt_read_rsp_t &rsp = evt.params.read_rsp; + uint8_t* current_element = &_response.buffer[_idx * _response.element_size]; + uint16_t expected_handle = bytes_to_u16(current_element); + + if (rsp.handle != expected_handle || rsp.offset != 0 || rsp.len != (1 + 2 + 16)) { + abort(); + } + + // note: elements are the pair characteristic declaration handle followed + // by the attribute value. + memcpy(current_element + 2, rsp.data, rsp.len); + + ++_idx; + + if (_idx == _response.count) { + forward_response_and_terminate(); + } else { + read_characteristic_uuid(); + } + } + + /** + * Terminate the procedure by forwarding the AttReadByTypeResponse built. + */ + void forward_response_and_terminate() { + terminate(SimpleAttReadByTypeResponse( + _response.element_size, + make_const_ArrayView( + _response.buffer, + _response.element_size * _response.count + ) + )); + } + + /** + * Convert a ble_gattc_evt_char_disc_rsp_t into a raw response. + * + * If UUIDs present are 16 bits long then the output contain the whole + * response. Otherwise only the handle declaration of each characteristic + * discovered is present and properties, handle value and UUID are populated + * by reading the attribute handle. + */ + static read_by_type_response_t flatten_response(const ble_gattc_evt_char_disc_rsp_t& resp) + { + read_by_type_response_t result = { resp.count, 0 }; + + bool short_uuid = (resp.chars[0].uuid.type == BLE_UUID_TYPE_BLE); + + // att handle + prop + value handle + uuid size + result.element_size = 5 + (short_uuid ? 2 : 16) ; + + size_t buffer_size = resp.count * result.element_size; + result.buffer = new(std::nothrow) uint8_t[buffer_size]; + if(!result.buffer) { + return result; + } + + uint8_t *it = result.buffer; + for(size_t i = 0; i < resp.count; ++i) { + u16_to_stream(it, resp.chars[i].handle_decl); + if (short_uuid) { + *it++ = get_properties(resp.chars[i]); + u16_to_stream(it, resp.chars[i].handle_value); + u16_to_stream(it, resp.chars[i].uuid.uuid); + } else { + // leave the characteristic value declaration empty; it will be + // fullfiled by a read of the attribute. + it += (1 + 2 + 16); + } + } + + return result; + } + + /** + * Compute characteristic properties from ble_gattc_char_t. + */ + static uint8_t get_properties(const ble_gattc_char_t& char_desc) + { + return + (char_desc.char_props.broadcast << 0) | + (char_desc.char_props.read << 1) | + (char_desc.char_props.write_wo_resp << 2) | + (char_desc.char_props.write << 3) | + (char_desc.char_props.notify << 4) | + (char_desc.char_props.indicate << 5) | + (char_desc.char_props.auth_signed_wr << 6) | + (char_desc.char_ext_props << 7); + } + + read_by_type_response_t _response; + uint16_t _idx; +}; + +/** + * Procedure that handle discovery of characteristic descriptors. + */ +struct nRF5XGattClient::DiscoverDescriptorsProcedure : RegularGattProcedure { + DiscoverDescriptorsProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::FIND_INFORMATION_REQUEST, + BLE_GATTC_EVT_ATTR_INFO_DISC_RSP + ) { + } + + ble_error_t start(attribute_handle_range_t discovery_range) + { + ble_gattc_handle_range_t range = to_nordic_handle_range(discovery_range); + uint32_t err = sd_ble_gattc_attr_info_discover( + connection_handle, + &range + ); + + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + /** + * Adapt ble_gattc_evt_attr_info_disc_rsp_t into + * pal::AttFindInformationResponse + */ + struct CustomFindInformationResponse : AttFindInformationResponse { + CustomFindInformationResponse(const ble_gattc_evt_attr_info_disc_rsp_t &resp) : + AttFindInformationResponse(), response(resp) {} + + virtual size_t size() const + { + return response.count; + } + + virtual information_data_t operator[](size_t i) const + { + information_data_t result = { + response.attr_info[i].handle + }; + + if (response.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { + result.uuid = UUID(response.attr_info[i].info.uuid16.uuid); + } else { + result.uuid = UUID( + response.attr_info[i].info.uuid128.uuid128, + UUID::LSB + ); + } + + return result; + } + + const ble_gattc_evt_attr_info_disc_rsp_t &response; + }; + + terminate(CustomFindInformationResponse(evt.params.attr_info_disc_rsp)); + } +}; + + +/** + * Procedure that handle read of attribute handles. + */ +struct nRF5XGattClient::ReadAttributeProcedure : RegularGattProcedure { + ReadAttributeProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, AttributeOpcode::READ_REQUEST, BLE_GATTC_EVT_READ_RSP + ) { } + + ble_error_t start(attribute_handle_t attribute_handle) + { + uint32_t err = sd_ble_gattc_read(connection_handle, attribute_handle, 0); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_read_rsp_t& rsp = evt.params.read_rsp; + if (rsp.offset != 0 ) { + abort(); + } + + terminate(AttReadResponse(make_const_ArrayView(rsp.data, rsp.len))); + } +}; + +/** + * Procedure that handle read of characteristic using characteristic UUID. + */ +struct nRF5XGattClient::ReadUsingCharacteristicUUIDProcedure : RegularGattProcedure { + ReadUsingCharacteristicUUIDProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::READ_BY_TYPE_REQUEST, + BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP + ) { } + + ble_error_t start(attribute_handle_range_t read_range, const UUID& uuid) + { + ble_uuid_t nordic_uuid = { 0 }; + ble_error_t ble_err = to_nordic_uuid(uuid, nordic_uuid); + if (ble_err) { + return ble_err; + } + + ble_gattc_handle_range_t range = { + read_range.begin, + read_range.end + }; + + uint32_t err = sd_ble_gattc_char_value_by_uuid_read( + connection_handle, + &nordic_uuid, + &range + ); + return convert_sd_error(err); + } + + /** + * Adapt ble_gattc_evt_char_val_by_uuid_read_rsp_t into AttReadByTypeResponse. + */ + virtual void do_handle(const ble_gattc_evt_t &evt) + { + struct CustomReadByTypeResponse : AttReadByTypeResponse { + CustomReadByTypeResponse(const ble_gattc_evt_char_val_by_uuid_read_rsp_t& rsp) : + AttReadByTypeResponse(), response(rsp) { } + + virtual size_t size() const + { + return response.count; + } + + virtual attribute_data_t operator[](size_t i) const + { + attribute_data_t result = { + response.handle_value[i].handle, + make_const_ArrayView( + response.handle_value[i].p_value, + response.value_len + ) + }; + return result; + } + + const ble_gattc_evt_char_val_by_uuid_read_rsp_t& response; + } + + terminate(CustomReadByTypeResponse(evt.params.char_val_by_uuid_read_rsp)); + } +}; + +/** + * Procedure that handles read blob transactions. + */ +struct nRF5XGattClient::ReadAttributeBlobProcedure : RegularGattProcedure { + ReadAttributeBlobProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, AttributeOpcode::READ_BLOB_REQUEST, BLE_GATTC_EVT_READ_RSP + ) { } + + ble_error_t start(attribute_handle_t attribute_handle, uint16_t offset) + { + uint32_t err = sd_ble_gattc_read( + connection_handle, attribute_handle, offset + ); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + terminate(AttReadBlobResponse(make_const_ArrayView( + evt.params.read_rsp.data, + evt.params.read_rsp.len + ))); + } +}; + +/** + * Procedure that handles Read Multiple Characteristic Values transactions. + */ +struct nRF5XGattClient::ReadMultipleCharacteristicsProcedure : RegularGattProcedure { + ReadMultipleCharacteristicsProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::READ_MULTIPLE_REQUEST, + BLE_GATTC_EVT_CHAR_VALS_READ_RSP + ) { } + + ble_error_t start(const ArrayView& characteristic_handles) + { + uint32_t err = sd_ble_gattc_char_values_read( + connection_handle, + characteristic_handles.data(), + characteristic_handles.size() + ); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + terminate(AttReadMultipleResponse(make_const_ArrayView( + evt.params.char_vals_read_rsp.values, + evt.params.char_vals_read_rsp.len + ))); + } +}; + +/** + * Procedure that handles Write transactions. + */ +struct nRF5XGattClient::WriteAttributeProcedure : RegularGattProcedure { + WriteAttributeProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, AttributeOpcode::WRITE_REQUEST, BLE_GATTC_EVT_WRITE_RSP + ) { } + + ble_error_t start( + attribute_handle_t attribute_handle, const ArrayView& value + ) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_WRITE_REQ, + /* exec flags */ 0, + attribute_handle, + /* offset */ 0, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + terminate(AttWriteResponse()); + } +}; + +/** + * Procedure that handles Prepare Write transactions. + */ +struct nRF5XGattClient::QueuePrepareWriteProcedure : RegularGattProcedure { + QueuePrepareWriteProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::PREPARE_WRITE_REQUEST, + BLE_GATTC_EVT_WRITE_RSP + ) { } + + ble_error_t start( + attribute_handle_t characteristic_value_handle, + const ArrayView& value, + uint16_t offset + ) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_PREP_WRITE_REQ, + /* exec flags */ 0, + characteristic_value_handle, + offset, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_write_rsp_t &response = evt.params.write_rsp; + + if (response.write_op != BLE_GATT_OP_PREP_WRITE_REQ) { + abort(); + return; + } + + terminate(AttPrepareWriteResponse( + response.handle, + response.offset, + make_const_ArrayView(response.data, response.len) + )); + } +}; + +/** + * Procedure that handles Execute Write transactions. + */ +struct nRF5XGattClient::ExecuteWriteQueueProcedure : RegularGattProcedure { + ExecuteWriteQueueProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::EXECUTE_WRITE_REQUEST, + BLE_GATTC_EVT_WRITE_RSP + ) { } + + ble_error_t start(bool execute) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_EXEC_WRITE_REQ, + static_cast( + execute ? + BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL : + BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE + ), + /* attribute handle */ 0, + /* value offset */ 0, + /* buffer size*/ 0, + /* buffer data */ NULL + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_write_rsp_t &response = evt.params.write_rsp; + if (response.write_op != BLE_GATT_OP_EXEC_WRITE_REQ) { + abort(); + return; + } + + terminate(AttExecuteWriteResponse()); + } +}; + +// NOTE: position after declaration of GattProcedure on purpose. +ble_error_t nRF5XGattClient::terminate() +{ + for (size_t i = 0; i < max_procedures_count; ++i) { + if (_procedures[i]) { + _procedures[i]->abort(); + _procedures[i] = NULL; + } + } + + return BLE_ERROR_NONE; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, const A0& a0 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, const A0& a0, const A1& a1 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0, a1); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0, a1, a2); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2, const A3& a3 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0, a1, a2, a3); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +nRF5XGattClient::GattProcedure* nRF5XGattClient::get_procedure( + connection_handle_t connection +) const { + for (size_t i = 0; i < max_procedures_count; ++i) { + if (_procedures[i] && _procedures[i]->connection_handle == connection) { + return _procedures[i]; + } + } + return NULL; +} + +bool nRF5XGattClient::register_procedure(GattProcedure *p) +{ + if (get_procedure(p->connection_handle)) { + return false; + } + + for (size_t i = 0; i < max_procedures_count; ++i) { + if (!_procedures[i]) { + _procedures[i] = p; + return true; + } + } + + return false; +} + +bool nRF5XGattClient::remove_procedure(nRF5XGattClient::GattProcedure* p) +{ + for (size_t i = 0; i < max_procedures_count; ++i) { + if (_procedures[i] == p) { + _procedures[i] = NULL; + return true; + } + } + + return false; +} + +// singleton of the ARM Cordio client +nRF5XGattClient& nRF5XGattClient::get_client() +{ + static nRF5XGattClient _client; + return _client; +} + +void nRF5XGattClient::handle_events(const ble_evt_t *evt) { + switch (evt->header.evt_id) { + case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: + case BLE_GATTC_EVT_REL_DISC_RSP: + case BLE_GATTC_EVT_CHAR_DISC_RSP: + case BLE_GATTC_EVT_DESC_DISC_RSP: + case BLE_GATTC_EVT_ATTR_INFO_DISC_RSP: + case BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP: + case BLE_GATTC_EVT_READ_RSP: + case BLE_GATTC_EVT_CHAR_VALS_READ_RSP: + case BLE_GATTC_EVT_WRITE_RSP: + get_client().handle_procedure_event(*evt); + break; + case BLE_GATTC_EVT_HVX: + get_client().handle_hvx_event(*evt); + break; + case BLE_GATTC_EVT_TIMEOUT: + get_client().handle_timeout_event(*evt); + break; + } +} + +void nRF5XGattClient::handle_procedure_event(const ble_evt_t &evt) +{ + GattProcedure* p = get_procedure(evt.evt.gattc_evt.conn_handle); + if (p) { + p->handle(evt); + } +} + +void nRF5XGattClient::handle_hvx_event(const ble_evt_t &evt) +{ + connection_handle_t connection = evt.evt.gattc_evt.conn_handle; + const ble_gattc_evt_hvx_t &hvx_evt = evt.evt.gattc_evt.params.hvx; + + switch (hvx_evt.type) { + case BLE_GATT_HVX_NOTIFICATION: + on_server_event( + connection, + AttHandleValueNotification( + hvx_evt.handle, + make_const_ArrayView(hvx_evt.data, hvx_evt.len) + ) + ); + return; + case BLE_GATT_HVX_INDICATION: + // send confirmation first then process the event + sd_ble_gattc_hv_confirm(connection, hvx_evt.handle); + on_server_event( + connection, + AttHandleValueIndication( + hvx_evt.handle, + make_const_ArrayView(hvx_evt.data, hvx_evt.len) + ) + ); + return; + default: + return; + } +} + +void nRF5XGattClient::handle_timeout_event(const ble_evt_t &evt) +{ + connection_handle_t connection = evt.evt.gattc_evt.conn_handle; + GattProcedure* p = get_procedure(connection); + if (p) { + p->abort(); + } + + on_transaction_timeout(connection); +} + +void nRF5XGattClient::handle_connection_termination(connection_handle_t connection) +{ + GattProcedure* p = get_client().get_procedure(connection); + if (p) { + p->abort(); + } +} + +} // cordio +} // vendor +} // pal +} // ble + + + + diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h new file mode 100644 index 0000000000..8776ae82e4 --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h @@ -0,0 +1,257 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_NORDIC_PAL_GATT_CLIENT_H_ +#define BLE_NORDIC_PAL_GATT_CLIENT_H_ + +#include "ble/pal/PalGattClient.h" +#include "ble/blecommon.h" +#include "ble/UUID.h" + +#include "nrf_ble_gatt.h" +#include "nrf_ble.h" +#include "nrf_ble_types.h" +#include "btle.h" + +namespace ble { +namespace pal { +namespace vendor { +namespace nordic { + +/** + * Implementation of pal::GattClient for the Nordic stack. + */ +class nRF5XGattClient : public ble::pal::GattClient { + +public: + nRF5XGattClient(); + + virtual ~nRF5XGattClient(); + + /** + * see pal::GattClient::initialize . + */ + virtual ble_error_t initialize(); + + /** + * see pal::GattClient::terminate . + */ + virtual ble_error_t terminate(); + + /** + * see pal::GattClient::exchange_mtu . + */ + virtual ble_error_t exchange_mtu(connection_handle_t connection); + + /** + * see pal::GattClient::get_mtu_size . + */ + virtual ble_error_t get_mtu_size( + connection_handle_t connection_handle, uint16_t& mtu_size + ); + + /** + * see pal::GattClient::discover_primary_service . + */ + virtual ble_error_t discover_primary_service( + connection_handle_t connection, + attribute_handle_t discovery_range_begining + ); + + /** + * see pal::GattClient::discover_primary_service_by_service_uuid . + */ + virtual ble_error_t discover_primary_service_by_service_uuid( + connection_handle_t connection_handle, + attribute_handle_t discovery_range_beginning, + const UUID& uuid + ); + + /** + * see pal::GattClient::find_included_service . + */ + virtual ble_error_t find_included_service( + connection_handle_t connection_handle, + attribute_handle_range_t service_range + ); + + /** + * see pal::GattClient::discover_characteristics_of_a_service . + */ + virtual ble_error_t discover_characteristics_of_a_service( + connection_handle_t connection_handle, + attribute_handle_range_t discovery_range + ); + + /** + * see pal::GattClient::discover_characteristics_descriptors . + */ + virtual ble_error_t discover_characteristics_descriptors( + connection_handle_t connection_handle, + attribute_handle_range_t descriptors_discovery_range + ); + + /** + * see pal::GattClient::read_attribute_value . + */ + virtual ble_error_t read_attribute_value( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle + ); + + /** + * see pal::GattClient::read_using_characteristic_uuid . + */ + virtual ble_error_t read_using_characteristic_uuid( + connection_handle_t connection_handle, + attribute_handle_range_t read_range, + const UUID& uuid + ); + + /** + * see pal::GattClient::read_attribute_blob . + */ + virtual ble_error_t read_attribute_blob( + connection_handle_t connection, + attribute_handle_t attribute_handle, + uint16_t offset + ); + + /** + * see pal::GattClient::read_multiple_characteristic_values . + */ + virtual ble_error_t read_multiple_characteristic_values( + connection_handle_t connection, + const ArrayView& characteristic_handles + ); + + /** + * see pal::GattClient::write_without_response . + */ + virtual ble_error_t write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value + ); + + /** + * see pal::GattClient::signed_write_without_response . + */ + virtual ble_error_t signed_write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value + ); + + /** + * see pal::GattClient::write_attribute . + */ + virtual ble_error_t write_attribute( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle, + const ArrayView& value + ); + + /** + * see pal::GattClient::queue_prepare_write . + */ + virtual ble_error_t queue_prepare_write( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value, + uint16_t offset + ); + + /** + * see pal::GattClient::execute_write_queue . + */ + virtual ble_error_t execute_write_queue( + connection_handle_t connection_handle, + bool execute + ); + + // singleton of the ARM Cordio client + static nRF5XGattClient& get_client(); + + /** + * Function call from btle.cpp + * + * Do not call directly. + */ + static void handle_events(const ble_evt_t *p_ble_evt); + + /** + * Called by btle.cpp when a disconnection happens. + */ + static void handle_connection_termination(connection_handle_t connection); + +private: + struct GattProcedure; + struct RegularGattProcedure; + struct DiscoverPrimaryServiceProcedure; + struct DiscoverPrimaryServiceByUUIDProcedure; + struct FindIncludedServicesProcedure; + struct DiscoverCharacteristicsProcedure; + struct DiscoverDescriptorsProcedure; + struct ReadAttributeProcedure; + struct ReadUsingCharacteristicUUIDProcedure; + struct ReadAttributeBlobProcedure; + struct ReadMultipleCharacteristicsProcedure; + struct WriteAttributeProcedure; + struct QueuePrepareWriteProcedure; + struct ExecuteWriteQueueProcedure; + + template + ble_error_t launch_procedure(connection_handle_t connection, const A0& a0); + + template + ble_error_t launch_procedure( + connection_handle_t connection, const A0& a0, const A1& a1 + ); + + template + ble_error_t launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2 + ); + + template + ble_error_t launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2, const A3& a3 + ); + + GattProcedure* get_procedure(connection_handle_t) const; + bool register_procedure(GattProcedure*); + bool remove_procedure(GattProcedure*); + + void handle_procedure_event(const ble_evt_t &evt); + void handle_hvx_event(const ble_evt_t &evt); + void handle_timeout_event(const ble_evt_t &evt); + + static const size_t max_procedures_count = + CENTRAL_LINK_COUNT + PERIPHERAL_LINK_COUNT; + + // Note: Ideally we would have used an array of variant here + GattProcedure* _procedures[max_procedures_count]; +}; + +} // cordio +} // vendor +} // pal +} // ble + +#endif /* BLE_NORDIC_PAL_GATT_CLIENT_H_ */ From 502bdf503835c288b5949f00dcae0299ada0678d Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 20 Dec 2017 16:26:40 +0000 Subject: [PATCH 105/118] BLE: Enable Generic client on Nordic targets. --- .../TARGET_NRF5/source/btle/btle.cpp | 35 +++++-------------- .../TARGET_NRF5/source/btle/btle.h | 7 ++++ .../TARGET_NRF5/source/nRF5xn.cpp | 12 +++---- .../TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h | 15 +++----- 4 files changed, 26 insertions(+), 43 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp index 811e715254..029016f9e4 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp @@ -51,11 +51,9 @@ extern "C" { } #include "nrf_ble_hci.h" -#include "btle_discovery.h" -#include "nRF5xGattClient.h" -#include "nRF5xServiceDiscovery.h" -#include "nRF5xCharacteristicDescriptorDiscoverer.h" +#include "nRF5XPalGattClient.h" + bool isEventsSignaled = false; @@ -67,23 +65,6 @@ extern "C" void SD_EVT_IRQHandler(void); // export the softdevice event handler static void btle_handler(ble_evt_t *p_ble_evt); -#if 0 -#define CENTRAL_LINK_COUNT (YOTTA_CFG_NORDIC_BLE_CENTRAL_LINKS) /**evt.gap_evt.params.connected.peer_addr; #if (NRF_SD_BLE_API_VERSION <= 2) const ble_gap_addr_t *own = &p_ble_evt->evt.gap_evt.params.connected.own_addr; - + gap.processConnectionEvent(handle, role, static_cast(peer->addr_type), peer->addr, @@ -275,9 +258,7 @@ static void btle_handler(ble_evt_t *p_ble_evt) #if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) // Close all pending discoveries for this connection - nRF5xGattClient& gattClient = ble.getGattClient(); - gattClient.characteristicDescriptorDiscoverer().terminate(handle, BLE_ERROR_INVALID_STATE); - gattClient.discovery().terminate(handle); + nRF5XGattClient::handle_connection_termination(handle); #endif gap.processDisconnectionEvent(handle, reason); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h index 021dd50513..dfeccef05b 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h @@ -26,6 +26,13 @@ extern "C" { #include "ble_srv_common.h" #include "headers/nrf_ble.h" +#define CENTRAL_LINK_COUNT 3 /**reset(); - if (error != BLE_ERROR_NONE) { - return error; - } + error = getGattClient().reset(); + if (error != BLE_ERROR_NONE) { + return error; } #endif diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h index 33c7926e0d..154b9e49dc 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h @@ -20,10 +20,10 @@ #include "ble/BLE.h" #include "ble/blecommon.h" #include "ble/BLEInstanceBase.h" +#include "ble/generic/GenericGattClient.h" #include "nRF5xGap.h" #include "nRF5xGattServer.h" -#include "nRF5xGattClient.h" #include "nRF5xSecurityManager.h" #include "btle.h" @@ -77,11 +77,8 @@ public: * * @return A reference to GattClient. */ - virtual nRF5xGattClient &getGattClient() { - if (gattClientInstance == NULL) { - gattClientInstance = new nRF5xGattClient(); - } - return *gattClientInstance; + virtual GattClient &getGattClient() { + return gattClient; } /** @@ -171,10 +168,8 @@ private: * If NULL, then GattServer has not been initialized. * The pointer has been declared as 'mutable' so that * it can be assigned inside a 'const' function. */ - mutable nRF5xGattClient *gattClientInstance; /**< Pointer to the GattClient object instance. - * If NULL, then GattClient has not been initialized. - * The pointer has been declared as 'mutable' so that - * it can be assigned inside a 'const' function. */ + ble::generic::GenericGattClient gattClient; + mutable nRF5xSecurityManager *securityManagerInstance; /**< Pointer to the SecurityManager object instance. * If NULL, then SecurityManager has not been initialized. * The pointer has been declared as 'mutable' so that From b6d40044fed2ca25f23bcd8752362da460efdb4b Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 20 Dec 2017 16:27:12 +0000 Subject: [PATCH 106/118] BLE: Remove old client implementation. --- .../source/btle/btle_discovery.cpp | 147 ------- .../TARGET_NRF5/source/btle/btle_discovery.h | 22 -- ...RF5xCharacteristicDescriptorDiscoverer.cpp | 325 ---------------- .../nRF5xCharacteristicDescriptorDiscoverer.h | 227 ----------- .../source/nRF5xDiscoveredCharacteristic.cpp | 63 --- .../source/nRF5xDiscoveredCharacteristic.h | 45 --- .../TARGET_NRF5/source/nRF5xGattClient.cpp | 50 --- .../TARGET_NRF5/source/nRF5xGattClient.h | 218 ----------- .../source/nRF5xServiceDiscovery.cpp | 329 ---------------- .../source/nRF5xServiceDiscovery.h | 366 ------------------ 10 files changed, 1792 deletions(-) delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp delete mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp deleted file mode 100644 index 5f7c899ae9..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp +++ /dev/null @@ -1,147 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "nRF5xServiceDiscovery.h" -#include "nRF5xCharacteristicDescriptorDiscoverer.h" -#include "nRF5xGattClient.h" -#include "nRF5xn.h" - -#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) -void bleGattcEventHandler(const ble_evt_t *p_ble_evt) -{ - nRF5xn &ble = nRF5xn::Instance(BLE::DEFAULT_INSTANCE); - nRF5xGattClient &gattClient = (nRF5xGattClient &) ble.getGattClient(); - nRF5xServiceDiscovery &sdSingleton = gattClient.discovery(); - nRF5xCharacteristicDescriptorDiscoverer &characteristicDescriptorDiscoverer = - gattClient.characteristicDescriptorDiscoverer(); - - switch (p_ble_evt->header.evt_id) { - case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: - switch (p_ble_evt->evt.gattc_evt.gatt_status) { - case BLE_GATT_STATUS_SUCCESS: - sdSingleton.setupDiscoveredServices(&p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp); - break; - - case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND: - default: - sdSingleton.terminate(); - break; - } - break; - - case BLE_GATTC_EVT_CHAR_DISC_RSP: - switch (p_ble_evt->evt.gattc_evt.gatt_status) { - case BLE_GATT_STATUS_SUCCESS: - sdSingleton.setupDiscoveredCharacteristics(&p_ble_evt->evt.gattc_evt.params.char_disc_rsp); - break; - - case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND: - default: - sdSingleton.terminateCharacteristicDiscovery(BLE_ERROR_NONE); - break; - } - break; - - case BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP: - if (sdSingleton.isActive()) { - sdSingleton.processDiscoverUUIDResponse(&p_ble_evt->evt.gattc_evt); - } - break; - - case BLE_GATTC_EVT_READ_RSP: { - GattReadCallbackParams response = { - /* .connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, - /* .handle = */ p_ble_evt->evt.gattc_evt.params.read_rsp.handle, - /* .offset = */ p_ble_evt->evt.gattc_evt.params.read_rsp.offset, - /* .len = */ p_ble_evt->evt.gattc_evt.params.read_rsp.len, - /* .data = */ p_ble_evt->evt.gattc_evt.params.read_rsp.data, - }; - gattClient.processReadResponse(&response); - } - break; - - case BLE_GATTC_EVT_WRITE_RSP: { - GattWriteCallbackParams response = { - /* .connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, - /* .handle = */ p_ble_evt->evt.gattc_evt.params.write_rsp.handle, - /* .writeOp = */ (GattWriteCallbackParams::WriteOp_t)(p_ble_evt->evt.gattc_evt.params.write_rsp.write_op), - /* .offset = */ p_ble_evt->evt.gattc_evt.params.write_rsp.offset, - /* .len = */ p_ble_evt->evt.gattc_evt.params.write_rsp.len, - /* .data = */ p_ble_evt->evt.gattc_evt.params.write_rsp.data, - }; - gattClient.processWriteResponse(&response); - } - break; - - case BLE_GATTC_EVT_HVX: { - GattHVXCallbackParams params = { - /* connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, - /* handle = */ p_ble_evt->evt.gattc_evt.params.hvx.handle, - /* type = */ static_cast(p_ble_evt->evt.gattc_evt.params.hvx.type), - /* len = */ p_ble_evt->evt.gattc_evt.params.hvx.len, - /* data = */ p_ble_evt->evt.gattc_evt.params.hvx.data - }; - - gattClient.processHVXEvent(¶ms); - } - break; - - case BLE_GATTC_EVT_DESC_DISC_RSP: { - uint16_t conn_handle = p_ble_evt->evt.gattc_evt.conn_handle; - uint16_t status = p_ble_evt->evt.gattc_evt.gatt_status; - const ble_gattc_evt_desc_disc_rsp_t& discovered_descriptors = p_ble_evt->evt.gattc_evt.params.desc_disc_rsp; - - switch(status) { - case BLE_GATT_STATUS_SUCCESS: - characteristicDescriptorDiscoverer.process( - conn_handle, - discovered_descriptors - ); - break; - case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND: - // end of discovery - characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_NONE); - break; - default: - characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_UNSPECIFIED); - break; - } - } break; - - case BLE_GATTC_EVT_ATTR_INFO_DISC_RSP : { - uint16_t conn_handle = p_ble_evt->evt.gattc_evt.conn_handle; - uint16_t status = p_ble_evt->evt.gattc_evt.gatt_status; - const ble_gattc_evt_attr_info_disc_rsp_t& infos = p_ble_evt->evt.gattc_evt.params.attr_info_disc_rsp; - - switch(status) { - case BLE_GATT_STATUS_SUCCESS: - characteristicDescriptorDiscoverer.processAttributeInformation( - conn_handle, - infos - ); - break; - default: - characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_UNSPECIFIED); - break; - } - - } break; - } - - sdSingleton.progressCharacteristicDiscovery(); - sdSingleton.progressServiceDiscovery(); -} -#endif diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h deleted file mode 100644 index 9b7613e782..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h +++ /dev/null @@ -1,22 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _BTLE_DISCOVERY_H_ -#define _BTLE_DISCOVERY_H_ - -void bleGattcEventHandler(const ble_evt_t *p_ble_evt); - -#endif /*_BTLE_DISCOVERY_H_*/ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp deleted file mode 100644 index 0dee44efbf..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp +++ /dev/null @@ -1,325 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "nRF5xCharacteristicDescriptorDiscoverer.h" -#include "headers/nrf_ble_err.h" -#include "ble/DiscoveredCharacteristicDescriptor.h" - -nRF5xCharacteristicDescriptorDiscoverer::nRF5xCharacteristicDescriptorDiscoverer() : - discoveryRunning() { - // nothing to do -} - -nRF5xCharacteristicDescriptorDiscoverer::~nRF5xCharacteristicDescriptorDiscoverer() { - // nothing to do -} - -ble_error_t nRF5xCharacteristicDescriptorDiscoverer::launch( - const DiscoveredCharacteristic& characteristic, - const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback -) { - Gap::Handle_t connHandle = characteristic.getConnectionHandle(); - // it is ok to deduce that the start handle for descriptors is after - // the characteristic declaration and the characteristic value declaration - // see BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part G] (3.3) - Gap::Handle_t descriptorStartHandle = characteristic.getDeclHandle() + 2; - Gap::Handle_t descriptorEndHandle = characteristic.getLastHandle(); - - // check if there is any descriptor to discover - if (descriptorEndHandle < descriptorStartHandle) { - CharacteristicDescriptorDiscovery::TerminationCallbackParams_t termParams = { - characteristic, - BLE_ERROR_NONE - }; - terminationCallback.call(&termParams); - return BLE_ERROR_NONE; - } - - // check if we can run this discovery - if (isConnectionInUse(connHandle)) { - return BLE_STACK_BUSY; - } - - // get a new discovery slot, if none are available, just return - Discovery* discovery = getAvailableDiscoverySlot(); - if(discovery == NULL) { - return BLE_STACK_BUSY; - } - - // try to launch the discovery - ble_error_t err = gattc_descriptors_discover(connHandle, descriptorStartHandle, descriptorEndHandle); - if(!err) { - // commit the new discovery to its slot - *discovery = Discovery(characteristic, discoveryCallback, terminationCallback); - } - - return err; -} - -bool nRF5xCharacteristicDescriptorDiscoverer::isActive(const DiscoveredCharacteristic& characteristic) const { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if(discoveryRunning[i].getCharacteristic() == characteristic) { - return true; - } - } - return false; -} - -void nRF5xCharacteristicDescriptorDiscoverer::requestTerminate(const DiscoveredCharacteristic& characteristic) { - Discovery* discovery = findRunningDiscovery(characteristic); - if(discovery) { - // call terminate anyway - terminate(discovery, BLE_ERROR_NONE); - } -} - -void nRF5xCharacteristicDescriptorDiscoverer::process(uint16_t connectionHandle, const ble_gattc_evt_desc_disc_rsp_t& descriptors) { - Discovery* discovery = findRunningDiscovery(connectionHandle); - // the discovery has been removed - if(!discovery) { - return; - } - - for (uint16_t i = 0; i < descriptors.count; ++i) { - const ble_gattc_desc_t& desc = descriptors.descs[i]; - const ble_uuid_t& uuid = desc.uuid; - - if (uuid.type == BLE_UUID_TYPE_BLE) { - discovery->process( - desc.handle, UUID(uuid.uuid) - ); - } else { - // discover attribute infos of the descriptor - ble_error_t err = gattc_attr_info_discover(connectionHandle, desc.handle, desc.handle); - if (err) { - terminate(discovery, err); - } - - return; - } - } - - // prepare the next discovery request (if needed) - uint16_t startHandle = descriptors.descs[descriptors.count - 1].handle + 1; - uint16_t endHandle = discovery->getCharacteristic().getLastHandle(); - - if(startHandle > endHandle) { - terminate(discovery, BLE_ERROR_NONE); - return; - } - - ble_error_t err = gattc_descriptors_discover(connectionHandle, startHandle, endHandle); - if(err) { - terminate(discovery, err); - return; - } -} - -void nRF5xCharacteristicDescriptorDiscoverer::processAttributeInformation( - uint16_t connectionHandle, const ble_gattc_evt_attr_info_disc_rsp_t& infos) { - Discovery* discovery = findRunningDiscovery(connectionHandle); - // the discovery has been removed - if(!discovery) { - return; - } - -#if (NRF_SD_BLE_API_VERSION <= 2) - // for all UUIDS found, process the discovery - for (uint16_t i = 0; i < infos.count; ++i) { - bool use_16bits_uuids = infos.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT; - const ble_gattc_attr_info_t& attr_info = infos.attr_info[i]; - UUID uuid = use_16bits_uuids ? UUID(attr_info.info.uuid16.uuid) : UUID(attr_info.info.uuid128.uuid128, UUID::LSB); - discovery->process(attr_info.handle, uuid); - } - - // prepare the next round of descriptors discovery - uint16_t startHandle = infos.attr_info[infos.count - 1].handle + 1; -#else - uint16_t startHandle; - // for all UUIDS found, process the discovery - if (infos.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { - for (uint16_t i = 0; i < infos.count; ++i) { - UUID uuid = UUID(infos.info.attr_info16[i].uuid.uuid); - discovery->process(infos.info.attr_info16[i].handle, uuid); - } - - // prepare the next round of descriptors discovery - startHandle = infos.info.attr_info16[infos.count - 1].handle + 1; - } else { - for (uint16_t i = 0; i < infos.count; ++i) { - UUID uuid = UUID(infos.info.attr_info128[i].uuid.uuid128, UUID::LSB); - discovery->process(infos.info.attr_info128[i].handle, uuid); - } - - // prepare the next round of descriptors discovery - startHandle = infos.info.attr_info128[infos.count - 1].handle + 1; - } -#endif - uint16_t endHandle = discovery->getCharacteristic().getLastHandle(); - - if(startHandle > endHandle) { - terminate(discovery, BLE_ERROR_NONE); - return; - } - - ble_error_t err = gattc_descriptors_discover(connectionHandle, startHandle, endHandle); - if(err) { - terminate(discovery, err); - return; - } -} - -void nRF5xCharacteristicDescriptorDiscoverer::terminate(uint16_t handle, ble_error_t err) { - Discovery* discovery = findRunningDiscovery(handle); - // the discovery has already been terminated - if(!discovery) { - return; - } - - terminate(discovery, err); -} - -void nRF5xCharacteristicDescriptorDiscoverer::terminate(Discovery* discovery, ble_error_t err) { - // temporary copy, user code can try to launch a new discovery in the onTerminate - // callback. So, this discovery should not appear in such case. - Discovery tmp = *discovery; - *discovery = Discovery(); - tmp.terminate(err); -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery* -nRF5xCharacteristicDescriptorDiscoverer::findRunningDiscovery(const DiscoveredCharacteristic& characteristic) { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if((discoveryRunning[i].getCharacteristic() == characteristic) && - (discoveryRunning[i].isEmpty() == false)) { - return &discoveryRunning[i]; - } - } - return NULL; -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery* -nRF5xCharacteristicDescriptorDiscoverer::findRunningDiscovery(uint16_t handle) { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if((discoveryRunning[i].getCharacteristic().getConnectionHandle() == handle) && - (discoveryRunning[i].isEmpty() == false)) { - return &discoveryRunning[i]; - } - } - return NULL; -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery* -nRF5xCharacteristicDescriptorDiscoverer::getAvailableDiscoverySlot() { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if(discoveryRunning[i].isEmpty()) { - return &discoveryRunning[i]; - } - } - return NULL; -} - -bool nRF5xCharacteristicDescriptorDiscoverer::isConnectionInUse(uint16_t connHandle) { - return findRunningDiscovery(connHandle) != NULL; -} - -ble_error_t nRF5xCharacteristicDescriptorDiscoverer::gattc_descriptors_discover( - uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle) { - - ble_gattc_handle_range_t discoveryRange = { - start_handle, - end_handle - }; - uint32_t err = sd_ble_gattc_descriptors_discover(connection_handle, &discoveryRange); - - switch(err) { - case NRF_SUCCESS: - return BLE_ERROR_NONE; - case BLE_ERROR_INVALID_CONN_HANDLE: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_INVALID_ADDR: - return BLE_ERROR_PARAM_OUT_OF_RANGE; - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - default: - return BLE_ERROR_UNSPECIFIED; - } -} - -ble_error_t nRF5xCharacteristicDescriptorDiscoverer::gattc_attr_info_discover( - uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle) { - ble_gattc_handle_range_t handle_range = { start_handle, end_handle }; - uint32_t err = sd_ble_gattc_attr_info_discover(connection_handle, &handle_range); - - switch(err) { - case NRF_SUCCESS: - return BLE_ERROR_NONE; - case BLE_ERROR_INVALID_CONN_HANDLE: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_INVALID_ADDR: - return BLE_ERROR_PARAM_OUT_OF_RANGE; - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - case NRF_ERROR_INVALID_STATE: - return BLE_ERROR_INVALID_STATE; - default: - return BLE_ERROR_UNSPECIFIED; - } -} - - - -// implementation of nRF5xCharacteristicDescriptorDiscoverer::Discovery - -nRF5xCharacteristicDescriptorDiscoverer::Discovery::Discovery() : - characteristic(), onDiscovery(), onTerminate() { -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery::Discovery( - const DiscoveredCharacteristic& c, const DiscoveryCallback_t& dCb, const TerminationCallback_t& tCb) : - characteristic(c), onDiscovery(dCb), onTerminate(tCb) { -} - -void nRF5xCharacteristicDescriptorDiscoverer::Discovery::process( - GattAttribute::Handle_t handle, const UUID& uuid) { - CharacteristicDescriptorDiscovery::DiscoveryCallbackParams_t params = { - characteristic, - DiscoveredCharacteristicDescriptor( - characteristic.getGattClient(), - characteristic.getConnectionHandle(), - handle, - uuid - ) - }; - onDiscovery.call(¶ms); -} - -void nRF5xCharacteristicDescriptorDiscoverer::Discovery::terminate(ble_error_t err) { - CharacteristicDescriptorDiscovery::TerminationCallbackParams_t params = { - characteristic, - err - }; - - onTerminate.call(¶ms); -} - -bool nRF5xCharacteristicDescriptorDiscoverer::Discovery::isEmpty() const { - return *this == Discovery(); -} - -const DiscoveredCharacteristic& nRF5xCharacteristicDescriptorDiscoverer::Discovery::getCharacteristic() const { - return characteristic; -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h deleted file mode 100644 index 753e368f0f..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h +++ /dev/null @@ -1,227 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__ -#define __NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__ - -#include "ble/Gap.h" -#include "ble/DiscoveredCharacteristic.h" -#include "ble/CharacteristicDescriptorDiscovery.h" -#include "ble/GattClient.h" -#include "headers/nrf_ble_gattc.h" - -/** - * @brief Manage the discovery of Characteristic descriptors - * @details is a bridge between BLE API and Nordic stack regarding Characteristic - * Descriptor discovery. The BLE API can launch, monitor and ask for termination - * of a discovery. The Nordic stack will provide new descriptors and indicate when - * the discovery is done. - */ -class nRF5xCharacteristicDescriptorDiscoverer -{ - typedef CharacteristicDescriptorDiscovery::DiscoveryCallback_t DiscoveryCallback_t; - typedef CharacteristicDescriptorDiscovery::TerminationCallback_t TerminationCallback_t; - -public: - /** - * @brief Construct a new characteristic descriptor discoverer. - */ - nRF5xCharacteristicDescriptorDiscoverer(); - - /** - * @brief Destroy a characteristic descriptor discoverer. - */ - ~nRF5xCharacteristicDescriptorDiscoverer(); - - /** - * Launch a new characteristic descriptor discovery for a given DiscoveredCharacteristic. - * @param characteristic The characteristic owning the descriptors to discover. - * @param discoveryCallback The callback called when a descriptor is discovered. - * @param terminationCallback The callback called when the discovery process end. - * @return BLE_ERROR_NONE if characteristic descriptor discovery is launched successfully; - * else an appropriate error. - * @note: this will be called by BLE API side. - */ - ble_error_t launch( - const DiscoveredCharacteristic& characteristic, - const DiscoveryCallback_t& discoveryCallback, - const TerminationCallback_t& terminationCallback - ); - - /** - * @brief indicate if a characteristic descriptor discovery is active for a - * given DiscoveredCharacteristic. - * @param characteristic The characteristic for whom the descriptor might be - * currently discovered. - * @return true if descriptors of characteristic are discovered, false otherwise. - * @note: this will be called by BLE API side. - */ - bool isActive(const DiscoveredCharacteristic& characteristic) const; - - /** - * @brief request the termination of characteristic descriptor discovery - * for a give DiscoveredCharacteristic - * @param characteristic The characteristic for whom the descriptor discovery - * should be stopped. - * @note: this will be called by BLE API side. - */ - void requestTerminate(const DiscoveredCharacteristic& characteristic); - - /** - * @brief process descriptors discovered from the Nordic stack. - * @param connectionHandle The connection handle upon which descriptors has been - * discovered. - * @param descriptors Discovered descriptors. - * @note This will be called by the Nordic stack. - */ - void process(uint16_t connectionHandle, const ble_gattc_evt_desc_disc_rsp_t& descriptors); - - /** - * @brief Called by the Nordic stack when the discovery is over. - * @param The connection handle upon which the discovery process is done. - * @param err An error if the termination is due to an error. - */ - void terminate(uint16_t connectionHandle, ble_error_t err); - - /** - * @brief process attribute informations from the Nordic stack. - * @param connectionHandle The connection handle upon which - * attribute informations has been fetch. - * @param infos Informations around attribute, in that case the - * 128bit UUID of a descriptor. - * @note This will be called by the Nordic stack. - */ - void processAttributeInformation(uint16_t handle, const ble_gattc_evt_attr_info_disc_rsp_t& infos); - -private: - // protection against copy construction and assignment - nRF5xCharacteristicDescriptorDiscoverer(const nRF5xCharacteristicDescriptorDiscoverer&); - nRF5xCharacteristicDescriptorDiscoverer& operator=(const nRF5xCharacteristicDescriptorDiscoverer&); - - /** - * @brief Discovery process, it store the DiscoveredCharacteristic, the - * discovery callback and the termination callback. - */ - class Discovery { - public: - /** - * @brief Construct an empty discovery, such can be considerate as a not running discovery. - * @note #isEmpty function will return true - */ - Discovery(); - - /** - * @brief Construct a valid discovery process. - * - * @param c the characteristic from whom descriptors will be discovered. - * @param dCb The discovery callback called each time a descriptor is discovered. - * @param tCb The termination callback called when the discovery terminate. - * - * @note #isEmpty function will return false - */ - Discovery(const DiscoveredCharacteristic& c, const DiscoveryCallback_t& dCb, const TerminationCallback_t& tCb); - - /** - * @brief Process the discovery of a descriptor. - * - * @param handle The attribute handle of the descriptor found - * @param uuid The UUID of the descriptor found. - */ - void process(GattAttribute::Handle_t handle, const UUID& uuid); - - /** - * @brief Terminate the discovery process. - * - * @param err Error associate with the termination - * @note after this call #isEmpty function will return true. - */ - void terminate(ble_error_t err); - - /** - * @brief check if the discovery process is empty or not. Empty discovery are - * not running. - * - * @detail Discovery are empty after: - * - a default construction - * - a copy construction form a default constructed - * - an assignment from a default constructed Discovery - * @return true if the Discovery is empty and false otherwise. - */ - bool isEmpty() const; - - /** - * @brief return the characteristic from whom descriptors are discovered. - * @return the characteristic from whom descriptors are discovered. - */ - const DiscoveredCharacteristic& getCharacteristic() const; - - /** - * @brief equal to operator, test if two discovery process are equal - * - * @param lhs left hand side of the expression - * @param rhs right hand side of the expression - * @return true if lhs == rhs - */ - friend bool operator==(const Discovery& lhs, const Discovery& rhs) { - return lhs.characteristic == rhs.characteristic && - lhs.onDiscovery == rhs.onDiscovery && - lhs.onTerminate == rhs.onTerminate; - } - - /** - * @brief not equal to operator, test if two discovery process are not equal - * - * @param lhs left hand side of the expression - * @param rhs right hand side of the expression - * @return true if lhs != rhs - */ - friend bool operator!=(const Discovery& lhs, const Discovery& rhs) { - return !(lhs == rhs); - } - - private: - DiscoveredCharacteristic characteristic; - DiscoveryCallback_t onDiscovery; - TerminationCallback_t onTerminate; - }; - - // find a running discovery process - Discovery* findRunningDiscovery(const DiscoveredCharacteristic& characteristic); - Discovery* findRunningDiscovery(uint16_t handle); - - // Called to terminate a discovery is over. - void terminate(Discovery* discovery, ble_error_t err); - - // get one slot for a discovery process - Discovery* getAvailableDiscoverySlot(); - - // indicate if a connection is already running a discovery - bool isConnectionInUse(uint16_t connHandle); - - // low level start of a discovery - static ble_error_t gattc_descriptors_discover(uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle); - - // discovery of 128bits UUIDS - static ble_error_t gattc_attr_info_discover(uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle); - - // count of concurrent connections which can run a descriptor discovery process - static const size_t MAXIMUM_CONCURRENT_CONNECTIONS_COUNT = 3; - - // array of running discoveries - Discovery discoveryRunning[MAXIMUM_CONCURRENT_CONNECTIONS_COUNT]; -}; - -#endif /*__NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__*/ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp deleted file mode 100644 index f7d6996f4d..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "nRF5xDiscoveredCharacteristic.h" -#include "nRF5xGattClient.h" -#include "headers/nrf_ble_gatt.h" - -void -nRF5xDiscoveredCharacteristic::setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn) -{ - gattc = gattcIn; - connHandle = connectionHandleIn; - declHandle = declHandleIn; - valueHandle = valueHandleIn; - - props._broadcast = propsIn.broadcast; - props._read = propsIn.read; - props._writeWoResp = propsIn.write_wo_resp; - props._write = propsIn.write; - props._notify = propsIn.notify; - props._indicate = propsIn.indicate; - props._authSignedWrite = propsIn.auth_signed_wr; -} - -void -nRF5xDiscoveredCharacteristic::setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - UUID::ShortUUIDBytes_t uuidIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn) -{ - gattc = gattcIn; - connHandle = connectionHandleIn; - uuid = uuidIn; - declHandle = declHandleIn; - valueHandle = valueHandleIn; - - props._broadcast = propsIn.broadcast; - props._read = propsIn.read; - props._writeWoResp = propsIn.write_wo_resp; - props._write = propsIn.write; - props._notify = propsIn.notify; - props._indicate = propsIn.indicate; - props._authSignedWrite = propsIn.auth_signed_wr; -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h deleted file mode 100644 index 87ebbbf767..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF_DISCOVERED_CHARACTERISTIC_H__ -#define __NRF_DISCOVERED_CHARACTERISTIC_H__ - -#include "ble/DiscoveredCharacteristic.h" -#include "headers/nrf_ble_gatt.h" - -class nRF5xGattClient; /* forward declaration */ - -class nRF5xDiscoveredCharacteristic : public DiscoveredCharacteristic { -public: - void setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn); - - void setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - UUID::ShortUUIDBytes_t uuidIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn); - - void setLastHandle(GattAttribute::Handle_t last) { - lastHandle = last; - } -}; - -#endif /* __NRF_DISCOVERED_CHARACTERISTIC_H__ */ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp deleted file mode 100644 index e79e47afa2..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp +++ /dev/null @@ -1,50 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "nRF5xGattClient.h" - -#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) -ble_error_t -nRF5xGattClient::launchServiceDiscovery(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t sc, - ServiceDiscovery::CharacteristicCallback_t cc, - const UUID &matchingServiceUUIDIn, - const UUID &matchingCharacteristicUUIDIn) -{ - return _discovery.launch(connectionHandle, sc, cc, matchingServiceUUIDIn, matchingCharacteristicUUIDIn); -} - -ble_error_t nRF5xGattClient::discoverCharacteristicDescriptors( - const DiscoveredCharacteristic& characteristic, - const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback) -{ - return _characteristicDescriptorDiscoverer.launch( - characteristic, - discoveryCallback, - terminationCallback - ); -} - -bool nRF5xGattClient::isCharacteristicDescriptorsDiscoveryActive(const DiscoveredCharacteristic& characteristic) const { - return _characteristicDescriptorDiscoverer.isActive(characteristic); -} - -void nRF5xGattClient::terminateCharacteristicDescriptorsDiscovery(const DiscoveredCharacteristic& characteristic) { - return _characteristicDescriptorDiscoverer.requestTerminate(characteristic); -} - -#endif diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h deleted file mode 100644 index 5670d15b9d..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h +++ /dev/null @@ -1,218 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF51822_GATT_CLIENT_H__ -#define __NRF51822_GATT_CLIENT_H__ - -#include "ble/GattClient.h" -#include "nRF5xServiceDiscovery.h" -#include "nRF5xCharacteristicDescriptorDiscoverer.h" - -class nRF5xGattClient : public GattClient -{ -public: - /** - * When using S110, all Gatt client features will return - * BLE_ERROR_NOT_IMPLEMENTED - */ -#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) - - /** - * Launch service discovery. Once launched, service discovery will remain - * active with callbacks being issued back into the application for matching - * services/characteristics. isActive() can be used to determine status; and - * a termination callback (if setup) will be invoked at the end. Service - * discovery can be terminated prematurely if needed using terminate(). - * - * @param connectionHandle - * Handle for the connection with the peer. - * @param sc - * This is the application callback for matching service. Taken as - * NULL by default. Note: service discovery may still be active - * when this callback is issued; calling asynchronous BLE-stack - * APIs from within this application callback might cause the - * stack to abort service discovery. If this becomes an issue, it - * may be better to make local copy of the discoveredService and - * wait for service discovery to terminate before operating on the - * service. - * @param cc - * This is the application callback for matching characteristic. - * Taken as NULL by default. Note: service discovery may still be - * active when this callback is issued; calling asynchronous - * BLE-stack APIs from within this application callback might cause - * the stack to abort service discovery. If this becomes an issue, - * it may be better to make local copy of the discoveredCharacteristic - * and wait for service discovery to terminate before operating on the - * characteristic. - * @param matchingServiceUUID - * UUID based filter for specifying a service in which the application is - * interested. By default it is set as the wildcard UUID_UNKNOWN, - * in which case it matches all services. If characteristic-UUID - * filter (below) is set to the wildcard value, then a service - * callback will be invoked for the matching service (or for every - * service if the service filter is a wildcard). - * @param matchingCharacteristicUUIDIn - * UUID based filter for specifying characteristic in which the application - * is interested. By default it is set as the wildcard UUID_UKNOWN - * to match against any characteristic. If both service-UUID - * filter and characteristic-UUID filter are used with non- wildcard - * values, then only a single characteristic callback is - * invoked for the matching characteristic. - * - * @Note Using wildcard values for both service-UUID and characteristic- - * UUID will result in complete service discovery--callbacks being - * called for every service and characteristic. - * - * @return - * BLE_ERROR_NONE if service discovery is launched successfully; else an appropriate error. - */ - virtual ble_error_t launchServiceDiscovery(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t sc = NULL, - ServiceDiscovery::CharacteristicCallback_t cc = NULL, - const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN), - const UUID &matchingCharacteristicUUIDIn = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)); - - virtual void onServiceDiscoveryTermination(ServiceDiscovery::TerminationCallback_t callback) { - _discovery.onTermination(callback); - } - - /** - * Is service-discovery currently active? - */ - virtual bool isServiceDiscoveryActive(void) const { - return _discovery.isActive(); - } - - /** - * Terminate an ongoing service-discovery. This should result in an - * invocation of the TerminationCallback if service-discovery is active. - */ - virtual void terminateServiceDiscovery(void) { - _discovery.terminate(); - } - - /** - * @brief Implementation of GattClient::discoverCharacteristicDescriptors - * @see GattClient::discoverCharacteristicDescriptors - */ - virtual ble_error_t discoverCharacteristicDescriptors( - const DiscoveredCharacteristic& characteristic, - const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback - ); - - /** - * @brief Implementation of GattClient::isCharacteristicDiscoveryActive - * @see GattClient::isCharacteristicDiscoveryActive - */ - virtual bool isCharacteristicDescriptorsDiscoveryActive(const DiscoveredCharacteristic& characteristic) const; - - /** - * @brief Implementation of GattClient::terminateCharacteristicDiscovery - * @see GattClient::terminateCharacteristicDiscovery - */ - virtual void terminateCharacteristicDescriptorsDiscovery(const DiscoveredCharacteristic& characteristic); - - virtual ble_error_t read(Gap::Handle_t connHandle, GattAttribute::Handle_t attributeHandle, uint16_t offset) const { - uint32_t rc = sd_ble_gattc_read(connHandle, attributeHandle, offset); - if (rc == NRF_SUCCESS) { - return BLE_ERROR_NONE; - } - switch (rc) { - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - case BLE_ERROR_INVALID_CONN_HANDLE: - case NRF_ERROR_INVALID_STATE: - case NRF_ERROR_INVALID_ADDR: - default: - return BLE_ERROR_INVALID_STATE; - } - } - - virtual ble_error_t write(GattClient::WriteOp_t cmd, Gap::Handle_t connHandle, GattAttribute::Handle_t attributeHandle, size_t length, const uint8_t *value) const { - ble_gattc_write_params_t writeParams; - writeParams.write_op = cmd; - writeParams.flags = 0; /* this is inconsequential */ - writeParams.handle = attributeHandle; - writeParams.offset = 0; - writeParams.len = length; - writeParams.p_value = const_cast(value); - - uint32_t rc = sd_ble_gattc_write(connHandle, &writeParams); - if (rc == NRF_SUCCESS) { - return BLE_ERROR_NONE; - } - switch (rc) { - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - case BLE_ERROR_NO_TX_PACKETS: - return BLE_ERROR_NO_MEM; - case BLE_ERROR_INVALID_CONN_HANDLE: - case NRF_ERROR_INVALID_STATE: - case NRF_ERROR_INVALID_ADDR: - default: - return BLE_ERROR_INVALID_STATE; - } - } - - /** - * @brief Clear nRF5xGattClient's state. - * - * @return - * BLE_ERROR_NONE if successful. - */ - virtual ble_error_t reset(void) { - /* Clear all state that is from the parent, including private members */ - if (GattClient::reset() != BLE_ERROR_NONE) { - return BLE_ERROR_INVALID_STATE; - } - - /* Clear derived class members */ - _discovery.reset(); - - return BLE_ERROR_NONE; - } - -public: - /* - * Allow instantiation from nRF5xn when required. - */ - friend class nRF5xn; - - nRF5xGattClient() : _discovery(this) { - /* empty */ - } - - nRF5xServiceDiscovery& discovery() { - return _discovery; - } - - nRF5xCharacteristicDescriptorDiscoverer& characteristicDescriptorDiscoverer() { - return _characteristicDescriptorDiscoverer; - } - -private: - nRF5xGattClient(const nRF5xGattClient &); - const nRF5xGattClient& operator=(const nRF5xGattClient &); - -private: - nRF5xServiceDiscovery _discovery; - nRF5xCharacteristicDescriptorDiscoverer _characteristicDescriptorDiscoverer; - -#endif // if !S110 -}; - -#endif // ifndef __NRF51822_GATT_CLIENT_H__ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp deleted file mode 100644 index 79f691bfcf..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp +++ /dev/null @@ -1,329 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "nRF5xServiceDiscovery.h" - -ble_error_t -nRF5xServiceDiscovery::launchCharacteristicDiscovery(Gap::Handle_t connectionHandle, - Gap::Handle_t startHandle, - Gap::Handle_t endHandle) -{ - characteristicDiscoveryStarted(connectionHandle); - - ble_gattc_handle_range_t handleRange = { - (uint16_t) startHandle, - (uint16_t) endHandle - }; - uint32_t rc = sd_ble_gattc_characteristics_discover(connectionHandle, &handleRange); - ble_error_t err = BLE_ERROR_NONE; - - switch (rc) { - case NRF_SUCCESS: - err = BLE_ERROR_NONE; - break; - case BLE_ERROR_INVALID_CONN_HANDLE: - case NRF_ERROR_INVALID_ADDR: - err = BLE_ERROR_INVALID_PARAM; - break; - case NRF_ERROR_BUSY: - err = BLE_STACK_BUSY; - break; - case NRF_ERROR_INVALID_STATE: - err = BLE_ERROR_INVALID_STATE; - break; - default: - err = BLE_ERROR_UNSPECIFIED; - break; - } - - if (err) { - terminateCharacteristicDiscovery(err); - } - return err; -} - -void -nRF5xServiceDiscovery::setupDiscoveredServices(const ble_gattc_evt_prim_srvc_disc_rsp_t *response) -{ - serviceIndex = 0; - numServices = response->count; - - /* Account for the limitation on the number of discovered services we can handle at a time. */ - if (numServices > BLE_DB_DISCOVERY_MAX_SRV) { - numServices = BLE_DB_DISCOVERY_MAX_SRV; - } - - serviceUUIDDiscoveryQueue.reset(); - for (unsigned i = 0; i < numServices; ++i) { - if (response->services[i].uuid.type == BLE_UUID_TYPE_UNKNOWN) { - serviceUUIDDiscoveryQueue.enqueue(i); - services[i].setup(response->services[i].handle_range.start_handle, - response->services[i].handle_range.end_handle); - } else { - services[i].setup(response->services[i].uuid.uuid, - response->services[i].handle_range.start_handle, - response->services[i].handle_range.end_handle); - } - } - - /* Trigger discovery of service UUID if necessary. */ - if (serviceUUIDDiscoveryQueue.getCount()) { - serviceUUIDDiscoveryQueue.triggerFirst(); - } -} - -void -nRF5xServiceDiscovery::setupDiscoveredCharacteristics(const ble_gattc_evt_char_disc_rsp_t *response) -{ - numCharacteristics = response->count; - - /* Account for the limitation on the number of discovered characteristics we can handle at a time. */ - if (numCharacteristics > BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV) { - numCharacteristics = BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV; - } - - charUUIDDiscoveryQueue.reset(); - for (unsigned charIndex = 0; charIndex < numCharacteristics; charIndex++) { - if (response->chars[charIndex].uuid.type == BLE_UUID_TYPE_UNKNOWN) { - charUUIDDiscoveryQueue.enqueue(charIndex); - characteristics[charIndex].setup(gattc, - connHandle, - response->chars[charIndex].char_props, - response->chars[charIndex].handle_decl, - response->chars[charIndex].handle_value); - } else { - characteristics[charIndex].setup(gattc, - connHandle, - response->chars[charIndex].uuid.uuid, - response->chars[charIndex].char_props, - response->chars[charIndex].handle_decl, - response->chars[charIndex].handle_value); - } - } - - /* Trigger discovery of char UUID if necessary. */ - if (charUUIDDiscoveryQueue.getCount()) { - charUUIDDiscoveryQueue.triggerFirst(); - } -} - -void -nRF5xServiceDiscovery::progressCharacteristicDiscovery(void) -{ - if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) { - return; - } - - if ((discoveredCharacteristic != nRF5xDiscoveredCharacteristic()) && (numCharacteristics > 0)) { - discoveredCharacteristic.setLastHandle(characteristics[0].getDeclHandle() - 1); - - if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - ((matchingCharacteristicUUID == discoveredCharacteristic.getUUID()) && - (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) { - if (characteristicCallback) { - characteristicCallback(&discoveredCharacteristic); - } - } - } - - for (uint8_t i = 0; i < numCharacteristics; ++i) { - if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) { - return; - } - - if (i == (numCharacteristics - 1)) { - discoveredCharacteristic = characteristics[i]; - break; - } else { - characteristics[i].setLastHandle(characteristics[i + 1].getDeclHandle() - 1); - } - - if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - ((matchingCharacteristicUUID == characteristics[i].getUUID()) && - (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) { - if (characteristicCallback) { - characteristicCallback(&characteristics[i]); - } - } - } - - if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) { - return; - } - - Gap::Handle_t startHandle = (numCharacteristics > 0) ? characteristics[numCharacteristics - 1].getValueHandle() + 1 : SRV_DISC_END_HANDLE; - Gap::Handle_t endHandle = services[serviceIndex].getEndHandle(); - resetDiscoveredCharacteristics(); /* Note: resetDiscoveredCharacteristics() must come after fetching start and end Handles. */ - - if (startHandle < endHandle) { - ble_gattc_handle_range_t handleRange = { - (uint16_t) startHandle, - (uint16_t) endHandle - }; - if (sd_ble_gattc_characteristics_discover(connHandle, &handleRange) != NRF_SUCCESS) { - terminateCharacteristicDiscovery(BLE_ERROR_UNSPECIFIED); - } - } else { - terminateCharacteristicDiscovery(BLE_ERROR_NONE); - } -} - -void -nRF5xServiceDiscovery::progressServiceDiscovery(void) -{ - /* Iterate through the previously discovered services cached in services[]. */ - while ((state == SERVICE_DISCOVERY_ACTIVE) && (serviceIndex < numServices)) { - if ((matchingServiceUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - (matchingServiceUUID == services[serviceIndex].getUUID())) { - - if (serviceCallback && (matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN))) { - serviceCallback(&services[serviceIndex]); - } - - if ((state == SERVICE_DISCOVERY_ACTIVE) && characteristicCallback) { - launchCharacteristicDiscovery(connHandle, services[serviceIndex].getStartHandle(), services[serviceIndex].getEndHandle()); - } else { - serviceIndex++; - } - } else { - serviceIndex++; - } - } - - /* Relaunch discovery of new services beyond the last entry cached in services[]. */ - if ((state == SERVICE_DISCOVERY_ACTIVE) && (numServices > 0) && (serviceIndex > 0)) { - /* Determine the ending handle of the last cached service. */ - Gap::Handle_t endHandle = services[serviceIndex - 1].getEndHandle(); - resetDiscoveredServices(); /* Note: resetDiscoveredServices() must come after fetching endHandle. */ - - if (endHandle == SRV_DISC_END_HANDLE) { - terminateServiceDiscovery(); - } else { - // the next service is located after the last handle discovered - // Launch a new discovery from [endHandle + 1 : 0xFFFF] - if (sd_ble_gattc_primary_services_discover(connHandle, endHandle + 1, NULL) != NRF_SUCCESS) { - terminateServiceDiscovery(); - } - } - } -} - -void -nRF5xServiceDiscovery::ServiceUUIDDiscoveryQueue::triggerFirst(void) -{ - while (numIndices) { /* loop until a call to char_value_by_uuid_read() succeeds or we run out of pending indices. */ - parentDiscoveryObject->state = DISCOVER_SERVICE_UUIDS; - - unsigned serviceIndex = getFirst(); - ble_uuid_t uuid = { - .uuid = BLE_UUID_SERVICE_PRIMARY, - .type = BLE_UUID_TYPE_BLE, - }; - ble_gattc_handle_range_t handleRange = { - .start_handle = parentDiscoveryObject->services[serviceIndex].getStartHandle(), - .end_handle = parentDiscoveryObject->services[serviceIndex].getEndHandle(), - }; - if (sd_ble_gattc_char_value_by_uuid_read(parentDiscoveryObject->connHandle, &uuid, &handleRange) == NRF_SUCCESS) { - return; - } - - /* Skip this service if we fail to launch a read for its service-declaration - * attribute. Its UUID will remain INVALID, and it may not match any filters. */ - dequeue(); - } - - /* Switch back to service discovery upon exhausting the service-indices pending UUID discovery. */ - if (parentDiscoveryObject->state == DISCOVER_SERVICE_UUIDS) { - parentDiscoveryObject->state = SERVICE_DISCOVERY_ACTIVE; - } -} - -void -nRF5xServiceDiscovery::CharUUIDDiscoveryQueue::triggerFirst(void) -{ - while (numIndices) { /* loop until a call to char_value_by_uuid_read() succeeds or we run out of pending indices. */ - parentDiscoveryObject->state = DISCOVER_CHARACTERISTIC_UUIDS; - - unsigned charIndex = getFirst(); - ble_uuid_t uuid = { - .uuid = BLE_UUID_CHARACTERISTIC, - .type = BLE_UUID_TYPE_BLE, - }; - ble_gattc_handle_range_t handleRange = { }; - handleRange.start_handle = parentDiscoveryObject->characteristics[charIndex].getDeclHandle(); - handleRange.end_handle = parentDiscoveryObject->characteristics[charIndex].getDeclHandle() + 1; - if (sd_ble_gattc_char_value_by_uuid_read(parentDiscoveryObject->connHandle, &uuid, &handleRange) == NRF_SUCCESS) { - return; - } - - /* Skip this service if we fail to launch a read for its service-declaration - * attribute. Its UUID will remain INVALID, and it may not match any filters. */ - dequeue(); - } - - /* Switch back to service discovery upon exhausting the service-indices pending UUID discovery. */ - if (parentDiscoveryObject->state == DISCOVER_CHARACTERISTIC_UUIDS) { - parentDiscoveryObject->state = CHARACTERISTIC_DISCOVERY_ACTIVE; - } -} - -void -nRF5xServiceDiscovery::processDiscoverUUIDResponse(const ble_gattc_evt_t *p_gattc_evt) -{ - const ble_gattc_evt_char_val_by_uuid_read_rsp_t * response = &p_gattc_evt->params.char_val_by_uuid_read_rsp; - - if (state == DISCOVER_SERVICE_UUIDS) { - if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID)) { - UUID::LongUUIDBytes_t uuid; - -#if (NRF_SD_BLE_API_VERSION >= 3) - ble_gattc_handle_value_t iter; - memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); - (void) sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(const_cast(p_gattc_evt), &iter); - memcpy(uuid, iter.p_value, UUID::LENGTH_OF_LONG_UUID); -#else - memcpy(uuid, &(response->handle_value[0].p_value[0]), UUID::LENGTH_OF_LONG_UUID); -#endif - - unsigned serviceIndex = serviceUUIDDiscoveryQueue.dequeue(); - services[serviceIndex].setupLongUUID(uuid, UUID::LSB); - - serviceUUIDDiscoveryQueue.triggerFirst(); - } else { - serviceUUIDDiscoveryQueue.dequeue(); - } - } else if (state == DISCOVER_CHARACTERISTIC_UUIDS) { - if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID + 1 /* props */ + 2 /* value handle */)) { - UUID::LongUUIDBytes_t uuid; - -#if (NRF_SD_BLE_API_VERSION >= 3) - ble_gattc_handle_value_t iter; - memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); - (void) sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(const_cast(p_gattc_evt), &iter); - memcpy(uuid, &(iter.p_value[3]), UUID::LENGTH_OF_LONG_UUID); -#else - memcpy(uuid, &(response->handle_value[0].p_value[3]), UUID::LENGTH_OF_LONG_UUID); -#endif - - unsigned charIndex = charUUIDDiscoveryQueue.dequeue(); - characteristics[charIndex].setupLongUUID(uuid, UUID::LSB); - - charUUIDDiscoveryQueue.triggerFirst(); - } else { - charUUIDDiscoveryQueue.dequeue(); - } - } -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h deleted file mode 100644 index 9fb28f1d79..0000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h +++ /dev/null @@ -1,366 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF_SERVICE_DISCOVERY_H__ -#define __NRF_SERVICE_DISCOVERY_H__ - -#include "ble/ServiceDiscovery.h" -#include "ble/DiscoveredService.h" -#include "nRF5xDiscoveredCharacteristic.h" - -#include "headers/nrf_ble.h" -#include "headers/nrf_ble_gattc.h" - -class nRF5xGattClient; /* forward declaration */ - -class nRF5xServiceDiscovery : public ServiceDiscovery -{ -public: - static const uint16_t SRV_DISC_START_HANDLE = 0x0001; /**< The start handle value used during service discovery. */ - static const uint16_t SRV_DISC_END_HANDLE = 0xFFFF; /**< The end handle value used during service discovery. */ - -public: - static const unsigned BLE_DB_DISCOVERY_MAX_SRV = 4; /**< Maximum number of services we can retain information for after a single discovery. */ - static const unsigned BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV = 4; /**< Maximum number of characteristics per service we can retain information for. */ - -public: - nRF5xServiceDiscovery(nRF5xGattClient *gattcIn) : - gattc(gattcIn), - serviceIndex(0), - numServices(0), - numCharacteristics(0), - state(INACTIVE), - services(), - characteristics(), - serviceUUIDDiscoveryQueue(this), - charUUIDDiscoveryQueue(this), - onTerminationCallback(NULL) { - /* empty */ - } - - virtual ble_error_t launch(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t sc, - ServiceDiscovery::CharacteristicCallback_t cc, - const UUID &matchingServiceUUIDIn, - const UUID &matchingCharacteristicUUIDIn) - { - if (isActive()) { - return BLE_ERROR_INVALID_STATE; - } - - serviceCallback = sc; - characteristicCallback = cc; - matchingServiceUUID = matchingServiceUUIDIn; - matchingCharacteristicUUID = matchingCharacteristicUUIDIn; - - serviceDiscoveryStarted(connectionHandle); - - uint32_t rc; - if ((rc = sd_ble_gattc_primary_services_discover(connectionHandle, SRV_DISC_START_HANDLE, NULL)) != NRF_SUCCESS) { - terminate(); - switch (rc) { - case NRF_ERROR_INVALID_PARAM: - case BLE_ERROR_INVALID_CONN_HANDLE: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - default: - case NRF_ERROR_INVALID_STATE: - return BLE_ERROR_INVALID_STATE; - } - } - - return BLE_ERROR_NONE; - } - - virtual bool isActive(void) const { - return state != INACTIVE; - } - - virtual void terminate(void) { - terminateServiceDiscovery(); - } - - void terminate(Gap::Handle_t connectionHandle) { - if(connHandle == connectionHandle) { - terminate(); - } - } - - virtual void onTermination(ServiceDiscovery::TerminationCallback_t callback) { - onTerminationCallback = callback; - } - - /** - * @brief Clear nRF5xServiceDiscovery's state. - * - * @return - * BLE_ERROR_NONE if successful. - */ - virtual ble_error_t reset(void) { - /* Clear all state that is from the parent, including private members */ - if (ServiceDiscovery::reset() != BLE_ERROR_NONE) { - return BLE_ERROR_INVALID_STATE; - } - - /* Clear derived class members */ - serviceIndex = 0; - numServices = 0; - numCharacteristics = 0; - - state = INACTIVE; - - serviceUUIDDiscoveryQueue.reset(); - charUUIDDiscoveryQueue.reset(); - - onTerminationCallback = NULL; - - return BLE_ERROR_NONE; - } - -private: - ble_error_t launchCharacteristicDiscovery(Gap::Handle_t connectionHandle, Gap::Handle_t startHandle, Gap::Handle_t endHandle); - -private: - void setupDiscoveredServices(const ble_gattc_evt_prim_srvc_disc_rsp_t *response); - void setupDiscoveredCharacteristics(const ble_gattc_evt_char_disc_rsp_t *response); - - void triggerServiceUUIDDiscovery(void); - void processDiscoverUUIDResponse(const ble_gattc_evt_t *p_gattc_evt); - void removeFirstServiceNeedingUUIDDiscovery(void); - - void terminateServiceDiscovery(void) { - discoveredCharacteristic = nRF5xDiscoveredCharacteristic(); - - bool wasActive = isActive(); - state = INACTIVE; - - if (wasActive && onTerminationCallback) { - onTerminationCallback(connHandle); - } - } - - void terminateCharacteristicDiscovery(ble_error_t err) { - if (state == CHARACTERISTIC_DISCOVERY_ACTIVE) { - if(discoveredCharacteristic != nRF5xDiscoveredCharacteristic()) { - if(err == BLE_ERROR_NONE) { - // fullfill the last characteristic - discoveredCharacteristic.setLastHandle(services[serviceIndex].getEndHandle()); - - if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - ((matchingCharacteristicUUID == discoveredCharacteristic.getUUID()) && - (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) { - if (characteristicCallback) { - characteristicCallback(&discoveredCharacteristic); - } - } - } - discoveredCharacteristic = nRF5xDiscoveredCharacteristic(); - } - - state = SERVICE_DISCOVERY_ACTIVE; - } - serviceIndex++; /* Progress service index to keep discovery alive. */ - } - -private: - void resetDiscoveredServices(void) { - numServices = 0; - serviceIndex = 0; - } - - void resetDiscoveredCharacteristics(void) { - numCharacteristics = 0; - } - -private: - void serviceDiscoveryStarted(Gap::Handle_t connectionHandle) { - connHandle = connectionHandle; - resetDiscoveredServices(); - state = SERVICE_DISCOVERY_ACTIVE; - } - -private: - void characteristicDiscoveryStarted(Gap::Handle_t connectionHandle) { - connHandle = connectionHandle; - resetDiscoveredCharacteristics(); - state = CHARACTERISTIC_DISCOVERY_ACTIVE; - } - -private: - /** - * A datatype to contain service-indices for which long UUIDs need to be - * discovered using read_val_by_uuid(). - */ - class ServiceUUIDDiscoveryQueue { - public: - ServiceUUIDDiscoveryQueue(nRF5xServiceDiscovery *parent) : - numIndices(0), - serviceIndices(), - parentDiscoveryObject(parent) { - /* empty */ - } - - public: - void reset(void) { - numIndices = 0; - for (unsigned i = 0; i < BLE_DB_DISCOVERY_MAX_SRV; i++) { - serviceIndices[i] = INVALID_INDEX; - } - } - void enqueue(int serviceIndex) { - serviceIndices[numIndices++] = serviceIndex; - } - int dequeue(void) { - if (numIndices == 0) { - return INVALID_INDEX; - } - - unsigned valueToReturn = serviceIndices[0]; - numIndices--; - for (unsigned i = 0; i < numIndices; i++) { - serviceIndices[i] = serviceIndices[i + 1]; - } - - return valueToReturn; - } - unsigned getFirst(void) const { - return serviceIndices[0]; - } - size_t getCount(void) const { - return numIndices; - } - - /** - * Trigger UUID discovery for the first of the enqueued ServiceIndices. - */ - void triggerFirst(void); - - private: - static const int INVALID_INDEX = -1; - - private: - size_t numIndices; - int serviceIndices[BLE_DB_DISCOVERY_MAX_SRV]; - - nRF5xServiceDiscovery *parentDiscoveryObject; - }; - friend class ServiceUUIDDiscoveryQueue; - - /** - * A datatype to contain characteristic-indices for which long UUIDs need to - * be discovered using read_val_by_uuid(). - */ - class CharUUIDDiscoveryQueue { - public: - CharUUIDDiscoveryQueue(nRF5xServiceDiscovery *parent) : - numIndices(0), - charIndices(), - parentDiscoveryObject(parent) { - /* empty */ - } - - public: - void reset(void) { - numIndices = 0; - for (unsigned i = 0; i < BLE_DB_DISCOVERY_MAX_SRV; i++) { - charIndices[i] = INVALID_INDEX; - } - } - void enqueue(int serviceIndex) { - charIndices[numIndices++] = serviceIndex; - } - int dequeue(void) { - if (numIndices == 0) { - return INVALID_INDEX; - } - - unsigned valueToReturn = charIndices[0]; - numIndices--; - for (unsigned i = 0; i < numIndices; i++) { - charIndices[i] = charIndices[i + 1]; - } - - return valueToReturn; - } - unsigned getFirst(void) const { - return charIndices[0]; - } - size_t getCount(void) const { - return numIndices; - } - - /** - * Trigger UUID discovery for the first of the enqueued charIndices. - */ - void triggerFirst(void); - - private: - static const int INVALID_INDEX = -1; - - private: - size_t numIndices; - int charIndices[BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV]; - - nRF5xServiceDiscovery *parentDiscoveryObject; - }; - friend class CharUUIDDiscoveryQueue; - -private: - friend void bleGattcEventHandler(const ble_evt_t *p_ble_evt); - void progressCharacteristicDiscovery(void); - void progressServiceDiscovery(void); - -private: - nRF5xGattClient *gattc; - -private: - uint8_t serviceIndex; /**< Index of the current service being discovered. This is intended for internal use during service discovery.*/ - uint8_t numServices; /**< Number of services at the peers GATT database.*/ - uint8_t numCharacteristics; /**< Number of characteristics within the service.*/ - - enum State_t { - INACTIVE, - SERVICE_DISCOVERY_ACTIVE, - CHARACTERISTIC_DISCOVERY_ACTIVE, - DISCOVER_SERVICE_UUIDS, - DISCOVER_CHARACTERISTIC_UUIDS, - } state; - - DiscoveredService services[BLE_DB_DISCOVERY_MAX_SRV]; /**< Information related to the current service being discovered. - * This is intended for internal use during service discovery. */ - nRF5xDiscoveredCharacteristic characteristics[BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV]; - - ServiceUUIDDiscoveryQueue serviceUUIDDiscoveryQueue; - CharUUIDDiscoveryQueue charUUIDDiscoveryQueue; - - TerminationCallback_t onTerminationCallback; - - /* - * The currently discovered characteristic. Discovery of a characteristic - * is a two phase process. - * First, declaration handle is fetched, it provide the UUID, the value handle and - * the properties of a characteristic. - * Second, the next declaration handle is fetched, with its declaration handle, it is - * possible to compute the last handle of the discovered characteristic and fill the - * missing part of the object. - * If there is no remaining characteristic to discover, the last handle of the - * discovered characteristic will be set to the last handle of its enclosing service. - */ - nRF5xDiscoveredCharacteristic discoveredCharacteristic; -}; - -#endif /*__NRF_SERVICE_DISCOVERY_H__*/ From 33cbff48670aba4afa8d939644dfdb10c2a8620e Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Thu, 21 Dec 2017 16:51:10 +0000 Subject: [PATCH 107/118] BLE: Address GattClient comments * invalid namespace name documentation * vocabulary * typo * Add constants to improve readability * Fix abort usages --- .../TARGET_NRF5/source/nRF5XPalGattClient.cpp | 24 ++++++++++++++----- .../TARGET_NRF5/source/nRF5XPalGattClient.h | 2 +- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp index 23b352c440..eb2d27ccb5 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp @@ -161,6 +161,10 @@ static uint8_t convert_sd_att_error_code(uint16_t err) } } +static const size_t long_uuid_length = 16; +static const size_t read_by_group_type_long_uuid_index = 4; +static const size_t characteristic_declaration_length = 1 + 2 + 16; + } // end of anonymous namespace nRF5XGattClient::nRF5XGattClient() : @@ -354,7 +358,7 @@ ble_error_t nRF5XGattClient::execute_write_queue( * The concept of procedures for Gatt operations formalize the process. A * procedure lifecycle is defined by three function: * - start: Launch of the procedure. It initiate the first request to send to - * the peer. It must be implemented by Procedure childs. + * the peer. It must be implemented by Procedure derived classes. * - handle: Event handler that process ble events comming from the softdevice. * This function drive the procedure flow and must be implemented by * Procedure childs. @@ -415,7 +419,7 @@ struct nRF5XGattClient::GattProcedure { /** * A regular procedure is a procedure that follows Gatt specification. * - * It initiate a single request to the peer and except a single response. This + * It initiate a single request to the peer and excepts a single response. This * kind of procedure doesn't requires extra processing step. * * Given that such procedure expect a single event type from the soft device, @@ -648,11 +652,13 @@ struct nRF5XGattClient::DiscoverPrimaryServiceProcedure : GattProcedure { uint16_t expected_handle = bytes_to_u16(&response[idx][0]); - if (rsp.handle != expected_handle || rsp.offset != 0 || rsp.len != 16) { + if (rsp.handle != expected_handle || rsp.offset != 0 || + rsp.len != long_uuid_length) { abort(); + return; } - memcpy(&response[idx][4], rsp.data, rsp.len); + memcpy(&response[idx][read_by_group_type_long_uuid_index], rsp.data, rsp.len); ++idx; @@ -801,6 +807,7 @@ struct nRF5XGattClient::FindIncludedServicesProcedure : RegularGattProcedure { uint8_t* buffer = new(std::nothrow) uint8_t[buffer_size]; if (!buffer) { abort(); + return; } uint8_t *it = buffer; @@ -898,6 +905,7 @@ struct nRF5XGattClient::DiscoverCharacteristicsProcedure : GattProcedure { _response = flatten_response(evt.params.char_disc_rsp); if (!_response.buffer) { abort(); + return; } // If element size is equal to 7 then the characteristic discovered @@ -940,6 +948,7 @@ struct nRF5XGattClient::DiscoverCharacteristicsProcedure : GattProcedure { // should never happen if (!_response.buffer) { abort(); + return; } if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { @@ -954,8 +963,10 @@ struct nRF5XGattClient::DiscoverCharacteristicsProcedure : GattProcedure { uint8_t* current_element = &_response.buffer[_idx * _response.element_size]; uint16_t expected_handle = bytes_to_u16(current_element); - if (rsp.handle != expected_handle || rsp.offset != 0 || rsp.len != (1 + 2 + 16)) { + if (rsp.handle != expected_handle || rsp.offset != 0 || + rsp.len != characteristic_declaration_length) { abort(); + return; } // note: elements are the pair characteristic declaration handle followed @@ -1128,6 +1139,7 @@ struct nRF5XGattClient::ReadAttributeProcedure : RegularGattProcedure { const ble_gattc_evt_read_rsp_t& rsp = evt.params.read_rsp; if (rsp.offset != 0 ) { abort(); + return; } terminate(AttReadResponse(make_const_ArrayView(rsp.data, rsp.len))); @@ -1606,7 +1618,7 @@ void nRF5XGattClient::handle_connection_termination(connection_handle_t connecti } } -} // cordio +} // nordic } // vendor } // pal } // ble diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h index 8776ae82e4..ede03ce3f4 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h @@ -249,7 +249,7 @@ private: GattProcedure* _procedures[max_procedures_count]; }; -} // cordio +} // nordic } // vendor } // pal } // ble From 9686fcc30c3ce5738d88cba1abc1dadb8b8c6869 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Mon, 8 Jan 2018 12:01:30 +0000 Subject: [PATCH 108/118] BLE: Fix include dependency in UUID.h. --- features/FEATURE_BLE/ble/UUID.h | 1 + 1 file changed, 1 insertion(+) diff --git a/features/FEATURE_BLE/ble/UUID.h b/features/FEATURE_BLE/ble/UUID.h index afe07e7f23..19acda27f5 100644 --- a/features/FEATURE_BLE/ble/UUID.h +++ b/features/FEATURE_BLE/ble/UUID.h @@ -17,6 +17,7 @@ #ifndef MBED_UUID_H__ #define MBED_UUID_H__ +#include #include #include #include From 46f02764ba511f52ac86575732f6538f111099a3 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Mon, 8 Jan 2018 12:04:02 +0000 Subject: [PATCH 109/118] Nordic BLE: Simplification and clarification of pal client implementation. --- .../TARGET_NRF5/source/nRF5XPalGattClient.cpp | 80 +++++++++---------- 1 file changed, 38 insertions(+), 42 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp index eb2d27ccb5..9ac31e34cc 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp @@ -78,6 +78,33 @@ static attribute_handle_range_t to_ble_handle_range(const ble_gattc_handle_range return result; } +/** + * Convert an error from the softdevice into a ble_error_t + */ +static ble_error_t convert_sd_error(uint32_t err) +{ + switch (err) { + case NRF_SUCCESS: + return BLE_ERROR_NONE; + case NRF_ERROR_INVALID_PARAM: + case BLE_ERROR_INVALID_CONN_HANDLE: + case NRF_ERROR_INVALID_ADDR: + return BLE_ERROR_INVALID_PARAM; + case NRF_ERROR_INVALID_STATE: + return BLE_ERROR_INVALID_STATE; + case NRF_ERROR_DATA_SIZE: + return BLE_ERROR_PARAM_OUT_OF_RANGE; + case BLE_ERROR_NO_TX_PACKETS: + return BLE_ERROR_NO_MEM; + case NRF_ERROR_BUSY: + return BLE_STACK_BUSY; + case NRF_ERROR_NO_MEM: + return BLE_ERROR_NO_MEM; + default: + return BLE_ERROR_UNSPECIFIED; + } +} + /** * Convert a UUID into a ble_uuid_t . * If the UUID is a 128 bit one then it is registered into the softdevice. @@ -101,22 +128,12 @@ static ble_error_t to_nordic_uuid(const UUID &uuid, ble_uuid_t &nordic_uuid) memcpy(uuid128.uuid128, uuid.getBaseUUID(), sizeof(uuid128.uuid128)); // UUID not found, try to register it - err = sd_ble_uuid_vs_add( - &uuid128, - &nordic_uuid.type - ); - - switch (err) { - case NRF_SUCCESS: - nordic_uuid.uuid = bytes_to_u16(uuid.getBaseUUID() + 12); - return BLE_ERROR_NONE; - case NRF_ERROR_INVALID_ADDR: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_NO_MEM: - return BLE_ERROR_NO_MEM; - default: - return BLE_ERROR_UNSPECIFIED; + err = sd_ble_uuid_vs_add(&uuid128, &nordic_uuid.type); + if (err == NRF_SUCCESS) { + nordic_uuid.uuid = bytes_to_u16(uuid.getBaseUUID() + 12); } + + return convert_sd_error(err); } else { nordic_uuid.type = BLE_UUID_TYPE_BLE; nordic_uuid.uuid = uuid.getShortUUID(); @@ -124,31 +141,6 @@ static ble_error_t to_nordic_uuid(const UUID &uuid, ble_uuid_t &nordic_uuid) } } -/** - * Convert an error from the softdevice into a ble_error_t - */ -static ble_error_t convert_sd_error(uint32_t err) -{ - switch (err) { - case NRF_SUCCESS: - return BLE_ERROR_NONE; - case NRF_ERROR_INVALID_PARAM: - case BLE_ERROR_INVALID_CONN_HANDLE: - case NRF_ERROR_INVALID_ADDR: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_INVALID_STATE: - return BLE_ERROR_INVALID_STATE; - case NRF_ERROR_DATA_SIZE: - return BLE_ERROR_PARAM_OUT_OF_RANGE; - case BLE_ERROR_NO_TX_PACKETS: - return BLE_ERROR_NO_MEM; - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - default: - return BLE_ERROR_UNSPECIFIED; - } -} - /** * Convert an attribute error code from the softdevice into a valid ATT error. */ @@ -186,6 +178,7 @@ ble_error_t nRF5XGattClient::initialize() ble_error_t nRF5XGattClient::exchange_mtu(connection_handle_t connection) { // Note: Not supported by the current softdevice + // FIXME: implement when SD 140 5.x.x is present return BLE_ERROR_NOT_IMPLEMENTED; } @@ -361,7 +354,7 @@ ble_error_t nRF5XGattClient::execute_write_queue( * the peer. It must be implemented by Procedure derived classes. * - handle: Event handler that process ble events comming from the softdevice. * This function drive the procedure flow and must be implemented by - * Procedure childs. + * Procedure derived classes. * - terminate: end the procedure and forward the result to the GattClient * event handle. * @@ -422,7 +415,7 @@ struct nRF5XGattClient::GattProcedure { * It initiate a single request to the peer and excepts a single response. This * kind of procedure doesn't requires extra processing step. * - * Given that such procedure expect a single event type from the soft device, + * Given that such procedure expects a single event type from the soft device, * error handling can be generalized. */ struct nRF5XGattClient::RegularGattProcedure : GattProcedure { @@ -675,6 +668,9 @@ struct nRF5XGattClient::DiscoverPrimaryServiceProcedure : GattProcedure { } } + // Hold read by group type response of services with 128 bit UUID. + // The response is composed of the service attribute handle (2 bytes), the + // end group handle (2 bytes) and the service UUID (16 bytes). typedef uint8_t packed_discovery_response_t[20]; packed_discovery_response_t* response; From 18343e192af57099c065dc86b5fc533b6b5c95a6 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Mon, 8 Jan 2018 13:52:42 +0000 Subject: [PATCH 110/118] Nordic BLE: Fix PalGattClient for SDK v13. --- .../TARGET_NRF5/source/nRF5XPalGattClient.cpp | 57 ++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp index 9ac31e34cc..baf7215856 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp @@ -177,15 +177,21 @@ ble_error_t nRF5XGattClient::initialize() ble_error_t nRF5XGattClient::exchange_mtu(connection_handle_t connection) { - // Note: Not supported by the current softdevice // FIXME: implement when SD 140 5.x.x is present + // (see sd_ble_gatts_exchange_mtu_reply) return BLE_ERROR_NOT_IMPLEMENTED; } ble_error_t nRF5XGattClient::get_mtu_size( connection_handle_t connection_handle, uint16_t& mtu_size ) { +#ifdef TARGET_SDK13 + // FIXME: implement when MTU size can be configured; the mtu size must be + // stored locally when BLE_GATTC_EVT_EXCHANGE_MTU_RSP has been received + mtu_size = BLE_GATT_MTU_SIZE_DEFAULT; +#else mtu_size = GATT_RX_MTU; +#endif return BLE_ERROR_NONE; } @@ -1089,6 +1095,7 @@ struct nRF5XGattClient::DiscoverDescriptorsProcedure : RegularGattProcedure { return response.count; } +#ifndef TARGET_SDK13 virtual information_data_t operator[](size_t i) const { information_data_t result = { @@ -1106,6 +1113,32 @@ struct nRF5XGattClient::DiscoverDescriptorsProcedure : RegularGattProcedure { return result; } +#else /* TARGET_SDK13 */ + virtual information_data_t operator[](size_t i) const + { + if (response.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { + information_data_t result = { + response.info.attr_info16[i].handle, + UUID(response.info.attr_info16[i].uuid.uuid) + }; + + return result; + } else { + information_data_t result = { + response.info.attr_info128[i].handle, + UUID( + response.info.attr_info128[i].uuid.uuid128, + UUID::LSB + ) + }; + + return result; + } + } + + +#endif + const ble_gattc_evt_attr_info_disc_rsp_t &response; }; @@ -1174,6 +1207,27 @@ struct nRF5XGattClient::ReadUsingCharacteristicUUIDProcedure : RegularGattProced return convert_sd_error(err); } +#ifdef TARGET_SDK13 + /** + * Adapt ble_gattc_evt_char_val_by_uuid_read_rsp_t into AttReadByTypeResponse. + */ + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_char_val_by_uuid_read_rsp_t &rsp = + evt.params.char_val_by_uuid_read_rsp; + + uint8_t element_size = sizeof(uint16_t) + rsp.value_len; + + terminate(SimpleAttReadByTypeResponse( + element_size, + make_const_ArrayView( + rsp.handle_value, + rsp.count * element_size + ) + )); + } + +#else /** * Adapt ble_gattc_evt_char_val_by_uuid_read_rsp_t into AttReadByTypeResponse. */ @@ -1205,6 +1259,7 @@ struct nRF5XGattClient::ReadUsingCharacteristicUUIDProcedure : RegularGattProced terminate(CustomReadByTypeResponse(evt.params.char_val_by_uuid_read_rsp)); } +#endif }; /** From 757a1f8cf5449706a864cfb2eb082965c096fa72 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Mon, 8 Jan 2018 14:00:23 +0000 Subject: [PATCH 111/118] Nordic BLE: Use SD API version rather than SDK define. --- .../TARGET_NRF5/source/nRF5XPalGattClient.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp index baf7215856..e1baf9569e 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp @@ -185,7 +185,7 @@ ble_error_t nRF5XGattClient::exchange_mtu(connection_handle_t connection) ble_error_t nRF5XGattClient::get_mtu_size( connection_handle_t connection_handle, uint16_t& mtu_size ) { -#ifdef TARGET_SDK13 +#if (NRF_SD_BLE_API_VERSION >= 3) // FIXME: implement when MTU size can be configured; the mtu size must be // stored locally when BLE_GATTC_EVT_EXCHANGE_MTU_RSP has been received mtu_size = BLE_GATT_MTU_SIZE_DEFAULT; @@ -1095,7 +1095,7 @@ struct nRF5XGattClient::DiscoverDescriptorsProcedure : RegularGattProcedure { return response.count; } -#ifndef TARGET_SDK13 +#if (NRF_SD_BLE_API_VERSION < 3) virtual information_data_t operator[](size_t i) const { information_data_t result = { @@ -1113,7 +1113,7 @@ struct nRF5XGattClient::DiscoverDescriptorsProcedure : RegularGattProcedure { return result; } -#else /* TARGET_SDK13 */ +#else virtual information_data_t operator[](size_t i) const { if (response.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { @@ -1207,7 +1207,7 @@ struct nRF5XGattClient::ReadUsingCharacteristicUUIDProcedure : RegularGattProced return convert_sd_error(err); } -#ifdef TARGET_SDK13 +#if (NRF_SD_BLE_API_VERSION >= 3) /** * Adapt ble_gattc_evt_char_val_by_uuid_read_rsp_t into AttReadByTypeResponse. */ From bab609fe2ac10a60b50d1e364a2b5756acfed480 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 10 Jan 2018 14:15:08 +0000 Subject: [PATCH 112/118] BLE: Put generic gattclient procedures inside the GattClient class --- .../ble/generic/GenericGattClient.h | 21 ++++++------------- .../source/generic/GenericGattClient.cpp | 14 ++++++------- 2 files changed, 13 insertions(+), 22 deletions(-) diff --git a/features/FEATURE_BLE/ble/generic/GenericGattClient.h b/features/FEATURE_BLE/ble/generic/GenericGattClient.h index adf4695949..3a04b0d03a 100644 --- a/features/FEATURE_BLE/ble/generic/GenericGattClient.h +++ b/features/FEATURE_BLE/ble/generic/GenericGattClient.h @@ -26,27 +26,12 @@ namespace ble { namespace generic { -// forward declarations -struct procedure_control_block_t; -struct discovery_control_block_t; -struct read_control_block_t; -struct write_control_block_t; -struct descriptor_discovery_control_block_t; - /** * Generic implementation of the GattClient. * It requires a pal::GattClient injected at construction site. * @attention: Not part of the public interface of BLE API. */ class GenericGattClient : public GattClient { - - // give access to control block classes - friend struct procedure_control_block_t; - friend struct discovery_control_block_t; - friend struct read_control_block_t; - friend struct write_control_block_t; - friend struct descriptor_discovery_control_block_t; - public: /** * Create a GenericGattClient from a pal::GattClient @@ -130,6 +115,12 @@ public: virtual ble_error_t reset(void); private: + struct procedure_control_block_t; + struct discovery_control_block_t; + struct read_control_block_t; + struct write_control_block_t; + struct descriptor_discovery_control_block_t; + procedure_control_block_t* get_control_block(Gap::Handle_t connection); const procedure_control_block_t* get_control_block(Gap::Handle_t connection) const; void insert_control_block(procedure_control_block_t* cb) const; diff --git a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp index 595babcccc..06c6001b87 100644 --- a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp +++ b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp @@ -55,7 +55,7 @@ enum procedure_type_t { /* * Base class for a procedure control block */ -struct procedure_control_block_t { +struct GenericGattClient::procedure_control_block_t { /* * Base constructor for procedure control block. */ @@ -83,7 +83,7 @@ struct procedure_control_block_t { /* * Procedure control block for the discovery process. */ -struct discovery_control_block_t : public procedure_control_block_t { +struct GenericGattClient::discovery_control_block_t : public procedure_control_block_t { discovery_control_block_t( Gap::Handle_t handle, ServiceDiscovery::ServiceCallback_t service_callback, @@ -409,7 +409,7 @@ struct discovery_control_block_t : public procedure_control_block_t { }; -struct read_control_block_t : public procedure_control_block_t { +struct GenericGattClient::read_control_block_t : public procedure_control_block_t { read_control_block_t( Gap::Handle_t connection_handle, uint16_t attribute_handle, uint16_t offset ) : procedure_control_block_t(READ_PROCEDURE, connection_handle), @@ -593,7 +593,7 @@ struct read_control_block_t : public procedure_control_block_t { /* * Control block for the write process */ -struct write_control_block_t : public procedure_control_block_t { +struct GenericGattClient::write_control_block_t : public procedure_control_block_t { write_control_block_t( Gap::Handle_t connection_handle, uint16_t attribute_handle, uint8_t* data, uint16_t len @@ -785,7 +785,7 @@ struct write_control_block_t : public procedure_control_block_t { /* * Control block for the descriptor discovery process */ -struct descriptor_discovery_control_block_t : public procedure_control_block_t { +struct GenericGattClient::descriptor_discovery_control_block_t : public procedure_control_block_t { descriptor_discovery_control_block_t( const DiscoveredCharacteristic& characteristic, const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, @@ -1278,7 +1278,7 @@ void GenericGattClient::on_transaction_timeout(connection_handle_t connection) { pcb->handle_timeout_error(this); } -procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) { +GenericGattClient::procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) { procedure_control_block_t* it = control_blocks; while (it && it->connection_handle != connection) { it = it->next; @@ -1286,7 +1286,7 @@ procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t co return it; } -const procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) const { +const GenericGattClient::procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) const { procedure_control_block_t* it = control_blocks; while (it && it->connection_handle != connection) { it = it->next; From 6ab18b94b80cc68712f075cc30f8870d632e5061 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 10 Jan 2018 14:18:00 +0000 Subject: [PATCH 113/118] BLE: Align naming of GattClient procedure control blocks. --- .../ble/generic/GenericGattClient.h | 20 ++--- .../source/generic/GenericGattClient.cpp | 86 +++++++++---------- 2 files changed, 53 insertions(+), 53 deletions(-) diff --git a/features/FEATURE_BLE/ble/generic/GenericGattClient.h b/features/FEATURE_BLE/ble/generic/GenericGattClient.h index 3a04b0d03a..71167f7577 100644 --- a/features/FEATURE_BLE/ble/generic/GenericGattClient.h +++ b/features/FEATURE_BLE/ble/generic/GenericGattClient.h @@ -115,16 +115,16 @@ public: virtual ble_error_t reset(void); private: - struct procedure_control_block_t; - struct discovery_control_block_t; - struct read_control_block_t; - struct write_control_block_t; - struct descriptor_discovery_control_block_t; + struct ProcedureControlBlock; + struct DiscoveryControlBlock; + struct ReadControlBlock; + struct WriteControlBlock; + struct DescriptorDiscoveryControlBlock; - procedure_control_block_t* get_control_block(Gap::Handle_t connection); - const procedure_control_block_t* get_control_block(Gap::Handle_t connection) const; - void insert_control_block(procedure_control_block_t* cb) const; - void remove_control_block(procedure_control_block_t* cb) const; + ProcedureControlBlock* get_control_block(Gap::Handle_t connection); + const ProcedureControlBlock* get_control_block(Gap::Handle_t connection) const; + void insert_control_block(ProcedureControlBlock* cb) const; + void remove_control_block(ProcedureControlBlock* cb) const; void on_termination(Gap::Handle_t connection_handle); void on_server_message_received(connection_handle_t, const pal::AttServerMessage&); @@ -136,7 +136,7 @@ private: pal::GattClient* const _pal_client; ServiceDiscovery::TerminationCallback_t _termination_callback; - mutable procedure_control_block_t* control_blocks; + mutable ProcedureControlBlock* control_blocks; }; } diff --git a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp index 06c6001b87..9028eca7b3 100644 --- a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp +++ b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp @@ -55,14 +55,14 @@ enum procedure_type_t { /* * Base class for a procedure control block */ -struct GenericGattClient::procedure_control_block_t { +struct GenericGattClient::ProcedureControlBlock { /* * Base constructor for procedure control block. */ - procedure_control_block_t(procedure_type_t type, Gap::Handle_t handle) : + ProcedureControlBlock(procedure_type_t type, Gap::Handle_t handle) : type(type), connection_handle(handle), next(NULL) { } - virtual ~procedure_control_block_t() { } + virtual ~ProcedureControlBlock() { } /* * Entry point of the control block stack machine. @@ -76,21 +76,21 @@ struct GenericGattClient::procedure_control_block_t { procedure_type_t type; Gap::Handle_t connection_handle; - procedure_control_block_t* next; + ProcedureControlBlock* next; }; /* * Procedure control block for the discovery process. */ -struct GenericGattClient::discovery_control_block_t : public procedure_control_block_t { - discovery_control_block_t( +struct GenericGattClient::DiscoveryControlBlock : public ProcedureControlBlock { + DiscoveryControlBlock( Gap::Handle_t handle, ServiceDiscovery::ServiceCallback_t service_callback, ServiceDiscovery::CharacteristicCallback_t characteristic_callback, UUID matching_service_uuid, UUID matching_characteristic_uuid - ) : procedure_control_block_t(COMPLETE_DISCOVERY_PROCEDURE, handle), + ) : ProcedureControlBlock(COMPLETE_DISCOVERY_PROCEDURE, handle), service_callback(service_callback), characteristic_callback(characteristic_callback), matching_service_uuid(matching_service_uuid), @@ -99,7 +99,7 @@ struct GenericGattClient::discovery_control_block_t : public procedure_control_b done(false) { } - virtual ~discovery_control_block_t() { + virtual ~DiscoveryControlBlock() { while(services_discovered) { service_t* tmp = services_discovered->next; delete services_discovered; @@ -409,15 +409,15 @@ struct GenericGattClient::discovery_control_block_t : public procedure_control_b }; -struct GenericGattClient::read_control_block_t : public procedure_control_block_t { - read_control_block_t( +struct GenericGattClient::ReadControlBlock : public ProcedureControlBlock { + ReadControlBlock( Gap::Handle_t connection_handle, uint16_t attribute_handle, uint16_t offset - ) : procedure_control_block_t(READ_PROCEDURE, connection_handle), + ) : ProcedureControlBlock(READ_PROCEDURE, connection_handle), attribute_handle(attribute_handle), offset(offset), current_offset(offset), data(NULL) { } - virtual ~read_control_block_t() { + virtual ~ReadControlBlock() { if (data != NULL) { free(data); } @@ -593,16 +593,16 @@ struct GenericGattClient::read_control_block_t : public procedure_control_block_ /* * Control block for the write process */ -struct GenericGattClient::write_control_block_t : public procedure_control_block_t { - write_control_block_t( +struct GenericGattClient::WriteControlBlock : public ProcedureControlBlock { + WriteControlBlock( Gap::Handle_t connection_handle, uint16_t attribute_handle, uint8_t* data, uint16_t len - ) : procedure_control_block_t(WRITE_PROCEDURE, connection_handle), + ) : ProcedureControlBlock(WRITE_PROCEDURE, connection_handle), attribute_handle(attribute_handle), len(len), offset(0), data(data), prepare_success(false), status(BLE_ERROR_UNSPECIFIED), error_code(0xFF) { } - virtual ~write_control_block_t() { + virtual ~WriteControlBlock() { free(data); } @@ -785,12 +785,12 @@ struct GenericGattClient::write_control_block_t : public procedure_control_block /* * Control block for the descriptor discovery process */ -struct GenericGattClient::descriptor_discovery_control_block_t : public procedure_control_block_t { - descriptor_discovery_control_block_t( +struct GenericGattClient::DescriptorDiscoveryControlBlock : public ProcedureControlBlock { + DescriptorDiscoveryControlBlock( const DiscoveredCharacteristic& characteristic, const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback - ) : procedure_control_block_t(DESCRIPTOR_DISCOVERY_PROCEDURE, characteristic.getConnectionHandle()), + ) : ProcedureControlBlock(DESCRIPTOR_DISCOVERY_PROCEDURE, characteristic.getConnectionHandle()), characteristic(characteristic), discovery_cb(discoveryCallback), termination_cb(terminationCallback), @@ -798,7 +798,7 @@ struct GenericGattClient::descriptor_discovery_control_block_t : public procedur done(false) { } - virtual ~descriptor_discovery_control_block_t() { } + virtual ~DescriptorDiscoveryControlBlock() { } ble_error_t start(GenericGattClient* client) { return client->_pal_client->discover_characteristics_descriptors( @@ -919,7 +919,7 @@ ble_error_t GenericGattClient::launchServiceDiscovery( return BLE_ERROR_NONE; } - discovery_control_block_t* discovery_pcb = new(std::nothrow) discovery_control_block_t( + DiscoveryControlBlock* discovery_pcb = new(std::nothrow) DiscoveryControlBlock( connection_handle, service_callback, characteristic_callback, @@ -959,7 +959,7 @@ ble_error_t GenericGattClient::launchServiceDiscovery( } bool GenericGattClient::isServiceDiscoveryActive() const { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == COMPLETE_DISCOVERY_PROCEDURE) { @@ -973,10 +973,10 @@ bool GenericGattClient::isServiceDiscoveryActive() const { void GenericGattClient::terminateServiceDiscovery() { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == COMPLETE_DISCOVERY_PROCEDURE) { - static_cast(pcb)->done = true; + static_cast(pcb)->done = true; } pcb = pcb->next; } @@ -992,7 +992,7 @@ ble_error_t GenericGattClient::read( return BLE_ERROR_INVALID_STATE; } - read_control_block_t* read_pcb = new(std::nothrow) read_control_block_t( + ReadControlBlock* read_pcb = new(std::nothrow) ReadControlBlock( connection_handle, attribute_handle, offset @@ -1058,7 +1058,7 @@ ble_error_t GenericGattClient::write( memcpy(data, value, length); } - write_control_block_t* write_pcb = new(std::nothrow) write_control_block_t( + WriteControlBlock* write_pcb = new(std::nothrow) WriteControlBlock( connection_handle, attribute_handle, data, @@ -1126,8 +1126,8 @@ ble_error_t GenericGattClient::discoverCharacteristicDescriptors( return BLE_ERROR_NONE; } - descriptor_discovery_control_block_t* discovery_pcb = - new(std::nothrow) descriptor_discovery_control_block_t( + DescriptorDiscoveryControlBlock* discovery_pcb = + new(std::nothrow) DescriptorDiscoveryControlBlock( characteristic, discoveryCallback, terminationCallback @@ -1152,11 +1152,11 @@ ble_error_t GenericGattClient::discoverCharacteristicDescriptors( bool GenericGattClient::isCharacteristicDescriptorDiscoveryActive( const DiscoveredCharacteristic& characteristic ) const { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == DESCRIPTOR_DISCOVERY_PROCEDURE && - static_cast(pcb)->characteristic == characteristic) { + static_cast(pcb)->characteristic == characteristic) { return true; } pcb = pcb->next; @@ -1168,12 +1168,12 @@ bool GenericGattClient::isCharacteristicDescriptorDiscoveryActive( void GenericGattClient::terminateCharacteristicDescriptorDiscovery( const DiscoveredCharacteristic& characteristic ) { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == DESCRIPTOR_DISCOVERY_PROCEDURE) { - descriptor_discovery_control_block_t* dpcb = - static_cast(pcb); + DescriptorDiscoveryControlBlock* dpcb = + static_cast(pcb); if (dpcb->characteristic == characteristic) { dpcb->done = true; return; @@ -1230,7 +1230,7 @@ void GenericGattClient::on_server_response( connection_handle_t connection, const AttServerMessage& message ) { - procedure_control_block_t* pcb = get_control_block(connection); + ProcedureControlBlock* pcb = get_control_block(connection); if (pcb == NULL) { return; } @@ -1270,7 +1270,7 @@ void GenericGattClient::on_server_event(connection_handle_t connection, const At } void GenericGattClient::on_transaction_timeout(connection_handle_t connection) { - procedure_control_block_t* pcb = get_control_block(connection); + ProcedureControlBlock* pcb = get_control_block(connection); if (pcb == NULL) { return; } @@ -1278,36 +1278,36 @@ void GenericGattClient::on_transaction_timeout(connection_handle_t connection) { pcb->handle_timeout_error(this); } -GenericGattClient::procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) { - procedure_control_block_t* it = control_blocks; +GenericGattClient::ProcedureControlBlock* GenericGattClient::get_control_block(Gap::Handle_t connection) { + ProcedureControlBlock* it = control_blocks; while (it && it->connection_handle != connection) { it = it->next; } return it; } -const GenericGattClient::procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) const { - procedure_control_block_t* it = control_blocks; +const GenericGattClient::ProcedureControlBlock* GenericGattClient::get_control_block(Gap::Handle_t connection) const { + ProcedureControlBlock* it = control_blocks; while (it && it->connection_handle != connection) { it = it->next; } return it; } -void GenericGattClient::insert_control_block(procedure_control_block_t* cb) const { +void GenericGattClient::insert_control_block(ProcedureControlBlock* cb) const { if (control_blocks == NULL) { control_blocks = cb; return; } - procedure_control_block_t* current = control_blocks; + ProcedureControlBlock* current = control_blocks; while (current->next) { current = current->next; } current->next = cb; } -void GenericGattClient::remove_control_block(procedure_control_block_t* cb) const { +void GenericGattClient::remove_control_block(ProcedureControlBlock* cb) const { if (control_blocks == NULL) { return; } @@ -1317,7 +1317,7 @@ void GenericGattClient::remove_control_block(procedure_control_block_t* cb) cons return; } - procedure_control_block_t* current = control_blocks; + ProcedureControlBlock* current = control_blocks; while (current->next && current->next != cb) { current = current->next; } From 0fdd1080ed7244217f4d31c1a05cc8801518dcf0 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 10 Jan 2018 14:31:52 +0000 Subject: [PATCH 114/118] BLE: Implement Generic GattClient reset logic. --- .../ble/generic/GenericGattClient.h | 1 + .../source/generic/GenericGattClient.cpp | 60 +++++++++++++++++-- 2 files changed, 55 insertions(+), 6 deletions(-) diff --git a/features/FEATURE_BLE/ble/generic/GenericGattClient.h b/features/FEATURE_BLE/ble/generic/GenericGattClient.h index 71167f7577..f0a8462ff9 100644 --- a/features/FEATURE_BLE/ble/generic/GenericGattClient.h +++ b/features/FEATURE_BLE/ble/generic/GenericGattClient.h @@ -137,6 +137,7 @@ private: pal::GattClient* const _pal_client; ServiceDiscovery::TerminationCallback_t _termination_callback; mutable ProcedureControlBlock* control_blocks; + bool _is_reseting; }; } diff --git a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp index 9028eca7b3..97c6d57fc0 100644 --- a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp +++ b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp @@ -74,6 +74,11 @@ struct GenericGattClient::ProcedureControlBlock { */ virtual void handle_timeout_error(GenericGattClient* client) = 0; + /** + * Function called when the procedure is aborted + */ + virtual void abort(GenericGattClient *client) = 0; + procedure_type_t type; Gap::Handle_t connection_handle; ProcedureControlBlock* next; @@ -111,6 +116,10 @@ struct GenericGattClient::DiscoveryControlBlock : public ProcedureControlBlock { terminate(client); } + virtual void abort(GenericGattClient *client) { + terminate(client); + } + virtual void handle(GenericGattClient* client, const AttServerMessage& message) { // if end of discovery has been requested, ends it immediately if (done) { @@ -436,6 +445,19 @@ struct GenericGattClient::ReadControlBlock : public ProcedureControlBlock { terminate(client, response); } + virtual void abort(GenericGattClient *client) { + GattReadCallbackParams response = { + connection_handle, + attribute_handle, + offset, + 0, // size of 0 + NULL, // no data + BLE_ERROR_INVALID_STATE, + + }; + terminate(client, response); + } + void terminate(GenericGattClient* client, const GattReadCallbackParams& response) { client->remove_control_block(this); client->processReadResponse(&response); @@ -617,6 +639,17 @@ struct GenericGattClient::WriteControlBlock : public ProcedureControlBlock { terminate(client, response); } + virtual void abort(GenericGattClient *client) { + GattWriteCallbackParams response = { + connection_handle, + attribute_handle, + GattWriteCallbackParams::OP_WRITE_REQ, + BLE_ERROR_INVALID_STATE, + 0x00 + }; + terminate(client, response); + } + void terminate(GenericGattClient* client, const GattWriteCallbackParams& response) { client->remove_control_block(this); client->processWriteResponse(&response); @@ -814,6 +847,10 @@ struct GenericGattClient::DescriptorDiscoveryControlBlock : public ProcedureCont terminate(client, BLE_ERROR_UNSPECIFIED); } + virtual void abort(GenericGattClient *client) { + terminate(client, BLE_ERROR_INVALID_STATE); + } + virtual void handle(GenericGattClient* client, const AttServerMessage& message) { if (done) { terminate(client, BLE_ERROR_NONE); @@ -892,7 +929,8 @@ struct GenericGattClient::DescriptorDiscoveryControlBlock : public ProcedureCont GenericGattClient::GenericGattClient(pal::GattClient* pal_client) : _pal_client(pal_client), _termination_callback(), - control_blocks(NULL) { + control_blocks(NULL), + _is_reseting(false) { _pal_client->when_server_message_received( mbed::callback(this, &GenericGattClient::on_server_message_received) ); @@ -909,7 +947,7 @@ ble_error_t GenericGattClient::launchServiceDiscovery( const UUID& matching_characteristic_uuid ) { // verify that there is no other procedures going on this connection - if (get_control_block(connection_handle)) { + if (_is_reseting || get_control_block(connection_handle)) { return BLE_ERROR_INVALID_STATE; } @@ -988,7 +1026,7 @@ ble_error_t GenericGattClient::read( uint16_t offset) const { // verify that there is no other procedures going on this connection - if (get_control_block(connection_handle)) { + if (_is_reseting || get_control_block(connection_handle)) { return BLE_ERROR_INVALID_STATE; } @@ -1032,7 +1070,7 @@ ble_error_t GenericGattClient::write( const uint8_t* value ) const { // verify that there is no other procedures going on this connection - if (get_control_block(connection_handle)) { + if (_is_reseting || get_control_block(connection_handle)) { return BLE_ERROR_INVALID_STATE; } @@ -1111,7 +1149,7 @@ ble_error_t GenericGattClient::discoverCharacteristicDescriptors( const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback ) { // verify that there is no other procedures going on this connection - if (get_control_block(characteristic.getConnectionHandle())) { + if (_is_reseting || get_control_block(characteristic.getConnectionHandle())) { return BLE_ERROR_INVALID_STATE; } @@ -1186,7 +1224,17 @@ void GenericGattClient::terminateCharacteristicDescriptorDiscovery( } ble_error_t GenericGattClient::reset(void) { - return BLE_ERROR_NOT_IMPLEMENTED; + + // _is_reseting prevent executions of new procedure while the instance resets. + // otherwise new procedures can be launched from callbacks generated by the + // reset. + _is_reseting = true; + while (control_blocks) { + control_blocks->abort(this); + } + _is_reseting = false; + + return BLE_ERROR_NONE; } void GenericGattClient::on_termination(Gap::Handle_t connection_handle) { From 4f331b615533b37f074de1d83f21f8c2854e63bc Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 10 Jan 2018 17:04:35 +0000 Subject: [PATCH 115/118] Nordic BLE: Fix stack event size Read By group type response can return 4 descriptor discovered when the remote server have 4 descriptors with a 16 bit UUID. The handle, UUID pair get stored in a ble_gattc_desc_t that is 20 bytes long. This PR increase buffer size to handle this use case. --- .../ble_stack_handler_types.h | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h index f40e4576e2..5e6392213b 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h @@ -1,28 +1,28 @@ -/* +/* * Copyright (c) 2013 Nordic Semiconductor ASA * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list + * + * 1. Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior * written permission. * - * 4. This software, with or without modification, must only be used with a + * 4. This software, with or without modification, must only be used with a * Nordic Semiconductor ASA integrated circuit. * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,7 +33,7 @@ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ @@ -57,7 +57,7 @@ #include "app_error.h" #include "app_util.h" -#define BLE_STACK_EVT_MSG_BUF_SIZE (sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT)) /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */ +#define BLE_STACK_EVT_MSG_BUF_SIZE (sizeof(ble_evt_t) + (3 * sizeof(ble_gattc_attr_info_t)) + (GATT_MTU_SIZE_DEFAULT)) /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */ #define BLE_STACK_HANDLER_SCHED_EVT_SIZE 0 /**< The size of the scheduler event used by SoftDevice handler when passing BLE events using the @ref app_scheduler. */ /**@brief Application stack event handler type. */ From 27c5dfc44fe02905f58032557ba7710627abdc0d Mon Sep 17 00:00:00 2001 From: Steven Cartmell Date: Mon, 18 Dec 2017 11:36:30 +0000 Subject: [PATCH 116/118] Fix bug allowing SPI::abort_transfer to incorrectly unlock deep sleep mode - Add flag to SPI class to track if the SPI instance has locked deep sleep mode. - Wrap call to sleep_manager_lock_deep_sleep to only be called if SPI instance hasn't already locked deep sleep. - Wrap call to sleep_manager_unlock_deep_sleep to only be called if SPI has currently locked deep sleep mode. --- drivers/SPI.cpp | 23 ++++++++++++++++++++--- drivers/SPI.h | 9 +++++++++ 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/SPI.cpp b/drivers/SPI.cpp index 9b2209b0fe..e21922b258 100644 --- a/drivers/SPI.cpp +++ b/drivers/SPI.cpp @@ -33,6 +33,7 @@ SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) : #if DEVICE_SPI_ASYNCH _irq(this), _usage(DMA_USAGE_NEVER), + _deep_sleep_locked(false), #endif _bits(8), _mode(0), @@ -140,7 +141,7 @@ int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_ void SPI::abort_transfer() { spi_abort_asynch(&_spi); - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); #if TRANSACTION_QUEUE_SIZE_SPI dequeue_transaction(); #endif @@ -200,13 +201,29 @@ int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, i void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event) { - sleep_manager_lock_deep_sleep(); + lock_deep_sleep(); _acquire(); _callback = callback; _irq.callback(&SPI::irq_handler_asynch); spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage); } +void SPI::lock_deep_sleep() +{ + if (_deep_sleep_locked == false) { + sleep_manager_lock_deep_sleep(); + _deep_sleep_locked = true; + } +} + +void SPI::unlock_deep_sleep() +{ + if (_deep_sleep_locked == true) { + sleep_manager_unlock_deep_sleep(); + _deep_sleep_locked = false; + } +} + #if TRANSACTION_QUEUE_SIZE_SPI void SPI::start_transaction(transaction_t *data) @@ -230,7 +247,7 @@ void SPI::irq_handler_asynch(void) { int event = spi_irq_handler_asynch(&_spi); if (_callback && (event & SPI_EVENT_ALL)) { - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); _callback.call(event & SPI_EVENT_ALL); } #if TRANSACTION_QUEUE_SIZE_SPI diff --git a/drivers/SPI.h b/drivers/SPI.h index e312dcc7b3..af102dc07c 100644 --- a/drivers/SPI.h +++ b/drivers/SPI.h @@ -246,6 +246,14 @@ protected: */ void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event); +private: + /** Lock deep sleep only if it is not yet locked */ + void lock_deep_sleep(); + + /** Unlock deep sleep in case it is locked */ + void unlock_deep_sleep(); + + #if TRANSACTION_QUEUE_SIZE_SPI /** Start a new transaction @@ -274,6 +282,7 @@ protected: CThunk _irq; event_callback_t _callback; DMAUsage _usage; + bool _deep_sleep_locked; #endif void aquire(void); From dc807b632e8472fd407d9a1ee7b4b0429ed79891 Mon Sep 17 00:00:00 2001 From: Steven Cartmell Date: Mon, 18 Dec 2017 11:21:24 +0000 Subject: [PATCH 117/118] Fix bug allowing I2C::abort_transfer to incorrectly unlock deep sleep mode - Add flag to I2C class to track if the I2C instance has locked deep sleep mode. - Wrap call to sleep_manager_lock_deep_sleep to only be called if I2C instance hasn't already locked deep sleep. - Wrap call to sleep_manager_unlock_deep_sleep to only be called if I2C has currently locked deep sleep mode. --- drivers/I2C.cpp | 26 +++++++++++++++++++++----- drivers/I2C.h | 10 +++++++++- 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/I2C.cpp b/drivers/I2C.cpp index 31d8532b40..c912e3f9e5 100644 --- a/drivers/I2C.cpp +++ b/drivers/I2C.cpp @@ -28,9 +28,10 @@ SingletonPtr I2C::_mutex; I2C::I2C(PinName sda, PinName scl) : #if DEVICE_I2C_ASYNCH - _irq(this), _usage(DMA_USAGE_NEVER), + _irq(this), _usage(DMA_USAGE_NEVER), _deep_sleep_locked(false), #endif - _i2c(), _hz(100000) { + _i2c(), _hz(100000) +{ // No lock needed in the constructor // The init function also set the frequency to 100000 @@ -133,7 +134,7 @@ int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_bu unlock(); return -1; // transaction ongoing } - sleep_manager_lock_deep_sleep(); + lock_deep_sleep(); aquire(); _callback = callback; @@ -148,7 +149,7 @@ void I2C::abort_transfer(void) { lock(); i2c_abort_asynch(&_i2c); - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); unlock(); } @@ -159,11 +160,26 @@ void I2C::irq_handler_asynch(void) _callback.call(event); } if (event) { - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); } } +void I2C::lock_deep_sleep() +{ + if (_deep_sleep_locked == false) { + sleep_manager_lock_deep_sleep(); + _deep_sleep_locked = true; + } +} + +void I2C::unlock_deep_sleep() +{ + if (_deep_sleep_locked == true) { + sleep_manager_unlock_deep_sleep(); + _deep_sleep_locked = false; + } +} #endif diff --git a/drivers/I2C.h b/drivers/I2C.h index b4fbc2f093..920a506eb7 100644 --- a/drivers/I2C.h +++ b/drivers/I2C.h @@ -176,11 +176,19 @@ public: /** Abort the on-going I2C transfer */ void abort_transfer(); -protected: + + protected: + /** Lock deep sleep only if it is not yet locked */ + void lock_deep_sleep(); + + /** Unlock deep sleep only if it has been locked */ + void unlock_deep_sleep(); + void irq_handler_asynch(void); event_callback_t _callback; CThunk _irq; DMAUsage _usage; + bool _deep_sleep_locked; #endif protected: From fd07de4985c4d34a4924255a522beabd4585c4e6 Mon Sep 17 00:00:00 2001 From: adbridge Date: Fri, 12 Jan 2018 15:01:50 +0000 Subject: [PATCH 118/118] Update Mbed version block for patch release --- mbed.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mbed.h b/mbed.h index 8673bfad51..fd27fba1a2 100644 --- a/mbed.h +++ b/mbed.h @@ -22,7 +22,7 @@ // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 7 -#define MBED_PATCH_VERSION 2 +#define MBED_PATCH_VERSION 3 #else // mbed 2